1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale i.MX7ULP LPSPI driver
4 //
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018, 2023, 2025 NXP
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma/imx-dma.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
28 #include <linux/types.h>
29
30 #define DRIVER_NAME "fsl_lpspi"
31
32 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
33
34 /* The maximum bytes that edma can transfer once.*/
35 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
36
37 /* i.MX7ULP LPSPI registers */
38 #define IMX7ULP_VERID 0x0
39 #define IMX7ULP_PARAM 0x4
40 #define IMX7ULP_CR 0x10
41 #define IMX7ULP_SR 0x14
42 #define IMX7ULP_IER 0x18
43 #define IMX7ULP_DER 0x1c
44 #define IMX7ULP_CFGR0 0x20
45 #define IMX7ULP_CFGR1 0x24
46 #define IMX7ULP_DMR0 0x30
47 #define IMX7ULP_DMR1 0x34
48 #define IMX7ULP_CCR 0x40
49 #define IMX7ULP_FCR 0x58
50 #define IMX7ULP_FSR 0x5c
51 #define IMX7ULP_TCR 0x60
52 #define IMX7ULP_TDR 0x64
53 #define IMX7ULP_RSR 0x70
54 #define IMX7ULP_RDR 0x74
55
56 /* General control register field define */
57 #define CR_RRF BIT(9)
58 #define CR_RTF BIT(8)
59 #define CR_RST BIT(1)
60 #define CR_MEN BIT(0)
61 #define SR_MBF BIT(24)
62 #define SR_TCF BIT(10)
63 #define SR_FCF BIT(9)
64 #define SR_RDF BIT(1)
65 #define SR_TDF BIT(0)
66 #define IER_TCIE BIT(10)
67 #define IER_FCIE BIT(9)
68 #define IER_RDIE BIT(1)
69 #define IER_TDIE BIT(0)
70 #define DER_RDDE BIT(1)
71 #define DER_TDDE BIT(0)
72 #define CFGR1_PCSCFG BIT(27)
73 #define CFGR1_PINCFG (BIT(24)|BIT(25))
74 #define CFGR1_PCSPOL_MASK GENMASK(11, 8)
75 #define CFGR1_NOSTALL BIT(3)
76 #define CFGR1_HOST BIT(0)
77 #define FSR_TXCOUNT (0xFF)
78 #define RSR_RXEMPTY BIT(1)
79 #define TCR_CPOL BIT(31)
80 #define TCR_CPHA BIT(30)
81 #define TCR_CONT BIT(21)
82 #define TCR_CONTC BIT(20)
83 #define TCR_RXMSK BIT(19)
84 #define TCR_TXMSK BIT(18)
85
86 #define SR_CLEAR_MASK GENMASK(13, 8)
87
88 struct fsl_lpspi_devtype_data {
89 u8 prescale_max;
90 };
91
92 struct lpspi_config {
93 u8 bpw;
94 u8 chip_select;
95 u8 prescale;
96 u16 mode;
97 u32 speed_hz;
98 };
99
100 struct fsl_lpspi_data {
101 struct device *dev;
102 void __iomem *base;
103 unsigned long base_phys;
104 struct clk *clk_ipg;
105 struct clk *clk_per;
106 bool is_target;
107 bool is_only_cs1;
108 bool is_first_byte;
109
110 void *rx_buf;
111 const void *tx_buf;
112 void (*tx)(struct fsl_lpspi_data *);
113 void (*rx)(struct fsl_lpspi_data *);
114
115 u32 remain;
116 u8 watermark;
117 u8 txfifosize;
118 u8 rxfifosize;
119
120 struct lpspi_config config;
121 struct completion xfer_done;
122
123 bool target_aborted;
124
125 /* DMA */
126 bool usedma;
127 struct completion dma_rx_completion;
128 struct completion dma_tx_completion;
129
130 const struct fsl_lpspi_devtype_data *devtype_data;
131 };
132
133 /*
134 * ERR051608 fixed or not:
135 * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
136 */
137 static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
138 .prescale_max = 1,
139 };
140
141 static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
142 .prescale_max = 7,
143 };
144
145 static const struct of_device_id fsl_lpspi_dt_ids[] = {
146 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
147 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
148 { /* sentinel */ }
149 };
150 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
151
152 #define LPSPI_BUF_RX(type) \
153 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
154 { \
155 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
156 \
157 if (fsl_lpspi->rx_buf) { \
158 *(type *)fsl_lpspi->rx_buf = val; \
159 fsl_lpspi->rx_buf += sizeof(type); \
160 } \
161 }
162
163 #define LPSPI_BUF_TX(type) \
164 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
165 { \
166 type val = 0; \
167 \
168 if (fsl_lpspi->tx_buf) { \
169 val = *(type *)fsl_lpspi->tx_buf; \
170 fsl_lpspi->tx_buf += sizeof(type); \
171 } \
172 \
173 fsl_lpspi->remain -= sizeof(type); \
174 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
175 }
176
177 LPSPI_BUF_RX(u8)
LPSPI_BUF_TX(u8)178 LPSPI_BUF_TX(u8)
179 LPSPI_BUF_RX(u16)
180 LPSPI_BUF_TX(u16)
181 LPSPI_BUF_RX(u32)
182 LPSPI_BUF_TX(u32)
183
184 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
185 unsigned int enable)
186 {
187 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
188 }
189
fsl_lpspi_bytes_per_word(const int bpw)190 static int fsl_lpspi_bytes_per_word(const int bpw)
191 {
192 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
193 }
194
fsl_lpspi_can_dma(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)195 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
196 struct spi_device *spi,
197 struct spi_transfer *transfer)
198 {
199 unsigned int bytes_per_word;
200
201 if (!controller->dma_rx)
202 return false;
203
204 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
205
206 switch (bytes_per_word) {
207 case 1:
208 case 2:
209 case 4:
210 break;
211 default:
212 return false;
213 }
214
215 return true;
216 }
217
lpspi_prepare_xfer_hardware(struct spi_controller * controller)218 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
219 {
220 struct fsl_lpspi_data *fsl_lpspi =
221 spi_controller_get_devdata(controller);
222 int ret;
223
224 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
225 if (ret < 0) {
226 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
227 return ret;
228 }
229
230 return 0;
231 }
232
lpspi_unprepare_xfer_hardware(struct spi_controller * controller)233 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
234 {
235 struct fsl_lpspi_data *fsl_lpspi =
236 spi_controller_get_devdata(controller);
237
238 pm_runtime_mark_last_busy(fsl_lpspi->dev);
239 pm_runtime_put_autosuspend(fsl_lpspi->dev);
240
241 return 0;
242 }
243
fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data * fsl_lpspi)244 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
245 {
246 u8 txfifo_cnt;
247 u32 temp;
248
249 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
250
251 while (txfifo_cnt < fsl_lpspi->txfifosize) {
252 if (!fsl_lpspi->remain)
253 break;
254 fsl_lpspi->tx(fsl_lpspi);
255 txfifo_cnt++;
256 }
257
258 if (txfifo_cnt < fsl_lpspi->txfifosize) {
259 if (!fsl_lpspi->is_target) {
260 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
261 temp &= ~TCR_CONTC;
262 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
263 }
264
265 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
266 } else
267 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
268 }
269
fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data * fsl_lpspi)270 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
271 {
272 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
273 fsl_lpspi->rx(fsl_lpspi);
274 }
275
fsl_lpspi_set_cmd(struct fsl_lpspi_data * fsl_lpspi)276 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
277 {
278 u32 temp = 0;
279
280 temp |= fsl_lpspi->config.bpw - 1;
281 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
282 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
283 if (!fsl_lpspi->is_target) {
284 temp |= fsl_lpspi->config.prescale << 27;
285 /*
286 * Set TCR_CONT will keep SS asserted after current transfer.
287 * For the first transfer, clear TCR_CONTC to assert SS.
288 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
289 */
290 if (!fsl_lpspi->usedma) {
291 temp |= TCR_CONT;
292 if (fsl_lpspi->is_first_byte)
293 temp &= ~TCR_CONTC;
294 else
295 temp |= TCR_CONTC;
296 }
297 }
298 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
299
300 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
301 }
302
fsl_lpspi_set_watermark(struct fsl_lpspi_data * fsl_lpspi)303 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
304 {
305 u32 temp;
306
307 if (!fsl_lpspi->usedma)
308 temp = fsl_lpspi->watermark >> 1 |
309 (fsl_lpspi->watermark >> 1) << 16;
310 else
311 temp = fsl_lpspi->watermark >> 1;
312
313 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
314
315 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
316 }
317
fsl_lpspi_set_bitrate(struct fsl_lpspi_data * fsl_lpspi)318 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
319 {
320 struct lpspi_config config = fsl_lpspi->config;
321 unsigned int perclk_rate, div;
322 u8 prescale_max;
323 u8 prescale;
324 int scldiv;
325
326 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
327 prescale_max = fsl_lpspi->devtype_data->prescale_max;
328
329 if (!config.speed_hz) {
330 dev_err(fsl_lpspi->dev,
331 "error: the transmission speed provided is 0!\n");
332 return -EINVAL;
333 }
334
335 if (config.speed_hz > perclk_rate / 2) {
336 div = 2;
337 } else {
338 div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
339 }
340
341 for (prescale = 0; prescale <= prescale_max; prescale++) {
342 scldiv = div / (1 << prescale) - 2;
343 if (scldiv >= 0 && scldiv < 256) {
344 fsl_lpspi->config.prescale = prescale;
345 break;
346 }
347 }
348
349 if (scldiv < 0 || scldiv >= 256)
350 return -EINVAL;
351
352 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
353 fsl_lpspi->base + IMX7ULP_CCR);
354
355 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
356 perclk_rate, config.speed_hz, prescale, scldiv);
357
358 return 0;
359 }
360
fsl_lpspi_dma_configure(struct spi_controller * controller)361 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
362 {
363 int ret;
364 enum dma_slave_buswidth buswidth;
365 struct dma_slave_config rx = {}, tx = {};
366 struct fsl_lpspi_data *fsl_lpspi =
367 spi_controller_get_devdata(controller);
368
369 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
370 case 4:
371 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
372 break;
373 case 2:
374 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
375 break;
376 case 1:
377 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
378 break;
379 default:
380 return -EINVAL;
381 }
382
383 tx.direction = DMA_MEM_TO_DEV;
384 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
385 tx.dst_addr_width = buswidth;
386 tx.dst_maxburst = 1;
387 ret = dmaengine_slave_config(controller->dma_tx, &tx);
388 if (ret) {
389 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
390 ret);
391 return ret;
392 }
393
394 rx.direction = DMA_DEV_TO_MEM;
395 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
396 rx.src_addr_width = buswidth;
397 rx.src_maxburst = 1;
398 ret = dmaengine_slave_config(controller->dma_rx, &rx);
399 if (ret) {
400 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
401 ret);
402 return ret;
403 }
404
405 return 0;
406 }
407
fsl_lpspi_config(struct fsl_lpspi_data * fsl_lpspi)408 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
409 {
410 u32 temp;
411 int ret;
412
413 if (!fsl_lpspi->is_target) {
414 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
415 if (ret)
416 return ret;
417 }
418
419 fsl_lpspi_set_watermark(fsl_lpspi);
420
421 if (!fsl_lpspi->is_target)
422 temp = CFGR1_HOST;
423 else
424 temp = CFGR1_PINCFG;
425 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
426 temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
427 BIT(fsl_lpspi->config.chip_select));
428
429 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
430
431 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
432 temp |= CR_RRF | CR_RTF | CR_MEN;
433 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
434
435 temp = 0;
436 if (fsl_lpspi->usedma)
437 temp = DER_TDDE | DER_RDDE;
438 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
439
440 return 0;
441 }
442
fsl_lpspi_setup_transfer(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)443 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
444 struct spi_device *spi,
445 struct spi_transfer *t)
446 {
447 struct fsl_lpspi_data *fsl_lpspi =
448 spi_controller_get_devdata(spi->controller);
449
450 if (t == NULL)
451 return -EINVAL;
452
453 fsl_lpspi->config.mode = spi->mode;
454 fsl_lpspi->config.bpw = t->bits_per_word;
455 fsl_lpspi->config.speed_hz = t->speed_hz;
456 if (fsl_lpspi->is_only_cs1)
457 fsl_lpspi->config.chip_select = 1;
458 else
459 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
460
461 if (!fsl_lpspi->config.speed_hz)
462 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
463 if (!fsl_lpspi->config.bpw)
464 fsl_lpspi->config.bpw = spi->bits_per_word;
465
466 /* Initialize the functions for transfer */
467 if (fsl_lpspi->config.bpw <= 8) {
468 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
469 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
470 } else if (fsl_lpspi->config.bpw <= 16) {
471 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
472 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
473 } else {
474 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
475 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
476 }
477
478 if (t->len <= fsl_lpspi->txfifosize)
479 fsl_lpspi->watermark = t->len;
480 else
481 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
482
483 if (fsl_lpspi_can_dma(controller, spi, t))
484 fsl_lpspi->usedma = true;
485 else
486 fsl_lpspi->usedma = false;
487
488 return fsl_lpspi_config(fsl_lpspi);
489 }
490
fsl_lpspi_target_abort(struct spi_controller * controller)491 static int fsl_lpspi_target_abort(struct spi_controller *controller)
492 {
493 struct fsl_lpspi_data *fsl_lpspi =
494 spi_controller_get_devdata(controller);
495
496 fsl_lpspi->target_aborted = true;
497 if (!fsl_lpspi->usedma)
498 complete(&fsl_lpspi->xfer_done);
499 else {
500 complete(&fsl_lpspi->dma_tx_completion);
501 complete(&fsl_lpspi->dma_rx_completion);
502 }
503
504 return 0;
505 }
506
fsl_lpspi_wait_for_completion(struct spi_controller * controller)507 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
508 {
509 struct fsl_lpspi_data *fsl_lpspi =
510 spi_controller_get_devdata(controller);
511
512 if (fsl_lpspi->is_target) {
513 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
514 fsl_lpspi->target_aborted) {
515 dev_dbg(fsl_lpspi->dev, "interrupted\n");
516 return -EINTR;
517 }
518 } else {
519 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
520 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
521 return -ETIMEDOUT;
522 }
523 }
524
525 return 0;
526 }
527
fsl_lpspi_reset(struct fsl_lpspi_data * fsl_lpspi)528 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
529 {
530 u32 temp;
531
532 if (!fsl_lpspi->usedma) {
533 /* Disable all interrupt */
534 fsl_lpspi_intctrl(fsl_lpspi, 0);
535 }
536
537 /* Clear FIFO and disable module */
538 temp = CR_RRF | CR_RTF;
539 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
540
541 /* W1C for all flags in SR */
542 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
543
544 return 0;
545 }
546
fsl_lpspi_dma_rx_callback(void * cookie)547 static void fsl_lpspi_dma_rx_callback(void *cookie)
548 {
549 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
550
551 complete(&fsl_lpspi->dma_rx_completion);
552 }
553
fsl_lpspi_dma_tx_callback(void * cookie)554 static void fsl_lpspi_dma_tx_callback(void *cookie)
555 {
556 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
557
558 complete(&fsl_lpspi->dma_tx_completion);
559 }
560
fsl_lpspi_calculate_timeout(struct fsl_lpspi_data * fsl_lpspi,int size)561 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
562 int size)
563 {
564 unsigned long timeout = 0;
565
566 /* Time with actual data transfer and CS change delay related to HW */
567 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
568
569 /* Add extra second for scheduler related activities */
570 timeout += 1;
571
572 /* Double calculated timeout */
573 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
574 }
575
fsl_lpspi_dma_transfer(struct spi_controller * controller,struct fsl_lpspi_data * fsl_lpspi,struct spi_transfer * transfer)576 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
577 struct fsl_lpspi_data *fsl_lpspi,
578 struct spi_transfer *transfer)
579 {
580 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
581 unsigned long transfer_timeout;
582 unsigned long time_left;
583 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
584 int ret;
585
586 ret = fsl_lpspi_dma_configure(controller);
587 if (ret)
588 return ret;
589
590 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
591 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
592 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
593 if (!desc_rx)
594 return -EINVAL;
595
596 desc_rx->callback = fsl_lpspi_dma_rx_callback;
597 desc_rx->callback_param = (void *)fsl_lpspi;
598 dmaengine_submit(desc_rx);
599 reinit_completion(&fsl_lpspi->dma_rx_completion);
600 dma_async_issue_pending(controller->dma_rx);
601
602 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
603 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
604 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
605 if (!desc_tx) {
606 dmaengine_terminate_all(controller->dma_tx);
607 return -EINVAL;
608 }
609
610 desc_tx->callback = fsl_lpspi_dma_tx_callback;
611 desc_tx->callback_param = (void *)fsl_lpspi;
612 dmaengine_submit(desc_tx);
613 reinit_completion(&fsl_lpspi->dma_tx_completion);
614 dma_async_issue_pending(controller->dma_tx);
615
616 fsl_lpspi->target_aborted = false;
617
618 if (!fsl_lpspi->is_target) {
619 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
620 transfer->len);
621
622 /* Wait eDMA to finish the data transfer.*/
623 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
624 transfer_timeout);
625 if (!time_left) {
626 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
627 dmaengine_terminate_all(controller->dma_tx);
628 dmaengine_terminate_all(controller->dma_rx);
629 fsl_lpspi_reset(fsl_lpspi);
630 return -ETIMEDOUT;
631 }
632
633 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
634 transfer_timeout);
635 if (!time_left) {
636 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
637 dmaengine_terminate_all(controller->dma_tx);
638 dmaengine_terminate_all(controller->dma_rx);
639 fsl_lpspi_reset(fsl_lpspi);
640 return -ETIMEDOUT;
641 }
642 } else {
643 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
644 fsl_lpspi->target_aborted) {
645 dev_dbg(fsl_lpspi->dev,
646 "I/O Error in DMA TX interrupted\n");
647 dmaengine_terminate_all(controller->dma_tx);
648 dmaengine_terminate_all(controller->dma_rx);
649 fsl_lpspi_reset(fsl_lpspi);
650 return -EINTR;
651 }
652
653 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
654 fsl_lpspi->target_aborted) {
655 dev_dbg(fsl_lpspi->dev,
656 "I/O Error in DMA RX interrupted\n");
657 dmaengine_terminate_all(controller->dma_tx);
658 dmaengine_terminate_all(controller->dma_rx);
659 fsl_lpspi_reset(fsl_lpspi);
660 return -EINTR;
661 }
662 }
663
664 fsl_lpspi_reset(fsl_lpspi);
665
666 return 0;
667 }
668
fsl_lpspi_dma_exit(struct spi_controller * controller)669 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
670 {
671 if (controller->dma_rx) {
672 dma_release_channel(controller->dma_rx);
673 controller->dma_rx = NULL;
674 }
675
676 if (controller->dma_tx) {
677 dma_release_channel(controller->dma_tx);
678 controller->dma_tx = NULL;
679 }
680 }
681
fsl_lpspi_dma_init(struct device * dev,struct fsl_lpspi_data * fsl_lpspi,struct spi_controller * controller)682 static int fsl_lpspi_dma_init(struct device *dev,
683 struct fsl_lpspi_data *fsl_lpspi,
684 struct spi_controller *controller)
685 {
686 int ret;
687
688 /* Prepare for TX DMA: */
689 controller->dma_tx = dma_request_chan(dev, "tx");
690 if (IS_ERR(controller->dma_tx)) {
691 ret = PTR_ERR(controller->dma_tx);
692 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
693 controller->dma_tx = NULL;
694 goto err;
695 }
696
697 /* Prepare for RX DMA: */
698 controller->dma_rx = dma_request_chan(dev, "rx");
699 if (IS_ERR(controller->dma_rx)) {
700 ret = PTR_ERR(controller->dma_rx);
701 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
702 controller->dma_rx = NULL;
703 goto err;
704 }
705
706 init_completion(&fsl_lpspi->dma_rx_completion);
707 init_completion(&fsl_lpspi->dma_tx_completion);
708 controller->can_dma = fsl_lpspi_can_dma;
709 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
710
711 return 0;
712 err:
713 fsl_lpspi_dma_exit(controller);
714 return ret;
715 }
716
fsl_lpspi_pio_transfer(struct spi_controller * controller,struct spi_transfer * t)717 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
718 struct spi_transfer *t)
719 {
720 struct fsl_lpspi_data *fsl_lpspi =
721 spi_controller_get_devdata(controller);
722 int ret;
723
724 fsl_lpspi->tx_buf = t->tx_buf;
725 fsl_lpspi->rx_buf = t->rx_buf;
726 fsl_lpspi->remain = t->len;
727
728 reinit_completion(&fsl_lpspi->xfer_done);
729 fsl_lpspi->target_aborted = false;
730
731 fsl_lpspi_write_tx_fifo(fsl_lpspi);
732
733 ret = fsl_lpspi_wait_for_completion(controller);
734
735 fsl_lpspi_reset(fsl_lpspi);
736
737 return ret;
738 }
739
fsl_lpspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)740 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
741 struct spi_device *spi,
742 struct spi_transfer *t)
743 {
744 struct fsl_lpspi_data *fsl_lpspi =
745 spi_controller_get_devdata(controller);
746 int ret;
747
748 fsl_lpspi->is_first_byte = true;
749 ret = fsl_lpspi_setup_transfer(controller, spi, t);
750 if (ret < 0)
751 return ret;
752
753 fsl_lpspi_set_cmd(fsl_lpspi);
754 fsl_lpspi->is_first_byte = false;
755
756 if (fsl_lpspi->usedma)
757 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
758 else
759 ret = fsl_lpspi_pio_transfer(controller, t);
760 if (ret < 0)
761 return ret;
762
763 return 0;
764 }
765
fsl_lpspi_isr(int irq,void * dev_id)766 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
767 {
768 u32 temp_SR, temp_IER;
769 struct fsl_lpspi_data *fsl_lpspi = dev_id;
770
771 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
772 fsl_lpspi_intctrl(fsl_lpspi, 0);
773 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
774
775 fsl_lpspi_read_rx_fifo(fsl_lpspi);
776
777 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
778 fsl_lpspi_write_tx_fifo(fsl_lpspi);
779 return IRQ_HANDLED;
780 }
781
782 if (temp_SR & SR_MBF ||
783 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
784 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
785 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE | (temp_IER & IER_TDIE));
786 return IRQ_HANDLED;
787 }
788
789 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
790 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
791 complete(&fsl_lpspi->xfer_done);
792 return IRQ_HANDLED;
793 }
794
795 return IRQ_NONE;
796 }
797
798 #ifdef CONFIG_PM
fsl_lpspi_runtime_resume(struct device * dev)799 static int fsl_lpspi_runtime_resume(struct device *dev)
800 {
801 struct spi_controller *controller = dev_get_drvdata(dev);
802 struct fsl_lpspi_data *fsl_lpspi;
803 int ret;
804
805 fsl_lpspi = spi_controller_get_devdata(controller);
806
807 ret = clk_prepare_enable(fsl_lpspi->clk_per);
808 if (ret)
809 return ret;
810
811 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
812 if (ret) {
813 clk_disable_unprepare(fsl_lpspi->clk_per);
814 return ret;
815 }
816
817 return 0;
818 }
819
fsl_lpspi_runtime_suspend(struct device * dev)820 static int fsl_lpspi_runtime_suspend(struct device *dev)
821 {
822 struct spi_controller *controller = dev_get_drvdata(dev);
823 struct fsl_lpspi_data *fsl_lpspi;
824
825 fsl_lpspi = spi_controller_get_devdata(controller);
826
827 clk_disable_unprepare(fsl_lpspi->clk_per);
828 clk_disable_unprepare(fsl_lpspi->clk_ipg);
829
830 return 0;
831 }
832 #endif
833
fsl_lpspi_init_rpm(struct fsl_lpspi_data * fsl_lpspi)834 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
835 {
836 struct device *dev = fsl_lpspi->dev;
837
838 pm_runtime_enable(dev);
839 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
840 pm_runtime_use_autosuspend(dev);
841
842 return 0;
843 }
844
fsl_lpspi_probe(struct platform_device * pdev)845 static int fsl_lpspi_probe(struct platform_device *pdev)
846 {
847 const struct fsl_lpspi_devtype_data *devtype_data;
848 struct fsl_lpspi_data *fsl_lpspi;
849 struct spi_controller *controller;
850 struct resource *res;
851 int ret, irq;
852 u32 num_cs;
853 u32 temp;
854 bool is_target;
855
856 devtype_data = of_device_get_match_data(&pdev->dev);
857 if (!devtype_data)
858 return -ENODEV;
859
860 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
861 if (is_target)
862 controller = devm_spi_alloc_target(&pdev->dev,
863 sizeof(struct fsl_lpspi_data));
864 else
865 controller = devm_spi_alloc_host(&pdev->dev,
866 sizeof(struct fsl_lpspi_data));
867
868 if (!controller)
869 return -ENOMEM;
870
871 platform_set_drvdata(pdev, controller);
872
873 fsl_lpspi = spi_controller_get_devdata(controller);
874 fsl_lpspi->dev = &pdev->dev;
875 fsl_lpspi->is_target = is_target;
876 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
877 "fsl,spi-only-use-cs1-sel");
878 fsl_lpspi->devtype_data = devtype_data;
879
880 init_completion(&fsl_lpspi->xfer_done);
881
882 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
883 if (IS_ERR(fsl_lpspi->base)) {
884 ret = PTR_ERR(fsl_lpspi->base);
885 return ret;
886 }
887 fsl_lpspi->base_phys = res->start;
888
889 irq = platform_get_irq(pdev, 0);
890 if (irq < 0) {
891 ret = irq;
892 return ret;
893 }
894
895 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN,
896 dev_name(&pdev->dev), fsl_lpspi);
897 if (ret) {
898 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
899 return ret;
900 }
901
902 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
903 if (IS_ERR(fsl_lpspi->clk_per)) {
904 ret = PTR_ERR(fsl_lpspi->clk_per);
905 return ret;
906 }
907
908 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
909 if (IS_ERR(fsl_lpspi->clk_ipg)) {
910 ret = PTR_ERR(fsl_lpspi->clk_ipg);
911 return ret;
912 }
913
914 /* enable the clock */
915 ret = fsl_lpspi_init_rpm(fsl_lpspi);
916 if (ret)
917 return ret;
918
919 ret = pm_runtime_get_sync(fsl_lpspi->dev);
920 if (ret < 0) {
921 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
922 goto out_pm_get;
923 }
924
925 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
926 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
927 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
928 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
929 &num_cs)) {
930 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
931 num_cs = ((temp >> 16) & 0xf);
932 else
933 num_cs = 1;
934 }
935
936 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
937 controller->transfer_one = fsl_lpspi_transfer_one;
938 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
939 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
940 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
941 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
942 controller->dev.of_node = pdev->dev.of_node;
943 controller->bus_num = pdev->id;
944 controller->num_chipselect = num_cs;
945 controller->target_abort = fsl_lpspi_target_abort;
946 if (!fsl_lpspi->is_target)
947 controller->use_gpio_descriptors = true;
948
949 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
950 if (ret == -EPROBE_DEFER)
951 goto out_pm_get;
952 if (ret < 0) {
953 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
954 enable_irq(irq);
955 }
956
957 ret = devm_spi_register_controller(&pdev->dev, controller);
958 if (ret < 0) {
959 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
960 goto free_dma;
961 }
962
963 pm_runtime_mark_last_busy(fsl_lpspi->dev);
964 pm_runtime_put_autosuspend(fsl_lpspi->dev);
965
966 return 0;
967
968 free_dma:
969 fsl_lpspi_dma_exit(controller);
970 out_pm_get:
971 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
972 pm_runtime_put_sync(fsl_lpspi->dev);
973 pm_runtime_disable(fsl_lpspi->dev);
974
975 return ret;
976 }
977
fsl_lpspi_remove(struct platform_device * pdev)978 static void fsl_lpspi_remove(struct platform_device *pdev)
979 {
980 struct spi_controller *controller = platform_get_drvdata(pdev);
981 struct fsl_lpspi_data *fsl_lpspi =
982 spi_controller_get_devdata(controller);
983
984 fsl_lpspi_dma_exit(controller);
985
986 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
987 pm_runtime_disable(fsl_lpspi->dev);
988 }
989
fsl_lpspi_suspend(struct device * dev)990 static int fsl_lpspi_suspend(struct device *dev)
991 {
992 pinctrl_pm_select_sleep_state(dev);
993 return pm_runtime_force_suspend(dev);
994 }
995
fsl_lpspi_resume(struct device * dev)996 static int fsl_lpspi_resume(struct device *dev)
997 {
998 int ret;
999
1000 ret = pm_runtime_force_resume(dev);
1001 if (ret) {
1002 dev_err(dev, "Error in resume: %d\n", ret);
1003 return ret;
1004 }
1005
1006 pinctrl_pm_select_default_state(dev);
1007
1008 return 0;
1009 }
1010
1011 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
1012 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
1013 fsl_lpspi_runtime_resume, NULL)
1014 SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1015 };
1016
1017 static struct platform_driver fsl_lpspi_driver = {
1018 .driver = {
1019 .name = DRIVER_NAME,
1020 .of_match_table = fsl_lpspi_dt_ids,
1021 .pm = pm_ptr(&fsl_lpspi_pm_ops),
1022 },
1023 .probe = fsl_lpspi_probe,
1024 .remove_new = fsl_lpspi_remove,
1025 };
1026 module_platform_driver(fsl_lpspi_driver);
1027
1028 MODULE_DESCRIPTION("LPSPI Controller driver");
1029 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1030 MODULE_LICENSE("GPL");
1031