1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interconnect/qcom,ipq9574.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clocks { 22 sleep_clk: sleep-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 }; 26 27 xo_board_clk: xo-board-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a73"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&L2_0>; 43 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 44 clock-names = "cpu"; 45 operating-points-v2 = <&cpu_opp_table>; 46 cpu-supply = <&ipq9574_s1>; 47 #cooling-cells = <2>; 48 }; 49 50 CPU1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a73"; 53 reg = <0x1>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-supply = <&ipq9574_s1>; 60 #cooling-cells = <2>; 61 }; 62 63 CPU2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a73"; 66 reg = <0x2>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu_opp_table>; 72 cpu-supply = <&ipq9574_s1>; 73 #cooling-cells = <2>; 74 }; 75 76 CPU3: cpu@3 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a73"; 79 reg = <0x3>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 83 clock-names = "cpu"; 84 operating-points-v2 = <&cpu_opp_table>; 85 cpu-supply = <&ipq9574_s1>; 86 #cooling-cells = <2>; 87 }; 88 89 L2_0: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 firmware { 97 scm { 98 compatible = "qcom,scm-ipq9574", "qcom,scm"; 99 qcom,dload-mode = <&tcsr 0x6100>; 100 }; 101 }; 102 103 memory@40000000 { 104 device_type = "memory"; 105 /* We expect the bootloader to fill in the size */ 106 reg = <0x0 0x40000000 0x0 0x0>; 107 }; 108 109 cpu_opp_table: opp-table-cpu { 110 compatible = "operating-points-v2-kryo-cpu"; 111 opp-shared; 112 nvmem-cells = <&cpu_speed_bin>; 113 114 opp-936000000 { 115 opp-hz = /bits/ 64 <936000000>; 116 opp-microvolt = <725000>; 117 opp-supported-hw = <0xf>; 118 clock-latency-ns = <200000>; 119 }; 120 121 opp-1104000000 { 122 opp-hz = /bits/ 64 <1104000000>; 123 opp-microvolt = <787500>; 124 opp-supported-hw = <0xf>; 125 clock-latency-ns = <200000>; 126 }; 127 128 opp-1200000000 { 129 opp-hz = /bits/ 64 <1200000000>; 130 opp-microvolt = <862500>; 131 opp-supported-hw = <0xf>; 132 clock-latency-ns = <200000>; 133 }; 134 135 opp-1416000000 { 136 opp-hz = /bits/ 64 <1416000000>; 137 opp-microvolt = <862500>; 138 opp-supported-hw = <0x7>; 139 clock-latency-ns = <200000>; 140 }; 141 142 opp-1488000000 { 143 opp-hz = /bits/ 64 <1488000000>; 144 opp-microvolt = <925000>; 145 opp-supported-hw = <0x7>; 146 clock-latency-ns = <200000>; 147 }; 148 149 opp-1800000000 { 150 opp-hz = /bits/ 64 <1800000000>; 151 opp-microvolt = <987500>; 152 opp-supported-hw = <0x5>; 153 clock-latency-ns = <200000>; 154 }; 155 156 opp-2208000000 { 157 opp-hz = /bits/ 64 <2208000000>; 158 opp-microvolt = <1062500>; 159 opp-supported-hw = <0x1>; 160 clock-latency-ns = <200000>; 161 }; 162 }; 163 164 pmu { 165 compatible = "arm,cortex-a73-pmu"; 166 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 167 }; 168 169 psci { 170 compatible = "arm,psci-1.0"; 171 method = "smc"; 172 }; 173 174 rpm: remoteproc { 175 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 176 177 glink-edge { 178 compatible = "qcom,glink-rpm"; 179 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 180 qcom,rpm-msg-ram = <&rpm_msg_ram>; 181 mboxes = <&apcs_glb 0>; 182 183 rpm_requests: rpm-requests { 184 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm"; 185 qcom,glink-channels = "rpm_requests"; 186 }; 187 }; 188 }; 189 190 reserved-memory { 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 195 bootloader@4a100000 { 196 reg = <0x0 0x4a100000 0x0 0x400000>; 197 no-map; 198 }; 199 200 sbl@4a500000 { 201 reg = <0x0 0x4a500000 0x0 0x100000>; 202 no-map; 203 }; 204 205 tz_region: tz@4a600000 { 206 reg = <0x0 0x4a600000 0x0 0x400000>; 207 no-map; 208 }; 209 210 smem@4aa00000 { 211 compatible = "qcom,smem"; 212 reg = <0x0 0x4aa00000 0x0 0x100000>; 213 hwlocks = <&tcsr_mutex 3>; 214 no-map; 215 }; 216 }; 217 218 soc: soc@0 { 219 compatible = "simple-bus"; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0 0 0 0xffffffff>; 223 224 rpm_msg_ram: sram@60000 { 225 compatible = "qcom,rpm-msg-ram"; 226 reg = <0x00060000 0x6000>; 227 }; 228 229 rng: rng@e3000 { 230 compatible = "qcom,prng-ee"; 231 reg = <0x000e3000 0x1000>; 232 clocks = <&gcc GCC_PRNG_AHB_CLK>; 233 clock-names = "core"; 234 }; 235 236 mdio: mdio@90000 { 237 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; 238 reg = <0x00090000 0x64>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 clocks = <&gcc GCC_MDIO_AHB_CLK>; 242 clock-names = "gcc_mdio_ahb_clk"; 243 status = "disabled"; 244 }; 245 246 qfprom: efuse@a4000 { 247 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 248 reg = <0x000a4000 0x5a1>; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 cpu_speed_bin: cpu-speed-bin@15 { 253 reg = <0x15 0x2>; 254 bits = <7 2>; 255 }; 256 }; 257 258 cryptobam: dma-controller@704000 { 259 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 260 reg = <0x00704000 0x20000>; 261 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 262 #dma-cells = <1>; 263 qcom,ee = <1>; 264 qcom,num-ees = <4>; 265 num-channels = <16>; 266 qcom,controlled-remotely; 267 }; 268 269 crypto: crypto@73a000 { 270 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 271 reg = <0x0073a000 0x6000>; 272 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 273 <&gcc GCC_CRYPTO_AXI_CLK>, 274 <&gcc GCC_CRYPTO_CLK>; 275 clock-names = "iface", "bus", "core"; 276 dmas = <&cryptobam 2>, <&cryptobam 3>; 277 dma-names = "rx", "tx"; 278 }; 279 280 tsens: thermal-sensor@4a9000 { 281 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 282 reg = <0x004a9000 0x1000>, 283 <0x004a8000 0x1000>; 284 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "combined"; 286 #qcom,sensors = <16>; 287 #thermal-sensor-cells = <1>; 288 }; 289 290 tlmm: pinctrl@1000000 { 291 compatible = "qcom,ipq9574-tlmm"; 292 reg = <0x01000000 0x300000>; 293 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 gpio-ranges = <&tlmm 0 0 65>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 300 uart2_pins: uart2-state { 301 pins = "gpio34", "gpio35"; 302 function = "blsp2_uart"; 303 drive-strength = <8>; 304 bias-disable; 305 }; 306 }; 307 308 gcc: clock-controller@1800000 { 309 compatible = "qcom,ipq9574-gcc"; 310 reg = <0x01800000 0x80000>; 311 clocks = <&xo_board_clk>, 312 <&sleep_clk>, 313 <0>, 314 <0>, 315 <0>, 316 <0>, 317 <0>, 318 <0>; 319 #clock-cells = <1>; 320 #reset-cells = <1>; 321 #interconnect-cells = <1>; 322 }; 323 324 tcsr_mutex: hwlock@1905000 { 325 compatible = "qcom,tcsr-mutex"; 326 reg = <0x01905000 0x20000>; 327 #hwlock-cells = <1>; 328 }; 329 330 tcsr: syscon@1937000 { 331 compatible = "qcom,tcsr-ipq9574", "syscon"; 332 reg = <0x01937000 0x21000>; 333 }; 334 335 sdhc_1: mmc@7804000 { 336 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 337 reg = <0x07804000 0x1000>, 338 <0x07805000 0x1000>, 339 <0x07808000 0x2000>; 340 reg-names = "hc", "cqhci", "ice"; 341 342 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "hc_irq", "pwr_irq"; 345 346 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 347 <&gcc GCC_SDCC1_APPS_CLK>, 348 <&xo_board_clk>, 349 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 350 clock-names = "iface", "core", "xo", "ice"; 351 non-removable; 352 supports-cqe; 353 status = "disabled"; 354 }; 355 356 blsp_dma: dma-controller@7884000 { 357 compatible = "qcom,bam-v1.7.0"; 358 reg = <0x07884000 0x2b000>; 359 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 361 clock-names = "bam_clk"; 362 #dma-cells = <1>; 363 qcom,ee = <0>; 364 }; 365 366 blsp1_uart0: serial@78af000 { 367 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 368 reg = <0x078af000 0x200>; 369 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 371 <&gcc GCC_BLSP1_AHB_CLK>; 372 clock-names = "core", "iface"; 373 status = "disabled"; 374 }; 375 376 blsp1_uart1: serial@78b0000 { 377 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 378 reg = <0x078b0000 0x200>; 379 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 381 <&gcc GCC_BLSP1_AHB_CLK>; 382 clock-names = "core", "iface"; 383 status = "disabled"; 384 }; 385 386 blsp1_uart2: serial@78b1000 { 387 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 388 reg = <0x078b1000 0x200>; 389 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 391 <&gcc GCC_BLSP1_AHB_CLK>; 392 clock-names = "core", "iface"; 393 status = "disabled"; 394 }; 395 396 blsp1_uart3: serial@78b2000 { 397 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 398 reg = <0x078b2000 0x200>; 399 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 401 <&gcc GCC_BLSP1_AHB_CLK>; 402 clock-names = "core", "iface"; 403 status = "disabled"; 404 }; 405 406 blsp1_uart4: serial@78b3000 { 407 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 408 reg = <0x078b3000 0x200>; 409 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 411 <&gcc GCC_BLSP1_AHB_CLK>; 412 clock-names = "core", "iface"; 413 status = "disabled"; 414 }; 415 416 blsp1_uart5: serial@78b4000 { 417 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 418 reg = <0x078b4000 0x200>; 419 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 421 <&gcc GCC_BLSP1_AHB_CLK>; 422 clock-names = "core", "iface"; 423 status = "disabled"; 424 }; 425 426 blsp1_spi0: spi@78b5000 { 427 compatible = "qcom,spi-qup-v2.2.1"; 428 reg = <0x078b5000 0x600>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 433 <&gcc GCC_BLSP1_AHB_CLK>; 434 clock-names = "core", "iface"; 435 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 436 dma-names = "tx", "rx"; 437 status = "disabled"; 438 }; 439 440 blsp1_i2c1: i2c@78b6000 { 441 compatible = "qcom,i2c-qup-v2.2.1"; 442 reg = <0x078b6000 0x600>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 447 <&gcc GCC_BLSP1_AHB_CLK>; 448 clock-names = "core", "iface"; 449 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 450 assigned-clock-rates = <50000000>; 451 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 452 dma-names = "tx", "rx"; 453 status = "disabled"; 454 }; 455 456 blsp1_spi1: spi@78b6000 { 457 compatible = "qcom,spi-qup-v2.2.1"; 458 reg = <0x078b6000 0x600>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 463 <&gcc GCC_BLSP1_AHB_CLK>; 464 clock-names = "core", "iface"; 465 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 466 dma-names = "tx", "rx"; 467 status = "disabled"; 468 }; 469 470 blsp1_i2c2: i2c@78b7000 { 471 compatible = "qcom,i2c-qup-v2.2.1"; 472 reg = <0x078b7000 0x600>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 477 <&gcc GCC_BLSP1_AHB_CLK>; 478 clock-names = "core", "iface"; 479 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 480 assigned-clock-rates = <50000000>; 481 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 482 dma-names = "tx", "rx"; 483 status = "disabled"; 484 }; 485 486 blsp1_spi2: spi@78b7000 { 487 compatible = "qcom,spi-qup-v2.2.1"; 488 reg = <0x078b7000 0x600>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 493 <&gcc GCC_BLSP1_AHB_CLK>; 494 clock-names = "core", "iface"; 495 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 496 dma-names = "tx", "rx"; 497 status = "disabled"; 498 }; 499 500 blsp1_i2c3: i2c@78b8000 { 501 compatible = "qcom,i2c-qup-v2.2.1"; 502 reg = <0x078b8000 0x600>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 507 <&gcc GCC_BLSP1_AHB_CLK>; 508 clock-names = "core", "iface"; 509 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 510 assigned-clock-rates = <50000000>; 511 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 512 dma-names = "tx", "rx"; 513 status = "disabled"; 514 }; 515 516 blsp1_spi3: spi@78b8000 { 517 compatible = "qcom,spi-qup-v2.2.1"; 518 reg = <0x078b8000 0x600>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 522 spi-max-frequency = <50000000>; 523 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 524 <&gcc GCC_BLSP1_AHB_CLK>; 525 clock-names = "core", "iface"; 526 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 527 dma-names = "tx", "rx"; 528 status = "disabled"; 529 }; 530 531 blsp1_i2c4: i2c@78b9000 { 532 compatible = "qcom,i2c-qup-v2.2.1"; 533 reg = <0x078b9000 0x600>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 538 <&gcc GCC_BLSP1_AHB_CLK>; 539 clock-names = "core", "iface"; 540 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 541 assigned-clock-rates = <50000000>; 542 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 543 dma-names = "tx", "rx"; 544 status = "disabled"; 545 }; 546 547 blsp1_spi4: spi@78b9000 { 548 compatible = "qcom,spi-qup-v2.2.1"; 549 reg = <0x078b9000 0x600>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 554 <&gcc GCC_BLSP1_AHB_CLK>; 555 clock-names = "core", "iface"; 556 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 557 dma-names = "tx", "rx"; 558 status = "disabled"; 559 }; 560 561 usb_0_qusbphy: phy@7b000 { 562 compatible = "qcom,ipq9574-qusb2-phy"; 563 reg = <0x0007b000 0x180>; 564 #phy-cells = <0>; 565 566 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 567 <&xo_board_clk>; 568 clock-names = "cfg_ahb", 569 "ref"; 570 571 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 572 status = "disabled"; 573 }; 574 575 usb_0_qmpphy: phy@7d000 { 576 compatible = "qcom,ipq9574-qmp-usb3-phy"; 577 reg = <0x0007d000 0xa00>; 578 #phy-cells = <0>; 579 580 clocks = <&gcc GCC_USB0_AUX_CLK>, 581 <&xo_board_clk>, 582 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 583 <&gcc GCC_USB0_PIPE_CLK>; 584 clock-names = "aux", 585 "ref", 586 "cfg_ahb", 587 "pipe"; 588 589 resets = <&gcc GCC_USB0_PHY_BCR>, 590 <&gcc GCC_USB3PHY_0_PHY_BCR>; 591 reset-names = "phy", 592 "phy_phy"; 593 594 #clock-cells = <0>; 595 clock-output-names = "usb0_pipe_clk"; 596 597 status = "disabled"; 598 }; 599 600 usb3: usb@8af8800 { 601 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 602 reg = <0x08af8800 0x400>; 603 #address-cells = <1>; 604 #size-cells = <1>; 605 ranges; 606 607 clocks = <&gcc GCC_SNOC_USB_CLK>, 608 <&gcc GCC_USB0_MASTER_CLK>, 609 <&gcc GCC_ANOC_USB_AXI_CLK>, 610 <&gcc GCC_USB0_SLEEP_CLK>, 611 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 612 613 clock-names = "cfg_noc", 614 "core", 615 "iface", 616 "sleep", 617 "mock_utmi"; 618 619 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 620 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 621 assigned-clock-rates = <200000000>, 622 <24000000>; 623 624 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "pwr_event"; 626 627 resets = <&gcc GCC_USB_BCR>; 628 status = "disabled"; 629 630 usb_0_dwc3: usb@8a00000 { 631 compatible = "snps,dwc3"; 632 reg = <0x8a00000 0xcd00>; 633 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 634 clock-names = "ref"; 635 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 636 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 637 phy-names = "usb2-phy", "usb3-phy"; 638 tx-fifo-resize; 639 snps,is-utmi-l1-suspend; 640 snps,hird-threshold = /bits/ 8 <0x0>; 641 snps,dis_u2_susphy_quirk; 642 snps,dis_u3_susphy_quirk; 643 }; 644 }; 645 646 intc: interrupt-controller@b000000 { 647 compatible = "qcom,msm-qgic2"; 648 reg = <0x0b000000 0x1000>, /* GICD */ 649 <0x0b002000 0x2000>, /* GICC */ 650 <0x0b001000 0x1000>, /* GICH */ 651 <0x0b004000 0x2000>; /* GICV */ 652 #address-cells = <1>; 653 #size-cells = <1>; 654 interrupt-controller; 655 #interrupt-cells = <3>; 656 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 657 ranges = <0 0x0b00c000 0x3000>; 658 659 v2m0: v2m@0 { 660 compatible = "arm,gic-v2m-frame"; 661 reg = <0x00000000 0xffd>; 662 msi-controller; 663 }; 664 665 v2m1: v2m@1000 { 666 compatible = "arm,gic-v2m-frame"; 667 reg = <0x00001000 0xffd>; 668 msi-controller; 669 }; 670 671 v2m2: v2m@2000 { 672 compatible = "arm,gic-v2m-frame"; 673 reg = <0x00002000 0xffd>; 674 msi-controller; 675 }; 676 }; 677 678 watchdog: watchdog@b017000 { 679 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 680 reg = <0x0b017000 0x1000>; 681 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 682 clocks = <&sleep_clk>; 683 timeout-sec = <30>; 684 }; 685 686 apcs_glb: mailbox@b111000 { 687 compatible = "qcom,ipq9574-apcs-apps-global", 688 "qcom,ipq6018-apcs-apps-global"; 689 reg = <0x0b111000 0x1000>; 690 #clock-cells = <1>; 691 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 692 clock-names = "pll", "xo", "gpll0"; 693 #mbox-cells = <1>; 694 }; 695 696 a73pll: clock@b116000 { 697 compatible = "qcom,ipq9574-a73pll"; 698 reg = <0x0b116000 0x40>; 699 #clock-cells = <0>; 700 clocks = <&xo_board_clk>; 701 clock-names = "xo"; 702 }; 703 704 timer@b120000 { 705 compatible = "arm,armv7-timer-mem"; 706 reg = <0x0b120000 0x1000>; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 ranges; 710 711 frame@b120000 { 712 reg = <0x0b121000 0x1000>, 713 <0x0b122000 0x1000>; 714 frame-number = <0>; 715 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 717 }; 718 719 frame@b123000 { 720 reg = <0x0b123000 0x1000>; 721 frame-number = <1>; 722 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 723 status = "disabled"; 724 }; 725 726 frame@b124000 { 727 reg = <0x0b124000 0x1000>; 728 frame-number = <2>; 729 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 730 status = "disabled"; 731 }; 732 733 frame@b125000 { 734 reg = <0x0b125000 0x1000>; 735 frame-number = <3>; 736 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 737 status = "disabled"; 738 }; 739 740 frame@b126000 { 741 reg = <0x0b126000 0x1000>; 742 frame-number = <4>; 743 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 744 status = "disabled"; 745 }; 746 747 frame@b127000 { 748 reg = <0x0b127000 0x1000>; 749 frame-number = <5>; 750 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 751 status = "disabled"; 752 }; 753 754 frame@b128000 { 755 reg = <0x0b128000 0x1000>; 756 frame-number = <6>; 757 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 758 status = "disabled"; 759 }; 760 }; 761 }; 762 763 thermal-zones { 764 nss-top-thermal { 765 thermal-sensors = <&tsens 3>; 766 767 trips { 768 nss-top-critical { 769 temperature = <125000>; 770 hysteresis = <1000>; 771 type = "critical"; 772 }; 773 }; 774 }; 775 776 ubi-0-thermal { 777 thermal-sensors = <&tsens 4>; 778 779 trips { 780 ubi_0-critical { 781 temperature = <125000>; 782 hysteresis = <1000>; 783 type = "critical"; 784 }; 785 }; 786 }; 787 788 ubi-1-thermal { 789 thermal-sensors = <&tsens 5>; 790 791 trips { 792 ubi_1-critical { 793 temperature = <125000>; 794 hysteresis = <1000>; 795 type = "critical"; 796 }; 797 }; 798 }; 799 800 ubi-2-thermal { 801 thermal-sensors = <&tsens 6>; 802 803 trips { 804 ubi_2-critical { 805 temperature = <125000>; 806 hysteresis = <1000>; 807 type = "critical"; 808 }; 809 }; 810 }; 811 812 ubi-3-thermal { 813 thermal-sensors = <&tsens 7>; 814 815 trips { 816 ubi_3-critical { 817 temperature = <125000>; 818 hysteresis = <1000>; 819 type = "critical"; 820 }; 821 }; 822 }; 823 824 cpuss0-thermal { 825 thermal-sensors = <&tsens 8>; 826 827 trips { 828 cpu-critical { 829 temperature = <125000>; 830 hysteresis = <1000>; 831 type = "critical"; 832 }; 833 }; 834 }; 835 836 cpuss1-thermal { 837 thermal-sensors = <&tsens 9>; 838 839 trips { 840 cpu-critical { 841 temperature = <125000>; 842 hysteresis = <1000>; 843 type = "critical"; 844 }; 845 }; 846 }; 847 848 cpu0-thermal { 849 thermal-sensors = <&tsens 10>; 850 851 trips { 852 cpu0_crit: cpu-critical { 853 temperature = <120000>; 854 hysteresis = <10000>; 855 type = "critical"; 856 }; 857 858 cpu0_alert: cpu-passive { 859 temperature = <110000>; 860 hysteresis = <1000>; 861 type = "passive"; 862 }; 863 }; 864 865 cooling-maps { 866 map0 { 867 trip = <&cpu0_alert>; 868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 872 }; 873 }; 874 }; 875 876 cpu1-thermal { 877 thermal-sensors = <&tsens 11>; 878 879 trips { 880 cpu1_crit: cpu-critical { 881 temperature = <120000>; 882 hysteresis = <10000>; 883 type = "critical"; 884 }; 885 886 cpu1_alert: cpu-passive { 887 temperature = <110000>; 888 hysteresis = <1000>; 889 type = "passive"; 890 }; 891 }; 892 893 cooling-maps { 894 map0 { 895 trip = <&cpu1_alert>; 896 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 897 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 898 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 899 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 900 }; 901 }; 902 }; 903 904 cpu2-thermal { 905 thermal-sensors = <&tsens 12>; 906 907 trips { 908 cpu2_crit: cpu-critical { 909 temperature = <120000>; 910 hysteresis = <10000>; 911 type = "critical"; 912 }; 913 914 cpu2_alert: cpu-passive { 915 temperature = <110000>; 916 hysteresis = <1000>; 917 type = "passive"; 918 }; 919 }; 920 921 cooling-maps { 922 map0 { 923 trip = <&cpu2_alert>; 924 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 925 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 926 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 927 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 928 }; 929 }; 930 }; 931 932 cpu3-thermal { 933 thermal-sensors = <&tsens 13>; 934 935 trips { 936 cpu3_crit: cpu-critical { 937 temperature = <120000>; 938 hysteresis = <10000>; 939 type = "critical"; 940 }; 941 942 cpu3_alert: cpu-passive { 943 temperature = <110000>; 944 hysteresis = <1000>; 945 type = "passive"; 946 }; 947 }; 948 949 cooling-maps { 950 map0 { 951 trip = <&cpu3_alert>; 952 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 953 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 954 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 955 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 956 }; 957 }; 958 }; 959 960 wcss-phyb-thermal { 961 thermal-sensors = <&tsens 14>; 962 963 trips { 964 wcss_phyb-critical { 965 temperature = <125000>; 966 hysteresis = <1000>; 967 type = "critical"; 968 }; 969 }; 970 }; 971 972 top-glue-thermal { 973 thermal-sensors = <&tsens 15>; 974 975 trips { 976 top_glue-critical { 977 temperature = <125000>; 978 hysteresis = <1000>; 979 type = "critical"; 980 }; 981 }; 982 }; 983 }; 984 985 timer { 986 compatible = "arm,armv8-timer"; 987 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 988 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 989 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 990 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 991 }; 992}; 993