1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,sm8350.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25#include <dt-bindings/interconnect/qcom,sm8350.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <38400000>; 40 clock-output-names = "xo_board"; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32764>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a55"; 57 reg = <0x0 0x0>; 58 clocks = <&cpufreq_hw 0>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a55"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&CPU_PD1>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 power-domains = <&CPU_PD2>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x300>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 power-domains = <&CPU_PD3>; 125 power-domain-names = "psci"; 126 #cooling-cells = <2>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a78"; 138 reg = <0x0 0x400>; 139 clocks = <&cpufreq_hw 1>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 power-domains = <&CPU_PD4>; 144 power-domain-names = "psci"; 145 #cooling-cells = <2>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a78"; 157 reg = <0x0 0x500>; 158 clocks = <&cpufreq_hw 1>; 159 enable-method = "psci"; 160 next-level-cache = <&L2_500>; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 power-domains = <&CPU_PD5>; 163 power-domain-names = "psci"; 164 #cooling-cells = <2>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a78"; 176 reg = <0x0 0x600>; 177 clocks = <&cpufreq_hw 1>; 178 enable-method = "psci"; 179 next-level-cache = <&L2_600>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 power-domains = <&CPU_PD6>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-x1"; 195 reg = <0x0 0x700>; 196 clocks = <&cpufreq_hw 2>; 197 enable-method = "psci"; 198 next-level-cache = <&L2_700>; 199 qcom,freq-domain = <&cpufreq_hw 2>; 200 power-domains = <&CPU_PD7>; 201 power-domain-names = "psci"; 202 #cooling-cells = <2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <360>; 255 exit-latency-us = <531>; 256 min-residency-us = <3934>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <702>; 265 exit-latency-us = <1061>; 266 min-residency-us = <4488>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <2752>; 276 exit-latency-us = <3048>; 277 min-residency-us = <6118>; 278 }; 279 280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8350", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 #reset-cells = <1>; 295 }; 296 }; 297 298 memory@80000000 { 299 device_type = "memory"; 300 /* We expect the bootloader to fill in the size */ 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 pmu-a55 { 305 compatible = "arm,cortex-a55-pmu"; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 307 }; 308 309 pmu-a78 { 310 compatible = "arm,cortex-a78-pmu"; 311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 312 }; 313 314 pmu-x1 { 315 compatible = "arm,cortex-x1-pmu"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 CPU_PD0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CPU_PD6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD>; 362 domain-idle-states = <&BIG_CPU_SLEEP_0>; 363 }; 364 365 CPU_PD7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD>; 368 domain-idle-states = <&BIG_CPU_SLEEP_0>; 369 }; 370 371 CLUSTER_PD: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup100mhz { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 qup_opp_table_120mhz: opp-table-qup120mhz { 397 compatible = "operating-points-v2"; 398 399 opp-50000000 { 400 opp-hz = /bits/ 64 <50000000>; 401 required-opps = <&rpmhpd_opp_min_svs>; 402 }; 403 404 opp-75000000 { 405 opp-hz = /bits/ 64 <75000000>; 406 required-opps = <&rpmhpd_opp_low_svs>; 407 }; 408 409 opp-120000000 { 410 opp-hz = /bits/ 64 <120000000>; 411 required-opps = <&rpmhpd_opp_svs>; 412 }; 413 }; 414 415 reserved_memory: reserved-memory { 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges; 419 420 hyp_mem: memory@80000000 { 421 reg = <0x0 0x80000000 0x0 0x600000>; 422 no-map; 423 }; 424 425 xbl_aop_mem: memory@80700000 { 426 no-map; 427 reg = <0x0 0x80700000 0x0 0x160000>; 428 }; 429 430 cmd_db: memory@80860000 { 431 compatible = "qcom,cmd-db"; 432 reg = <0x0 0x80860000 0x0 0x20000>; 433 no-map; 434 }; 435 436 reserved_xbl_uefi_log: memory@80880000 { 437 reg = <0x0 0x80880000 0x0 0x14000>; 438 no-map; 439 }; 440 441 smem@80900000 { 442 compatible = "qcom,smem"; 443 reg = <0x0 0x80900000 0x0 0x200000>; 444 hwlocks = <&tcsr_mutex 3>; 445 no-map; 446 }; 447 448 cpucp_fw_mem: memory@80b00000 { 449 reg = <0x0 0x80b00000 0x0 0x100000>; 450 no-map; 451 }; 452 453 cdsp_secure_heap: memory@80c00000 { 454 reg = <0x0 0x80c00000 0x0 0x4600000>; 455 no-map; 456 }; 457 458 pil_camera_mem: memory@85200000 { 459 reg = <0x0 0x85200000 0x0 0x500000>; 460 no-map; 461 }; 462 463 pil_video_mem: memory@85700000 { 464 reg = <0x0 0x85700000 0x0 0x500000>; 465 no-map; 466 }; 467 468 pil_cvp_mem: memory@85c00000 { 469 reg = <0x0 0x85c00000 0x0 0x500000>; 470 no-map; 471 }; 472 473 pil_adsp_mem: memory@86100000 { 474 reg = <0x0 0x86100000 0x0 0x2100000>; 475 no-map; 476 }; 477 478 pil_slpi_mem: memory@88200000 { 479 reg = <0x0 0x88200000 0x0 0x1500000>; 480 no-map; 481 }; 482 483 pil_cdsp_mem: memory@89700000 { 484 reg = <0x0 0x89700000 0x0 0x1e00000>; 485 no-map; 486 }; 487 488 pil_ipa_fw_mem: memory@8b500000 { 489 reg = <0x0 0x8b500000 0x0 0x10000>; 490 no-map; 491 }; 492 493 pil_ipa_gsi_mem: memory@8b510000 { 494 reg = <0x0 0x8b510000 0x0 0xa000>; 495 no-map; 496 }; 497 498 pil_gpu_mem: memory@8b51a000 { 499 reg = <0x0 0x8b51a000 0x0 0x2000>; 500 no-map; 501 }; 502 503 pil_spss_mem: memory@8b600000 { 504 reg = <0x0 0x8b600000 0x0 0x100000>; 505 no-map; 506 }; 507 508 pil_modem_mem: memory@8b800000 { 509 reg = <0x0 0x8b800000 0x0 0x10000000>; 510 no-map; 511 }; 512 513 rmtfs_mem: memory@9b800000 { 514 compatible = "qcom,rmtfs-mem"; 515 reg = <0x0 0x9b800000 0x0 0x280000>; 516 no-map; 517 518 qcom,client-id = <1>; 519 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 520 }; 521 522 hyp_reserved_mem: memory@d0000000 { 523 reg = <0x0 0xd0000000 0x0 0x800000>; 524 no-map; 525 }; 526 527 pil_trustedvm_mem: memory@d0800000 { 528 reg = <0x0 0xd0800000 0x0 0x76f7000>; 529 no-map; 530 }; 531 532 qrtr_shbuf: memory@d7ef7000 { 533 reg = <0x0 0xd7ef7000 0x0 0x9000>; 534 no-map; 535 }; 536 537 chan0_shbuf: memory@d7f00000 { 538 reg = <0x0 0xd7f00000 0x0 0x80000>; 539 no-map; 540 }; 541 542 chan1_shbuf: memory@d7f80000 { 543 reg = <0x0 0xd7f80000 0x0 0x80000>; 544 no-map; 545 }; 546 547 removed_mem: memory@d8800000 { 548 reg = <0x0 0xd8800000 0x0 0x6800000>; 549 no-map; 550 }; 551 }; 552 553 smp2p-adsp { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <443>, <429>; 556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 557 IPCC_MPROC_SIGNAL_SMP2P 558 IRQ_TYPE_EDGE_RISING>; 559 mboxes = <&ipcc IPCC_CLIENT_LPASS 560 IPCC_MPROC_SIGNAL_SMP2P>; 561 562 qcom,local-pid = <0>; 563 qcom,remote-pid = <2>; 564 565 smp2p_adsp_out: master-kernel { 566 qcom,entry-name = "master-kernel"; 567 #qcom,smem-state-cells = <1>; 568 }; 569 570 smp2p_adsp_in: slave-kernel { 571 qcom,entry-name = "slave-kernel"; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 smp2p-cdsp { 578 compatible = "qcom,smp2p"; 579 qcom,smem = <94>, <432>; 580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 581 IPCC_MPROC_SIGNAL_SMP2P 582 IRQ_TYPE_EDGE_RISING>; 583 mboxes = <&ipcc IPCC_CLIENT_CDSP 584 IPCC_MPROC_SIGNAL_SMP2P>; 585 586 qcom,local-pid = <0>; 587 qcom,remote-pid = <5>; 588 589 smp2p_cdsp_out: master-kernel { 590 qcom,entry-name = "master-kernel"; 591 #qcom,smem-state-cells = <1>; 592 }; 593 594 smp2p_cdsp_in: slave-kernel { 595 qcom,entry-name = "slave-kernel"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 }; 600 601 smp2p-modem { 602 compatible = "qcom,smp2p"; 603 qcom,smem = <435>, <428>; 604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 605 IPCC_MPROC_SIGNAL_SMP2P 606 IRQ_TYPE_EDGE_RISING>; 607 mboxes = <&ipcc IPCC_CLIENT_MPSS 608 IPCC_MPROC_SIGNAL_SMP2P>; 609 610 qcom,local-pid = <0>; 611 qcom,remote-pid = <1>; 612 613 smp2p_modem_out: master-kernel { 614 qcom,entry-name = "master-kernel"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 smp2p_modem_in: slave-kernel { 619 qcom,entry-name = "slave-kernel"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 ipa_smp2p_out: ipa-ap-to-modem { 625 qcom,entry-name = "ipa"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 ipa_smp2p_in: ipa-modem-to-ap { 630 qcom,entry-name = "ipa"; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-slpi { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <481>, <430>; 639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 640 IPCC_MPROC_SIGNAL_SMP2P 641 IRQ_TYPE_EDGE_RISING>; 642 mboxes = <&ipcc IPCC_CLIENT_SLPI 643 IPCC_MPROC_SIGNAL_SMP2P>; 644 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <3>; 647 648 smp2p_slpi_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_slpi_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 soc: soc@0 { 661 #address-cells = <2>; 662 #size-cells = <2>; 663 ranges = <0 0 0 0 0x10 0>; 664 dma-ranges = <0 0 0 0 0x10 0>; 665 compatible = "simple-bus"; 666 667 gcc: clock-controller@100000 { 668 compatible = "qcom,gcc-sm8350"; 669 reg = <0x0 0x00100000 0x0 0x1f0000>; 670 #clock-cells = <1>; 671 #reset-cells = <1>; 672 #power-domain-cells = <1>; 673 clock-names = "bi_tcxo", 674 "sleep_clk", 675 "pcie_0_pipe_clk", 676 "pcie_1_pipe_clk", 677 "ufs_card_rx_symbol_0_clk", 678 "ufs_card_rx_symbol_1_clk", 679 "ufs_card_tx_symbol_0_clk", 680 "ufs_phy_rx_symbol_0_clk", 681 "ufs_phy_rx_symbol_1_clk", 682 "ufs_phy_tx_symbol_0_clk", 683 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 684 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 685 clocks = <&rpmhcc RPMH_CXO_CLK>, 686 <&sleep_clk>, 687 <&pcie0_phy>, 688 <&pcie1_phy>, 689 <0>, 690 <0>, 691 <0>, 692 <&ufs_mem_phy 0>, 693 <&ufs_mem_phy 1>, 694 <&ufs_mem_phy 2>, 695 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 696 <0>; 697 }; 698 699 ipcc: mailbox@408000 { 700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 701 reg = <0 0x00408000 0 0x1000>; 702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-controller; 704 #interrupt-cells = <3>; 705 #mbox-cells = <2>; 706 }; 707 708 gpi_dma2: dma-controller@800000 { 709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 710 reg = <0 0x00800000 0 0x60000>; 711 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 723 dma-channels = <12>; 724 dma-channel-mask = <0xff>; 725 iommus = <&apps_smmu 0x5f6 0x0>; 726 #dma-cells = <3>; 727 status = "disabled"; 728 }; 729 730 qupv3_id_2: geniqup@8c0000 { 731 compatible = "qcom,geni-se-qup"; 732 reg = <0x0 0x008c0000 0x0 0x6000>; 733 clock-names = "m-ahb", "s-ahb"; 734 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 735 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 736 iommus = <&apps_smmu 0x5e3 0x0>; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges; 740 status = "disabled"; 741 742 i2c14: i2c@880000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00880000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c14_default>; 749 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 750 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 751 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi14: spi@880000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00880000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 763 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 764 power-domains = <&rpmhpd RPMHPD_CX>; 765 operating-points-v2 = <&qup_opp_table_120mhz>; 766 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 767 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 768 dma-names = "tx", "rx"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 i2c15: i2c@884000 { 775 compatible = "qcom,geni-i2c"; 776 reg = <0 0x00884000 0 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_i2c15_default>; 781 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 783 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 784 dma-names = "tx", "rx"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 spi15: spi@884000 { 791 compatible = "qcom,geni-spi"; 792 reg = <0 0x00884000 0 0x4000>; 793 clock-names = "se"; 794 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 795 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 796 power-domains = <&rpmhpd RPMHPD_CX>; 797 operating-points-v2 = <&qup_opp_table_120mhz>; 798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 799 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 800 dma-names = "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 i2c16: i2c@888000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0 0x00888000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c16_default>; 813 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 814 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 815 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi16: spi@888000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0 0x00888000 0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 827 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 828 power-domains = <&rpmhpd RPMHPD_CX>; 829 operating-points-v2 = <&qup_opp_table_100mhz>; 830 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 831 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c17: i2c@88c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0088c000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c17_default>; 845 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 846 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi17: spi@88c000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x0088c000 0 0x4000>; 857 clock-names = "se"; 858 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 859 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 860 power-domains = <&rpmhpd RPMHPD_CX>; 861 operating-points-v2 = <&qup_opp_table_100mhz>; 862 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 863 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 /* QUP no. 18 seems to be strictly SPI/UART-only */ 871 872 spi18: spi@890000 { 873 compatible = "qcom,geni-spi"; 874 reg = <0 0x00890000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 877 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd RPMHPD_CX>; 879 operating-points-v2 = <&qup_opp_table_100mhz>; 880 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 881 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 882 dma-names = "tx", "rx"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 status = "disabled"; 886 }; 887 888 uart18: serial@890000 { 889 compatible = "qcom,geni-uart"; 890 reg = <0 0x00890000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_uart18_default>; 895 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&rpmhpd RPMHPD_CX>; 897 operating-points-v2 = <&qup_opp_table_100mhz>; 898 status = "disabled"; 899 }; 900 901 i2c19: i2c@894000 { 902 compatible = "qcom,geni-i2c"; 903 reg = <0 0x00894000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_i2c19_default>; 908 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 909 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 910 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 911 dma-names = "tx", "rx"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 status = "disabled"; 915 }; 916 917 spi19: spi@894000 { 918 compatible = "qcom,geni-spi"; 919 reg = <0 0x00894000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd RPMHPD_CX>; 924 operating-points-v2 = <&qup_opp_table_100mhz>; 925 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 926 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 }; 933 934 gpi_dma0: dma-controller@900000 { 935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 936 reg = <0 0x00900000 0 0x60000>; 937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 949 dma-channels = <12>; 950 dma-channel-mask = <0x7e>; 951 iommus = <&apps_smmu 0x5b6 0x0>; 952 #dma-cells = <3>; 953 status = "disabled"; 954 }; 955 956 qupv3_id_0: geniqup@9c0000 { 957 compatible = "qcom,geni-se-qup"; 958 reg = <0x0 0x009c0000 0x0 0x6000>; 959 clock-names = "m-ahb", "s-ahb"; 960 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 961 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 962 iommus = <&apps_smmu 0x5a3 0>; 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges; 966 status = "disabled"; 967 968 i2c0: i2c@980000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0 0x00980000 0 0x4000>; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_i2c0_default>; 975 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 976 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 977 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 978 dma-names = "tx", "rx"; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 status = "disabled"; 982 }; 983 984 spi0: spi@980000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00980000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 990 power-domains = <&rpmhpd RPMHPD_CX>; 991 operating-points-v2 = <&qup_opp_table_100mhz>; 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 993 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c1: i2c@984000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00984000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c1_default>; 1007 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1009 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi1: spi@984000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00984000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022 power-domains = <&rpmhpd RPMHPD_CX>; 1023 operating-points-v2 = <&qup_opp_table_100mhz>; 1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1025 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c2: i2c@988000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00988000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c2_default>; 1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1040 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1041 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1042 dma-names = "tx", "rx"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 spi2: spi@988000 { 1049 compatible = "qcom,geni-spi"; 1050 reg = <0 0x00988000 0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1053 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1057 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 uart2: serial@98c000 { 1065 compatible = "qcom,geni-debug-uart"; 1066 reg = <0 0x0098c000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_uart3_default_state>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 status = "disabled"; 1075 }; 1076 1077 /* QUP no. 3 seems to be strictly SPI-only */ 1078 1079 spi3: spi@98c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0098c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1085 power-domains = <&rpmhpd RPMHPD_CX>; 1086 operating-points-v2 = <&qup_opp_table_100mhz>; 1087 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1088 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2c4: i2c@990000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00990000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_i2c4_default>; 1102 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1103 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi4: spi@990000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x00990000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1116 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1117 power-domains = <&rpmhpd RPMHPD_CX>; 1118 operating-points-v2 = <&qup_opp_table_100mhz>; 1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c5: i2c@994000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00994000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c5_default>; 1134 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1135 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1136 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi5: spi@994000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00994000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd RPMHPD_CX>; 1150 operating-points-v2 = <&qup_opp_table_100mhz>; 1151 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c6: i2c@998000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0 0x00998000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_i2c6_default>; 1166 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1167 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1168 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1169 dma-names = "tx", "rx"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 spi6: spi@998000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0 0x00998000 0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1180 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1181 power-domains = <&rpmhpd RPMHPD_CX>; 1182 operating-points-v2 = <&qup_opp_table_100mhz>; 1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 uart6: serial@998000 { 1192 compatible = "qcom,geni-uart"; 1193 reg = <0 0x00998000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_uart6_default>; 1198 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&rpmhpd RPMHPD_CX>; 1200 operating-points-v2 = <&qup_opp_table_100mhz>; 1201 status = "disabled"; 1202 }; 1203 1204 i2c7: i2c@99c000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x0099c000 0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c7_default>; 1211 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1212 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1213 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1214 dma-names = "tx", "rx"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 spi7: spi@99c000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0 0x0099c000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1225 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 operating-points-v2 = <&qup_opp_table_100mhz>; 1228 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1229 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 }; 1236 1237 gpi_dma1: dma-controller@a00000 { 1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1239 reg = <0 0x00a00000 0 0x60000>; 1240 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1252 dma-channels = <12>; 1253 dma-channel-mask = <0xff>; 1254 iommus = <&apps_smmu 0x56 0x0>; 1255 #dma-cells = <3>; 1256 status = "disabled"; 1257 }; 1258 1259 qupv3_id_1: geniqup@ac0000 { 1260 compatible = "qcom,geni-se-qup"; 1261 reg = <0x0 0x00ac0000 0x0 0x6000>; 1262 clock-names = "m-ahb", "s-ahb"; 1263 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1264 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1265 iommus = <&apps_smmu 0x43 0>; 1266 #address-cells = <2>; 1267 #size-cells = <2>; 1268 ranges; 1269 status = "disabled"; 1270 1271 i2c8: i2c@a80000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0 0x00a80000 0 0x4000>; 1274 clock-names = "se"; 1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_i2c8_default>; 1278 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1281 dma-names = "tx", "rx"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi8: spi@a80000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a80000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd RPMHPD_CX>; 1294 operating-points-v2 = <&qup_opp_table_120mhz>; 1295 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1297 dma-names = "tx", "rx"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 i2c9: i2c@a84000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a84000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c9_default>; 1310 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1312 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 spi9: spi@a84000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1325 power-domains = <&rpmhpd RPMHPD_CX>; 1326 operating-points-v2 = <&qup_opp_table_100mhz>; 1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1328 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1329 dma-names = "tx", "rx"; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 i2c10: i2c@a88000 { 1336 compatible = "qcom,geni-i2c"; 1337 reg = <0 0x00a88000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_i2c10_default>; 1342 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1343 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 spi10: spi@a88000 { 1352 compatible = "qcom,geni-spi"; 1353 reg = <0 0x00a88000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1356 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1357 power-domains = <&rpmhpd RPMHPD_CX>; 1358 operating-points-v2 = <&qup_opp_table_100mhz>; 1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1361 dma-names = "tx", "rx"; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 i2c11: i2c@a8c000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a8c000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c11_default>; 1374 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1376 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 spi11: spi@a8c000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a8c000 0 0x4000>; 1386 clock-names = "se"; 1387 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 power-domains = <&rpmhpd RPMHPD_CX>; 1390 operating-points-v2 = <&qup_opp_table_100mhz>; 1391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1392 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c12: i2c@a90000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0 0x00a90000 0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_i2c12_default>; 1406 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1407 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1408 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 spi12: spi@a90000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00a90000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1421 power-domains = <&rpmhpd RPMHPD_CX>; 1422 operating-points-v2 = <&qup_opp_table_100mhz>; 1423 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1424 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 i2c13: i2c@a94000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00a94000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_i2c13_default>; 1438 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1439 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1440 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1441 dma-names = "tx", "rx"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 spi13: spi@a94000 { 1448 compatible = "qcom,geni-spi"; 1449 reg = <0 0x00a94000 0 0x4000>; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1452 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1453 power-domains = <&rpmhpd RPMHPD_CX>; 1454 operating-points-v2 = <&qup_opp_table_100mhz>; 1455 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1456 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1457 dma-names = "tx", "rx"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 rng: rng@10d3000 { 1465 compatible = "qcom,prng-ee"; 1466 reg = <0 0x010d3000 0 0x1000>; 1467 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1468 clock-names = "core"; 1469 }; 1470 1471 config_noc: interconnect@1500000 { 1472 compatible = "qcom,sm8350-config-noc"; 1473 reg = <0 0x01500000 0 0xa580>; 1474 #interconnect-cells = <2>; 1475 qcom,bcm-voters = <&apps_bcm_voter>; 1476 }; 1477 1478 mc_virt: interconnect@1580000 { 1479 compatible = "qcom,sm8350-mc-virt"; 1480 reg = <0 0x01580000 0 0x1000>; 1481 #interconnect-cells = <2>; 1482 qcom,bcm-voters = <&apps_bcm_voter>; 1483 }; 1484 1485 system_noc: interconnect@1680000 { 1486 compatible = "qcom,sm8350-system-noc"; 1487 reg = <0 0x01680000 0 0x1c200>; 1488 #interconnect-cells = <2>; 1489 qcom,bcm-voters = <&apps_bcm_voter>; 1490 }; 1491 1492 aggre1_noc: interconnect@16e0000 { 1493 compatible = "qcom,sm8350-aggre1-noc"; 1494 reg = <0 0x016e0000 0 0x1f180>; 1495 #interconnect-cells = <2>; 1496 qcom,bcm-voters = <&apps_bcm_voter>; 1497 }; 1498 1499 aggre2_noc: interconnect@1700000 { 1500 compatible = "qcom,sm8350-aggre2-noc"; 1501 reg = <0 0x01700000 0 0x33000>; 1502 #interconnect-cells = <2>; 1503 qcom,bcm-voters = <&apps_bcm_voter>; 1504 }; 1505 1506 mmss_noc: interconnect@1740000 { 1507 compatible = "qcom,sm8350-mmss-noc"; 1508 reg = <0 0x01740000 0 0x1f080>; 1509 #interconnect-cells = <2>; 1510 qcom,bcm-voters = <&apps_bcm_voter>; 1511 }; 1512 1513 pcie0: pcie@1c00000 { 1514 compatible = "qcom,pcie-sm8350"; 1515 reg = <0 0x01c00000 0 0x3000>, 1516 <0 0x60000000 0 0xf1d>, 1517 <0 0x60000f20 0 0xa8>, 1518 <0 0x60001000 0 0x1000>, 1519 <0 0x60100000 0 0x100000>; 1520 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1521 device_type = "pci"; 1522 linux,pci-domain = <0>; 1523 bus-range = <0x00 0xff>; 1524 num-lanes = <1>; 1525 1526 #address-cells = <3>; 1527 #size-cells = <2>; 1528 1529 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1530 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1531 1532 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "msi0", 1541 "msi1", 1542 "msi2", 1543 "msi3", 1544 "msi4", 1545 "msi5", 1546 "msi6", 1547 "msi7"; 1548 #interrupt-cells = <1>; 1549 interrupt-map-mask = <0 0 0 0x7>; 1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1551 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1552 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1553 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1554 1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1556 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1557 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1558 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1559 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1560 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1561 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1562 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1563 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1564 clock-names = "aux", 1565 "cfg", 1566 "bus_master", 1567 "bus_slave", 1568 "slave_q2a", 1569 "tbu", 1570 "ddrss_sf_tbu", 1571 "aggre1", 1572 "aggre0"; 1573 1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1575 <0x100 &apps_smmu 0x1c01 0x1>; 1576 1577 resets = <&gcc GCC_PCIE_0_BCR>; 1578 reset-names = "pci"; 1579 1580 power-domains = <&gcc PCIE_0_GDSC>; 1581 1582 phys = <&pcie0_phy>; 1583 phy-names = "pciephy"; 1584 1585 status = "disabled"; 1586 1587 pcie@0 { 1588 device_type = "pci"; 1589 reg = <0x0 0x0 0x0 0x0 0x0>; 1590 bus-range = <0x01 0xff>; 1591 1592 #address-cells = <3>; 1593 #size-cells = <2>; 1594 ranges; 1595 }; 1596 }; 1597 1598 pcie0_phy: phy@1c06000 { 1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1600 reg = <0 0x01c06000 0 0x2000>; 1601 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1602 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1603 <&gcc GCC_PCIE_0_CLKREF_EN>, 1604 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1605 <&gcc GCC_PCIE_0_PIPE_CLK>; 1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1607 1608 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1609 reset-names = "phy"; 1610 1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1612 assigned-clock-rates = <100000000>; 1613 1614 #clock-cells = <0>; 1615 clock-output-names = "pcie_0_pipe_clk"; 1616 1617 #phy-cells = <0>; 1618 1619 status = "disabled"; 1620 }; 1621 1622 pcie1: pcie@1c08000 { 1623 compatible = "qcom,pcie-sm8350"; 1624 reg = <0 0x01c08000 0 0x3000>, 1625 <0 0x40000000 0 0xf1d>, 1626 <0 0x40000f20 0 0xa8>, 1627 <0 0x40001000 0 0x1000>, 1628 <0 0x40100000 0 0x100000>; 1629 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1630 device_type = "pci"; 1631 linux,pci-domain = <1>; 1632 bus-range = <0x00 0xff>; 1633 num-lanes = <2>; 1634 1635 #address-cells = <3>; 1636 #size-cells = <2>; 1637 1638 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1639 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1640 1641 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1649 interrupt-names = "msi0", 1650 "msi1", 1651 "msi2", 1652 "msi3", 1653 "msi4", 1654 "msi5", 1655 "msi6", 1656 "msi7"; 1657 #interrupt-cells = <1>; 1658 interrupt-map-mask = <0 0 0 0x7>; 1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1660 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1661 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1662 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1663 1664 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1665 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1666 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1667 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1668 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1669 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1670 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1671 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1672 clock-names = "aux", 1673 "cfg", 1674 "bus_master", 1675 "bus_slave", 1676 "slave_q2a", 1677 "tbu", 1678 "ddrss_sf_tbu", 1679 "aggre1"; 1680 1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1682 <0x100 &apps_smmu 0x1c81 0x1>; 1683 1684 resets = <&gcc GCC_PCIE_1_BCR>; 1685 reset-names = "pci"; 1686 1687 power-domains = <&gcc PCIE_1_GDSC>; 1688 1689 phys = <&pcie1_phy>; 1690 phy-names = "pciephy"; 1691 1692 status = "disabled"; 1693 1694 pcie@0 { 1695 device_type = "pci"; 1696 reg = <0x0 0x0 0x0 0x0 0x0>; 1697 bus-range = <0x01 0xff>; 1698 1699 #address-cells = <3>; 1700 #size-cells = <2>; 1701 ranges; 1702 }; 1703 }; 1704 1705 pcie1_phy: phy@1c0e000 { 1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1707 reg = <0 0x01c0e000 0 0x2000>; 1708 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1709 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1710 <&gcc GCC_PCIE_1_CLKREF_EN>, 1711 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1712 <&gcc GCC_PCIE_1_PIPE_CLK>; 1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1714 1715 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1716 reset-names = "phy"; 1717 1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1719 assigned-clock-rates = <100000000>; 1720 1721 #clock-cells = <0>; 1722 clock-output-names = "pcie_1_pipe_clk"; 1723 1724 #phy-cells = <0>; 1725 1726 status = "disabled"; 1727 }; 1728 1729 ufs_mem_hc: ufshc@1d84000 { 1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1731 "jedec,ufs-2.0"; 1732 reg = <0 0x01d84000 0 0x3000>; 1733 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1734 phys = <&ufs_mem_phy>; 1735 phy-names = "ufsphy"; 1736 lanes-per-direction = <2>; 1737 #reset-cells = <1>; 1738 resets = <&gcc GCC_UFS_PHY_BCR>; 1739 reset-names = "rst"; 1740 1741 power-domains = <&gcc UFS_PHY_GDSC>; 1742 1743 iommus = <&apps_smmu 0xe0 0x0>; 1744 dma-coherent; 1745 1746 clock-names = 1747 "core_clk", 1748 "bus_aggr_clk", 1749 "iface_clk", 1750 "core_clk_unipro", 1751 "ref_clk", 1752 "tx_lane0_sync_clk", 1753 "rx_lane0_sync_clk", 1754 "rx_lane1_sync_clk"; 1755 clocks = 1756 <&gcc GCC_UFS_PHY_AXI_CLK>, 1757 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1758 <&gcc GCC_UFS_PHY_AHB_CLK>, 1759 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1760 <&rpmhcc RPMH_CXO_CLK>, 1761 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1762 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1763 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1764 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1767 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "ufs-ddr", "cpu-ufs"; 1769 freq-table-hz = 1770 <75000000 300000000>, 1771 <0 0>, 1772 <0 0>, 1773 <75000000 300000000>, 1774 <0 0>, 1775 <0 0>, 1776 <0 0>, 1777 <0 0>; 1778 status = "disabled"; 1779 }; 1780 1781 ufs_mem_phy: phy@1d87000 { 1782 compatible = "qcom,sm8350-qmp-ufs-phy"; 1783 reg = <0 0x01d87000 0 0x1000>; 1784 1785 clocks = <&rpmhcc RPMH_CXO_CLK>, 1786 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1787 <&gcc GCC_UFS_1_CLKREF_EN>; 1788 clock-names = "ref", 1789 "ref_aux", 1790 "qref"; 1791 1792 power-domains = <&gcc UFS_PHY_GDSC>; 1793 1794 resets = <&ufs_mem_hc 0>; 1795 reset-names = "ufsphy"; 1796 1797 #clock-cells = <1>; 1798 #phy-cells = <0>; 1799 1800 status = "disabled"; 1801 }; 1802 1803 cryptobam: dma-controller@1dc4000 { 1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1805 reg = <0 0x01dc4000 0 0x24000>; 1806 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1807 #dma-cells = <1>; 1808 qcom,ee = <0>; 1809 qcom,num-ees = <4>; 1810 num-channels = <16>; 1811 qcom,controlled-remotely; 1812 iommus = <&apps_smmu 0x594 0x0011>, 1813 <&apps_smmu 0x596 0x0011>; 1814 }; 1815 1816 crypto: crypto@1dfa000 { 1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1818 reg = <0 0x01dfa000 0 0x6000>; 1819 dmas = <&cryptobam 4>, <&cryptobam 5>; 1820 dma-names = "rx", "tx"; 1821 iommus = <&apps_smmu 0x594 0x0011>, 1822 <&apps_smmu 0x596 0x0011>; 1823 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1824 interconnect-names = "memory"; 1825 }; 1826 1827 ipa: ipa@1e40000 { 1828 compatible = "qcom,sm8350-ipa"; 1829 1830 iommus = <&apps_smmu 0x5c0 0x0>, 1831 <&apps_smmu 0x5c2 0x0>; 1832 reg = <0 0x01e40000 0 0x8000>, 1833 <0 0x01e50000 0 0x4b20>, 1834 <0 0x01e04000 0 0x23000>; 1835 reg-names = "ipa-reg", 1836 "ipa-shared", 1837 "gsi"; 1838 1839 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1840 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1841 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1842 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1843 interrupt-names = "ipa", 1844 "gsi", 1845 "ipa-clock-query", 1846 "ipa-setup-ready"; 1847 1848 clocks = <&rpmhcc RPMH_IPA_CLK>; 1849 clock-names = "core"; 1850 1851 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1853 interconnect-names = "memory", 1854 "config"; 1855 1856 qcom,qmp = <&aoss_qmp>; 1857 1858 qcom,smem-states = <&ipa_smp2p_out 0>, 1859 <&ipa_smp2p_out 1>; 1860 qcom,smem-state-names = "ipa-clock-enabled-valid", 1861 "ipa-clock-enabled"; 1862 1863 status = "disabled"; 1864 }; 1865 1866 tcsr_mutex: hwlock@1f40000 { 1867 compatible = "qcom,tcsr-mutex"; 1868 reg = <0x0 0x01f40000 0x0 0x40000>; 1869 #hwlock-cells = <1>; 1870 }; 1871 1872 tcsr: syscon@1fc0000 { 1873 compatible = "qcom,sm8350-tcsr", "syscon"; 1874 reg = <0x0 0x1fc0000 0x0 0x30000>; 1875 }; 1876 1877 adsp: remoteproc@3000000 { 1878 compatible = "qcom,sm8350-adsp-pas"; 1879 reg = <0x0 0x03000000 0x0 0x10000>; 1880 1881 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1882 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1883 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1884 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1885 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1886 interrupt-names = "wdog", "fatal", "ready", 1887 "handover", "stop-ack"; 1888 1889 clocks = <&rpmhcc RPMH_CXO_CLK>; 1890 clock-names = "xo"; 1891 1892 power-domains = <&rpmhpd RPMHPD_LCX>, 1893 <&rpmhpd RPMHPD_LMX>; 1894 power-domain-names = "lcx", "lmx"; 1895 1896 memory-region = <&pil_adsp_mem>; 1897 1898 qcom,qmp = <&aoss_qmp>; 1899 1900 qcom,smem-states = <&smp2p_adsp_out 0>; 1901 qcom,smem-state-names = "stop"; 1902 1903 status = "disabled"; 1904 1905 glink-edge { 1906 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1907 IPCC_MPROC_SIGNAL_GLINK_QMP 1908 IRQ_TYPE_EDGE_RISING>; 1909 mboxes = <&ipcc IPCC_CLIENT_LPASS 1910 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1911 1912 label = "lpass"; 1913 qcom,remote-pid = <2>; 1914 1915 apr { 1916 compatible = "qcom,apr-v2"; 1917 qcom,glink-channels = "apr_audio_svc"; 1918 qcom,domain = <APR_DOMAIN_ADSP>; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 1922 service@3 { 1923 reg = <APR_SVC_ADSP_CORE>; 1924 compatible = "qcom,q6core"; 1925 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1926 }; 1927 1928 q6afe: service@4 { 1929 compatible = "qcom,q6afe"; 1930 reg = <APR_SVC_AFE>; 1931 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1932 1933 q6afedai: dais { 1934 compatible = "qcom,q6afe-dais"; 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 #sound-dai-cells = <1>; 1938 }; 1939 1940 q6afecc: clock-controller { 1941 compatible = "qcom,q6afe-clocks"; 1942 #clock-cells = <2>; 1943 }; 1944 }; 1945 1946 q6asm: service@7 { 1947 compatible = "qcom,q6asm"; 1948 reg = <APR_SVC_ASM>; 1949 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1950 1951 q6asmdai: dais { 1952 compatible = "qcom,q6asm-dais"; 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 #sound-dai-cells = <1>; 1956 iommus = <&apps_smmu 0x1801 0x0>; 1957 1958 dai@0 { 1959 reg = <0>; 1960 }; 1961 1962 dai@1 { 1963 reg = <1>; 1964 }; 1965 1966 dai@2 { 1967 reg = <2>; 1968 }; 1969 }; 1970 }; 1971 1972 q6adm: service@8 { 1973 compatible = "qcom,q6adm"; 1974 reg = <APR_SVC_ADM>; 1975 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1976 1977 q6routing: routing { 1978 compatible = "qcom,q6adm-routing"; 1979 #sound-dai-cells = <0>; 1980 }; 1981 }; 1982 }; 1983 1984 fastrpc { 1985 compatible = "qcom,fastrpc"; 1986 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1987 label = "adsp"; 1988 qcom,non-secure-domain; 1989 #address-cells = <1>; 1990 #size-cells = <0>; 1991 1992 compute-cb@3 { 1993 compatible = "qcom,fastrpc-compute-cb"; 1994 reg = <3>; 1995 iommus = <&apps_smmu 0x1803 0x0>; 1996 }; 1997 1998 compute-cb@4 { 1999 compatible = "qcom,fastrpc-compute-cb"; 2000 reg = <4>; 2001 iommus = <&apps_smmu 0x1804 0x0>; 2002 }; 2003 2004 compute-cb@5 { 2005 compatible = "qcom,fastrpc-compute-cb"; 2006 reg = <5>; 2007 iommus = <&apps_smmu 0x1805 0x0>; 2008 }; 2009 }; 2010 }; 2011 }; 2012 2013 lpass_tlmm: pinctrl@33c0000 { 2014 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 2015 reg = <0 0x033c0000 0 0x20000>, 2016 <0 0x03550000 0 0x10000>; 2017 2018 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2019 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2020 clock-names = "core", "audio"; 2021 2022 gpio-controller; 2023 #gpio-cells = <2>; 2024 gpio-ranges = <&lpass_tlmm 0 0 15>; 2025 }; 2026 2027 gpu: gpu@3d00000 { 2028 compatible = "qcom,adreno-660.1", "qcom,adreno"; 2029 2030 reg = <0 0x03d00000 0 0x40000>, 2031 <0 0x03d9e000 0 0x1000>, 2032 <0 0x03d61000 0 0x800>; 2033 reg-names = "kgsl_3d0_reg_memory", 2034 "cx_mem", 2035 "cx_dbgc"; 2036 2037 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2038 2039 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 2040 2041 operating-points-v2 = <&gpu_opp_table>; 2042 2043 qcom,gmu = <&gmu>; 2044 #cooling-cells = <2>; 2045 2046 status = "disabled"; 2047 2048 zap-shader { 2049 memory-region = <&pil_gpu_mem>; 2050 }; 2051 2052 /* note: downstream checks gpu binning for 670 Mhz */ 2053 gpu_opp_table: opp-table { 2054 compatible = "operating-points-v2"; 2055 2056 opp-840000000 { 2057 opp-hz = /bits/ 64 <840000000>; 2058 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2059 }; 2060 2061 opp-778000000 { 2062 opp-hz = /bits/ 64 <778000000>; 2063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2064 }; 2065 2066 opp-738000000 { 2067 opp-hz = /bits/ 64 <738000000>; 2068 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2069 }; 2070 2071 opp-676000000 { 2072 opp-hz = /bits/ 64 <676000000>; 2073 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2074 }; 2075 2076 opp-608000000 { 2077 opp-hz = /bits/ 64 <608000000>; 2078 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2079 }; 2080 2081 opp-540000000 { 2082 opp-hz = /bits/ 64 <540000000>; 2083 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2084 }; 2085 2086 opp-491000000 { 2087 opp-hz = /bits/ 64 <491000000>; 2088 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2089 }; 2090 2091 opp-443000000 { 2092 opp-hz = /bits/ 64 <443000000>; 2093 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2094 }; 2095 2096 opp-379000000 { 2097 opp-hz = /bits/ 64 <379000000>; 2098 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 2099 }; 2100 2101 opp-315000000 { 2102 opp-hz = /bits/ 64 <315000000>; 2103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2104 }; 2105 }; 2106 }; 2107 2108 gmu: gmu@3d6a000 { 2109 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 2110 2111 reg = <0 0x03d6a000 0 0x34000>, 2112 <0 0x03de0000 0 0x10000>, 2113 <0 0x0b290000 0 0x10000>; 2114 reg-names = "gmu", "rscc", "gmu_pdc"; 2115 2116 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2118 interrupt-names = "hfi", "gmu"; 2119 2120 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2121 <&gpucc GPU_CC_CXO_CLK>, 2122 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2123 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2124 <&gpucc GPU_CC_AHB_CLK>, 2125 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2126 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2127 clock-names = "gmu", 2128 "cxo", 2129 "axi", 2130 "memnoc", 2131 "ahb", 2132 "hub", 2133 "smmu_vote"; 2134 2135 power-domains = <&gpucc GPU_CX_GDSC>, 2136 <&gpucc GPU_GX_GDSC>; 2137 power-domain-names = "cx", 2138 "gx"; 2139 2140 iommus = <&adreno_smmu 5 0x400>; 2141 2142 operating-points-v2 = <&gmu_opp_table>; 2143 2144 gmu_opp_table: opp-table { 2145 compatible = "operating-points-v2"; 2146 2147 opp-200000000 { 2148 opp-hz = /bits/ 64 <200000000>; 2149 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2150 }; 2151 }; 2152 }; 2153 2154 gpucc: clock-controller@3d90000 { 2155 compatible = "qcom,sm8350-gpucc"; 2156 reg = <0 0x03d90000 0 0x9000>; 2157 clocks = <&rpmhcc RPMH_CXO_CLK>, 2158 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2159 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2160 clock-names = "bi_tcxo", 2161 "gcc_gpu_gpll0_clk_src", 2162 "gcc_gpu_gpll0_div_clk_src"; 2163 #clock-cells = <1>; 2164 #reset-cells = <1>; 2165 #power-domain-cells = <1>; 2166 }; 2167 2168 adreno_smmu: iommu@3da0000 { 2169 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2170 "qcom,smmu-500", "arm,mmu-500"; 2171 reg = <0 0x03da0000 0 0x20000>; 2172 #iommu-cells = <2>; 2173 #global-interrupts = <2>; 2174 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2186 2187 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2188 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2189 <&gpucc GPU_CC_AHB_CLK>, 2190 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2191 <&gpucc GPU_CC_CX_GMU_CLK>, 2192 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2193 <&gpucc GPU_CC_HUB_AON_CLK>; 2194 clock-names = "bus", 2195 "iface", 2196 "ahb", 2197 "hlos1_vote_gpu_smmu", 2198 "cx_gmu", 2199 "hub_cx_int", 2200 "hub_aon"; 2201 2202 power-domains = <&gpucc GPU_CX_GDSC>; 2203 dma-coherent; 2204 }; 2205 2206 lpass_ag_noc: interconnect@3c40000 { 2207 compatible = "qcom,sm8350-lpass-ag-noc"; 2208 reg = <0 0x03c40000 0 0xf080>; 2209 #interconnect-cells = <2>; 2210 qcom,bcm-voters = <&apps_bcm_voter>; 2211 }; 2212 2213 mpss: remoteproc@4080000 { 2214 compatible = "qcom,sm8350-mpss-pas"; 2215 reg = <0x0 0x04080000 0x0 0x10000>; 2216 2217 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2218 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2219 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2220 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2221 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2222 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2223 interrupt-names = "wdog", "fatal", "ready", "handover", 2224 "stop-ack", "shutdown-ack"; 2225 2226 clocks = <&rpmhcc RPMH_CXO_CLK>; 2227 clock-names = "xo"; 2228 2229 power-domains = <&rpmhpd RPMHPD_CX>, 2230 <&rpmhpd RPMHPD_MSS>; 2231 power-domain-names = "cx", "mss"; 2232 2233 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2234 2235 memory-region = <&pil_modem_mem>; 2236 2237 qcom,qmp = <&aoss_qmp>; 2238 2239 qcom,smem-states = <&smp2p_modem_out 0>; 2240 qcom,smem-state-names = "stop"; 2241 2242 status = "disabled"; 2243 2244 glink-edge { 2245 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2246 IPCC_MPROC_SIGNAL_GLINK_QMP 2247 IRQ_TYPE_EDGE_RISING>; 2248 mboxes = <&ipcc IPCC_CLIENT_MPSS 2249 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2250 label = "modem"; 2251 qcom,remote-pid = <1>; 2252 }; 2253 }; 2254 2255 slpi: remoteproc@5c00000 { 2256 compatible = "qcom,sm8350-slpi-pas"; 2257 reg = <0 0x05c00000 0 0x4000>; 2258 2259 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2260 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2261 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2262 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2263 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2264 interrupt-names = "wdog", "fatal", "ready", 2265 "handover", "stop-ack"; 2266 2267 clocks = <&rpmhcc RPMH_CXO_CLK>; 2268 clock-names = "xo"; 2269 2270 power-domains = <&rpmhpd RPMHPD_LCX>, 2271 <&rpmhpd RPMHPD_LMX>; 2272 power-domain-names = "lcx", "lmx"; 2273 2274 memory-region = <&pil_slpi_mem>; 2275 2276 qcom,qmp = <&aoss_qmp>; 2277 2278 qcom,smem-states = <&smp2p_slpi_out 0>; 2279 qcom,smem-state-names = "stop"; 2280 2281 status = "disabled"; 2282 2283 glink-edge { 2284 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2285 IPCC_MPROC_SIGNAL_GLINK_QMP 2286 IRQ_TYPE_EDGE_RISING>; 2287 mboxes = <&ipcc IPCC_CLIENT_SLPI 2288 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2289 2290 label = "slpi"; 2291 qcom,remote-pid = <3>; 2292 2293 fastrpc { 2294 compatible = "qcom,fastrpc"; 2295 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2296 label = "sdsp"; 2297 qcom,non-secure-domain; 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 2301 compute-cb@1 { 2302 compatible = "qcom,fastrpc-compute-cb"; 2303 reg = <1>; 2304 iommus = <&apps_smmu 0x0541 0x0>; 2305 }; 2306 2307 compute-cb@2 { 2308 compatible = "qcom,fastrpc-compute-cb"; 2309 reg = <2>; 2310 iommus = <&apps_smmu 0x0542 0x0>; 2311 }; 2312 2313 compute-cb@3 { 2314 compatible = "qcom,fastrpc-compute-cb"; 2315 reg = <3>; 2316 iommus = <&apps_smmu 0x0543 0x0>; 2317 /* note: shared-cb = <4> in downstream */ 2318 }; 2319 }; 2320 }; 2321 }; 2322 2323 sdhc_2: mmc@8804000 { 2324 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2325 reg = <0 0x08804000 0 0x1000>; 2326 2327 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2329 interrupt-names = "hc_irq", "pwr_irq"; 2330 2331 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2332 <&gcc GCC_SDCC2_APPS_CLK>, 2333 <&rpmhcc RPMH_CXO_CLK>; 2334 clock-names = "iface", "core", "xo"; 2335 resets = <&gcc GCC_SDCC2_BCR>; 2336 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2338 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2339 iommus = <&apps_smmu 0x4a0 0x0>; 2340 power-domains = <&rpmhpd RPMHPD_CX>; 2341 operating-points-v2 = <&sdhc2_opp_table>; 2342 bus-width = <4>; 2343 dma-coherent; 2344 2345 status = "disabled"; 2346 2347 sdhc2_opp_table: opp-table { 2348 compatible = "operating-points-v2"; 2349 2350 opp-100000000 { 2351 opp-hz = /bits/ 64 <100000000>; 2352 required-opps = <&rpmhpd_opp_low_svs>; 2353 }; 2354 2355 opp-202000000 { 2356 opp-hz = /bits/ 64 <202000000>; 2357 required-opps = <&rpmhpd_opp_svs_l1>; 2358 }; 2359 }; 2360 }; 2361 2362 usb_1_hsphy: phy@88e3000 { 2363 compatible = "qcom,sm8350-usb-hs-phy", 2364 "qcom,usb-snps-hs-7nm-phy"; 2365 reg = <0 0x088e3000 0 0x400>; 2366 status = "disabled"; 2367 #phy-cells = <0>; 2368 2369 clocks = <&rpmhcc RPMH_CXO_CLK>; 2370 clock-names = "ref"; 2371 2372 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2373 }; 2374 2375 usb_2_hsphy: phy@88e4000 { 2376 compatible = "qcom,sm8250-usb-hs-phy", 2377 "qcom,usb-snps-hs-7nm-phy"; 2378 reg = <0 0x088e4000 0 0x400>; 2379 status = "disabled"; 2380 #phy-cells = <0>; 2381 2382 clocks = <&rpmhcc RPMH_CXO_CLK>; 2383 clock-names = "ref"; 2384 2385 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2386 }; 2387 2388 refgen: regulator@88e7000 { 2389 compatible = "qcom,sm8350-refgen-regulator", 2390 "qcom,sm8250-refgen-regulator"; 2391 reg = <0x0 0x088e7000 0x0 0x84>; 2392 }; 2393 2394 usb_1_qmpphy: phy@88e8000 { 2395 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2396 reg = <0 0x088e8000 0 0x3000>; 2397 2398 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2399 <&rpmhcc RPMH_CXO_CLK>, 2400 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2401 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2402 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2403 2404 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2405 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2406 reset-names = "phy", "common"; 2407 2408 #clock-cells = <1>; 2409 #phy-cells = <1>; 2410 2411 orientation-switch; 2412 2413 status = "disabled"; 2414 2415 ports { 2416 #address-cells = <1>; 2417 #size-cells = <0>; 2418 2419 port@0 { 2420 reg = <0>; 2421 2422 usb_1_qmpphy_out: endpoint { 2423 }; 2424 }; 2425 2426 port@1 { 2427 reg = <1>; 2428 2429 usb_1_qmpphy_usb_ss_in: endpoint { 2430 remote-endpoint = <&usb_1_dwc3_ss>; 2431 }; 2432 }; 2433 2434 port@2 { 2435 reg = <2>; 2436 2437 usb_1_qmpphy_dp_in: endpoint { 2438 remote-endpoint = <&mdss_dp_out>; 2439 }; 2440 }; 2441 }; 2442 }; 2443 2444 usb_2_qmpphy: phy@88eb000 { 2445 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2446 reg = <0 0x088eb000 0 0x2000>; 2447 status = "disabled"; 2448 2449 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2450 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2451 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2452 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2453 clock-names = "aux", 2454 "ref", 2455 "com_aux", 2456 "pipe"; 2457 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2458 #clock-cells = <0>; 2459 #phy-cells = <0>; 2460 2461 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2462 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2463 reset-names = "phy", 2464 "phy_phy"; 2465 }; 2466 2467 dc_noc: interconnect@90c0000 { 2468 compatible = "qcom,sm8350-dc-noc"; 2469 reg = <0 0x090c0000 0 0x4200>; 2470 #interconnect-cells = <2>; 2471 qcom,bcm-voters = <&apps_bcm_voter>; 2472 }; 2473 2474 gem_noc: interconnect@9100000 { 2475 compatible = "qcom,sm8350-gem-noc"; 2476 reg = <0 0x09100000 0 0xb4000>; 2477 #interconnect-cells = <2>; 2478 qcom,bcm-voters = <&apps_bcm_voter>; 2479 }; 2480 2481 system-cache-controller@9200000 { 2482 compatible = "qcom,sm8350-llcc"; 2483 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2484 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2485 <0 0x09600000 0 0x58000>; 2486 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2487 "llcc3_base", "llcc_broadcast_base"; 2488 }; 2489 2490 compute_noc: interconnect@a0c0000 { 2491 compatible = "qcom,sm8350-compute-noc"; 2492 reg = <0 0x0a0c0000 0 0xa180>; 2493 #interconnect-cells = <2>; 2494 qcom,bcm-voters = <&apps_bcm_voter>; 2495 }; 2496 2497 cdsp: remoteproc@a300000 { 2498 compatible = "qcom,sm8350-cdsp-pas"; 2499 reg = <0x0 0x0a300000 0x0 0x10000>; 2500 2501 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2502 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2503 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2504 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2505 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2506 interrupt-names = "wdog", "fatal", "ready", 2507 "handover", "stop-ack"; 2508 2509 clocks = <&rpmhcc RPMH_CXO_CLK>; 2510 clock-names = "xo"; 2511 2512 power-domains = <&rpmhpd RPMHPD_CX>, 2513 <&rpmhpd RPMHPD_MXC>; 2514 power-domain-names = "cx", "mxc"; 2515 2516 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 2517 2518 memory-region = <&pil_cdsp_mem>; 2519 2520 qcom,qmp = <&aoss_qmp>; 2521 2522 qcom,smem-states = <&smp2p_cdsp_out 0>; 2523 qcom,smem-state-names = "stop"; 2524 2525 status = "disabled"; 2526 2527 glink-edge { 2528 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2529 IPCC_MPROC_SIGNAL_GLINK_QMP 2530 IRQ_TYPE_EDGE_RISING>; 2531 mboxes = <&ipcc IPCC_CLIENT_CDSP 2532 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2533 2534 label = "cdsp"; 2535 qcom,remote-pid = <5>; 2536 2537 fastrpc { 2538 compatible = "qcom,fastrpc"; 2539 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2540 label = "cdsp"; 2541 qcom,non-secure-domain; 2542 #address-cells = <1>; 2543 #size-cells = <0>; 2544 2545 compute-cb@1 { 2546 compatible = "qcom,fastrpc-compute-cb"; 2547 reg = <1>; 2548 iommus = <&apps_smmu 0x2161 0x0400>, 2549 <&apps_smmu 0x1181 0x0420>; 2550 }; 2551 2552 compute-cb@2 { 2553 compatible = "qcom,fastrpc-compute-cb"; 2554 reg = <2>; 2555 iommus = <&apps_smmu 0x2162 0x0400>, 2556 <&apps_smmu 0x1182 0x0420>; 2557 }; 2558 2559 compute-cb@3 { 2560 compatible = "qcom,fastrpc-compute-cb"; 2561 reg = <3>; 2562 iommus = <&apps_smmu 0x2163 0x0400>, 2563 <&apps_smmu 0x1183 0x0420>; 2564 }; 2565 2566 compute-cb@4 { 2567 compatible = "qcom,fastrpc-compute-cb"; 2568 reg = <4>; 2569 iommus = <&apps_smmu 0x2164 0x0400>, 2570 <&apps_smmu 0x1184 0x0420>; 2571 }; 2572 2573 compute-cb@5 { 2574 compatible = "qcom,fastrpc-compute-cb"; 2575 reg = <5>; 2576 iommus = <&apps_smmu 0x2165 0x0400>, 2577 <&apps_smmu 0x1185 0x0420>; 2578 }; 2579 2580 compute-cb@6 { 2581 compatible = "qcom,fastrpc-compute-cb"; 2582 reg = <6>; 2583 iommus = <&apps_smmu 0x2166 0x0400>, 2584 <&apps_smmu 0x1186 0x0420>; 2585 }; 2586 2587 compute-cb@7 { 2588 compatible = "qcom,fastrpc-compute-cb"; 2589 reg = <7>; 2590 iommus = <&apps_smmu 0x2167 0x0400>, 2591 <&apps_smmu 0x1187 0x0420>; 2592 }; 2593 2594 compute-cb@8 { 2595 compatible = "qcom,fastrpc-compute-cb"; 2596 reg = <8>; 2597 iommus = <&apps_smmu 0x2168 0x0400>, 2598 <&apps_smmu 0x1188 0x0420>; 2599 }; 2600 2601 /* note: secure cb9 in downstream */ 2602 }; 2603 }; 2604 }; 2605 2606 usb_1: usb@a6f8800 { 2607 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2608 reg = <0 0x0a6f8800 0 0x400>; 2609 status = "disabled"; 2610 #address-cells = <2>; 2611 #size-cells = <2>; 2612 ranges; 2613 2614 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2615 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2616 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2617 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2618 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2619 clock-names = "cfg_noc", 2620 "core", 2621 "iface", 2622 "sleep", 2623 "mock_utmi"; 2624 2625 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2626 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2627 assigned-clock-rates = <19200000>, <200000000>; 2628 2629 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2630 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2631 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2632 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2633 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2634 interrupt-names = "pwr_event", 2635 "hs_phy_irq", 2636 "dp_hs_phy_irq", 2637 "dm_hs_phy_irq", 2638 "ss_phy_irq"; 2639 2640 power-domains = <&gcc USB30_PRIM_GDSC>; 2641 2642 resets = <&gcc GCC_USB30_PRIM_BCR>; 2643 2644 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2645 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2646 interconnect-names = "usb-ddr", "apps-usb"; 2647 2648 usb_1_dwc3: usb@a600000 { 2649 compatible = "snps,dwc3"; 2650 reg = <0 0x0a600000 0 0xcd00>; 2651 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2652 iommus = <&apps_smmu 0x0 0x0>; 2653 snps,dis_u2_susphy_quirk; 2654 snps,dis_enblslpm_quirk; 2655 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2656 phy-names = "usb2-phy", "usb3-phy"; 2657 2658 ports { 2659 #address-cells = <1>; 2660 #size-cells = <0>; 2661 2662 port@0 { 2663 reg = <0>; 2664 2665 usb_1_dwc3_hs: endpoint { 2666 }; 2667 }; 2668 2669 port@1 { 2670 reg = <1>; 2671 2672 usb_1_dwc3_ss: endpoint { 2673 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2674 }; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 usb_2: usb@a8f8800 { 2681 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2682 reg = <0 0x0a8f8800 0 0x400>; 2683 status = "disabled"; 2684 #address-cells = <2>; 2685 #size-cells = <2>; 2686 ranges; 2687 2688 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2689 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2690 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2691 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2692 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2693 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2694 clock-names = "cfg_noc", 2695 "core", 2696 "iface", 2697 "sleep", 2698 "mock_utmi", 2699 "xo"; 2700 2701 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2702 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2703 assigned-clock-rates = <19200000>, <200000000>; 2704 2705 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2706 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2707 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2708 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2709 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2710 interrupt-names = "pwr_event", 2711 "hs_phy_irq", 2712 "dp_hs_phy_irq", 2713 "dm_hs_phy_irq", 2714 "ss_phy_irq"; 2715 2716 power-domains = <&gcc USB30_SEC_GDSC>; 2717 2718 resets = <&gcc GCC_USB30_SEC_BCR>; 2719 2720 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2721 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2722 interconnect-names = "usb-ddr", "apps-usb"; 2723 2724 usb_2_dwc3: usb@a800000 { 2725 compatible = "snps,dwc3"; 2726 reg = <0 0x0a800000 0 0xcd00>; 2727 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2728 iommus = <&apps_smmu 0x20 0x0>; 2729 snps,dis_u2_susphy_quirk; 2730 snps,dis_enblslpm_quirk; 2731 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2732 phy-names = "usb2-phy", "usb3-phy"; 2733 }; 2734 }; 2735 2736 mdss: display-subsystem@ae00000 { 2737 compatible = "qcom,sm8350-mdss"; 2738 reg = <0 0x0ae00000 0 0x1000>; 2739 reg-names = "mdss"; 2740 2741 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2742 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, 2743 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2744 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2745 interconnect-names = "mdp0-mem", 2746 "mdp1-mem", 2747 "cpu-cfg"; 2748 2749 power-domains = <&dispcc MDSS_GDSC>; 2750 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2751 2752 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2753 <&gcc GCC_DISP_HF_AXI_CLK>, 2754 <&gcc GCC_DISP_SF_AXI_CLK>, 2755 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2756 clock-names = "iface", "bus", "nrt_bus", "core"; 2757 2758 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2759 interrupt-controller; 2760 #interrupt-cells = <1>; 2761 2762 iommus = <&apps_smmu 0x820 0x402>; 2763 2764 status = "disabled"; 2765 2766 #address-cells = <2>; 2767 #size-cells = <2>; 2768 ranges; 2769 2770 mdss_mdp: display-controller@ae01000 { 2771 compatible = "qcom,sm8350-dpu"; 2772 reg = <0 0x0ae01000 0 0x8f000>, 2773 <0 0x0aeb0000 0 0x2008>; 2774 reg-names = "mdp", "vbif"; 2775 2776 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2777 <&gcc GCC_DISP_SF_AXI_CLK>, 2778 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2779 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2780 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2781 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2782 clock-names = "bus", 2783 "nrt_bus", 2784 "iface", 2785 "lut", 2786 "core", 2787 "vsync"; 2788 2789 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2790 assigned-clock-rates = <19200000>; 2791 2792 operating-points-v2 = <&dpu_opp_table>; 2793 power-domains = <&rpmhpd RPMHPD_MMCX>; 2794 2795 interrupt-parent = <&mdss>; 2796 interrupts = <0>; 2797 2798 dpu_opp_table: opp-table { 2799 compatible = "operating-points-v2"; 2800 2801 /* TODO: opp-200000000 should work with 2802 * &rpmhpd_opp_low_svs, but one some of 2803 * sm8350_hdk boards reboot using this 2804 * opp. 2805 */ 2806 opp-200000000 { 2807 opp-hz = /bits/ 64 <200000000>; 2808 required-opps = <&rpmhpd_opp_svs>; 2809 }; 2810 2811 opp-300000000 { 2812 opp-hz = /bits/ 64 <300000000>; 2813 required-opps = <&rpmhpd_opp_svs>; 2814 }; 2815 2816 opp-345000000 { 2817 opp-hz = /bits/ 64 <345000000>; 2818 required-opps = <&rpmhpd_opp_svs_l1>; 2819 }; 2820 2821 opp-460000000 { 2822 opp-hz = /bits/ 64 <460000000>; 2823 required-opps = <&rpmhpd_opp_nom>; 2824 }; 2825 }; 2826 2827 ports { 2828 #address-cells = <1>; 2829 #size-cells = <0>; 2830 2831 port@0 { 2832 reg = <0>; 2833 dpu_intf1_out: endpoint { 2834 remote-endpoint = <&mdss_dsi0_in>; 2835 }; 2836 }; 2837 2838 port@1 { 2839 reg = <1>; 2840 dpu_intf2_out: endpoint { 2841 remote-endpoint = <&mdss_dsi1_in>; 2842 }; 2843 }; 2844 2845 port@2 { 2846 reg = <2>; 2847 dpu_intf0_out: endpoint { 2848 remote-endpoint = <&mdss_dp_in>; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 mdss_dp: displayport-controller@ae90000 { 2855 compatible = "qcom,sm8350-dp"; 2856 reg = <0 0xae90000 0 0x200>, 2857 <0 0xae90200 0 0x200>, 2858 <0 0xae90400 0 0x600>, 2859 <0 0xae91000 0 0x400>, 2860 <0 0xae91400 0 0x400>; 2861 interrupt-parent = <&mdss>; 2862 interrupts = <12>; 2863 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2864 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2865 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2866 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2867 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2868 clock-names = "core_iface", 2869 "core_aux", 2870 "ctrl_link", 2871 "ctrl_link_iface", 2872 "stream_pixel"; 2873 2874 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2875 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2876 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2877 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2878 2879 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2880 phy-names = "dp"; 2881 2882 #sound-dai-cells = <0>; 2883 2884 operating-points-v2 = <&dp_opp_table>; 2885 power-domains = <&rpmhpd RPMHPD_MMCX>; 2886 2887 status = "disabled"; 2888 2889 ports { 2890 #address-cells = <1>; 2891 #size-cells = <0>; 2892 2893 port@0 { 2894 reg = <0>; 2895 mdss_dp_in: endpoint { 2896 remote-endpoint = <&dpu_intf0_out>; 2897 }; 2898 }; 2899 2900 port@1 { 2901 reg = <1>; 2902 2903 mdss_dp_out: endpoint { 2904 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2905 }; 2906 }; 2907 }; 2908 2909 dp_opp_table: opp-table { 2910 compatible = "operating-points-v2"; 2911 2912 opp-160000000 { 2913 opp-hz = /bits/ 64 <160000000>; 2914 required-opps = <&rpmhpd_opp_low_svs>; 2915 }; 2916 2917 opp-270000000 { 2918 opp-hz = /bits/ 64 <270000000>; 2919 required-opps = <&rpmhpd_opp_svs>; 2920 }; 2921 2922 opp-540000000 { 2923 opp-hz = /bits/ 64 <540000000>; 2924 required-opps = <&rpmhpd_opp_svs_l1>; 2925 }; 2926 2927 opp-810000000 { 2928 opp-hz = /bits/ 64 <810000000>; 2929 required-opps = <&rpmhpd_opp_nom>; 2930 }; 2931 }; 2932 }; 2933 2934 mdss_dsi0: dsi@ae94000 { 2935 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2936 reg = <0 0x0ae94000 0 0x400>; 2937 reg-names = "dsi_ctrl"; 2938 2939 interrupt-parent = <&mdss>; 2940 interrupts = <4>; 2941 2942 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2943 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2944 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2945 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2946 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2947 <&gcc GCC_DISP_HF_AXI_CLK>; 2948 clock-names = "byte", 2949 "byte_intf", 2950 "pixel", 2951 "core", 2952 "iface", 2953 "bus"; 2954 2955 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2956 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2957 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2958 <&mdss_dsi0_phy 1>; 2959 2960 operating-points-v2 = <&dsi0_opp_table>; 2961 power-domains = <&rpmhpd RPMHPD_MMCX>; 2962 refgen-supply = <&refgen>; 2963 2964 phys = <&mdss_dsi0_phy>; 2965 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 2969 status = "disabled"; 2970 2971 dsi0_opp_table: opp-table { 2972 compatible = "operating-points-v2"; 2973 2974 /* TODO: opp-187500000 should work with 2975 * &rpmhpd_opp_low_svs, but one some of 2976 * sm8350_hdk boards reboot using this 2977 * opp. 2978 */ 2979 opp-187500000 { 2980 opp-hz = /bits/ 64 <187500000>; 2981 required-opps = <&rpmhpd_opp_svs>; 2982 }; 2983 2984 opp-300000000 { 2985 opp-hz = /bits/ 64 <300000000>; 2986 required-opps = <&rpmhpd_opp_svs>; 2987 }; 2988 2989 opp-358000000 { 2990 opp-hz = /bits/ 64 <358000000>; 2991 required-opps = <&rpmhpd_opp_svs_l1>; 2992 }; 2993 }; 2994 2995 ports { 2996 #address-cells = <1>; 2997 #size-cells = <0>; 2998 2999 port@0 { 3000 reg = <0>; 3001 mdss_dsi0_in: endpoint { 3002 remote-endpoint = <&dpu_intf1_out>; 3003 }; 3004 }; 3005 3006 port@1 { 3007 reg = <1>; 3008 mdss_dsi0_out: endpoint { 3009 }; 3010 }; 3011 }; 3012 }; 3013 3014 mdss_dsi0_phy: phy@ae94400 { 3015 compatible = "qcom,sm8350-dsi-phy-5nm"; 3016 reg = <0 0x0ae94400 0 0x200>, 3017 <0 0x0ae94600 0 0x280>, 3018 <0 0x0ae94900 0 0x27c>; 3019 reg-names = "dsi_phy", 3020 "dsi_phy_lane", 3021 "dsi_pll"; 3022 3023 #clock-cells = <1>; 3024 #phy-cells = <0>; 3025 3026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3027 <&rpmhcc RPMH_CXO_CLK>; 3028 clock-names = "iface", "ref"; 3029 3030 status = "disabled"; 3031 }; 3032 3033 mdss_dsi1: dsi@ae96000 { 3034 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3035 reg = <0 0x0ae96000 0 0x400>; 3036 reg-names = "dsi_ctrl"; 3037 3038 interrupt-parent = <&mdss>; 3039 interrupts = <5>; 3040 3041 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3042 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3043 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3044 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3045 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3046 <&gcc GCC_DISP_HF_AXI_CLK>; 3047 clock-names = "byte", 3048 "byte_intf", 3049 "pixel", 3050 "core", 3051 "iface", 3052 "bus"; 3053 3054 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3055 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3056 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3057 <&mdss_dsi1_phy 1>; 3058 3059 operating-points-v2 = <&dsi1_opp_table>; 3060 power-domains = <&rpmhpd RPMHPD_MMCX>; 3061 refgen-supply = <&refgen>; 3062 3063 phys = <&mdss_dsi1_phy>; 3064 3065 #address-cells = <1>; 3066 #size-cells = <0>; 3067 3068 status = "disabled"; 3069 3070 dsi1_opp_table: opp-table { 3071 compatible = "operating-points-v2"; 3072 3073 /* TODO: opp-187500000 should work with 3074 * &rpmhpd_opp_low_svs, but one some of 3075 * sm8350_hdk boards reboot using this 3076 * opp. 3077 */ 3078 opp-187500000 { 3079 opp-hz = /bits/ 64 <187500000>; 3080 required-opps = <&rpmhpd_opp_svs>; 3081 }; 3082 3083 opp-300000000 { 3084 opp-hz = /bits/ 64 <300000000>; 3085 required-opps = <&rpmhpd_opp_svs>; 3086 }; 3087 3088 opp-358000000 { 3089 opp-hz = /bits/ 64 <358000000>; 3090 required-opps = <&rpmhpd_opp_svs_l1>; 3091 }; 3092 }; 3093 3094 ports { 3095 #address-cells = <1>; 3096 #size-cells = <0>; 3097 3098 port@0 { 3099 reg = <0>; 3100 mdss_dsi1_in: endpoint { 3101 remote-endpoint = <&dpu_intf2_out>; 3102 }; 3103 }; 3104 3105 port@1 { 3106 reg = <1>; 3107 mdss_dsi1_out: endpoint { 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 mdss_dsi1_phy: phy@ae96400 { 3114 compatible = "qcom,sm8350-dsi-phy-5nm"; 3115 reg = <0 0x0ae96400 0 0x200>, 3116 <0 0x0ae96600 0 0x280>, 3117 <0 0x0ae96900 0 0x27c>; 3118 reg-names = "dsi_phy", 3119 "dsi_phy_lane", 3120 "dsi_pll"; 3121 3122 #clock-cells = <1>; 3123 #phy-cells = <0>; 3124 3125 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3126 <&rpmhcc RPMH_CXO_CLK>; 3127 clock-names = "iface", "ref"; 3128 3129 status = "disabled"; 3130 }; 3131 }; 3132 3133 dispcc: clock-controller@af00000 { 3134 compatible = "qcom,sm8350-dispcc"; 3135 reg = <0 0x0af00000 0 0x10000>; 3136 clocks = <&rpmhcc RPMH_CXO_CLK>, 3137 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 3138 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 3139 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3140 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3141 clock-names = "bi_tcxo", 3142 "dsi0_phy_pll_out_byteclk", 3143 "dsi0_phy_pll_out_dsiclk", 3144 "dsi1_phy_pll_out_byteclk", 3145 "dsi1_phy_pll_out_dsiclk", 3146 "dp_phy_pll_link_clk", 3147 "dp_phy_pll_vco_div_clk"; 3148 #clock-cells = <1>; 3149 #reset-cells = <1>; 3150 #power-domain-cells = <1>; 3151 3152 power-domains = <&rpmhpd RPMHPD_MMCX>; 3153 }; 3154 3155 pdc: interrupt-controller@b220000 { 3156 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 3157 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3158 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 3159 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 3160 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 3161 <156 716 12>; 3162 #interrupt-cells = <2>; 3163 interrupt-parent = <&intc>; 3164 interrupt-controller; 3165 }; 3166 3167 tsens0: thermal-sensor@c263000 { 3168 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3169 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3170 <0 0x0c222000 0 0x8>; /* SROT */ 3171 #qcom,sensors = <15>; 3172 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3173 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3174 interrupt-names = "uplow", "critical"; 3175 #thermal-sensor-cells = <1>; 3176 }; 3177 3178 tsens1: thermal-sensor@c265000 { 3179 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3180 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3181 <0 0x0c223000 0 0x8>; /* SROT */ 3182 #qcom,sensors = <14>; 3183 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3184 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3185 interrupt-names = "uplow", "critical"; 3186 #thermal-sensor-cells = <1>; 3187 }; 3188 3189 aoss_qmp: power-management@c300000 { 3190 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 3191 reg = <0 0x0c300000 0 0x400>; 3192 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3193 IRQ_TYPE_EDGE_RISING>; 3194 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3195 3196 #clock-cells = <0>; 3197 }; 3198 3199 sram@c3f0000 { 3200 compatible = "qcom,rpmh-stats"; 3201 reg = <0 0x0c3f0000 0 0x400>; 3202 }; 3203 3204 spmi_bus: spmi@c440000 { 3205 compatible = "qcom,spmi-pmic-arb"; 3206 reg = <0x0 0x0c440000 0x0 0x1100>, 3207 <0x0 0x0c600000 0x0 0x2000000>, 3208 <0x0 0x0e600000 0x0 0x100000>, 3209 <0x0 0x0e700000 0x0 0xa0000>, 3210 <0x0 0x0c40a000 0x0 0x26000>; 3211 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3212 interrupt-names = "periph_irq"; 3213 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3214 qcom,ee = <0>; 3215 qcom,channel = <0>; 3216 #address-cells = <2>; 3217 #size-cells = <0>; 3218 interrupt-controller; 3219 #interrupt-cells = <4>; 3220 }; 3221 3222 tlmm: pinctrl@f100000 { 3223 compatible = "qcom,sm8350-tlmm"; 3224 reg = <0 0x0f100000 0 0x300000>; 3225 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3226 gpio-controller; 3227 #gpio-cells = <2>; 3228 interrupt-controller; 3229 #interrupt-cells = <2>; 3230 gpio-ranges = <&tlmm 0 0 204>; 3231 wakeup-parent = <&pdc>; 3232 3233 sdc2_default_state: sdc2-default-state { 3234 clk-pins { 3235 pins = "sdc2_clk"; 3236 drive-strength = <16>; 3237 bias-disable; 3238 }; 3239 3240 cmd-pins { 3241 pins = "sdc2_cmd"; 3242 drive-strength = <16>; 3243 bias-pull-up; 3244 }; 3245 3246 data-pins { 3247 pins = "sdc2_data"; 3248 drive-strength = <16>; 3249 bias-pull-up; 3250 }; 3251 }; 3252 3253 sdc2_sleep_state: sdc2-sleep-state { 3254 clk-pins { 3255 pins = "sdc2_clk"; 3256 drive-strength = <2>; 3257 bias-disable; 3258 }; 3259 3260 cmd-pins { 3261 pins = "sdc2_cmd"; 3262 drive-strength = <2>; 3263 bias-pull-up; 3264 }; 3265 3266 data-pins { 3267 pins = "sdc2_data"; 3268 drive-strength = <2>; 3269 bias-pull-up; 3270 }; 3271 }; 3272 3273 qup_uart3_default_state: qup-uart3-default-state { 3274 rx-pins { 3275 pins = "gpio18"; 3276 function = "qup3"; 3277 }; 3278 tx-pins { 3279 pins = "gpio19"; 3280 function = "qup3"; 3281 }; 3282 }; 3283 3284 qup_uart6_default: qup-uart6-default-state { 3285 pins = "gpio30", "gpio31"; 3286 function = "qup6"; 3287 drive-strength = <2>; 3288 bias-disable; 3289 }; 3290 3291 qup_uart18_default: qup-uart18-default-state { 3292 pins = "gpio68", "gpio69"; 3293 function = "qup18"; 3294 drive-strength = <2>; 3295 bias-disable; 3296 }; 3297 3298 qup_i2c0_default: qup-i2c0-default-state { 3299 pins = "gpio4", "gpio5"; 3300 function = "qup0"; 3301 drive-strength = <2>; 3302 bias-pull-up; 3303 }; 3304 3305 qup_i2c1_default: qup-i2c1-default-state { 3306 pins = "gpio8", "gpio9"; 3307 function = "qup1"; 3308 drive-strength = <2>; 3309 bias-pull-up; 3310 }; 3311 3312 qup_i2c2_default: qup-i2c2-default-state { 3313 pins = "gpio12", "gpio13"; 3314 function = "qup2"; 3315 drive-strength = <2>; 3316 bias-pull-up; 3317 }; 3318 3319 qup_i2c4_default: qup-i2c4-default-state { 3320 pins = "gpio20", "gpio21"; 3321 function = "qup4"; 3322 drive-strength = <2>; 3323 bias-pull-up; 3324 }; 3325 3326 qup_i2c5_default: qup-i2c5-default-state { 3327 pins = "gpio24", "gpio25"; 3328 function = "qup5"; 3329 drive-strength = <2>; 3330 bias-pull-up; 3331 }; 3332 3333 qup_i2c6_default: qup-i2c6-default-state { 3334 pins = "gpio28", "gpio29"; 3335 function = "qup6"; 3336 drive-strength = <2>; 3337 bias-pull-up; 3338 }; 3339 3340 qup_i2c7_default: qup-i2c7-default-state { 3341 pins = "gpio32", "gpio33"; 3342 function = "qup7"; 3343 drive-strength = <2>; 3344 bias-disable; 3345 }; 3346 3347 qup_i2c8_default: qup-i2c8-default-state { 3348 pins = "gpio36", "gpio37"; 3349 function = "qup8"; 3350 drive-strength = <2>; 3351 bias-pull-up; 3352 }; 3353 3354 qup_i2c9_default: qup-i2c9-default-state { 3355 pins = "gpio40", "gpio41"; 3356 function = "qup9"; 3357 drive-strength = <2>; 3358 bias-pull-up; 3359 }; 3360 3361 qup_i2c10_default: qup-i2c10-default-state { 3362 pins = "gpio44", "gpio45"; 3363 function = "qup10"; 3364 drive-strength = <2>; 3365 bias-pull-up; 3366 }; 3367 3368 qup_i2c11_default: qup-i2c11-default-state { 3369 pins = "gpio48", "gpio49"; 3370 function = "qup11"; 3371 drive-strength = <2>; 3372 bias-pull-up; 3373 }; 3374 3375 qup_i2c12_default: qup-i2c12-default-state { 3376 pins = "gpio52", "gpio53"; 3377 function = "qup12"; 3378 drive-strength = <2>; 3379 bias-pull-up; 3380 }; 3381 3382 qup_i2c13_default: qup-i2c13-default-state { 3383 pins = "gpio0", "gpio1"; 3384 function = "qup13"; 3385 drive-strength = <2>; 3386 bias-pull-up; 3387 }; 3388 3389 qup_i2c14_default: qup-i2c14-default-state { 3390 pins = "gpio56", "gpio57"; 3391 function = "qup14"; 3392 drive-strength = <2>; 3393 bias-disable; 3394 }; 3395 3396 qup_i2c15_default: qup-i2c15-default-state { 3397 pins = "gpio60", "gpio61"; 3398 function = "qup15"; 3399 drive-strength = <2>; 3400 bias-disable; 3401 }; 3402 3403 qup_i2c16_default: qup-i2c16-default-state { 3404 pins = "gpio64", "gpio65"; 3405 function = "qup16"; 3406 drive-strength = <2>; 3407 bias-disable; 3408 }; 3409 3410 qup_i2c17_default: qup-i2c17-default-state { 3411 pins = "gpio72", "gpio73"; 3412 function = "qup17"; 3413 drive-strength = <2>; 3414 bias-disable; 3415 }; 3416 3417 qup_i2c19_default: qup-i2c19-default-state { 3418 pins = "gpio76", "gpio77"; 3419 function = "qup19"; 3420 drive-strength = <2>; 3421 bias-disable; 3422 }; 3423 }; 3424 3425 apps_smmu: iommu@15000000 { 3426 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3427 reg = <0 0x15000000 0 0x100000>; 3428 #iommu-cells = <2>; 3429 #global-interrupts = <2>; 3430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3528 }; 3529 3530 intc: interrupt-controller@17a00000 { 3531 compatible = "arm,gic-v3"; 3532 #interrupt-cells = <3>; 3533 interrupt-controller; 3534 #redistributor-regions = <1>; 3535 redistributor-stride = <0 0x20000>; 3536 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3537 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3538 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3539 }; 3540 3541 timer@17c20000 { 3542 compatible = "arm,armv7-timer-mem"; 3543 #address-cells = <1>; 3544 #size-cells = <1>; 3545 ranges = <0 0 0 0x20000000>; 3546 reg = <0x0 0x17c20000 0x0 0x1000>; 3547 clock-frequency = <19200000>; 3548 3549 frame@17c21000 { 3550 frame-number = <0>; 3551 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3553 reg = <0x17c21000 0x1000>, 3554 <0x17c22000 0x1000>; 3555 }; 3556 3557 frame@17c23000 { 3558 frame-number = <1>; 3559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3560 reg = <0x17c23000 0x1000>; 3561 status = "disabled"; 3562 }; 3563 3564 frame@17c25000 { 3565 frame-number = <2>; 3566 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3567 reg = <0x17c25000 0x1000>; 3568 status = "disabled"; 3569 }; 3570 3571 frame@17c27000 { 3572 frame-number = <3>; 3573 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3574 reg = <0x17c27000 0x1000>; 3575 status = "disabled"; 3576 }; 3577 3578 frame@17c29000 { 3579 frame-number = <4>; 3580 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3581 reg = <0x17c29000 0x1000>; 3582 status = "disabled"; 3583 }; 3584 3585 frame@17c2b000 { 3586 frame-number = <5>; 3587 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3588 reg = <0x17c2b000 0x1000>; 3589 status = "disabled"; 3590 }; 3591 3592 frame@17c2d000 { 3593 frame-number = <6>; 3594 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3595 reg = <0x17c2d000 0x1000>; 3596 status = "disabled"; 3597 }; 3598 }; 3599 3600 apps_rsc: rsc@18200000 { 3601 label = "apps_rsc"; 3602 compatible = "qcom,rpmh-rsc"; 3603 reg = <0x0 0x18200000 0x0 0x10000>, 3604 <0x0 0x18210000 0x0 0x10000>, 3605 <0x0 0x18220000 0x0 0x10000>; 3606 reg-names = "drv-0", "drv-1", "drv-2"; 3607 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3610 qcom,tcs-offset = <0xd00>; 3611 qcom,drv-id = <2>; 3612 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3613 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3614 power-domains = <&CLUSTER_PD>; 3615 3616 rpmhcc: clock-controller { 3617 compatible = "qcom,sm8350-rpmh-clk"; 3618 #clock-cells = <1>; 3619 clock-names = "xo"; 3620 clocks = <&xo_board>; 3621 }; 3622 3623 rpmhpd: power-controller { 3624 compatible = "qcom,sm8350-rpmhpd"; 3625 #power-domain-cells = <1>; 3626 operating-points-v2 = <&rpmhpd_opp_table>; 3627 3628 rpmhpd_opp_table: opp-table { 3629 compatible = "operating-points-v2"; 3630 3631 rpmhpd_opp_ret: opp1 { 3632 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3633 }; 3634 3635 rpmhpd_opp_min_svs: opp2 { 3636 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3637 }; 3638 3639 rpmhpd_opp_low_svs: opp3 { 3640 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3641 }; 3642 3643 rpmhpd_opp_svs: opp4 { 3644 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3645 }; 3646 3647 rpmhpd_opp_svs_l1: opp5 { 3648 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3649 }; 3650 3651 rpmhpd_opp_nom: opp6 { 3652 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3653 }; 3654 3655 rpmhpd_opp_nom_l1: opp7 { 3656 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3657 }; 3658 3659 rpmhpd_opp_nom_l2: opp8 { 3660 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3661 }; 3662 3663 rpmhpd_opp_turbo: opp9 { 3664 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3665 }; 3666 3667 rpmhpd_opp_turbo_l1: opp10 { 3668 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3669 }; 3670 }; 3671 }; 3672 3673 apps_bcm_voter: bcm-voter { 3674 compatible = "qcom,bcm-voter"; 3675 }; 3676 }; 3677 3678 cpufreq_hw: cpufreq@18591000 { 3679 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3680 reg = <0 0x18591000 0 0x1000>, 3681 <0 0x18592000 0 0x1000>, 3682 <0 0x18593000 0 0x1000>; 3683 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3684 3685 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3688 interrupt-names = "dcvsh-irq-0", 3689 "dcvsh-irq-1", 3690 "dcvsh-irq-2"; 3691 3692 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3693 clock-names = "xo", "alternate"; 3694 3695 #freq-domain-cells = <1>; 3696 #clock-cells = <1>; 3697 }; 3698 }; 3699 3700 thermal_zones: thermal-zones { 3701 cpu0-thermal { 3702 polling-delay-passive = <250>; 3703 3704 thermal-sensors = <&tsens0 1>; 3705 3706 trips { 3707 cpu0_alert0: trip-point0 { 3708 temperature = <90000>; 3709 hysteresis = <2000>; 3710 type = "passive"; 3711 }; 3712 3713 cpu0_alert1: trip-point1 { 3714 temperature = <95000>; 3715 hysteresis = <2000>; 3716 type = "passive"; 3717 }; 3718 3719 cpu0_crit: cpu-crit { 3720 temperature = <110000>; 3721 hysteresis = <1000>; 3722 type = "critical"; 3723 }; 3724 }; 3725 3726 cooling-maps { 3727 map0 { 3728 trip = <&cpu0_alert0>; 3729 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3730 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3733 }; 3734 map1 { 3735 trip = <&cpu0_alert1>; 3736 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3740 }; 3741 }; 3742 }; 3743 3744 cpu1-thermal { 3745 polling-delay-passive = <250>; 3746 3747 thermal-sensors = <&tsens0 2>; 3748 3749 trips { 3750 cpu1_alert0: trip-point0 { 3751 temperature = <90000>; 3752 hysteresis = <2000>; 3753 type = "passive"; 3754 }; 3755 3756 cpu1_alert1: trip-point1 { 3757 temperature = <95000>; 3758 hysteresis = <2000>; 3759 type = "passive"; 3760 }; 3761 3762 cpu1_crit: cpu-crit { 3763 temperature = <110000>; 3764 hysteresis = <1000>; 3765 type = "critical"; 3766 }; 3767 }; 3768 3769 cooling-maps { 3770 map0 { 3771 trip = <&cpu1_alert0>; 3772 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 map1 { 3778 trip = <&cpu1_alert1>; 3779 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3783 }; 3784 }; 3785 }; 3786 3787 cpu2-thermal { 3788 polling-delay-passive = <250>; 3789 3790 thermal-sensors = <&tsens0 3>; 3791 3792 trips { 3793 cpu2_alert0: trip-point0 { 3794 temperature = <90000>; 3795 hysteresis = <2000>; 3796 type = "passive"; 3797 }; 3798 3799 cpu2_alert1: trip-point1 { 3800 temperature = <95000>; 3801 hysteresis = <2000>; 3802 type = "passive"; 3803 }; 3804 3805 cpu2_crit: cpu-crit { 3806 temperature = <110000>; 3807 hysteresis = <1000>; 3808 type = "critical"; 3809 }; 3810 }; 3811 3812 cooling-maps { 3813 map0 { 3814 trip = <&cpu2_alert0>; 3815 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3819 }; 3820 map1 { 3821 trip = <&cpu2_alert1>; 3822 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3826 }; 3827 }; 3828 }; 3829 3830 cpu3-thermal { 3831 polling-delay-passive = <250>; 3832 3833 thermal-sensors = <&tsens0 4>; 3834 3835 trips { 3836 cpu3_alert0: trip-point0 { 3837 temperature = <90000>; 3838 hysteresis = <2000>; 3839 type = "passive"; 3840 }; 3841 3842 cpu3_alert1: trip-point1 { 3843 temperature = <95000>; 3844 hysteresis = <2000>; 3845 type = "passive"; 3846 }; 3847 3848 cpu3_crit: cpu-crit { 3849 temperature = <110000>; 3850 hysteresis = <1000>; 3851 type = "critical"; 3852 }; 3853 }; 3854 3855 cooling-maps { 3856 map0 { 3857 trip = <&cpu3_alert0>; 3858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3862 }; 3863 map1 { 3864 trip = <&cpu3_alert1>; 3865 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3869 }; 3870 }; 3871 }; 3872 3873 cpu4-top-thermal { 3874 polling-delay-passive = <250>; 3875 3876 thermal-sensors = <&tsens0 7>; 3877 3878 trips { 3879 cpu4_top_alert0: trip-point0 { 3880 temperature = <90000>; 3881 hysteresis = <2000>; 3882 type = "passive"; 3883 }; 3884 3885 cpu4_top_alert1: trip-point1 { 3886 temperature = <95000>; 3887 hysteresis = <2000>; 3888 type = "passive"; 3889 }; 3890 3891 cpu4_top_crit: cpu-crit { 3892 temperature = <110000>; 3893 hysteresis = <1000>; 3894 type = "critical"; 3895 }; 3896 }; 3897 3898 cooling-maps { 3899 map0 { 3900 trip = <&cpu4_top_alert0>; 3901 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3905 }; 3906 map1 { 3907 trip = <&cpu4_top_alert1>; 3908 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3912 }; 3913 }; 3914 }; 3915 3916 cpu5-top-thermal { 3917 polling-delay-passive = <250>; 3918 3919 thermal-sensors = <&tsens0 8>; 3920 3921 trips { 3922 cpu5_top_alert0: trip-point0 { 3923 temperature = <90000>; 3924 hysteresis = <2000>; 3925 type = "passive"; 3926 }; 3927 3928 cpu5_top_alert1: trip-point1 { 3929 temperature = <95000>; 3930 hysteresis = <2000>; 3931 type = "passive"; 3932 }; 3933 3934 cpu5_top_crit: cpu-crit { 3935 temperature = <110000>; 3936 hysteresis = <1000>; 3937 type = "critical"; 3938 }; 3939 }; 3940 3941 cooling-maps { 3942 map0 { 3943 trip = <&cpu5_top_alert0>; 3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948 }; 3949 map1 { 3950 trip = <&cpu5_top_alert1>; 3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3955 }; 3956 }; 3957 }; 3958 3959 cpu6-top-thermal { 3960 polling-delay-passive = <250>; 3961 3962 thermal-sensors = <&tsens0 9>; 3963 3964 trips { 3965 cpu6_top_alert0: trip-point0 { 3966 temperature = <90000>; 3967 hysteresis = <2000>; 3968 type = "passive"; 3969 }; 3970 3971 cpu6_top_alert1: trip-point1 { 3972 temperature = <95000>; 3973 hysteresis = <2000>; 3974 type = "passive"; 3975 }; 3976 3977 cpu6_top_crit: cpu-crit { 3978 temperature = <110000>; 3979 hysteresis = <1000>; 3980 type = "critical"; 3981 }; 3982 }; 3983 3984 cooling-maps { 3985 map0 { 3986 trip = <&cpu6_top_alert0>; 3987 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3991 }; 3992 map1 { 3993 trip = <&cpu6_top_alert1>; 3994 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3995 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3997 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3998 }; 3999 }; 4000 }; 4001 4002 cpu7-top-thermal { 4003 polling-delay-passive = <250>; 4004 4005 thermal-sensors = <&tsens0 10>; 4006 4007 trips { 4008 cpu7_top_alert0: trip-point0 { 4009 temperature = <90000>; 4010 hysteresis = <2000>; 4011 type = "passive"; 4012 }; 4013 4014 cpu7_top_alert1: trip-point1 { 4015 temperature = <95000>; 4016 hysteresis = <2000>; 4017 type = "passive"; 4018 }; 4019 4020 cpu7_top_crit: cpu-crit { 4021 temperature = <110000>; 4022 hysteresis = <1000>; 4023 type = "critical"; 4024 }; 4025 }; 4026 4027 cooling-maps { 4028 map0 { 4029 trip = <&cpu7_top_alert0>; 4030 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4034 }; 4035 map1 { 4036 trip = <&cpu7_top_alert1>; 4037 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4038 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4039 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 }; 4043 }; 4044 4045 cpu4-bottom-thermal { 4046 polling-delay-passive = <250>; 4047 4048 thermal-sensors = <&tsens0 11>; 4049 4050 trips { 4051 cpu4_bottom_alert0: trip-point0 { 4052 temperature = <90000>; 4053 hysteresis = <2000>; 4054 type = "passive"; 4055 }; 4056 4057 cpu4_bottom_alert1: trip-point1 { 4058 temperature = <95000>; 4059 hysteresis = <2000>; 4060 type = "passive"; 4061 }; 4062 4063 cpu4_bottom_crit: cpu-crit { 4064 temperature = <110000>; 4065 hysteresis = <1000>; 4066 type = "critical"; 4067 }; 4068 }; 4069 4070 cooling-maps { 4071 map0 { 4072 trip = <&cpu4_bottom_alert0>; 4073 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 map1 { 4079 trip = <&cpu4_bottom_alert1>; 4080 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4084 }; 4085 }; 4086 }; 4087 4088 cpu5-bottom-thermal { 4089 polling-delay-passive = <250>; 4090 4091 thermal-sensors = <&tsens0 12>; 4092 4093 trips { 4094 cpu5_bottom_alert0: trip-point0 { 4095 temperature = <90000>; 4096 hysteresis = <2000>; 4097 type = "passive"; 4098 }; 4099 4100 cpu5_bottom_alert1: trip-point1 { 4101 temperature = <95000>; 4102 hysteresis = <2000>; 4103 type = "passive"; 4104 }; 4105 4106 cpu5_bottom_crit: cpu-crit { 4107 temperature = <110000>; 4108 hysteresis = <1000>; 4109 type = "critical"; 4110 }; 4111 }; 4112 4113 cooling-maps { 4114 map0 { 4115 trip = <&cpu5_bottom_alert0>; 4116 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4118 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4120 }; 4121 map1 { 4122 trip = <&cpu5_bottom_alert1>; 4123 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4127 }; 4128 }; 4129 }; 4130 4131 cpu6-bottom-thermal { 4132 polling-delay-passive = <250>; 4133 4134 thermal-sensors = <&tsens0 13>; 4135 4136 trips { 4137 cpu6_bottom_alert0: trip-point0 { 4138 temperature = <90000>; 4139 hysteresis = <2000>; 4140 type = "passive"; 4141 }; 4142 4143 cpu6_bottom_alert1: trip-point1 { 4144 temperature = <95000>; 4145 hysteresis = <2000>; 4146 type = "passive"; 4147 }; 4148 4149 cpu6_bottom_crit: cpu-crit { 4150 temperature = <110000>; 4151 hysteresis = <1000>; 4152 type = "critical"; 4153 }; 4154 }; 4155 4156 cooling-maps { 4157 map0 { 4158 trip = <&cpu6_bottom_alert0>; 4159 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4163 }; 4164 map1 { 4165 trip = <&cpu6_bottom_alert1>; 4166 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170 }; 4171 }; 4172 }; 4173 4174 cpu7-bottom-thermal { 4175 polling-delay-passive = <250>; 4176 4177 thermal-sensors = <&tsens0 14>; 4178 4179 trips { 4180 cpu7_bottom_alert0: trip-point0 { 4181 temperature = <90000>; 4182 hysteresis = <2000>; 4183 type = "passive"; 4184 }; 4185 4186 cpu7_bottom_alert1: trip-point1 { 4187 temperature = <95000>; 4188 hysteresis = <2000>; 4189 type = "passive"; 4190 }; 4191 4192 cpu7_bottom_crit: cpu-crit { 4193 temperature = <110000>; 4194 hysteresis = <1000>; 4195 type = "critical"; 4196 }; 4197 }; 4198 4199 cooling-maps { 4200 map0 { 4201 trip = <&cpu7_bottom_alert0>; 4202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206 }; 4207 map1 { 4208 trip = <&cpu7_bottom_alert1>; 4209 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213 }; 4214 }; 4215 }; 4216 4217 aoss0-thermal { 4218 polling-delay-passive = <250>; 4219 4220 thermal-sensors = <&tsens0 0>; 4221 4222 trips { 4223 aoss0_alert0: trip-point0 { 4224 temperature = <90000>; 4225 hysteresis = <2000>; 4226 type = "hot"; 4227 }; 4228 }; 4229 }; 4230 4231 cluster0-thermal { 4232 polling-delay-passive = <250>; 4233 4234 thermal-sensors = <&tsens0 5>; 4235 4236 trips { 4237 cluster0_alert0: trip-point0 { 4238 temperature = <90000>; 4239 hysteresis = <2000>; 4240 type = "hot"; 4241 }; 4242 cluster0_crit: cluster0-crit { 4243 temperature = <110000>; 4244 hysteresis = <2000>; 4245 type = "critical"; 4246 }; 4247 }; 4248 }; 4249 4250 cluster1-thermal { 4251 polling-delay-passive = <250>; 4252 4253 thermal-sensors = <&tsens0 6>; 4254 4255 trips { 4256 cluster1_alert0: trip-point0 { 4257 temperature = <90000>; 4258 hysteresis = <2000>; 4259 type = "hot"; 4260 }; 4261 cluster1_crit: cluster1-crit { 4262 temperature = <110000>; 4263 hysteresis = <2000>; 4264 type = "critical"; 4265 }; 4266 }; 4267 }; 4268 4269 aoss1-thermal { 4270 polling-delay-passive = <250>; 4271 4272 thermal-sensors = <&tsens1 0>; 4273 4274 trips { 4275 aoss1_alert0: trip-point0 { 4276 temperature = <90000>; 4277 hysteresis = <2000>; 4278 type = "hot"; 4279 }; 4280 }; 4281 }; 4282 4283 gpu-top-thermal { 4284 polling-delay-passive = <250>; 4285 4286 thermal-sensors = <&tsens1 1>; 4287 4288 cooling-maps { 4289 map0 { 4290 trip = <&gpu_top_alert0>; 4291 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4292 }; 4293 }; 4294 4295 trips { 4296 gpu_top_alert0: trip-point0 { 4297 temperature = <85000>; 4298 hysteresis = <1000>; 4299 type = "passive"; 4300 }; 4301 4302 trip-point1 { 4303 temperature = <90000>; 4304 hysteresis = <1000>; 4305 type = "hot"; 4306 }; 4307 4308 trip-point2 { 4309 temperature = <110000>; 4310 hysteresis = <1000>; 4311 type = "critical"; 4312 }; 4313 }; 4314 }; 4315 4316 gpu-bottom-thermal { 4317 polling-delay-passive = <250>; 4318 4319 thermal-sensors = <&tsens1 2>; 4320 4321 cooling-maps { 4322 map0 { 4323 trip = <&gpu_bottom_alert0>; 4324 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4325 }; 4326 }; 4327 4328 trips { 4329 gpu_bottom_alert0: trip-point0 { 4330 temperature = <85000>; 4331 hysteresis = <1000>; 4332 type = "passive"; 4333 }; 4334 4335 trip-point1 { 4336 temperature = <90000>; 4337 hysteresis = <1000>; 4338 type = "hot"; 4339 }; 4340 4341 trip-point2 { 4342 temperature = <110000>; 4343 hysteresis = <1000>; 4344 type = "critical"; 4345 }; 4346 }; 4347 }; 4348 4349 nspss1-thermal { 4350 polling-delay-passive = <250>; 4351 4352 thermal-sensors = <&tsens1 3>; 4353 4354 trips { 4355 nspss1_alert0: trip-point0 { 4356 temperature = <90000>; 4357 hysteresis = <1000>; 4358 type = "hot"; 4359 }; 4360 }; 4361 }; 4362 4363 nspss2-thermal { 4364 polling-delay-passive = <250>; 4365 4366 thermal-sensors = <&tsens1 4>; 4367 4368 trips { 4369 nspss2_alert0: trip-point0 { 4370 temperature = <90000>; 4371 hysteresis = <1000>; 4372 type = "hot"; 4373 }; 4374 }; 4375 }; 4376 4377 nspss3-thermal { 4378 polling-delay-passive = <250>; 4379 4380 thermal-sensors = <&tsens1 5>; 4381 4382 trips { 4383 nspss3_alert0: trip-point0 { 4384 temperature = <90000>; 4385 hysteresis = <1000>; 4386 type = "hot"; 4387 }; 4388 }; 4389 }; 4390 4391 video-thermal { 4392 polling-delay-passive = <250>; 4393 4394 thermal-sensors = <&tsens1 6>; 4395 4396 trips { 4397 video_alert0: trip-point0 { 4398 temperature = <90000>; 4399 hysteresis = <2000>; 4400 type = "hot"; 4401 }; 4402 }; 4403 }; 4404 4405 mem-thermal { 4406 polling-delay-passive = <250>; 4407 4408 thermal-sensors = <&tsens1 7>; 4409 4410 trips { 4411 mem_alert0: trip-point0 { 4412 temperature = <90000>; 4413 hysteresis = <2000>; 4414 type = "hot"; 4415 }; 4416 }; 4417 }; 4418 4419 modem1-top-thermal { 4420 polling-delay-passive = <250>; 4421 4422 thermal-sensors = <&tsens1 8>; 4423 4424 trips { 4425 modem1_alert0: trip-point0 { 4426 temperature = <90000>; 4427 hysteresis = <2000>; 4428 type = "hot"; 4429 }; 4430 }; 4431 }; 4432 4433 modem2-top-thermal { 4434 polling-delay-passive = <250>; 4435 4436 thermal-sensors = <&tsens1 9>; 4437 4438 trips { 4439 modem2_alert0: trip-point0 { 4440 temperature = <90000>; 4441 hysteresis = <2000>; 4442 type = "hot"; 4443 }; 4444 }; 4445 }; 4446 4447 modem3-top-thermal { 4448 polling-delay-passive = <250>; 4449 4450 thermal-sensors = <&tsens1 10>; 4451 4452 trips { 4453 modem3_alert0: trip-point0 { 4454 temperature = <90000>; 4455 hysteresis = <2000>; 4456 type = "hot"; 4457 }; 4458 }; 4459 }; 4460 4461 modem4-top-thermal { 4462 polling-delay-passive = <250>; 4463 4464 thermal-sensors = <&tsens1 11>; 4465 4466 trips { 4467 modem4_alert0: trip-point0 { 4468 temperature = <90000>; 4469 hysteresis = <2000>; 4470 type = "hot"; 4471 }; 4472 }; 4473 }; 4474 4475 camera-top-thermal { 4476 polling-delay-passive = <250>; 4477 4478 thermal-sensors = <&tsens1 12>; 4479 4480 trips { 4481 camera1_alert0: trip-point0 { 4482 temperature = <90000>; 4483 hysteresis = <2000>; 4484 type = "hot"; 4485 }; 4486 }; 4487 }; 4488 4489 cam-bottom-thermal { 4490 polling-delay-passive = <250>; 4491 4492 thermal-sensors = <&tsens1 13>; 4493 4494 trips { 4495 camera2_alert0: trip-point0 { 4496 temperature = <90000>; 4497 hysteresis = <2000>; 4498 type = "hot"; 4499 }; 4500 }; 4501 }; 4502 }; 4503 4504 timer { 4505 compatible = "arm,armv8-timer"; 4506 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4507 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4508 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4509 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4510 }; 4511}; 4512