1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 compatible = "fixed-factor-clock"; 57 #clock-cells = <0>; 58 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 CPU0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "qcom,oryon"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&L2_0>; 75 power-domains = <&CPU_PD0>; 76 power-domain-names = "psci"; 77 cpu-idle-states = <&CLUSTER_C4>; 78 79 L2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 cache-unified; 83 }; 84 }; 85 86 CPU1: cpu@100 { 87 device_type = "cpu"; 88 compatible = "qcom,oryon"; 89 reg = <0x0 0x100>; 90 enable-method = "psci"; 91 next-level-cache = <&L2_0>; 92 power-domains = <&CPU_PD1>; 93 power-domain-names = "psci"; 94 cpu-idle-states = <&CLUSTER_C4>; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,oryon"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_0>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 cpu-idle-states = <&CLUSTER_C4>; 106 }; 107 108 CPU3: cpu@300 { 109 device_type = "cpu"; 110 compatible = "qcom,oryon"; 111 reg = <0x0 0x300>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_0>; 114 power-domains = <&CPU_PD3>; 115 power-domain-names = "psci"; 116 cpu-idle-states = <&CLUSTER_C4>; 117 }; 118 119 CPU4: cpu@10000 { 120 device_type = "cpu"; 121 compatible = "qcom,oryon"; 122 reg = <0x0 0x10000>; 123 enable-method = "psci"; 124 next-level-cache = <&L2_1>; 125 power-domains = <&CPU_PD4>; 126 power-domain-names = "psci"; 127 cpu-idle-states = <&CLUSTER_C4>; 128 129 L2_1: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 }; 134 }; 135 136 CPU5: cpu@10100 { 137 device_type = "cpu"; 138 compatible = "qcom,oryon"; 139 reg = <0x0 0x10100>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_1>; 142 power-domains = <&CPU_PD5>; 143 power-domain-names = "psci"; 144 cpu-idle-states = <&CLUSTER_C4>; 145 }; 146 147 CPU6: cpu@10200 { 148 device_type = "cpu"; 149 compatible = "qcom,oryon"; 150 reg = <0x0 0x10200>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_1>; 153 power-domains = <&CPU_PD6>; 154 power-domain-names = "psci"; 155 cpu-idle-states = <&CLUSTER_C4>; 156 }; 157 158 CPU7: cpu@10300 { 159 device_type = "cpu"; 160 compatible = "qcom,oryon"; 161 reg = <0x0 0x10300>; 162 enable-method = "psci"; 163 next-level-cache = <&L2_1>; 164 power-domains = <&CPU_PD7>; 165 power-domain-names = "psci"; 166 cpu-idle-states = <&CLUSTER_C4>; 167 }; 168 169 CPU8: cpu@20000 { 170 device_type = "cpu"; 171 compatible = "qcom,oryon"; 172 reg = <0x0 0x20000>; 173 enable-method = "psci"; 174 next-level-cache = <&L2_2>; 175 power-domains = <&CPU_PD8>; 176 power-domain-names = "psci"; 177 cpu-idle-states = <&CLUSTER_C4>; 178 179 L2_2: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 }; 184 }; 185 186 CPU9: cpu@20100 { 187 device_type = "cpu"; 188 compatible = "qcom,oryon"; 189 reg = <0x0 0x20100>; 190 enable-method = "psci"; 191 next-level-cache = <&L2_2>; 192 power-domains = <&CPU_PD9>; 193 power-domain-names = "psci"; 194 cpu-idle-states = <&CLUSTER_C4>; 195 }; 196 197 CPU10: cpu@20200 { 198 device_type = "cpu"; 199 compatible = "qcom,oryon"; 200 reg = <0x0 0x20200>; 201 enable-method = "psci"; 202 next-level-cache = <&L2_2>; 203 power-domains = <&CPU_PD10>; 204 power-domain-names = "psci"; 205 cpu-idle-states = <&CLUSTER_C4>; 206 }; 207 208 CPU11: cpu@20300 { 209 device_type = "cpu"; 210 compatible = "qcom,oryon"; 211 reg = <0x0 0x20300>; 212 enable-method = "psci"; 213 next-level-cache = <&L2_2>; 214 power-domains = <&CPU_PD11>; 215 power-domain-names = "psci"; 216 cpu-idle-states = <&CLUSTER_C4>; 217 }; 218 219 cpu-map { 220 cluster0 { 221 core0 { 222 cpu = <&CPU0>; 223 }; 224 225 core1 { 226 cpu = <&CPU1>; 227 }; 228 229 core2 { 230 cpu = <&CPU2>; 231 }; 232 233 core3 { 234 cpu = <&CPU3>; 235 }; 236 }; 237 238 cluster1 { 239 core0 { 240 cpu = <&CPU4>; 241 }; 242 243 core1 { 244 cpu = <&CPU5>; 245 }; 246 247 core2 { 248 cpu = <&CPU6>; 249 }; 250 251 core3 { 252 cpu = <&CPU7>; 253 }; 254 }; 255 256 cluster2 { 257 core0 { 258 cpu = <&CPU8>; 259 }; 260 261 core1 { 262 cpu = <&CPU9>; 263 }; 264 265 core2 { 266 cpu = <&CPU10>; 267 }; 268 269 core3 { 270 cpu = <&CPU11>; 271 }; 272 }; 273 }; 274 275 idle-states { 276 entry-method = "psci"; 277 278 CLUSTER_C4: cpu-sleep-0 { 279 compatible = "arm,idle-state"; 280 idle-state-name = "ret"; 281 arm,psci-suspend-param = <0x00000004>; 282 entry-latency-us = <180>; 283 exit-latency-us = <500>; 284 min-residency-us = <600>; 285 }; 286 }; 287 288 domain-idle-states { 289 CLUSTER_CL4: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 idle-state-name = "l2-ret"; 292 arm,psci-suspend-param = <0x01000044>; 293 entry-latency-us = <350>; 294 exit-latency-us = <500>; 295 min-residency-us = <2500>; 296 }; 297 298 CLUSTER_CL5: cluster-sleep-1 { 299 compatible = "domain-idle-state"; 300 idle-state-name = "ret-pll-off"; 301 arm,psci-suspend-param = <0x01000054>; 302 entry-latency-us = <2200>; 303 exit-latency-us = <4000>; 304 min-residency-us = <7000>; 305 }; 306 }; 307 }; 308 309 firmware { 310 scm: scm { 311 compatible = "qcom,scm-x1e80100", "qcom,scm"; 312 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 314 }; 315 }; 316 317 clk_virt: interconnect-0 { 318 compatible = "qcom,x1e80100-clk-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 mc_virt: interconnect-1 { 324 compatible = "qcom,x1e80100-mc-virt"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 memory@80000000 { 330 device_type = "memory"; 331 /* We expect the bootloader to fill in the size */ 332 reg = <0 0x80000000 0 0>; 333 }; 334 335 pmu { 336 compatible = "arm,armv8-pmuv3"; 337 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 338 }; 339 340 psci { 341 compatible = "arm,psci-1.0"; 342 method = "smc"; 343 344 CPU_PD0: power-domain-cpu0 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD0>; 347 }; 348 349 CPU_PD1: power-domain-cpu1 { 350 #power-domain-cells = <0>; 351 power-domains = <&CLUSTER_PD0>; 352 }; 353 354 CPU_PD2: power-domain-cpu2 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD0>; 357 }; 358 359 CPU_PD3: power-domain-cpu3 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD0>; 362 }; 363 364 CPU_PD4: power-domain-cpu4 { 365 #power-domain-cells = <0>; 366 power-domains = <&CLUSTER_PD1>; 367 }; 368 369 CPU_PD5: power-domain-cpu5 { 370 #power-domain-cells = <0>; 371 power-domains = <&CLUSTER_PD1>; 372 }; 373 374 CPU_PD6: power-domain-cpu6 { 375 #power-domain-cells = <0>; 376 power-domains = <&CLUSTER_PD1>; 377 }; 378 379 CPU_PD7: power-domain-cpu7 { 380 #power-domain-cells = <0>; 381 power-domains = <&CLUSTER_PD1>; 382 }; 383 384 CPU_PD8: power-domain-cpu8 { 385 #power-domain-cells = <0>; 386 power-domains = <&CLUSTER_PD2>; 387 }; 388 389 CPU_PD9: power-domain-cpu9 { 390 #power-domain-cells = <0>; 391 power-domains = <&CLUSTER_PD2>; 392 }; 393 394 CPU_PD10: power-domain-cpu10 { 395 #power-domain-cells = <0>; 396 power-domains = <&CLUSTER_PD2>; 397 }; 398 399 CPU_PD11: power-domain-cpu11 { 400 #power-domain-cells = <0>; 401 power-domains = <&CLUSTER_PD2>; 402 }; 403 404 CLUSTER_PD0: power-domain-cpu-cluster0 { 405 #power-domain-cells = <0>; 406 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 407 power-domains = <&SYSTEM_PD>; 408 }; 409 410 CLUSTER_PD1: power-domain-cpu-cluster1 { 411 #power-domain-cells = <0>; 412 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 413 power-domains = <&SYSTEM_PD>; 414 }; 415 416 CLUSTER_PD2: power-domain-cpu-cluster2 { 417 #power-domain-cells = <0>; 418 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 419 power-domains = <&SYSTEM_PD>; 420 }; 421 422 SYSTEM_PD: power-domain-system { 423 #power-domain-cells = <0>; 424 /* TODO: system-wide idle states */ 425 }; 426 }; 427 428 reserved-memory { 429 #address-cells = <2>; 430 #size-cells = <2>; 431 ranges; 432 433 gunyah_hyp_mem: gunyah-hyp@80000000 { 434 reg = <0x0 0x80000000 0x0 0x800000>; 435 no-map; 436 }; 437 438 hyp_elf_package_mem: hyp-elf-package@80800000 { 439 reg = <0x0 0x80800000 0x0 0x200000>; 440 no-map; 441 }; 442 443 ncc_mem: ncc@80a00000 { 444 reg = <0x0 0x80a00000 0x0 0x400000>; 445 no-map; 446 }; 447 448 cpucp_log_mem: cpucp-log@80e00000 { 449 reg = <0x0 0x80e00000 0x0 0x40000>; 450 no-map; 451 }; 452 453 cpucp_mem: cpucp@80e40000 { 454 reg = <0x0 0x80e40000 0x0 0x540000>; 455 no-map; 456 }; 457 458 reserved-region@81380000 { 459 reg = <0x0 0x81380000 0x0 0x80000>; 460 no-map; 461 }; 462 463 tags_mem: tags-region@81400000 { 464 reg = <0x0 0x81400000 0x0 0x1a0000>; 465 no-map; 466 }; 467 468 xbl_dtlog_mem: xbl-dtlog@81a00000 { 469 reg = <0x0 0x81a00000 0x0 0x40000>; 470 no-map; 471 }; 472 473 xbl_ramdump_mem: xbl-ramdump@81a40000 { 474 reg = <0x0 0x81a40000 0x0 0x1c0000>; 475 no-map; 476 }; 477 478 aop_image_mem: aop-image@81c00000 { 479 reg = <0x0 0x81c00000 0x0 0x60000>; 480 no-map; 481 }; 482 483 aop_cmd_db_mem: aop-cmd-db@81c60000 { 484 compatible = "qcom,cmd-db"; 485 reg = <0x0 0x81c60000 0x0 0x20000>; 486 no-map; 487 }; 488 489 aop_config_mem: aop-config@81c80000 { 490 reg = <0x0 0x81c80000 0x0 0x20000>; 491 no-map; 492 }; 493 494 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 495 reg = <0x0 0x81ca0000 0x0 0x40000>; 496 no-map; 497 }; 498 499 tme_log_mem: tme-log@81ce0000 { 500 reg = <0x0 0x81ce0000 0x0 0x4000>; 501 no-map; 502 }; 503 504 uefi_log_mem: uefi-log@81ce4000 { 505 reg = <0x0 0x81ce4000 0x0 0x10000>; 506 no-map; 507 }; 508 509 secdata_apss_mem: secdata-apss@81cff000 { 510 reg = <0x0 0x81cff000 0x0 0x1000>; 511 no-map; 512 }; 513 514 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 515 reg = <0x0 0x81e00000 0x0 0x100000>; 516 no-map; 517 }; 518 519 gpu_prr_mem: gpu-prr@81f00000 { 520 reg = <0x0 0x81f00000 0x0 0x10000>; 521 no-map; 522 }; 523 524 tpm_control_mem: tpm-control@81f10000 { 525 reg = <0x0 0x81f10000 0x0 0x10000>; 526 no-map; 527 }; 528 529 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 530 reg = <0x0 0x81f20000 0x0 0x10000>; 531 no-map; 532 }; 533 534 pld_pep_mem: pld-pep@81f30000 { 535 reg = <0x0 0x81f30000 0x0 0x6000>; 536 no-map; 537 }; 538 539 pld_gmu_mem: pld-gmu@81f36000 { 540 reg = <0x0 0x81f36000 0x0 0x1000>; 541 no-map; 542 }; 543 544 pld_pdp_mem: pld-pdp@81f37000 { 545 reg = <0x0 0x81f37000 0x0 0x1000>; 546 no-map; 547 }; 548 549 tz_stat_mem: tz-stat@82700000 { 550 reg = <0x0 0x82700000 0x0 0x100000>; 551 no-map; 552 }; 553 554 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 555 reg = <0x0 0x82800000 0x0 0xc00000>; 556 no-map; 557 }; 558 559 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 560 reg = <0x0 0x84b00000 0x0 0x800000>; 561 no-map; 562 }; 563 564 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 565 reg = <0x0 0x85300000 0x0 0x80000>; 566 no-map; 567 }; 568 569 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 570 reg = <0x0 0x866c0000 0x0 0x40000>; 571 no-map; 572 }; 573 574 spss_region_mem: spss-region@86700000 { 575 reg = <0x0 0x86700000 0x0 0x400000>; 576 no-map; 577 }; 578 579 adsp_boot_mem: adsp-boot@86b00000 { 580 reg = <0x0 0x86b00000 0x0 0xc00000>; 581 no-map; 582 }; 583 584 video_mem: video@87700000 { 585 reg = <0x0 0x87700000 0x0 0x700000>; 586 no-map; 587 }; 588 589 adspslpi_mem: adspslpi@87e00000 { 590 reg = <0x0 0x87e00000 0x0 0x3a00000>; 591 no-map; 592 }; 593 594 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 595 reg = <0x0 0x8b800000 0x0 0x80000>; 596 no-map; 597 }; 598 599 cdsp_mem: cdsp@8b900000 { 600 reg = <0x0 0x8b900000 0x0 0x2000000>; 601 no-map; 602 }; 603 604 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 605 reg = <0x0 0x8d900000 0x0 0x80000>; 606 no-map; 607 }; 608 609 gpu_microcode_mem: gpu-microcode@8d9fe000 { 610 reg = <0x0 0x8d9fe000 0x0 0x2000>; 611 no-map; 612 }; 613 614 cvp_mem: cvp@8da00000 { 615 reg = <0x0 0x8da00000 0x0 0x700000>; 616 no-map; 617 }; 618 619 camera_mem: camera@8e100000 { 620 reg = <0x0 0x8e100000 0x0 0x800000>; 621 no-map; 622 }; 623 624 av1_encoder_mem: av1-encoder@8e900000 { 625 reg = <0x0 0x8e900000 0x0 0x700000>; 626 no-map; 627 }; 628 629 reserved-region@8f000000 { 630 reg = <0x0 0x8f000000 0x0 0xa00000>; 631 no-map; 632 }; 633 634 wpss_mem: wpss@8fa00000 { 635 reg = <0x0 0x8fa00000 0x0 0x1900000>; 636 no-map; 637 }; 638 639 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 640 reg = <0x0 0x91300000 0x0 0x80000>; 641 no-map; 642 }; 643 644 xbl_sc_mem: xbl-sc@d8000000 { 645 reg = <0x0 0xd8000000 0x0 0x40000>; 646 no-map; 647 }; 648 649 reserved-region@d8040000 { 650 reg = <0x0 0xd8040000 0x0 0xa0000>; 651 no-map; 652 }; 653 654 qtee_mem: qtee@d80e0000 { 655 reg = <0x0 0xd80e0000 0x0 0x520000>; 656 no-map; 657 }; 658 659 ta_mem: ta@d8600000 { 660 reg = <0x0 0xd8600000 0x0 0x8a00000>; 661 no-map; 662 }; 663 664 tags_mem1: tags@e1000000 { 665 reg = <0x0 0xe1000000 0x0 0x26a0000>; 666 no-map; 667 }; 668 669 llcc_lpi_mem: llcc-lpi@ff800000 { 670 reg = <0x0 0xff800000 0x0 0x600000>; 671 no-map; 672 }; 673 674 smem_mem: smem@ffe00000 { 675 compatible = "qcom,smem"; 676 reg = <0x0 0xffe00000 0x0 0x200000>; 677 hwlocks = <&tcsr_mutex 3>; 678 no-map; 679 }; 680 }; 681 682 smp2p-adsp { 683 compatible = "qcom,smp2p"; 684 685 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 689 mboxes = <&ipcc IPCC_CLIENT_LPASS 690 IPCC_MPROC_SIGNAL_SMP2P>; 691 692 qcom,smem = <443>, <429>; 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <2>; 695 696 smp2p_adsp_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 smp2p_adsp_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 }; 707 708 smp2p-cdsp { 709 compatible = "qcom,smp2p"; 710 711 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 712 IPCC_MPROC_SIGNAL_SMP2P 713 IRQ_TYPE_EDGE_RISING>; 714 715 mboxes = <&ipcc IPCC_CLIENT_CDSP 716 IPCC_MPROC_SIGNAL_SMP2P>; 717 718 qcom,smem = <94>, <432>; 719 qcom,local-pid = <0>; 720 qcom,remote-pid = <5>; 721 722 smp2p_cdsp_out: master-kernel { 723 qcom,entry-name = "master-kernel"; 724 #qcom,smem-state-cells = <1>; 725 }; 726 727 smp2p_cdsp_in: slave-kernel { 728 qcom,entry-name = "slave-kernel"; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 }; 732 }; 733 734 soc: soc@0 { 735 compatible = "simple-bus"; 736 737 #address-cells = <2>; 738 #size-cells = <2>; 739 dma-ranges = <0 0 0 0 0x10 0>; 740 ranges = <0 0 0 0 0x10 0>; 741 742 gcc: clock-controller@100000 { 743 compatible = "qcom,x1e80100-gcc"; 744 reg = <0 0x00100000 0 0x200000>; 745 746 clocks = <&bi_tcxo_div2>, 747 <&sleep_clk>, 748 <0>, 749 <&pcie4_phy>, 750 <&pcie5_phy>, 751 <&pcie6a_phy>, 752 <0>, 753 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 754 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 755 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 756 757 power-domains = <&rpmhpd RPMHPD_CX>; 758 #clock-cells = <1>; 759 #reset-cells = <1>; 760 #power-domain-cells = <1>; 761 }; 762 763 ipcc: mailbox@408000 { 764 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 765 reg = <0 0x00408000 0 0x1000>; 766 767 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-controller; 769 #interrupt-cells = <3>; 770 771 #mbox-cells = <2>; 772 }; 773 774 gpi_dma2: dma-controller@800000 { 775 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 776 reg = <0 0x00800000 0 0x60000>; 777 778 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 790 791 dma-channels = <12>; 792 dma-channel-mask = <0x3e>; 793 #dma-cells = <3>; 794 795 iommus = <&apps_smmu 0x436 0x0>; 796 797 status = "disabled"; 798 }; 799 800 qupv3_2: geniqup@8c0000 { 801 compatible = "qcom,geni-se-qup"; 802 reg = <0 0x008c0000 0 0x2000>; 803 804 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 805 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 806 clock-names = "m-ahb", 807 "s-ahb"; 808 809 iommus = <&apps_smmu 0x423 0x0>; 810 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges; 814 815 status = "disabled"; 816 817 i2c16: i2c@880000 { 818 compatible = "qcom,geni-i2c"; 819 reg = <0 0x00880000 0 0x4000>; 820 821 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 822 823 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 824 clock-names = "se"; 825 826 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 827 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 828 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 829 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 830 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 831 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 832 interconnect-names = "qup-core", 833 "qup-config", 834 "qup-memory"; 835 836 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 837 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 838 dma-names = "tx", 839 "rx"; 840 841 pinctrl-0 = <&qup_i2c16_data_clk>; 842 pinctrl-names = "default"; 843 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 status = "disabled"; 848 }; 849 850 spi16: spi@880000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x00880000 0 0x4000>; 853 854 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 855 856 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 857 clock-names = "se"; 858 859 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 860 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 861 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 862 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 863 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 864 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 865 interconnect-names = "qup-core", 866 "qup-config", 867 "qup-memory"; 868 869 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 870 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 871 dma-names = "tx", 872 "rx"; 873 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 875 pinctrl-names = "default"; 876 877 #address-cells = <1>; 878 #size-cells = <0>; 879 880 status = "disabled"; 881 }; 882 883 i2c17: i2c@884000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0 0x00884000 0 0x4000>; 886 887 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 888 889 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 890 clock-names = "se"; 891 892 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 893 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 895 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 896 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 897 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 898 interconnect-names = "qup-core", 899 "qup-config", 900 "qup-memory"; 901 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 903 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 904 dma-names = "tx", 905 "rx"; 906 907 pinctrl-0 = <&qup_i2c17_data_clk>; 908 pinctrl-names = "default"; 909 910 #address-cells = <1>; 911 #size-cells = <0>; 912 913 status = "disabled"; 914 }; 915 916 spi17: spi@884000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00884000 0 0x4000>; 919 920 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 921 922 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 923 clock-names = "se"; 924 925 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 926 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 927 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 928 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 929 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 930 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 931 interconnect-names = "qup-core", 932 "qup-config", 933 "qup-memory"; 934 935 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 936 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 937 dma-names = "tx", 938 "rx"; 939 940 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 941 pinctrl-names = "default"; 942 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 status = "disabled"; 947 }; 948 949 i2c18: i2c@888000 { 950 compatible = "qcom,geni-i2c"; 951 reg = <0 0x00888000 0 0x4000>; 952 953 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 954 955 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 956 clock-names = "se"; 957 958 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 959 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 960 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 961 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 962 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 963 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 964 interconnect-names = "qup-core", 965 "qup-config", 966 "qup-memory"; 967 968 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 969 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 970 dma-names = "tx", 971 "rx"; 972 973 pinctrl-0 = <&qup_i2c18_data_clk>; 974 pinctrl-names = "default"; 975 976 #address-cells = <1>; 977 #size-cells = <0>; 978 979 status = "disabled"; 980 }; 981 982 spi18: spi@888000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0 0x00888000 0 0x4000>; 985 986 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 987 988 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 989 clock-names = "se"; 990 991 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 992 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 993 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 994 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 995 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 997 interconnect-names = "qup-core", 998 "qup-config", 999 "qup-memory"; 1000 1001 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1002 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1003 dma-names = "tx", 1004 "rx"; 1005 1006 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1007 pinctrl-names = "default"; 1008 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 1012 status = "disabled"; 1013 }; 1014 1015 i2c19: i2c@88c000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x0088c000 0 0x4000>; 1018 1019 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1020 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1022 clock-names = "se"; 1023 1024 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1025 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1026 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1027 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1028 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1029 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1030 interconnect-names = "qup-core", 1031 "qup-config", 1032 "qup-memory"; 1033 1034 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1035 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1036 dma-names = "tx", 1037 "rx"; 1038 1039 pinctrl-0 = <&qup_i2c19_data_clk>; 1040 pinctrl-names = "default"; 1041 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 1045 status = "disabled"; 1046 }; 1047 1048 spi19: spi@88c000 { 1049 compatible = "qcom,geni-spi"; 1050 reg = <0 0x0088c000 0 0x4000>; 1051 1052 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1053 1054 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1055 clock-names = "se"; 1056 1057 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1058 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1060 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1061 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1063 interconnect-names = "qup-core", 1064 "qup-config", 1065 "qup-memory"; 1066 1067 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1068 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1069 dma-names = "tx", 1070 "rx"; 1071 1072 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1073 pinctrl-names = "default"; 1074 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 1078 status = "disabled"; 1079 }; 1080 1081 i2c20: i2c@890000 { 1082 compatible = "qcom,geni-i2c"; 1083 reg = <0 0x00890000 0 0x4000>; 1084 1085 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1086 1087 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1088 clock-names = "se"; 1089 1090 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1091 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1093 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1094 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1095 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1096 interconnect-names = "qup-core", 1097 "qup-config", 1098 "qup-memory"; 1099 1100 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1101 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1102 dma-names = "tx", 1103 "rx"; 1104 1105 pinctrl-0 = <&qup_i2c20_data_clk>; 1106 pinctrl-names = "default"; 1107 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 1111 status = "disabled"; 1112 }; 1113 1114 spi20: spi@890000 { 1115 compatible = "qcom,geni-spi"; 1116 reg = <0 0x00890000 0 0x4000>; 1117 1118 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1119 1120 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1121 clock-names = "se"; 1122 1123 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1124 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1126 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1127 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1129 interconnect-names = "qup-core", 1130 "qup-config", 1131 "qup-memory"; 1132 1133 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1134 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1135 dma-names = "tx", 1136 "rx"; 1137 1138 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1139 pinctrl-names = "default"; 1140 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 1144 status = "disabled"; 1145 }; 1146 1147 i2c21: i2c@894000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0 0x00894000 0 0x4000>; 1150 1151 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1152 1153 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1154 clock-names = "se"; 1155 1156 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1157 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1158 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1159 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1160 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1162 interconnect-names = "qup-core", 1163 "qup-config", 1164 "qup-memory"; 1165 1166 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1167 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1168 dma-names = "tx", 1169 "rx"; 1170 1171 pinctrl-0 = <&qup_i2c21_data_clk>; 1172 pinctrl-names = "default"; 1173 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 1177 status = "disabled"; 1178 }; 1179 1180 spi21: spi@894000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0 0x00894000 0 0x4000>; 1183 1184 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1185 1186 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1187 clock-names = "se"; 1188 1189 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1190 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1192 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1193 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1195 interconnect-names = "qup-core", 1196 "qup-config", 1197 "qup-memory"; 1198 1199 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1200 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1201 dma-names = "tx", 1202 "rx"; 1203 1204 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1205 pinctrl-names = "default"; 1206 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 1210 status = "disabled"; 1211 }; 1212 1213 uart21: serial@894000 { 1214 compatible = "qcom,geni-uart"; 1215 reg = <0 0x00894000 0 0x4000>; 1216 1217 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1218 1219 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1220 clock-names = "se"; 1221 1222 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1223 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1224 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1225 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1226 interconnect-names = "qup-core", 1227 "qup-config"; 1228 1229 pinctrl-0 = <&qup_uart21_default>; 1230 pinctrl-names = "default"; 1231 1232 status = "disabled"; 1233 }; 1234 1235 i2c22: i2c@898000 { 1236 compatible = "qcom,geni-i2c"; 1237 reg = <0 0x00898000 0 0x4000>; 1238 1239 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1240 1241 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1242 clock-names = "se"; 1243 1244 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1245 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1247 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1248 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1249 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1250 interconnect-names = "qup-core", 1251 "qup-config", 1252 "qup-memory"; 1253 1254 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1255 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1256 dma-names = "tx", 1257 "rx"; 1258 1259 pinctrl-0 = <&qup_i2c22_data_clk>; 1260 pinctrl-names = "default"; 1261 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 1265 status = "disabled"; 1266 }; 1267 1268 spi22: spi@898000 { 1269 compatible = "qcom,geni-spi"; 1270 reg = <0 0x00898000 0 0x4000>; 1271 1272 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1273 1274 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1275 clock-names = "se"; 1276 1277 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1280 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1281 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1283 interconnect-names = "qup-core", 1284 "qup-config", 1285 "qup-memory"; 1286 1287 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1288 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1289 dma-names = "tx", 1290 "rx"; 1291 1292 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1293 pinctrl-names = "default"; 1294 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 1298 status = "disabled"; 1299 }; 1300 1301 i2c23: i2c@89c000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x0089c000 0 0x4000>; 1304 1305 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1306 1307 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1308 clock-names = "se"; 1309 1310 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1311 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1312 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1313 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1314 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1316 interconnect-names = "qup-core", 1317 "qup-config", 1318 "qup-memory"; 1319 1320 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1321 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1322 dma-names = "tx", 1323 "rx"; 1324 1325 pinctrl-0 = <&qup_i2c23_data_clk>; 1326 pinctrl-names = "default"; 1327 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 status = "disabled"; 1332 }; 1333 1334 spi23: spi@89c000 { 1335 compatible = "qcom,geni-spi"; 1336 reg = <0 0x0089c000 0 0x4000>; 1337 1338 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1339 1340 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1341 clock-names = "se"; 1342 1343 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1344 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1346 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1347 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1349 interconnect-names = "qup-core", 1350 "qup-config", 1351 "qup-memory"; 1352 1353 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1354 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1355 dma-names = "tx", 1356 "rx"; 1357 1358 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1359 pinctrl-names = "default"; 1360 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 gpi_dma1: dma-controller@a00000 { 1369 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1370 reg = <0 0x00a00000 0 0x60000>; 1371 1372 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1384 1385 dma-channels = <12>; 1386 dma-channel-mask = <0x3e>; 1387 #dma-cells = <3>; 1388 1389 iommus = <&apps_smmu 0x136 0x0>; 1390 1391 status = "disabled"; 1392 }; 1393 1394 qupv3_1: geniqup@ac0000 { 1395 compatible = "qcom,geni-se-qup"; 1396 reg = <0 0x00ac0000 0 0x2000>; 1397 1398 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1399 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1400 clock-names = "m-ahb", 1401 "s-ahb"; 1402 1403 iommus = <&apps_smmu 0x123 0x0>; 1404 1405 #address-cells = <2>; 1406 #size-cells = <2>; 1407 ranges; 1408 1409 status = "disabled"; 1410 1411 i2c8: i2c@a80000 { 1412 compatible = "qcom,geni-i2c"; 1413 reg = <0 0x00a80000 0 0x4000>; 1414 1415 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1416 1417 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1418 clock-names = "se"; 1419 1420 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1421 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1422 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1423 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1424 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1425 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1426 interconnect-names = "qup-core", 1427 "qup-config", 1428 "qup-memory"; 1429 1430 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1431 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1432 dma-names = "tx", 1433 "rx"; 1434 1435 pinctrl-0 = <&qup_i2c8_data_clk>; 1436 pinctrl-names = "default"; 1437 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 1441 status = "disabled"; 1442 }; 1443 1444 spi8: spi@a80000 { 1445 compatible = "qcom,geni-spi"; 1446 reg = <0 0x00a80000 0 0x4000>; 1447 1448 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1449 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1451 clock-names = "se"; 1452 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1454 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1456 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1457 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1458 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1459 interconnect-names = "qup-core", 1460 "qup-config", 1461 "qup-memory"; 1462 1463 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1464 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1465 dma-names = "tx", 1466 "rx"; 1467 1468 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1469 pinctrl-names = "default"; 1470 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 1474 status = "disabled"; 1475 }; 1476 1477 i2c9: i2c@a84000 { 1478 compatible = "qcom,geni-i2c"; 1479 reg = <0 0x00a84000 0 0x4000>; 1480 1481 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1482 1483 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1484 clock-names = "se"; 1485 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1487 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1488 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1489 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1490 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1491 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1492 interconnect-names = "qup-core", 1493 "qup-config", 1494 "qup-memory"; 1495 1496 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1497 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1498 dma-names = "tx", 1499 "rx"; 1500 1501 pinctrl-0 = <&qup_i2c9_data_clk>; 1502 pinctrl-names = "default"; 1503 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 1507 status = "disabled"; 1508 }; 1509 1510 spi9: spi@a84000 { 1511 compatible = "qcom,geni-spi"; 1512 reg = <0 0x00a84000 0 0x4000>; 1513 1514 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1515 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 clock-names = "se"; 1518 1519 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1520 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1521 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1522 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1523 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1525 interconnect-names = "qup-core", 1526 "qup-config", 1527 "qup-memory"; 1528 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1530 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1531 dma-names = "tx", 1532 "rx"; 1533 1534 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1535 pinctrl-names = "default"; 1536 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 1540 status = "disabled"; 1541 }; 1542 1543 i2c10: i2c@a88000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00a88000 0 0x4000>; 1546 1547 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1548 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1550 clock-names = "se"; 1551 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1553 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1555 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1556 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1557 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1558 interconnect-names = "qup-core", 1559 "qup-config", 1560 "qup-memory"; 1561 1562 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1563 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1564 dma-names = "tx", 1565 "rx"; 1566 1567 pinctrl-0 = <&qup_i2c10_data_clk>; 1568 pinctrl-names = "default"; 1569 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 1573 status = "disabled"; 1574 }; 1575 1576 spi10: spi@a88000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00a88000 0 0x4000>; 1579 1580 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1581 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1583 clock-names = "se"; 1584 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1586 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1587 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1588 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1589 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1590 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1591 interconnect-names = "qup-core", 1592 "qup-config", 1593 "qup-memory"; 1594 1595 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1596 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1597 dma-names = "tx", 1598 "rx"; 1599 1600 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1601 pinctrl-names = "default"; 1602 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 1606 status = "disabled"; 1607 }; 1608 1609 i2c11: i2c@a8c000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0 0x00a8c000 0 0x4000>; 1612 1613 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1614 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1616 clock-names = "se"; 1617 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1619 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1621 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1622 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1623 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1624 interconnect-names = "qup-core", 1625 "qup-config", 1626 "qup-memory"; 1627 1628 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1629 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1630 dma-names = "tx", 1631 "rx"; 1632 1633 pinctrl-0 = <&qup_i2c11_data_clk>; 1634 pinctrl-names = "default"; 1635 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 1639 status = "disabled"; 1640 }; 1641 1642 spi11: spi@a8c000 { 1643 compatible = "qcom,geni-spi"; 1644 reg = <0 0x00a8c000 0 0x4000>; 1645 1646 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1647 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1649 clock-names = "se"; 1650 1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1652 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1654 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1655 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1656 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1657 interconnect-names = "qup-core", 1658 "qup-config", 1659 "qup-memory"; 1660 1661 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1662 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1663 dma-names = "tx", 1664 "rx"; 1665 1666 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1667 pinctrl-names = "default"; 1668 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 status = "disabled"; 1673 }; 1674 1675 i2c12: i2c@a90000 { 1676 compatible = "qcom,geni-i2c"; 1677 reg = <0 0x00a90000 0 0x4000>; 1678 1679 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1680 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1682 clock-names = "se"; 1683 1684 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1685 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1686 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1687 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1688 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1689 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1690 interconnect-names = "qup-core", 1691 "qup-config", 1692 "qup-memory"; 1693 1694 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1695 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1696 dma-names = "tx", 1697 "rx"; 1698 1699 pinctrl-0 = <&qup_i2c12_data_clk>; 1700 pinctrl-names = "default"; 1701 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 1705 status = "disabled"; 1706 }; 1707 1708 spi12: spi@a90000 { 1709 compatible = "qcom,geni-spi"; 1710 reg = <0 0x00a90000 0 0x4000>; 1711 1712 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1713 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1715 clock-names = "se"; 1716 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1718 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1719 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1720 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1721 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1723 interconnect-names = "qup-core", 1724 "qup-config", 1725 "qup-memory"; 1726 1727 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1728 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1729 dma-names = "tx", 1730 "rx"; 1731 1732 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1733 pinctrl-names = "default"; 1734 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 1738 status = "disabled"; 1739 }; 1740 1741 i2c13: i2c@a94000 { 1742 compatible = "qcom,geni-i2c"; 1743 reg = <0 0x00a94000 0 0x4000>; 1744 1745 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1746 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1748 clock-names = "se"; 1749 1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1751 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1752 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1753 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1754 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1755 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1756 interconnect-names = "qup-core", 1757 "qup-config", 1758 "qup-memory"; 1759 1760 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1761 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1762 dma-names = "tx", 1763 "rx"; 1764 1765 pinctrl-0 = <&qup_i2c13_data_clk>; 1766 pinctrl-names = "default"; 1767 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 1771 status = "disabled"; 1772 }; 1773 1774 spi13: spi@a94000 { 1775 compatible = "qcom,geni-spi"; 1776 reg = <0 0x00a94000 0 0x4000>; 1777 1778 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1779 1780 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1781 clock-names = "se"; 1782 1783 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1784 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1785 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1786 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1787 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1788 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1789 interconnect-names = "qup-core", 1790 "qup-config", 1791 "qup-memory"; 1792 1793 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1794 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1795 dma-names = "tx", 1796 "rx"; 1797 1798 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1799 pinctrl-names = "default"; 1800 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 1804 status = "disabled"; 1805 }; 1806 1807 i2c14: i2c@a98000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0 0x00a98000 0 0x4000>; 1810 1811 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1812 1813 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1814 clock-names = "se"; 1815 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1817 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1818 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1819 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1820 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1821 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1822 interconnect-names = "qup-core", 1823 "qup-config", 1824 "qup-memory"; 1825 1826 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1827 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1828 dma-names = "tx", 1829 "rx"; 1830 1831 pinctrl-0 = <&qup_i2c14_data_clk>; 1832 pinctrl-names = "default"; 1833 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 1837 status = "disabled"; 1838 }; 1839 1840 spi14: spi@a98000 { 1841 compatible = "qcom,geni-spi"; 1842 reg = <0 0x00a98000 0 0x4000>; 1843 1844 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1845 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1847 clock-names = "se"; 1848 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", 1856 "qup-config", 1857 "qup-memory"; 1858 1859 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1860 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1861 dma-names = "tx", 1862 "rx"; 1863 1864 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1865 pinctrl-names = "default"; 1866 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 1870 status = "disabled"; 1871 }; 1872 1873 i2c15: i2c@a9c000 { 1874 compatible = "qcom,geni-i2c"; 1875 reg = <0 0x00a9c000 0 0x4000>; 1876 1877 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1878 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1880 clock-names = "se"; 1881 1882 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1883 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1884 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1885 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1886 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1888 interconnect-names = "qup-core", 1889 "qup-config", 1890 "qup-memory"; 1891 1892 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1893 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1894 dma-names = "tx", 1895 "rx"; 1896 1897 pinctrl-0 = <&qup_i2c15_data_clk>; 1898 pinctrl-names = "default"; 1899 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 1903 status = "disabled"; 1904 }; 1905 1906 spi15: spi@a9c000 { 1907 compatible = "qcom,geni-spi"; 1908 reg = <0 0x00a9c000 0 0x4000>; 1909 1910 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1911 1912 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1913 clock-names = "se"; 1914 1915 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1916 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1917 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1918 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1919 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1920 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1921 interconnect-names = "qup-core", 1922 "qup-config", 1923 "qup-memory"; 1924 1925 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1926 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1927 dma-names = "tx", 1928 "rx"; 1929 1930 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1931 pinctrl-names = "default"; 1932 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 1936 status = "disabled"; 1937 }; 1938 }; 1939 1940 gpi_dma0: dma-controller@b00000 { 1941 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1942 reg = <0 0x00b00000 0 0x60000>; 1943 1944 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1956 1957 dma-channels = <12>; 1958 dma-channel-mask = <0x3e>; 1959 #dma-cells = <3>; 1960 1961 iommus = <&apps_smmu 0x456 0x0>; 1962 1963 status = "disabled"; 1964 }; 1965 1966 qupv3_0: geniqup@bc0000 { 1967 compatible = "qcom,geni-se-qup"; 1968 reg = <0 0x00bc0000 0 0x2000>; 1969 1970 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1971 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1972 clock-names = "m-ahb", 1973 "s-ahb"; 1974 1975 iommus = <&apps_smmu 0x443 0x0>; 1976 #address-cells = <2>; 1977 #size-cells = <2>; 1978 ranges; 1979 1980 status = "disabled"; 1981 1982 i2c0: i2c@b80000 { 1983 compatible = "qcom,geni-i2c"; 1984 reg = <0 0x00b80000 0 0x4000>; 1985 1986 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1987 1988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1989 clock-names = "se"; 1990 1991 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1992 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1993 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1994 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1995 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1997 interconnect-names = "qup-core", 1998 "qup-config", 1999 "qup-memory"; 2000 2001 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2002 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2003 dma-names = "tx", 2004 "rx"; 2005 2006 pinctrl-0 = <&qup_i2c0_data_clk>; 2007 pinctrl-names = "default"; 2008 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 2012 status = "disabled"; 2013 }; 2014 2015 spi0: spi@b80000 { 2016 compatible = "qcom,geni-spi"; 2017 reg = <0 0x00b80000 0 0x4000>; 2018 2019 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2020 2021 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2022 clock-names = "se"; 2023 2024 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2025 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2026 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2027 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2028 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2029 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2030 interconnect-names = "qup-core", 2031 "qup-config", 2032 "qup-memory"; 2033 2034 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2035 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2036 dma-names = "tx", 2037 "rx"; 2038 2039 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2040 pinctrl-names = "default"; 2041 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 2045 status = "disabled"; 2046 }; 2047 2048 i2c1: i2c@b84000 { 2049 compatible = "qcom,geni-i2c"; 2050 reg = <0 0x00b84000 0 0x4000>; 2051 2052 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2053 2054 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2055 clock-names = "se"; 2056 2057 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2058 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2060 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2061 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2063 interconnect-names = "qup-core", 2064 "qup-config", 2065 "qup-memory"; 2066 2067 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2068 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2069 dma-names = "tx", 2070 "rx"; 2071 2072 pinctrl-0 = <&qup_i2c1_data_clk>; 2073 pinctrl-names = "default"; 2074 2075 #address-cells = <1>; 2076 #size-cells = <0>; 2077 2078 status = "disabled"; 2079 }; 2080 2081 spi1: spi@b84000 { 2082 compatible = "qcom,geni-spi"; 2083 reg = <0 0x00b84000 0 0x4000>; 2084 2085 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2086 2087 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2088 clock-names = "se"; 2089 2090 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2091 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2093 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2094 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2095 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2096 interconnect-names = "qup-core", 2097 "qup-config", 2098 "qup-memory"; 2099 2100 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2101 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2102 dma-names = "tx", 2103 "rx"; 2104 2105 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2106 pinctrl-names = "default"; 2107 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 2111 status = "disabled"; 2112 }; 2113 2114 i2c2: i2c@b88000 { 2115 compatible = "qcom,geni-i2c"; 2116 reg = <0 0x00b88000 0 0x4000>; 2117 2118 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2119 2120 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2121 clock-names = "se"; 2122 2123 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2124 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2126 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2127 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2129 interconnect-names = "qup-core", 2130 "qup-config", 2131 "qup-memory"; 2132 2133 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2134 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2135 dma-names = "tx", 2136 "rx"; 2137 2138 pinctrl-0 = <&qup_i2c2_data_clk>; 2139 pinctrl-names = "default"; 2140 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 2144 status = "disabled"; 2145 }; 2146 2147 uart2: serial@b88000 { 2148 compatible = "qcom,geni-uart"; 2149 reg = <0 0x00b88000 0 0x4000>; 2150 2151 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2152 2153 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2154 clock-names = "se"; 2155 2156 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2157 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2158 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2159 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2160 interconnect-names = "qup-core", 2161 "qup-config"; 2162 2163 pinctrl-0 = <&qup_uart2_default>; 2164 pinctrl-names = "default"; 2165 2166 status = "disabled"; 2167 }; 2168 2169 spi2: spi@b88000 { 2170 compatible = "qcom,geni-spi"; 2171 reg = <0 0x00b88000 0 0x4000>; 2172 2173 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2174 2175 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2176 clock-names = "se"; 2177 2178 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2179 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2181 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2182 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2183 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2184 interconnect-names = "qup-core", 2185 "qup-config", 2186 "qup-memory"; 2187 2188 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2189 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2190 dma-names = "tx", 2191 "rx"; 2192 2193 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2194 pinctrl-names = "default"; 2195 2196 #address-cells = <1>; 2197 #size-cells = <0>; 2198 2199 status = "disabled"; 2200 }; 2201 2202 i2c3: i2c@b8c000 { 2203 compatible = "qcom,geni-i2c"; 2204 reg = <0 0x00b8c000 0 0x4000>; 2205 2206 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2207 2208 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2209 clock-names = "se"; 2210 2211 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2212 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2214 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2215 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2217 interconnect-names = "qup-core", 2218 "qup-config", 2219 "qup-memory"; 2220 2221 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2222 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2223 dma-names = "tx", 2224 "rx"; 2225 2226 pinctrl-0 = <&qup_i2c3_data_clk>; 2227 pinctrl-names = "default"; 2228 2229 #address-cells = <1>; 2230 #size-cells = <0>; 2231 2232 status = "disabled"; 2233 }; 2234 2235 spi3: spi@b8c000 { 2236 compatible = "qcom,geni-spi"; 2237 reg = <0 0x00b8c000 0 0x4000>; 2238 2239 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2240 2241 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2242 clock-names = "se"; 2243 2244 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2245 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2246 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2247 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2248 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2249 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2250 interconnect-names = "qup-core", 2251 "qup-config", 2252 "qup-memory"; 2253 2254 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2255 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2256 dma-names = "tx", 2257 "rx"; 2258 2259 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2260 pinctrl-names = "default"; 2261 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 2265 status = "disabled"; 2266 }; 2267 2268 i2c4: i2c@b90000 { 2269 compatible = "qcom,geni-i2c"; 2270 reg = <0 0x00b90000 0 0x4000>; 2271 2272 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2275 clock-names = "se"; 2276 2277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2280 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2281 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2283 interconnect-names = "qup-core", 2284 "qup-config", 2285 "qup-memory"; 2286 2287 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2288 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2289 dma-names = "tx", 2290 "rx"; 2291 2292 pinctrl-0 = <&qup_i2c4_data_clk>; 2293 pinctrl-names = "default"; 2294 2295 #address-cells = <1>; 2296 #size-cells = <0>; 2297 2298 status = "disabled"; 2299 }; 2300 2301 spi4: spi@b90000 { 2302 compatible = "qcom,geni-spi"; 2303 reg = <0 0x00b90000 0 0x4000>; 2304 2305 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2306 2307 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2308 clock-names = "se"; 2309 2310 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2311 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2312 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2313 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2314 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2316 interconnect-names = "qup-core", 2317 "qup-config", 2318 "qup-memory"; 2319 2320 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2321 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2322 dma-names = "tx", 2323 "rx"; 2324 2325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2326 pinctrl-names = "default"; 2327 2328 #address-cells = <1>; 2329 #size-cells = <0>; 2330 2331 status = "disabled"; 2332 }; 2333 2334 i2c5: i2c@b94000 { 2335 compatible = "qcom,geni-i2c"; 2336 reg = <0 0x00b94000 0 0x4000>; 2337 2338 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2339 2340 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2341 clock-names = "se"; 2342 2343 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2344 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2346 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2347 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2349 interconnect-names = "qup-core", 2350 "qup-config", 2351 "qup-memory"; 2352 2353 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2354 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2355 dma-names = "tx", 2356 "rx"; 2357 2358 pinctrl-0 = <&qup_i2c5_data_clk>; 2359 pinctrl-names = "default"; 2360 2361 #address-cells = <1>; 2362 #size-cells = <0>; 2363 2364 status = "disabled"; 2365 }; 2366 2367 spi5: spi@b94000 { 2368 compatible = "qcom,geni-spi"; 2369 reg = <0 0x00b94000 0 0x4000>; 2370 2371 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2372 2373 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2374 clock-names = "se"; 2375 2376 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2377 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2378 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2379 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2380 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2382 interconnect-names = "qup-core", 2383 "qup-config", 2384 "qup-memory"; 2385 2386 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2387 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2388 dma-names = "tx", 2389 "rx"; 2390 2391 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2392 pinctrl-names = "default"; 2393 2394 #address-cells = <1>; 2395 #size-cells = <0>; 2396 2397 status = "disabled"; 2398 }; 2399 2400 i2c6: i2c@b98000 { 2401 compatible = "qcom,geni-i2c"; 2402 reg = <0 0x00b98000 0 0x4000>; 2403 2404 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2405 2406 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2407 clock-names = "se"; 2408 2409 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2410 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2412 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2413 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2415 interconnect-names = "qup-core", 2416 "qup-config", 2417 "qup-memory"; 2418 2419 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2420 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2421 dma-names = "tx", 2422 "rx"; 2423 2424 pinctrl-0 = <&qup_i2c6_data_clk>; 2425 pinctrl-names = "default"; 2426 2427 #address-cells = <1>; 2428 #size-cells = <0>; 2429 2430 status = "disabled"; 2431 }; 2432 2433 spi6: spi@b98000 { 2434 compatible = "qcom,geni-spi"; 2435 reg = <0 0x00b98000 0 0x4000>; 2436 2437 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2438 2439 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2440 clock-names = "se"; 2441 2442 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2443 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2444 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2445 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2446 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2448 interconnect-names = "qup-core", 2449 "qup-config", 2450 "qup-memory"; 2451 2452 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2453 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2454 dma-names = "tx", 2455 "rx"; 2456 2457 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2458 pinctrl-names = "default"; 2459 2460 #address-cells = <1>; 2461 #size-cells = <0>; 2462 2463 status = "disabled"; 2464 }; 2465 2466 i2c7: i2c@b9c000 { 2467 compatible = "qcom,geni-i2c"; 2468 reg = <0 0x00b9c000 0 0x4000>; 2469 2470 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2471 2472 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2473 clock-names = "se"; 2474 2475 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2476 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2477 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2478 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2479 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2480 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2481 interconnect-names = "qup-core", 2482 "qup-config", 2483 "qup-memory"; 2484 2485 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2486 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2487 dma-names = "tx", 2488 "rx"; 2489 2490 pinctrl-0 = <&qup_i2c7_data_clk>; 2491 pinctrl-names = "default"; 2492 2493 #address-cells = <1>; 2494 #size-cells = <0>; 2495 2496 status = "disabled"; 2497 }; 2498 2499 spi7: spi@b9c000 { 2500 compatible = "qcom,geni-spi"; 2501 reg = <0 0x00b9c000 0 0x4000>; 2502 2503 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2504 2505 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2506 clock-names = "se"; 2507 2508 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2509 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2511 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2512 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2513 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2514 interconnect-names = "qup-core", 2515 "qup-config", 2516 "qup-memory"; 2517 2518 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2519 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2520 dma-names = "tx", 2521 "rx"; 2522 2523 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2524 pinctrl-names = "default"; 2525 2526 #address-cells = <1>; 2527 #size-cells = <0>; 2528 2529 status = "disabled"; 2530 }; 2531 }; 2532 2533 tsens0: thermal-sensor@c271000 { 2534 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2535 reg = <0 0x0c271000 0 0x1000>, 2536 <0 0x0c222000 0 0x1000>; 2537 2538 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2539 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2540 interrupt-names = "uplow", 2541 "critical"; 2542 2543 #qcom,sensors = <16>; 2544 2545 #thermal-sensor-cells = <1>; 2546 }; 2547 2548 tsens1: thermal-sensor@c272000 { 2549 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2550 reg = <0 0x0c272000 0 0x1000>, 2551 <0 0x0c223000 0 0x1000>; 2552 2553 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2554 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2555 interrupt-names = "uplow", 2556 "critical"; 2557 2558 #qcom,sensors = <16>; 2559 2560 #thermal-sensor-cells = <1>; 2561 }; 2562 2563 tsens2: thermal-sensor@c273000 { 2564 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2565 reg = <0 0x0c273000 0 0x1000>, 2566 <0 0x0c224000 0 0x1000>; 2567 2568 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2569 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2570 interrupt-names = "uplow", 2571 "critical"; 2572 2573 #qcom,sensors = <16>; 2574 2575 #thermal-sensor-cells = <1>; 2576 }; 2577 2578 tsens3: thermal-sensor@c274000 { 2579 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2580 reg = <0 0x0c274000 0 0x1000>, 2581 <0 0x0c225000 0 0x1000>; 2582 2583 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2584 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2585 interrupt-names = "uplow", 2586 "critical"; 2587 2588 #qcom,sensors = <16>; 2589 2590 #thermal-sensor-cells = <1>; 2591 }; 2592 2593 usb_1_ss0_hsphy: phy@fd3000 { 2594 compatible = "qcom,x1e80100-snps-eusb2-phy", 2595 "qcom,sm8550-snps-eusb2-phy"; 2596 reg = <0 0x00fd3000 0 0x154>; 2597 #phy-cells = <0>; 2598 2599 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2600 clock-names = "ref"; 2601 2602 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2603 2604 status = "disabled"; 2605 }; 2606 2607 usb_1_ss0_qmpphy: phy@fd5000 { 2608 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2609 reg = <0 0x00fd5000 0 0x4000>; 2610 2611 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2612 <&rpmhcc RPMH_CXO_CLK>, 2613 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2614 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2615 clock-names = "aux", 2616 "ref", 2617 "com_aux", 2618 "usb3_pipe"; 2619 2620 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2621 2622 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2623 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2624 reset-names = "phy", 2625 "common"; 2626 2627 #clock-cells = <1>; 2628 #phy-cells = <1>; 2629 2630 orientation-switch; 2631 2632 status = "disabled"; 2633 2634 ports { 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 port@0 { 2639 reg = <0>; 2640 2641 usb_1_ss0_qmpphy_out: endpoint { 2642 }; 2643 }; 2644 2645 port@1 { 2646 reg = <1>; 2647 2648 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2649 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2650 }; 2651 }; 2652 2653 port@2 { 2654 reg = <2>; 2655 2656 usb_1_ss0_qmpphy_dp_in: endpoint { 2657 remote-endpoint = <&mdss_dp0_out>; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 usb_1_ss1_hsphy: phy@fd9000 { 2664 compatible = "qcom,x1e80100-snps-eusb2-phy", 2665 "qcom,sm8550-snps-eusb2-phy"; 2666 reg = <0 0x00fd9000 0 0x154>; 2667 #phy-cells = <0>; 2668 2669 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2670 clock-names = "ref"; 2671 2672 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2673 2674 status = "disabled"; 2675 }; 2676 2677 usb_1_ss1_qmpphy: phy@fda000 { 2678 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2679 reg = <0 0x00fda000 0 0x4000>; 2680 2681 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2682 <&rpmhcc RPMH_CXO_CLK>, 2683 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2684 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2685 clock-names = "aux", 2686 "ref", 2687 "com_aux", 2688 "usb3_pipe"; 2689 2690 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2691 2692 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2693 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2694 reset-names = "phy", 2695 "common"; 2696 2697 #clock-cells = <1>; 2698 #phy-cells = <1>; 2699 2700 orientation-switch; 2701 2702 status = "disabled"; 2703 2704 ports { 2705 #address-cells = <1>; 2706 #size-cells = <0>; 2707 2708 port@0 { 2709 reg = <0>; 2710 2711 usb_1_ss1_qmpphy_out: endpoint { 2712 }; 2713 }; 2714 2715 port@1 { 2716 reg = <1>; 2717 2718 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2719 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2720 }; 2721 }; 2722 2723 port@2 { 2724 reg = <2>; 2725 2726 usb_1_ss1_qmpphy_dp_in: endpoint { 2727 remote-endpoint = <&mdss_dp1_out>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 usb_1_ss2_hsphy: phy@fde000 { 2734 compatible = "qcom,x1e80100-snps-eusb2-phy", 2735 "qcom,sm8550-snps-eusb2-phy"; 2736 reg = <0 0x00fde000 0 0x154>; 2737 #phy-cells = <0>; 2738 2739 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2740 clock-names = "ref"; 2741 2742 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2743 2744 status = "disabled"; 2745 }; 2746 2747 usb_1_ss2_qmpphy: phy@fdf000 { 2748 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2749 reg = <0 0x00fdf000 0 0x4000>; 2750 2751 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2752 <&rpmhcc RPMH_CXO_CLK>, 2753 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2754 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2755 clock-names = "aux", 2756 "ref", 2757 "com_aux", 2758 "usb3_pipe"; 2759 2760 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2761 2762 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2763 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2764 reset-names = "phy", 2765 "common"; 2766 2767 #clock-cells = <1>; 2768 #phy-cells = <1>; 2769 2770 orientation-switch; 2771 2772 status = "disabled"; 2773 2774 ports { 2775 #address-cells = <1>; 2776 #size-cells = <0>; 2777 2778 port@0 { 2779 reg = <0>; 2780 2781 usb_1_ss2_qmpphy_out: endpoint { 2782 }; 2783 }; 2784 2785 port@1 { 2786 reg = <1>; 2787 2788 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 2789 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 2790 }; 2791 }; 2792 2793 port@2 { 2794 reg = <2>; 2795 2796 usb_1_ss2_qmpphy_dp_in: endpoint { 2797 remote-endpoint = <&mdss_dp2_out>; 2798 }; 2799 }; 2800 }; 2801 }; 2802 2803 cnoc_main: interconnect@1500000 { 2804 compatible = "qcom,x1e80100-cnoc-main"; 2805 reg = <0 0x01500000 0 0x14400>; 2806 2807 qcom,bcm-voters = <&apps_bcm_voter>; 2808 2809 #interconnect-cells = <2>; 2810 }; 2811 2812 config_noc: interconnect@1600000 { 2813 compatible = "qcom,x1e80100-cnoc-cfg"; 2814 reg = <0 0x01600000 0 0x6600>; 2815 2816 qcom,bcm-voters = <&apps_bcm_voter>; 2817 2818 #interconnect-cells = <2>; 2819 }; 2820 2821 system_noc: interconnect@1680000 { 2822 compatible = "qcom,x1e80100-system-noc"; 2823 reg = <0 0x01680000 0 0x1c080>; 2824 2825 qcom,bcm-voters = <&apps_bcm_voter>; 2826 2827 #interconnect-cells = <2>; 2828 }; 2829 2830 pcie_south_anoc: interconnect@16c0000 { 2831 compatible = "qcom,x1e80100-pcie-south-anoc"; 2832 reg = <0 0x016c0000 0 0xd080>; 2833 2834 qcom,bcm-voters = <&apps_bcm_voter>; 2835 2836 #interconnect-cells = <2>; 2837 }; 2838 2839 pcie_center_anoc: interconnect@16d0000 { 2840 compatible = "qcom,x1e80100-pcie-center-anoc"; 2841 reg = <0 0x016d0000 0 0x7000>; 2842 2843 qcom,bcm-voters = <&apps_bcm_voter>; 2844 2845 #interconnect-cells = <2>; 2846 }; 2847 2848 aggre1_noc: interconnect@16e0000 { 2849 compatible = "qcom,x1e80100-aggre1-noc"; 2850 reg = <0 0x016e0000 0 0x14400>; 2851 2852 qcom,bcm-voters = <&apps_bcm_voter>; 2853 2854 #interconnect-cells = <2>; 2855 }; 2856 2857 aggre2_noc: interconnect@1700000 { 2858 compatible = "qcom,x1e80100-aggre2-noc"; 2859 reg = <0 0x01700000 0 0x1c400>; 2860 2861 qcom,bcm-voters = <&apps_bcm_voter>; 2862 2863 #interconnect-cells = <2>; 2864 }; 2865 2866 pcie_north_anoc: interconnect@1740000 { 2867 compatible = "qcom,x1e80100-pcie-north-anoc"; 2868 reg = <0 0x01740000 0 0x9080>; 2869 2870 qcom,bcm-voters = <&apps_bcm_voter>; 2871 2872 #interconnect-cells = <2>; 2873 }; 2874 2875 usb_center_anoc: interconnect@1750000 { 2876 compatible = "qcom,x1e80100-usb-center-anoc"; 2877 reg = <0 0x01750000 0 0x8800>; 2878 2879 qcom,bcm-voters = <&apps_bcm_voter>; 2880 2881 #interconnect-cells = <2>; 2882 }; 2883 2884 usb_north_anoc: interconnect@1760000 { 2885 compatible = "qcom,x1e80100-usb-north-anoc"; 2886 reg = <0 0x01760000 0 0x7080>; 2887 2888 qcom,bcm-voters = <&apps_bcm_voter>; 2889 2890 #interconnect-cells = <2>; 2891 }; 2892 2893 usb_south_anoc: interconnect@1770000 { 2894 compatible = "qcom,x1e80100-usb-south-anoc"; 2895 reg = <0 0x01770000 0 0xf080>; 2896 2897 qcom,bcm-voters = <&apps_bcm_voter>; 2898 2899 #interconnect-cells = <2>; 2900 }; 2901 2902 mmss_noc: interconnect@1780000 { 2903 compatible = "qcom,x1e80100-mmss-noc"; 2904 reg = <0 0x01780000 0 0x5B800>; 2905 2906 qcom,bcm-voters = <&apps_bcm_voter>; 2907 2908 #interconnect-cells = <2>; 2909 }; 2910 2911 pcie6a: pci@1bf8000 { 2912 device_type = "pci"; 2913 compatible = "qcom,pcie-x1e80100"; 2914 reg = <0 0x01bf8000 0 0x3000>, 2915 <0 0x70000000 0 0xf20>, 2916 <0 0x70000f40 0 0xa8>, 2917 <0 0x70001000 0 0x1000>, 2918 <0 0x70100000 0 0x100000>, 2919 <0 0x01bfb000 0 0x1000>; 2920 reg-names = "parf", 2921 "dbi", 2922 "elbi", 2923 "atu", 2924 "config", 2925 "mhi"; 2926 #address-cells = <3>; 2927 #size-cells = <2>; 2928 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 2929 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2930 bus-range = <0x00 0xff>; 2931 2932 dma-coherent; 2933 2934 linux,pci-domain = <6>; 2935 num-lanes = <4>; 2936 2937 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2945 interrupt-names = "msi0", 2946 "msi1", 2947 "msi2", 2948 "msi3", 2949 "msi4", 2950 "msi5", 2951 "msi6", 2952 "msi7"; 2953 2954 #interrupt-cells = <1>; 2955 interrupt-map-mask = <0 0 0 0x7>; 2956 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 2957 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 2958 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 2959 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 2960 2961 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 2962 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2963 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 2964 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 2965 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 2966 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 2967 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 2968 clock-names = "aux", 2969 "cfg", 2970 "bus_master", 2971 "bus_slave", 2972 "slave_q2a", 2973 "noc_aggr", 2974 "cnoc_sf_axi"; 2975 2976 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 2977 assigned-clock-rates = <19200000>; 2978 2979 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 2980 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2981 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2982 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 2983 interconnect-names = "pcie-mem", 2984 "cpu-pcie"; 2985 2986 resets = <&gcc GCC_PCIE_6A_BCR>, 2987 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 2988 reset-names = "pci", 2989 "link_down"; 2990 2991 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 2992 required-opps = <&rpmhpd_opp_nom>; 2993 2994 phys = <&pcie6a_phy>; 2995 phy-names = "pciephy"; 2996 2997 status = "disabled"; 2998 }; 2999 3000 pcie6a_phy: phy@1bfc000 { 3001 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3002 reg = <0 0x01bfc000 0 0x2000>, 3003 <0 0x01bfe000 0 0x2000>; 3004 3005 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3006 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3007 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3008 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3009 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3010 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3011 clock-names = "aux", 3012 "cfg_ahb", 3013 "ref", 3014 "rchng", 3015 "pipe", 3016 "pipediv2"; 3017 3018 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3019 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3020 reset-names = "phy", 3021 "phy_nocsr"; 3022 3023 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3024 assigned-clock-rates = <100000000>; 3025 3026 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3027 3028 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3029 3030 #clock-cells = <0>; 3031 clock-output-names = "pcie6a_pipe_clk"; 3032 3033 #phy-cells = <0>; 3034 3035 status = "disabled"; 3036 }; 3037 3038 pcie5: pci@1c00000 { 3039 device_type = "pci"; 3040 compatible = "qcom,pcie-x1e80100"; 3041 reg = <0 0x01c00000 0 0x3000>, 3042 <0 0x7e000000 0 0xf1d>, 3043 <0 0x7e000f40 0 0xa8>, 3044 <0 0x7e001000 0 0x1000>, 3045 <0 0x7e100000 0 0x100000>, 3046 <0 0x01c03000 0 0x1000>; 3047 reg-names = "parf", 3048 "dbi", 3049 "elbi", 3050 "atu", 3051 "config", 3052 "mhi"; 3053 #address-cells = <3>; 3054 #size-cells = <2>; 3055 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3056 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3057 bus-range = <0x00 0xff>; 3058 3059 dma-coherent; 3060 3061 linux,pci-domain = <5>; 3062 num-lanes = <2>; 3063 3064 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3072 interrupt-names = "msi0", 3073 "msi1", 3074 "msi2", 3075 "msi3", 3076 "msi4", 3077 "msi5", 3078 "msi6", 3079 "msi7"; 3080 3081 #interrupt-cells = <1>; 3082 interrupt-map-mask = <0 0 0 0x7>; 3083 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 3084 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, 3085 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, 3086 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; 3087 3088 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3089 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3090 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3091 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3092 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3093 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3094 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3095 clock-names = "aux", 3096 "cfg", 3097 "bus_master", 3098 "bus_slave", 3099 "slave_q2a", 3100 "noc_aggr", 3101 "cnoc_sf_axi"; 3102 3103 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3104 assigned-clock-rates = <19200000>; 3105 3106 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3107 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3108 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3109 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3110 interconnect-names = "pcie-mem", 3111 "cpu-pcie"; 3112 3113 resets = <&gcc GCC_PCIE_5_BCR>, 3114 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3115 reset-names = "pci", 3116 "link_down"; 3117 3118 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3119 required-opps = <&rpmhpd_opp_nom>; 3120 3121 phys = <&pcie5_phy>; 3122 phy-names = "pciephy"; 3123 3124 status = "disabled"; 3125 }; 3126 3127 pcie5_phy: phy@1c06000 { 3128 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3129 reg = <0 0x01c06000 0 0x2000>; 3130 3131 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3132 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3133 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3134 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3135 <&gcc GCC_PCIE_5_PIPE_CLK>, 3136 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3137 clock-names = "aux", 3138 "cfg_ahb", 3139 "ref", 3140 "rchng", 3141 "pipe", 3142 "pipediv2"; 3143 3144 resets = <&gcc GCC_PCIE_5_PHY_BCR>; 3145 reset-names = "phy"; 3146 3147 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3148 assigned-clock-rates = <100000000>; 3149 3150 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3151 3152 #clock-cells = <0>; 3153 clock-output-names = "pcie5_pipe_clk"; 3154 3155 #phy-cells = <0>; 3156 3157 status = "disabled"; 3158 }; 3159 3160 pcie4: pci@1c08000 { 3161 device_type = "pci"; 3162 compatible = "qcom,pcie-x1e80100"; 3163 reg = <0 0x01c08000 0 0x3000>, 3164 <0 0x7c000000 0 0xf1d>, 3165 <0 0x7c000f40 0 0xa8>, 3166 <0 0x7c001000 0 0x1000>, 3167 <0 0x7c100000 0 0x100000>, 3168 <0 0x01c0b000 0 0x1000>; 3169 reg-names = "parf", 3170 "dbi", 3171 "elbi", 3172 "atu", 3173 "config", 3174 "mhi"; 3175 #address-cells = <3>; 3176 #size-cells = <2>; 3177 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3178 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3179 bus-range = <0x00 0xff>; 3180 3181 dma-coherent; 3182 3183 linux,pci-domain = <4>; 3184 num-lanes = <2>; 3185 3186 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3194 interrupt-names = "msi0", 3195 "msi1", 3196 "msi2", 3197 "msi3", 3198 "msi4", 3199 "msi5", 3200 "msi6", 3201 "msi7"; 3202 3203 #interrupt-cells = <1>; 3204 interrupt-map-mask = <0 0 0 0x7>; 3205 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3206 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3207 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3208 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3209 3210 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3211 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3212 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3213 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3214 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3215 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3216 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3217 clock-names = "aux", 3218 "cfg", 3219 "bus_master", 3220 "bus_slave", 3221 "slave_q2a", 3222 "noc_aggr", 3223 "cnoc_sf_axi"; 3224 3225 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3226 assigned-clock-rates = <19200000>; 3227 3228 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3231 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 3232 interconnect-names = "pcie-mem", 3233 "cpu-pcie"; 3234 3235 resets = <&gcc GCC_PCIE_4_BCR>, 3236 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3237 reset-names = "pci", 3238 "link_down"; 3239 3240 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3241 required-opps = <&rpmhpd_opp_nom>; 3242 3243 phys = <&pcie4_phy>; 3244 phy-names = "pciephy"; 3245 3246 status = "disabled"; 3247 3248 pcie4_port0: pcie@0 { 3249 device_type = "pci"; 3250 reg = <0x0 0x0 0x0 0x0 0x0>; 3251 bus-range = <0x01 0xff>; 3252 3253 #address-cells = <3>; 3254 #size-cells = <2>; 3255 ranges; 3256 }; 3257 }; 3258 3259 pcie4_phy: phy@1c0e000 { 3260 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3261 reg = <0 0x01c0e000 0 0x2000>; 3262 3263 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3264 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3265 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3266 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3267 <&gcc GCC_PCIE_4_PIPE_CLK>, 3268 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3269 clock-names = "aux", 3270 "cfg_ahb", 3271 "ref", 3272 "rchng", 3273 "pipe", 3274 "pipediv2"; 3275 3276 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 3277 reset-names = "phy"; 3278 3279 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3280 assigned-clock-rates = <100000000>; 3281 3282 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3283 3284 #clock-cells = <0>; 3285 clock-output-names = "pcie4_pipe_clk"; 3286 3287 #phy-cells = <0>; 3288 3289 status = "disabled"; 3290 }; 3291 3292 tcsr_mutex: hwlock@1f40000 { 3293 compatible = "qcom,tcsr-mutex"; 3294 reg = <0 0x01f40000 0 0x20000>; 3295 #hwlock-cells = <1>; 3296 }; 3297 3298 tcsr: clock-controller@1fc0000 { 3299 compatible = "qcom,x1e80100-tcsr", "syscon"; 3300 reg = <0 0x01fc0000 0 0x30000>; 3301 clocks = <&rpmhcc RPMH_CXO_CLK>; 3302 #clock-cells = <1>; 3303 #reset-cells = <1>; 3304 }; 3305 3306 gpu: gpu@3d00000 { 3307 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3308 reg = <0x0 0x03d00000 0x0 0x40000>, 3309 <0x0 0x03d9e000 0x0 0x1000>, 3310 <0x0 0x03d61000 0x0 0x800>; 3311 3312 reg-names = "kgsl_3d0_reg_memory", 3313 "cx_mem", 3314 "cx_dbgc"; 3315 3316 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3317 3318 iommus = <&adreno_smmu 0 0x0>, 3319 <&adreno_smmu 1 0x0>; 3320 3321 operating-points-v2 = <&gpu_opp_table>; 3322 3323 qcom,gmu = <&gmu>; 3324 #cooling-cells = <2>; 3325 3326 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3327 interconnect-names = "gfx-mem"; 3328 3329 status = "disabled"; 3330 3331 zap-shader { 3332 memory-region = <&gpu_microcode_mem>; 3333 }; 3334 3335 gpu_opp_table: opp-table { 3336 compatible = "operating-points-v2"; 3337 3338 opp-1100000000 { 3339 opp-hz = /bits/ 64 <1100000000>; 3340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3341 opp-peak-kBps = <16500000>; 3342 }; 3343 3344 opp-1000000000 { 3345 opp-hz = /bits/ 64 <1000000000>; 3346 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3347 opp-peak-kBps = <14398438>; 3348 }; 3349 3350 opp-925000000 { 3351 opp-hz = /bits/ 64 <925000000>; 3352 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3353 opp-peak-kBps = <14398438>; 3354 }; 3355 3356 opp-800000000 { 3357 opp-hz = /bits/ 64 <800000000>; 3358 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3359 opp-peak-kBps = <12449219>; 3360 }; 3361 3362 opp-744000000 { 3363 opp-hz = /bits/ 64 <744000000>; 3364 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3365 opp-peak-kBps = <10687500>; 3366 }; 3367 3368 opp-687000000 { 3369 opp-hz = /bits/ 64 <687000000>; 3370 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3371 opp-peak-kBps = <8171875>; 3372 }; 3373 3374 opp-550000000 { 3375 opp-hz = /bits/ 64 <550000000>; 3376 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3377 opp-peak-kBps = <6074219>; 3378 }; 3379 3380 opp-390000000 { 3381 opp-hz = /bits/ 64 <390000000>; 3382 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3383 opp-peak-kBps = <3000000>; 3384 }; 3385 3386 opp-300000000 { 3387 opp-hz = /bits/ 64 <300000000>; 3388 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3389 opp-peak-kBps = <2136719>; 3390 }; 3391 }; 3392 }; 3393 3394 gmu: gmu@3d6a000 { 3395 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3396 reg = <0x0 0x03d6a000 0x0 0x35000>, 3397 <0x0 0x03d50000 0x0 0x10000>, 3398 <0x0 0x0b280000 0x0 0x10000>; 3399 reg-names = "gmu", "rscc", "gmu_pdc"; 3400 3401 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3403 interrupt-names = "hfi", "gmu"; 3404 3405 clocks = <&gpucc GPU_CC_AHB_CLK>, 3406 <&gpucc GPU_CC_CX_GMU_CLK>, 3407 <&gpucc GPU_CC_CXO_CLK>, 3408 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3409 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3410 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3411 <&gpucc GPU_CC_DEMET_CLK>; 3412 clock-names = "ahb", 3413 "gmu", 3414 "cxo", 3415 "axi", 3416 "memnoc", 3417 "hub", 3418 "demet"; 3419 3420 power-domains = <&gpucc GPU_CX_GDSC>, 3421 <&gpucc GPU_GX_GDSC>; 3422 power-domain-names = "cx", 3423 "gx"; 3424 3425 iommus = <&adreno_smmu 5 0x0>; 3426 3427 qcom,qmp = <&aoss_qmp>; 3428 3429 operating-points-v2 = <&gmu_opp_table>; 3430 3431 gmu_opp_table: opp-table { 3432 compatible = "operating-points-v2"; 3433 3434 opp-550000000 { 3435 opp-hz = /bits/ 64 <550000000>; 3436 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3437 }; 3438 3439 opp-220000000 { 3440 opp-hz = /bits/ 64 <220000000>; 3441 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3442 }; 3443 }; 3444 }; 3445 3446 gpucc: clock-controller@3d90000 { 3447 compatible = "qcom,x1e80100-gpucc"; 3448 reg = <0 0x03d90000 0 0xa000>; 3449 clocks = <&bi_tcxo_div2>, 3450 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3451 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3452 #clock-cells = <1>; 3453 #reset-cells = <1>; 3454 #power-domain-cells = <1>; 3455 }; 3456 3457 adreno_smmu: iommu@3da0000 { 3458 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3459 "qcom,smmu-500", "arm,mmu-500"; 3460 reg = <0x0 0x03da0000 0x0 0x40000>; 3461 #iommu-cells = <2>; 3462 #global-interrupts = <1>; 3463 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3489 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3490 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3491 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3492 <&gpucc GPU_CC_AHB_CLK>; 3493 clock-names = "hlos", 3494 "bus", 3495 "iface", 3496 "ahb"; 3497 power-domains = <&gpucc GPU_CX_GDSC>; 3498 dma-coherent; 3499 }; 3500 3501 gem_noc: interconnect@26400000 { 3502 compatible = "qcom,x1e80100-gem-noc"; 3503 reg = <0 0x26400000 0 0x311200>; 3504 3505 qcom,bcm-voters = <&apps_bcm_voter>; 3506 3507 #interconnect-cells = <2>; 3508 }; 3509 3510 nsp_noc: interconnect@320c0000 { 3511 compatible = "qcom,x1e80100-nsp-noc"; 3512 reg = <0 0x320C0000 0 0xe080>; 3513 3514 qcom,bcm-voters = <&apps_bcm_voter>; 3515 3516 #interconnect-cells = <2>; 3517 }; 3518 3519 remoteproc_adsp: remoteproc@6800000 { 3520 compatible = "qcom,x1e80100-adsp-pas"; 3521 reg = <0x0 0x06800000 0x0 0x10000>; 3522 3523 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3524 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3525 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3526 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3527 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3528 interrupt-names = "wdog", 3529 "fatal", 3530 "ready", 3531 "handover", 3532 "stop-ack"; 3533 3534 clocks = <&rpmhcc RPMH_CXO_CLK>; 3535 clock-names = "xo"; 3536 3537 power-domains = <&rpmhpd RPMHPD_LCX>, 3538 <&rpmhpd RPMHPD_LMX>; 3539 power-domain-names = "lcx", 3540 "lmx"; 3541 3542 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3544 3545 memory-region = <&adspslpi_mem>, 3546 <&q6_adsp_dtb_mem>; 3547 3548 qcom,qmp = <&aoss_qmp>; 3549 3550 qcom,smem-states = <&smp2p_adsp_out 0>; 3551 qcom,smem-state-names = "stop"; 3552 3553 status = "disabled"; 3554 3555 glink-edge { 3556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3557 IPCC_MPROC_SIGNAL_GLINK_QMP 3558 IRQ_TYPE_EDGE_RISING>; 3559 mboxes = <&ipcc IPCC_CLIENT_LPASS 3560 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3561 3562 label = "lpass"; 3563 qcom,remote-pid = <2>; 3564 3565 fastrpc { 3566 compatible = "qcom,fastrpc"; 3567 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3568 label = "adsp"; 3569 qcom,non-secure-domain; 3570 #address-cells = <1>; 3571 #size-cells = <0>; 3572 3573 compute-cb@3 { 3574 compatible = "qcom,fastrpc-compute-cb"; 3575 reg = <3>; 3576 iommus = <&apps_smmu 0x1003 0x80>, 3577 <&apps_smmu 0x1063 0x0>; 3578 dma-coherent; 3579 }; 3580 3581 compute-cb@4 { 3582 compatible = "qcom,fastrpc-compute-cb"; 3583 reg = <4>; 3584 iommus = <&apps_smmu 0x1004 0x80>, 3585 <&apps_smmu 0x1064 0x0>; 3586 dma-coherent; 3587 }; 3588 3589 compute-cb@5 { 3590 compatible = "qcom,fastrpc-compute-cb"; 3591 reg = <5>; 3592 iommus = <&apps_smmu 0x1005 0x80>, 3593 <&apps_smmu 0x1065 0x0>; 3594 dma-coherent; 3595 }; 3596 3597 compute-cb@6 { 3598 compatible = "qcom,fastrpc-compute-cb"; 3599 reg = <6>; 3600 iommus = <&apps_smmu 0x1006 0x80>, 3601 <&apps_smmu 0x1066 0x0>; 3602 dma-coherent; 3603 }; 3604 3605 compute-cb@7 { 3606 compatible = "qcom,fastrpc-compute-cb"; 3607 reg = <7>; 3608 iommus = <&apps_smmu 0x1007 0x80>, 3609 <&apps_smmu 0x1067 0x0>; 3610 dma-coherent; 3611 }; 3612 }; 3613 3614 gpr { 3615 compatible = "qcom,gpr"; 3616 qcom,glink-channels = "adsp_apps"; 3617 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3618 qcom,intents = <512 20>; 3619 #address-cells = <1>; 3620 #size-cells = <0>; 3621 3622 q6apm: service@1 { 3623 compatible = "qcom,q6apm"; 3624 reg = <GPR_APM_MODULE_IID>; 3625 #sound-dai-cells = <0>; 3626 qcom,protection-domain = "avs/audio", 3627 "msm/adsp/audio_pd"; 3628 3629 q6apmbedai: bedais { 3630 compatible = "qcom,q6apm-lpass-dais"; 3631 #sound-dai-cells = <1>; 3632 }; 3633 3634 q6apmdai: dais { 3635 compatible = "qcom,q6apm-dais"; 3636 iommus = <&apps_smmu 0x1001 0x80>, 3637 <&apps_smmu 0x1061 0x0>; 3638 }; 3639 }; 3640 3641 q6prm: service@2 { 3642 compatible = "qcom,q6prm"; 3643 reg = <GPR_PRM_MODULE_IID>; 3644 qcom,protection-domain = "avs/audio", 3645 "msm/adsp/audio_pd"; 3646 3647 q6prmcc: clock-controller { 3648 compatible = "qcom,q6prm-lpass-clocks"; 3649 #clock-cells = <2>; 3650 }; 3651 }; 3652 }; 3653 }; 3654 }; 3655 3656 lpass_wsa2macro: codec@6aa0000 { 3657 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3658 reg = <0 0x06aa0000 0 0x1000>; 3659 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3660 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3661 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3662 <&lpass_vamacro>; 3663 clock-names = "mclk", 3664 "macro", 3665 "dcodec", 3666 "fsgen"; 3667 3668 #clock-cells = <0>; 3669 clock-output-names = "wsa2-mclk"; 3670 #sound-dai-cells = <1>; 3671 sound-name-prefix = "WSA2"; 3672 }; 3673 3674 swr3: soundwire@6ab0000 { 3675 compatible = "qcom,soundwire-v2.0.0"; 3676 reg = <0 0x06ab0000 0 0x10000>; 3677 clocks = <&lpass_wsa2macro>; 3678 clock-names = "iface"; 3679 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3680 label = "WSA2"; 3681 3682 pinctrl-0 = <&wsa2_swr_active>; 3683 pinctrl-names = "default"; 3684 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 3685 reset-names = "swr_audio_cgcr"; 3686 3687 qcom,din-ports = <4>; 3688 qcom,dout-ports = <9>; 3689 3690 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3691 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3692 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3693 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3694 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3695 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3696 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3697 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3698 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3699 3700 #address-cells = <2>; 3701 #size-cells = <0>; 3702 #sound-dai-cells = <1>; 3703 status = "disabled"; 3704 }; 3705 3706 lpass_rxmacro: codec@6ac0000 { 3707 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3708 reg = <0 0x06ac0000 0 0x1000>; 3709 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3710 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3711 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3712 <&lpass_vamacro>; 3713 clock-names = "mclk", 3714 "macro", 3715 "dcodec", 3716 "fsgen"; 3717 3718 #clock-cells = <0>; 3719 clock-output-names = "mclk"; 3720 #sound-dai-cells = <1>; 3721 }; 3722 3723 swr1: soundwire@6ad0000 { 3724 compatible = "qcom,soundwire-v2.0.0"; 3725 reg = <0 0x06ad0000 0 0x10000>; 3726 clocks = <&lpass_rxmacro>; 3727 clock-names = "iface"; 3728 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3729 label = "RX"; 3730 3731 pinctrl-0 = <&rx_swr_active>; 3732 pinctrl-names = "default"; 3733 3734 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3735 reset-names = "swr_audio_cgcr"; 3736 qcom,din-ports = <1>; 3737 qcom,dout-ports = <11>; 3738 3739 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3740 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3741 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3742 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3743 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3744 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3745 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3746 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3747 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3748 3749 #address-cells = <2>; 3750 #size-cells = <0>; 3751 #sound-dai-cells = <1>; 3752 status = "disabled"; 3753 }; 3754 3755 lpass_txmacro: codec@6ae0000 { 3756 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3757 reg = <0 0x06ae0000 0 0x1000>; 3758 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3759 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3760 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3761 <&lpass_vamacro>; 3762 clock-names = "mclk", 3763 "macro", 3764 "dcodec", 3765 "fsgen"; 3766 3767 #clock-cells = <0>; 3768 clock-output-names = "mclk"; 3769 #sound-dai-cells = <1>; 3770 }; 3771 3772 lpass_wsamacro: codec@6b00000 { 3773 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3774 reg = <0 0x06b00000 0 0x1000>; 3775 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3776 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3777 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3778 <&lpass_vamacro>; 3779 clock-names = "mclk", 3780 "macro", 3781 "dcodec", 3782 "fsgen"; 3783 3784 #clock-cells = <0>; 3785 clock-output-names = "mclk"; 3786 #sound-dai-cells = <1>; 3787 sound-name-prefix = "WSA"; 3788 }; 3789 3790 swr0: soundwire@6b10000 { 3791 compatible = "qcom,soundwire-v2.0.0"; 3792 reg = <0 0x06b10000 0 0x10000>; 3793 clocks = <&lpass_wsamacro>; 3794 clock-names = "iface"; 3795 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3796 label = "WSA"; 3797 3798 pinctrl-0 = <&wsa_swr_active>; 3799 pinctrl-names = "default"; 3800 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3801 reset-names = "swr_audio_cgcr"; 3802 3803 qcom,din-ports = <4>; 3804 qcom,dout-ports = <9>; 3805 3806 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3807 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3808 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3809 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3810 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3811 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3812 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3813 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3814 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3815 3816 #address-cells = <2>; 3817 #size-cells = <0>; 3818 #sound-dai-cells = <1>; 3819 status = "disabled"; 3820 }; 3821 3822 lpass_audiocc: clock-controller@6b6c000 { 3823 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 3824 reg = <0 0x06b6c000 0 0x1000>; 3825 #clock-cells = <1>; 3826 #reset-cells = <1>; 3827 }; 3828 3829 swr2: soundwire@6d30000 { 3830 compatible = "qcom,soundwire-v2.0.0"; 3831 reg = <0 0x06d30000 0 0x10000>; 3832 clocks = <&lpass_txmacro>; 3833 clock-names = "iface"; 3834 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3836 interrupt-names = "core", "wakeup"; 3837 label = "TX"; 3838 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3839 reset-names = "swr_audio_cgcr"; 3840 3841 pinctrl-0 = <&tx_swr_active>; 3842 pinctrl-names = "default"; 3843 3844 qcom,din-ports = <4>; 3845 qcom,dout-ports = <1>; 3846 3847 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 3848 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 3849 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 3850 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3851 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3852 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3853 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3854 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3855 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 3856 3857 #address-cells = <2>; 3858 #size-cells = <0>; 3859 #sound-dai-cells = <1>; 3860 status = "disabled"; 3861 }; 3862 3863 lpass_vamacro: codec@6d44000 { 3864 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3865 reg = <0 0x06d44000 0 0x1000>; 3866 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3867 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3868 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3869 clock-names = "mclk", 3870 "macro", 3871 "dcodec"; 3872 3873 #clock-cells = <0>; 3874 clock-output-names = "fsgen"; 3875 #sound-dai-cells = <1>; 3876 }; 3877 3878 lpass_tlmm: pinctrl@6e80000 { 3879 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 3880 reg = <0 0x06e80000 0 0x20000>, 3881 <0 0x07250000 0 0x10000>; 3882 3883 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3884 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3885 clock-names = "core", "audio"; 3886 3887 gpio-controller; 3888 #gpio-cells = <2>; 3889 gpio-ranges = <&lpass_tlmm 0 0 23>; 3890 3891 tx_swr_active: tx-swr-active-state { 3892 clk-pins { 3893 pins = "gpio0"; 3894 function = "swr_tx_clk"; 3895 drive-strength = <2>; 3896 slew-rate = <1>; 3897 bias-disable; 3898 }; 3899 3900 data-pins { 3901 pins = "gpio1", "gpio2"; 3902 function = "swr_tx_data"; 3903 drive-strength = <2>; 3904 slew-rate = <1>; 3905 bias-bus-hold; 3906 }; 3907 }; 3908 3909 rx_swr_active: rx-swr-active-state { 3910 clk-pins { 3911 pins = "gpio3"; 3912 function = "swr_rx_clk"; 3913 drive-strength = <2>; 3914 slew-rate = <1>; 3915 bias-disable; 3916 }; 3917 3918 data-pins { 3919 pins = "gpio4", "gpio5"; 3920 function = "swr_rx_data"; 3921 drive-strength = <2>; 3922 slew-rate = <1>; 3923 bias-bus-hold; 3924 }; 3925 }; 3926 3927 dmic01_default: dmic01-default-state { 3928 clk-pins { 3929 pins = "gpio6"; 3930 function = "dmic1_clk"; 3931 drive-strength = <8>; 3932 output-high; 3933 }; 3934 3935 data-pins { 3936 pins = "gpio7"; 3937 function = "dmic1_data"; 3938 drive-strength = <8>; 3939 input-enable; 3940 }; 3941 }; 3942 3943 dmic23_default: dmic23-default-state { 3944 clk-pins { 3945 pins = "gpio8"; 3946 function = "dmic2_clk"; 3947 drive-strength = <8>; 3948 output-high; 3949 }; 3950 3951 data-pins { 3952 pins = "gpio9"; 3953 function = "dmic2_data"; 3954 drive-strength = <8>; 3955 input-enable; 3956 }; 3957 }; 3958 3959 wsa_swr_active: wsa-swr-active-state { 3960 clk-pins { 3961 pins = "gpio10"; 3962 function = "wsa_swr_clk"; 3963 drive-strength = <2>; 3964 slew-rate = <1>; 3965 bias-disable; 3966 }; 3967 3968 data-pins { 3969 pins = "gpio11"; 3970 function = "wsa_swr_data"; 3971 drive-strength = <2>; 3972 slew-rate = <1>; 3973 bias-bus-hold; 3974 }; 3975 }; 3976 3977 wsa2_swr_active: wsa2-swr-active-state { 3978 clk-pins { 3979 pins = "gpio15"; 3980 function = "wsa2_swr_clk"; 3981 drive-strength = <2>; 3982 slew-rate = <1>; 3983 bias-disable; 3984 }; 3985 3986 data-pins { 3987 pins = "gpio16"; 3988 function = "wsa2_swr_data"; 3989 drive-strength = <2>; 3990 slew-rate = <1>; 3991 bias-bus-hold; 3992 }; 3993 }; 3994 }; 3995 3996 lpasscc: clock-controller@6ea0000 { 3997 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 3998 reg = <0 0x06ea0000 0 0x12000>; 3999 #clock-cells = <1>; 4000 #reset-cells = <1>; 4001 }; 4002 4003 lpass_ag_noc: interconnect@7e40000 { 4004 compatible = "qcom,x1e80100-lpass-ag-noc"; 4005 reg = <0 0x07e40000 0 0xe080>; 4006 4007 qcom,bcm-voters = <&apps_bcm_voter>; 4008 4009 #interconnect-cells = <2>; 4010 }; 4011 4012 lpass_lpiaon_noc: interconnect@7400000 { 4013 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4014 reg = <0 0x07400000 0 0x19080>; 4015 4016 qcom,bcm-voters = <&apps_bcm_voter>; 4017 4018 #interconnect-cells = <2>; 4019 }; 4020 4021 lpass_lpicx_noc: interconnect@7430000 { 4022 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4023 reg = <0 0x07430000 0 0x3A200>; 4024 4025 qcom,bcm-voters = <&apps_bcm_voter>; 4026 4027 #interconnect-cells = <2>; 4028 }; 4029 4030 usb_2_hsphy: phy@88e0000 { 4031 compatible = "qcom,x1e80100-snps-eusb2-phy", 4032 "qcom,sm8550-snps-eusb2-phy"; 4033 reg = <0 0x088e0000 0 0x154>; 4034 #phy-cells = <0>; 4035 4036 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4037 clock-names = "ref"; 4038 4039 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4040 4041 status = "disabled"; 4042 }; 4043 4044 usb_mp_hsphy0: phy@88e1000 { 4045 compatible = "qcom,x1e80100-snps-eusb2-phy", 4046 "qcom,sm8550-snps-eusb2-phy"; 4047 reg = <0 0x088e1000 0 0x154>; 4048 #phy-cells = <0>; 4049 4050 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4051 clock-names = "ref"; 4052 4053 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4054 4055 status = "disabled"; 4056 }; 4057 4058 usb_mp_hsphy1: phy@88e2000 { 4059 compatible = "qcom,x1e80100-snps-eusb2-phy", 4060 "qcom,sm8550-snps-eusb2-phy"; 4061 reg = <0 0x088e2000 0 0x154>; 4062 #phy-cells = <0>; 4063 4064 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4065 clock-names = "ref"; 4066 4067 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4068 4069 status = "disabled"; 4070 }; 4071 4072 usb_mp_qmpphy0: phy@88e3000 { 4073 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4074 reg = <0 0x088e3000 0 0x2000>; 4075 4076 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4077 <&rpmhcc RPMH_CXO_CLK>, 4078 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4079 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4080 clock-names = "aux", 4081 "ref", 4082 "com_aux", 4083 "pipe"; 4084 4085 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4086 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4087 reset-names = "phy", 4088 "phy_phy"; 4089 4090 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4091 4092 #clock-cells = <0>; 4093 clock-output-names = "usb_mp_phy0_pipe_clk"; 4094 4095 #phy-cells = <0>; 4096 4097 status = "disabled"; 4098 }; 4099 4100 usb_mp_qmpphy1: phy@88e5000 { 4101 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4102 reg = <0 0x088e5000 0 0x2000>; 4103 4104 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4105 <&rpmhcc RPMH_CXO_CLK>, 4106 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4107 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4108 clock-names = "aux", 4109 "ref", 4110 "com_aux", 4111 "pipe"; 4112 4113 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4114 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4115 reset-names = "phy", 4116 "phy_phy"; 4117 4118 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4119 4120 #clock-cells = <0>; 4121 clock-output-names = "usb_mp_phy1_pipe_clk"; 4122 4123 #phy-cells = <0>; 4124 4125 status = "disabled"; 4126 }; 4127 4128 usb_1_ss2: usb@a0f8800 { 4129 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4130 reg = <0 0x0a0f8800 0 0x400>; 4131 4132 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4133 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4134 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4135 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4136 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4137 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4138 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4139 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4140 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4141 clock-names = "cfg_noc", 4142 "core", 4143 "iface", 4144 "sleep", 4145 "mock_utmi", 4146 "noc_aggr", 4147 "noc_aggr_north", 4148 "noc_aggr_south", 4149 "noc_sys"; 4150 4151 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4152 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4153 assigned-clock-rates = <19200000>, 4154 <200000000>; 4155 4156 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4157 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4158 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4159 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4160 interrupt-names = "pwr_event", 4161 "dp_hs_phy_irq", 4162 "dm_hs_phy_irq", 4163 "ss_phy_irq"; 4164 4165 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4166 required-opps = <&rpmhpd_opp_nom>; 4167 4168 resets = <&gcc GCC_USB30_TERT_BCR>; 4169 4170 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4173 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 4174 interconnect-names = "usb-ddr", 4175 "apps-usb"; 4176 4177 wakeup-source; 4178 4179 #address-cells = <2>; 4180 #size-cells = <2>; 4181 ranges; 4182 4183 status = "disabled"; 4184 4185 usb_1_ss2_dwc3: usb@a000000 { 4186 compatible = "snps,dwc3"; 4187 reg = <0 0x0a000000 0 0xcd00>; 4188 4189 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4190 4191 iommus = <&apps_smmu 0x14a0 0x0>; 4192 4193 phys = <&usb_1_ss2_hsphy>, 4194 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4195 phy-names = "usb2-phy", 4196 "usb3-phy"; 4197 4198 snps,dis_u2_susphy_quirk; 4199 snps,dis_enblslpm_quirk; 4200 snps,usb3_lpm_capable; 4201 4202 dma-coherent; 4203 4204 ports { 4205 #address-cells = <1>; 4206 #size-cells = <0>; 4207 4208 port@0 { 4209 reg = <0>; 4210 4211 usb_1_ss2_dwc3_hs: endpoint { 4212 }; 4213 }; 4214 4215 port@1 { 4216 reg = <1>; 4217 4218 usb_1_ss2_dwc3_ss: endpoint { 4219 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4220 }; 4221 }; 4222 }; 4223 }; 4224 }; 4225 4226 usb_2: usb@a2f8800 { 4227 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4228 reg = <0 0x0a2f8800 0 0x400>; 4229 #address-cells = <2>; 4230 #size-cells = <2>; 4231 ranges; 4232 4233 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4234 <&gcc GCC_USB20_MASTER_CLK>, 4235 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4236 <&gcc GCC_USB20_SLEEP_CLK>, 4237 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4238 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4239 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4240 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4241 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4242 clock-names = "cfg_noc", 4243 "core", 4244 "iface", 4245 "sleep", 4246 "mock_utmi", 4247 "noc_aggr", 4248 "noc_aggr_north", 4249 "noc_aggr_south", 4250 "noc_sys"; 4251 4252 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4253 <&gcc GCC_USB20_MASTER_CLK>; 4254 assigned-clock-rates = <19200000>, <200000000>; 4255 4256 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4257 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4258 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4259 interrupt-names = "pwr_event", 4260 "dp_hs_phy_irq", 4261 "dm_hs_phy_irq"; 4262 4263 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4264 required-opps = <&rpmhpd_opp_nom>; 4265 4266 resets = <&gcc GCC_USB20_PRIM_BCR>; 4267 4268 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4269 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4270 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4271 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4272 interconnect-names = "usb-ddr", 4273 "apps-usb"; 4274 4275 wakeup-source; 4276 4277 status = "disabled"; 4278 4279 usb_2_dwc3: usb@a200000 { 4280 compatible = "snps,dwc3"; 4281 reg = <0 0x0a200000 0 0xcd00>; 4282 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4283 iommus = <&apps_smmu 0x14e0 0x0>; 4284 phys = <&usb_2_hsphy>; 4285 phy-names = "usb2-phy"; 4286 maximum-speed = "high-speed"; 4287 4288 dma-coherent; 4289 4290 ports { 4291 #address-cells = <1>; 4292 #size-cells = <0>; 4293 4294 port@0 { 4295 reg = <0>; 4296 4297 usb_2_dwc3_hs: endpoint { 4298 }; 4299 }; 4300 }; 4301 }; 4302 }; 4303 4304 usb_mp: usb@a4f8800 { 4305 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4306 reg = <0 0x0a4f8800 0 0x400>; 4307 4308 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4309 <&gcc GCC_USB30_MP_MASTER_CLK>, 4310 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4311 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4312 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4313 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4314 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4315 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4316 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4317 clock-names = "cfg_noc", 4318 "core", 4319 "iface", 4320 "sleep", 4321 "mock_utmi", 4322 "noc_aggr", 4323 "noc_aggr_north", 4324 "noc_aggr_south", 4325 "noc_sys"; 4326 4327 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4328 <&gcc GCC_USB30_MP_MASTER_CLK>; 4329 assigned-clock-rates = <19200000>, 4330 <200000000>; 4331 4332 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4333 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4334 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4335 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4336 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4337 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4338 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4339 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4340 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4341 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4342 interrupt-names = "pwr_event_1", "pwr_event_2", 4343 "hs_phy_1", "hs_phy_2", 4344 "dp_hs_phy_1", "dm_hs_phy_1", 4345 "dp_hs_phy_2", "dm_hs_phy_2", 4346 "ss_phy_1", "ss_phy_2"; 4347 4348 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4349 required-opps = <&rpmhpd_opp_nom>; 4350 4351 resets = <&gcc GCC_USB30_MP_BCR>; 4352 4353 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 4354 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4356 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; 4357 interconnect-names = "usb-ddr", 4358 "apps-usb"; 4359 4360 wakeup-source; 4361 4362 #address-cells = <2>; 4363 #size-cells = <2>; 4364 ranges; 4365 4366 status = "disabled"; 4367 4368 usb_mp_dwc3: usb@a400000 { 4369 compatible = "snps,dwc3"; 4370 reg = <0 0x0a400000 0 0xcd00>; 4371 4372 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 4373 4374 iommus = <&apps_smmu 0x1400 0x0>; 4375 4376 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 4377 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 4378 phy-names = "usb2-0", "usb3-0", 4379 "usb2-1", "usb3-1"; 4380 dr_mode = "host"; 4381 4382 snps,dis_u2_susphy_quirk; 4383 snps,dis_enblslpm_quirk; 4384 snps,usb3_lpm_capable; 4385 4386 dma-coherent; 4387 }; 4388 }; 4389 4390 usb_1_ss0: usb@a6f8800 { 4391 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4392 reg = <0 0x0a6f8800 0 0x400>; 4393 4394 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4395 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4396 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4397 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4398 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4399 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4400 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 4401 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 4402 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4403 clock-names = "cfg_noc", 4404 "core", 4405 "iface", 4406 "sleep", 4407 "mock_utmi", 4408 "noc_aggr", 4409 "noc_aggr_north", 4410 "noc_aggr_south", 4411 "noc_sys"; 4412 4413 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4414 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4415 assigned-clock-rates = <19200000>, 4416 <200000000>; 4417 4418 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4419 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 4420 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4421 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4422 interrupt-names = "pwr_event", 4423 "dp_hs_phy_irq", 4424 "dm_hs_phy_irq", 4425 "ss_phy_irq"; 4426 4427 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4428 required-opps = <&rpmhpd_opp_nom>; 4429 4430 resets = <&gcc GCC_USB30_PRIM_BCR>; 4431 4432 wakeup-source; 4433 4434 #address-cells = <2>; 4435 #size-cells = <2>; 4436 ranges; 4437 4438 status = "disabled"; 4439 4440 usb_1_ss0_dwc3: usb@a600000 { 4441 compatible = "snps,dwc3"; 4442 reg = <0 0x0a600000 0 0xcd00>; 4443 4444 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 4445 4446 iommus = <&apps_smmu 0x1420 0x0>; 4447 4448 phys = <&usb_1_ss0_hsphy>, 4449 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 4450 phy-names = "usb2-phy", 4451 "usb3-phy"; 4452 4453 snps,dis_u2_susphy_quirk; 4454 snps,dis_enblslpm_quirk; 4455 snps,usb3_lpm_capable; 4456 4457 dma-coherent; 4458 4459 ports { 4460 #address-cells = <1>; 4461 #size-cells = <0>; 4462 4463 port@0 { 4464 reg = <0>; 4465 4466 usb_1_ss0_dwc3_hs: endpoint { 4467 }; 4468 }; 4469 4470 port@1 { 4471 reg = <1>; 4472 4473 usb_1_ss0_dwc3_ss: endpoint { 4474 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 4475 }; 4476 }; 4477 }; 4478 }; 4479 }; 4480 4481 usb_1_ss1: usb@a8f8800 { 4482 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4483 reg = <0 0x0a8f8800 0 0x400>; 4484 4485 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4486 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4487 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4488 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4489 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4490 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4491 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4492 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4493 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4494 clock-names = "cfg_noc", 4495 "core", 4496 "iface", 4497 "sleep", 4498 "mock_utmi", 4499 "noc_aggr", 4500 "noc_aggr_north", 4501 "noc_aggr_south", 4502 "noc_sys"; 4503 4504 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4505 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4506 assigned-clock-rates = <19200000>, 4507 <200000000>; 4508 4509 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 4510 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4511 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4512 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 4513 interrupt-names = "pwr_event", 4514 "dp_hs_phy_irq", 4515 "dm_hs_phy_irq", 4516 "ss_phy_irq"; 4517 4518 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4519 required-opps = <&rpmhpd_opp_nom>; 4520 4521 resets = <&gcc GCC_USB30_SEC_BCR>; 4522 4523 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 4524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4525 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4526 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 4527 interconnect-names = "usb-ddr", 4528 "apps-usb"; 4529 4530 wakeup-source; 4531 4532 #address-cells = <2>; 4533 #size-cells = <2>; 4534 ranges; 4535 4536 status = "disabled"; 4537 4538 usb_1_ss1_dwc3: usb@a800000 { 4539 compatible = "snps,dwc3"; 4540 reg = <0 0x0a800000 0 0xcd00>; 4541 4542 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 4543 4544 iommus = <&apps_smmu 0x1460 0x0>; 4545 4546 phys = <&usb_1_ss1_hsphy>, 4547 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 4548 phy-names = "usb2-phy", 4549 "usb3-phy"; 4550 4551 snps,dis_u2_susphy_quirk; 4552 snps,dis_enblslpm_quirk; 4553 snps,usb3_lpm_capable; 4554 4555 dma-coherent; 4556 4557 ports { 4558 #address-cells = <1>; 4559 #size-cells = <0>; 4560 4561 port@0 { 4562 reg = <0>; 4563 4564 usb_1_ss1_dwc3_hs: endpoint { 4565 }; 4566 }; 4567 4568 port@1 { 4569 reg = <1>; 4570 4571 usb_1_ss1_dwc3_ss: endpoint { 4572 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 4573 }; 4574 }; 4575 }; 4576 }; 4577 }; 4578 4579 mdss: display-subsystem@ae00000 { 4580 compatible = "qcom,x1e80100-mdss"; 4581 reg = <0 0x0ae00000 0 0x1000>; 4582 reg-names = "mdss"; 4583 4584 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4585 4586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4587 <&gcc GCC_DISP_HF_AXI_CLK>, 4588 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4589 4590 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4591 4592 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4593 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 4594 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4595 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4596 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4597 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4598 interconnect-names = "mdp0-mem", 4599 "mdp1-mem", 4600 "cpu-cfg"; 4601 4602 power-domains = <&dispcc MDSS_GDSC>; 4603 4604 iommus = <&apps_smmu 0x1c00 0x2>; 4605 4606 interrupt-controller; 4607 #interrupt-cells = <1>; 4608 4609 #address-cells = <2>; 4610 #size-cells = <2>; 4611 ranges; 4612 4613 status = "disabled"; 4614 4615 mdss_mdp: display-controller@ae01000 { 4616 compatible = "qcom,x1e80100-dpu"; 4617 reg = <0 0x0ae01000 0 0x8f000>, 4618 <0 0x0aeb0000 0 0x2008>; 4619 reg-names = "mdp", 4620 "vbif"; 4621 4622 interrupts-extended = <&mdss 0>; 4623 4624 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4625 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4626 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4627 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4628 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4629 clock-names = "nrt_bus", 4630 "iface", 4631 "lut", 4632 "core", 4633 "vsync"; 4634 4635 operating-points-v2 = <&mdp_opp_table>; 4636 4637 power-domains = <&rpmhpd RPMHPD_MMCX>; 4638 4639 ports { 4640 #address-cells = <1>; 4641 #size-cells = <0>; 4642 4643 port@0 { 4644 reg = <0>; 4645 4646 mdss_intf0_out: endpoint { 4647 remote-endpoint = <&mdss_dp0_in>; 4648 }; 4649 }; 4650 4651 port@4 { 4652 reg = <4>; 4653 4654 mdss_intf4_out: endpoint { 4655 remote-endpoint = <&mdss_dp1_in>; 4656 }; 4657 }; 4658 4659 port@5 { 4660 reg = <5>; 4661 4662 mdss_intf5_out: endpoint { 4663 remote-endpoint = <&mdss_dp3_in>; 4664 }; 4665 }; 4666 4667 port@6 { 4668 reg = <6>; 4669 4670 mdss_intf6_out: endpoint { 4671 remote-endpoint = <&mdss_dp2_in>; 4672 }; 4673 }; 4674 }; 4675 4676 mdp_opp_table: opp-table { 4677 compatible = "operating-points-v2"; 4678 4679 opp-200000000 { 4680 opp-hz = /bits/ 64 <200000000>; 4681 required-opps = <&rpmhpd_opp_low_svs>; 4682 }; 4683 4684 opp-325000000 { 4685 opp-hz = /bits/ 64 <325000000>; 4686 required-opps = <&rpmhpd_opp_svs>; 4687 }; 4688 4689 opp-375000000 { 4690 opp-hz = /bits/ 64 <375000000>; 4691 required-opps = <&rpmhpd_opp_svs_l1>; 4692 }; 4693 4694 opp-514000000 { 4695 opp-hz = /bits/ 64 <514000000>; 4696 required-opps = <&rpmhpd_opp_nom>; 4697 }; 4698 4699 opp-575000000 { 4700 opp-hz = /bits/ 64 <575000000>; 4701 required-opps = <&rpmhpd_opp_nom_l1>; 4702 }; 4703 }; 4704 }; 4705 4706 mdss_dp0: displayport-controller@ae90000 { 4707 compatible = "qcom,x1e80100-dp"; 4708 reg = <0 0x0ae90000 0 0x200>, 4709 <0 0x0ae90200 0 0x200>, 4710 <0 0x0ae90400 0 0x600>, 4711 <0 0x0ae91000 0 0x400>, 4712 <0 0x0ae91400 0 0x400>; 4713 4714 interrupts-extended = <&mdss 12>; 4715 4716 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4717 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4718 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4719 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4720 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4721 clock-names = "core_iface", 4722 "core_aux", 4723 "ctrl_link", 4724 "ctrl_link_iface", 4725 "stream_pixel"; 4726 4727 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4728 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4729 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4730 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4731 4732 operating-points-v2 = <&mdss_dp0_opp_table>; 4733 4734 power-domains = <&rpmhpd RPMHPD_MMCX>; 4735 4736 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 4737 phy-names = "dp"; 4738 4739 #sound-dai-cells = <0>; 4740 4741 status = "disabled"; 4742 4743 ports { 4744 #address-cells = <1>; 4745 #size-cells = <0>; 4746 4747 port@0 { 4748 reg = <0>; 4749 4750 mdss_dp0_in: endpoint { 4751 remote-endpoint = <&mdss_intf0_out>; 4752 }; 4753 }; 4754 4755 port@1 { 4756 reg = <1>; 4757 4758 mdss_dp0_out: endpoint { 4759 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 4760 }; 4761 }; 4762 }; 4763 4764 mdss_dp0_opp_table: opp-table { 4765 compatible = "operating-points-v2"; 4766 4767 opp-160000000 { 4768 opp-hz = /bits/ 64 <160000000>; 4769 required-opps = <&rpmhpd_opp_low_svs>; 4770 }; 4771 4772 opp-270000000 { 4773 opp-hz = /bits/ 64 <270000000>; 4774 required-opps = <&rpmhpd_opp_svs>; 4775 }; 4776 4777 opp-540000000 { 4778 opp-hz = /bits/ 64 <540000000>; 4779 required-opps = <&rpmhpd_opp_svs_l1>; 4780 }; 4781 4782 opp-810000000 { 4783 opp-hz = /bits/ 64 <810000000>; 4784 required-opps = <&rpmhpd_opp_nom>; 4785 }; 4786 }; 4787 }; 4788 4789 mdss_dp1: displayport-controller@ae98000 { 4790 compatible = "qcom,x1e80100-dp"; 4791 reg = <0 0x0ae98000 0 0x200>, 4792 <0 0x0ae98200 0 0x200>, 4793 <0 0x0ae98400 0 0x600>, 4794 <0 0x0ae99000 0 0x400>, 4795 <0 0x0ae99400 0 0x400>; 4796 4797 interrupts-extended = <&mdss 13>; 4798 4799 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4800 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4801 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4802 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4803 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4804 clock-names = "core_iface", 4805 "core_aux", 4806 "ctrl_link", 4807 "ctrl_link_iface", 4808 "stream_pixel"; 4809 4810 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4811 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4812 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4813 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4814 4815 operating-points-v2 = <&mdss_dp1_opp_table>; 4816 4817 power-domains = <&rpmhpd RPMHPD_MMCX>; 4818 4819 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 4820 phy-names = "dp"; 4821 4822 #sound-dai-cells = <0>; 4823 4824 status = "disabled"; 4825 4826 ports { 4827 #address-cells = <1>; 4828 #size-cells = <0>; 4829 4830 port@0 { 4831 reg = <0>; 4832 4833 mdss_dp1_in: endpoint { 4834 remote-endpoint = <&mdss_intf4_out>; 4835 }; 4836 }; 4837 4838 port@1 { 4839 reg = <1>; 4840 4841 mdss_dp1_out: endpoint { 4842 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 4843 }; 4844 }; 4845 }; 4846 4847 mdss_dp1_opp_table: opp-table { 4848 compatible = "operating-points-v2"; 4849 4850 opp-160000000 { 4851 opp-hz = /bits/ 64 <160000000>; 4852 required-opps = <&rpmhpd_opp_low_svs>; 4853 }; 4854 4855 opp-270000000 { 4856 opp-hz = /bits/ 64 <270000000>; 4857 required-opps = <&rpmhpd_opp_svs>; 4858 }; 4859 4860 opp-540000000 { 4861 opp-hz = /bits/ 64 <540000000>; 4862 required-opps = <&rpmhpd_opp_svs_l1>; 4863 }; 4864 4865 opp-810000000 { 4866 opp-hz = /bits/ 64 <810000000>; 4867 required-opps = <&rpmhpd_opp_nom>; 4868 }; 4869 }; 4870 }; 4871 4872 mdss_dp2: displayport-controller@ae9a000 { 4873 compatible = "qcom,x1e80100-dp"; 4874 reg = <0 0x0ae9a000 0 0x200>, 4875 <0 0x0ae9a200 0 0x200>, 4876 <0 0x0ae9a400 0 0x600>, 4877 <0 0x0ae9b000 0 0x400>, 4878 <0 0x0ae9b400 0 0x400>; 4879 4880 interrupts-extended = <&mdss 14>; 4881 4882 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4883 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4884 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4885 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4886 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4887 clock-names = "core_iface", 4888 "core_aux", 4889 "ctrl_link", 4890 "ctrl_link_iface", 4891 "stream_pixel"; 4892 4893 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4894 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4895 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4896 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4897 4898 operating-points-v2 = <&mdss_dp2_opp_table>; 4899 4900 power-domains = <&rpmhpd RPMHPD_MMCX>; 4901 4902 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 4903 phy-names = "dp"; 4904 4905 #sound-dai-cells = <0>; 4906 4907 status = "disabled"; 4908 4909 ports { 4910 #address-cells = <1>; 4911 #size-cells = <0>; 4912 4913 port@0 { 4914 reg = <0>; 4915 mdss_dp2_in: endpoint { 4916 remote-endpoint = <&mdss_intf6_out>; 4917 }; 4918 }; 4919 4920 port@1 { 4921 reg = <1>; 4922 4923 mdss_dp2_out: endpoint { 4924 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 4925 }; 4926 }; 4927 }; 4928 4929 mdss_dp2_opp_table: opp-table { 4930 compatible = "operating-points-v2"; 4931 4932 opp-160000000 { 4933 opp-hz = /bits/ 64 <160000000>; 4934 required-opps = <&rpmhpd_opp_low_svs>; 4935 }; 4936 4937 opp-270000000 { 4938 opp-hz = /bits/ 64 <270000000>; 4939 required-opps = <&rpmhpd_opp_svs>; 4940 }; 4941 4942 opp-540000000 { 4943 opp-hz = /bits/ 64 <540000000>; 4944 required-opps = <&rpmhpd_opp_svs_l1>; 4945 }; 4946 4947 opp-810000000 { 4948 opp-hz = /bits/ 64 <810000000>; 4949 required-opps = <&rpmhpd_opp_nom>; 4950 }; 4951 }; 4952 }; 4953 4954 mdss_dp3: displayport-controller@aea0000 { 4955 compatible = "qcom,x1e80100-dp"; 4956 reg = <0 0x0aea0000 0 0x200>, 4957 <0 0x0aea0200 0 0x200>, 4958 <0 0x0aea0400 0 0x600>, 4959 <0 0x0aea1000 0 0x400>, 4960 <0 0x0aea1400 0 0x400>; 4961 4962 interrupts-extended = <&mdss 15>; 4963 4964 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4965 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4966 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4967 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4968 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4969 clock-names = "core_iface", 4970 "core_aux", 4971 "ctrl_link", 4972 "ctrl_link_iface", 4973 "stream_pixel"; 4974 4975 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4976 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4977 assigned-clock-parents = <&mdss_dp3_phy 0>, 4978 <&mdss_dp3_phy 1>; 4979 4980 operating-points-v2 = <&mdss_dp3_opp_table>; 4981 4982 power-domains = <&rpmhpd RPMHPD_MMCX>; 4983 4984 phys = <&mdss_dp3_phy>; 4985 phy-names = "dp"; 4986 4987 #sound-dai-cells = <0>; 4988 4989 status = "disabled"; 4990 4991 ports { 4992 #address-cells = <1>; 4993 #size-cells = <0>; 4994 4995 port@0 { 4996 reg = <0>; 4997 4998 mdss_dp3_in: endpoint { 4999 remote-endpoint = <&mdss_intf5_out>; 5000 }; 5001 }; 5002 5003 port@1 { 5004 reg = <1>; 5005 }; 5006 }; 5007 5008 mdss_dp3_opp_table: opp-table { 5009 compatible = "operating-points-v2"; 5010 5011 opp-160000000 { 5012 opp-hz = /bits/ 64 <160000000>; 5013 required-opps = <&rpmhpd_opp_low_svs>; 5014 }; 5015 5016 opp-270000000 { 5017 opp-hz = /bits/ 64 <270000000>; 5018 required-opps = <&rpmhpd_opp_svs>; 5019 }; 5020 5021 opp-540000000 { 5022 opp-hz = /bits/ 64 <540000000>; 5023 required-opps = <&rpmhpd_opp_svs_l1>; 5024 }; 5025 5026 opp-810000000 { 5027 opp-hz = /bits/ 64 <810000000>; 5028 required-opps = <&rpmhpd_opp_nom>; 5029 }; 5030 }; 5031 }; 5032 5033 }; 5034 5035 mdss_dp2_phy: phy@aec2a00 { 5036 compatible = "qcom,x1e80100-dp-phy"; 5037 reg = <0 0x0aec2a00 0 0x19c>, 5038 <0 0x0aec2200 0 0xec>, 5039 <0 0x0aec2600 0 0xec>, 5040 <0 0x0aec2000 0 0x1c8>; 5041 5042 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5043 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5044 clock-names = "aux", 5045 "cfg_ahb"; 5046 5047 power-domains = <&rpmhpd RPMHPD_MX>; 5048 5049 #clock-cells = <1>; 5050 #phy-cells = <0>; 5051 5052 status = "disabled"; 5053 }; 5054 5055 mdss_dp3_phy: phy@aec5a00 { 5056 compatible = "qcom,x1e80100-dp-phy"; 5057 reg = <0 0x0aec5a00 0 0x19c>, 5058 <0 0x0aec5200 0 0xec>, 5059 <0 0x0aec5600 0 0xec>, 5060 <0 0x0aec5000 0 0x1c8>; 5061 5062 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5063 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5064 clock-names = "aux", 5065 "cfg_ahb"; 5066 5067 power-domains = <&rpmhpd RPMHPD_MX>; 5068 5069 #clock-cells = <1>; 5070 #phy-cells = <0>; 5071 5072 status = "disabled"; 5073 }; 5074 5075 dispcc: clock-controller@af00000 { 5076 compatible = "qcom,x1e80100-dispcc"; 5077 reg = <0 0x0af00000 0 0x20000>; 5078 clocks = <&bi_tcxo_div2>, 5079 <&bi_tcxo_ao_div2>, 5080 <&gcc GCC_DISP_AHB_CLK>, 5081 <&sleep_clk>, 5082 <0>, /* dsi0 */ 5083 <0>, 5084 <0>, /* dsi1 */ 5085 <0>, 5086 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5087 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5088 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5089 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5090 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5091 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5092 <&mdss_dp3_phy 0>, /* dp3 */ 5093 <&mdss_dp3_phy 1>; 5094 power-domains = <&rpmhpd RPMHPD_MMCX>; 5095 required-opps = <&rpmhpd_opp_low_svs>; 5096 #clock-cells = <1>; 5097 #reset-cells = <1>; 5098 #power-domain-cells = <1>; 5099 }; 5100 5101 pdc: interrupt-controller@b220000 { 5102 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5103 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5104 5105 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5106 <47 522 52>, <99 609 32>, 5107 <131 717 12>, <143 816 19>; 5108 #interrupt-cells = <2>; 5109 interrupt-parent = <&intc>; 5110 interrupt-controller; 5111 }; 5112 5113 aoss_qmp: power-management@c300000 { 5114 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5115 reg = <0 0x0c300000 0 0x400>; 5116 interrupt-parent = <&ipcc>; 5117 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5118 IRQ_TYPE_EDGE_RISING>; 5119 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5120 5121 #clock-cells = <0>; 5122 }; 5123 5124 sram@c3f0000 { 5125 compatible = "qcom,rpmh-stats"; 5126 reg = <0 0x0c3f0000 0 0x400>; 5127 }; 5128 5129 spmi: arbiter@c400000 { 5130 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5131 reg = <0 0x0c400000 0 0x3000>, 5132 <0 0x0c500000 0 0x400000>, 5133 <0 0x0c440000 0 0x80000>; 5134 reg-names = "core", "chnls", "obsrvr"; 5135 5136 qcom,ee = <0>; 5137 qcom,channel = <0>; 5138 5139 #address-cells = <2>; 5140 #size-cells = <2>; 5141 ranges; 5142 5143 spmi_bus0: spmi@c42d000 { 5144 reg = <0 0x0c42d000 0 0x4000>, 5145 <0 0x0c4c0000 0 0x10000>; 5146 reg-names = "cnfg", "intr"; 5147 5148 interrupt-names = "periph_irq"; 5149 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5150 interrupt-controller; 5151 #interrupt-cells = <4>; 5152 5153 #address-cells = <2>; 5154 #size-cells = <0>; 5155 }; 5156 5157 spmi_bus1: spmi@c432000 { 5158 reg = <0 0x0c432000 0 0x4000>, 5159 <0 0x0c4d0000 0 0x10000>; 5160 reg-names = "cnfg", "intr"; 5161 5162 interrupt-names = "periph_irq"; 5163 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5164 interrupt-controller; 5165 #interrupt-cells = <4>; 5166 5167 #address-cells = <2>; 5168 #size-cells = <0>; 5169 }; 5170 }; 5171 5172 tlmm: pinctrl@f100000 { 5173 compatible = "qcom,x1e80100-tlmm"; 5174 reg = <0 0x0f100000 0 0xf00000>; 5175 5176 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5177 5178 gpio-controller; 5179 #gpio-cells = <2>; 5180 5181 interrupt-controller; 5182 #interrupt-cells = <2>; 5183 5184 gpio-ranges = <&tlmm 0 0 239>; 5185 wakeup-parent = <&pdc>; 5186 5187 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5188 /* SDA, SCL */ 5189 pins = "gpio0", "gpio1"; 5190 function = "qup0_se0"; 5191 drive-strength = <2>; 5192 bias-pull-up = <2200>; 5193 }; 5194 5195 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5196 /* SDA, SCL */ 5197 pins = "gpio4", "gpio5"; 5198 function = "qup0_se1"; 5199 drive-strength = <2>; 5200 bias-pull-up = <2200>; 5201 }; 5202 5203 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5204 /* SDA, SCL */ 5205 pins = "gpio8", "gpio9"; 5206 function = "qup0_se2"; 5207 drive-strength = <2>; 5208 bias-pull-up = <2200>; 5209 }; 5210 5211 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5212 /* SDA, SCL */ 5213 pins = "gpio12", "gpio13"; 5214 function = "qup0_se3"; 5215 drive-strength = <2>; 5216 bias-pull-up = <2200>; 5217 }; 5218 5219 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5220 /* SDA, SCL */ 5221 pins = "gpio16", "gpio17"; 5222 function = "qup0_se4"; 5223 drive-strength = <2>; 5224 bias-pull-up = <2200>; 5225 }; 5226 5227 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5228 /* SDA, SCL */ 5229 pins = "gpio20", "gpio21"; 5230 function = "qup0_se5"; 5231 drive-strength = <2>; 5232 bias-pull-up = <2200>; 5233 }; 5234 5235 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5236 /* SDA, SCL */ 5237 pins = "gpio24", "gpio25"; 5238 function = "qup0_se6"; 5239 drive-strength = <2>; 5240 bias-pull-up = <2200>; 5241 }; 5242 5243 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5244 /* SDA, SCL */ 5245 pins = "gpio14", "gpio15"; 5246 function = "qup0_se7"; 5247 drive-strength = <2>; 5248 bias-pull-up = <2200>; 5249 }; 5250 5251 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5252 /* SDA, SCL */ 5253 pins = "gpio32", "gpio33"; 5254 function = "qup1_se0"; 5255 drive-strength = <2>; 5256 bias-pull-up = <2200>; 5257 }; 5258 5259 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5260 /* SDA, SCL */ 5261 pins = "gpio36", "gpio37"; 5262 function = "qup1_se1"; 5263 drive-strength = <2>; 5264 bias-pull-up = <2200>; 5265 }; 5266 5267 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5268 /* SDA, SCL */ 5269 pins = "gpio40", "gpio41"; 5270 function = "qup1_se2"; 5271 drive-strength = <2>; 5272 bias-pull-up = <2200>; 5273 }; 5274 5275 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5276 /* SDA, SCL */ 5277 pins = "gpio44", "gpio45"; 5278 function = "qup1_se3"; 5279 drive-strength = <2>; 5280 bias-pull-up = <2200>; 5281 }; 5282 5283 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5284 /* SDA, SCL */ 5285 pins = "gpio48", "gpio49"; 5286 function = "qup1_se4"; 5287 drive-strength = <2>; 5288 bias-pull-up = <2200>; 5289 }; 5290 5291 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5292 /* SDA, SCL */ 5293 pins = "gpio52", "gpio53"; 5294 function = "qup1_se5"; 5295 drive-strength = <2>; 5296 bias-pull-up = <2200>; 5297 }; 5298 5299 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5300 /* SDA, SCL */ 5301 pins = "gpio56", "gpio57"; 5302 function = "qup1_se6"; 5303 drive-strength = <2>; 5304 bias-pull-up = <2200>; 5305 }; 5306 5307 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5308 /* SDA, SCL */ 5309 pins = "gpio54", "gpio55"; 5310 function = "qup1_se7"; 5311 drive-strength = <2>; 5312 bias-pull-up = <2200>; 5313 }; 5314 5315 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5316 /* SDA, SCL */ 5317 pins = "gpio64", "gpio65"; 5318 function = "qup2_se0"; 5319 drive-strength = <2>; 5320 bias-pull-up = <2200>; 5321 }; 5322 5323 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5324 /* SDA, SCL */ 5325 pins = "gpio68", "gpio69"; 5326 function = "qup2_se1"; 5327 drive-strength = <2>; 5328 bias-pull-up = <2200>; 5329 }; 5330 5331 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5332 /* SDA, SCL */ 5333 pins = "gpio72", "gpio73"; 5334 function = "qup2_se2"; 5335 drive-strength = <2>; 5336 bias-pull-up = <2200>; 5337 }; 5338 5339 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5340 /* SDA, SCL */ 5341 pins = "gpio76", "gpio77"; 5342 function = "qup2_se3"; 5343 drive-strength = <2>; 5344 bias-pull-up = <2200>; 5345 }; 5346 5347 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5348 /* SDA, SCL */ 5349 pins = "gpio80", "gpio81"; 5350 function = "qup2_se4"; 5351 drive-strength = <2>; 5352 bias-pull-up = <2200>; 5353 }; 5354 5355 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5356 /* SDA, SCL */ 5357 pins = "gpio84", "gpio85"; 5358 function = "qup2_se5"; 5359 drive-strength = <2>; 5360 bias-pull-up = <2200>; 5361 }; 5362 5363 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5364 /* SDA, SCL */ 5365 pins = "gpio88", "gpio89"; 5366 function = "qup2_se6"; 5367 drive-strength = <2>; 5368 bias-pull-up = <2200>; 5369 }; 5370 5371 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5372 /* SDA, SCL */ 5373 pins = "gpio86", "gpio87"; 5374 function = "qup2_se7"; 5375 drive-strength = <2>; 5376 bias-pull-up = <2200>; 5377 }; 5378 5379 qup_spi0_cs: qup-spi0-cs-state { 5380 pins = "gpio3"; 5381 function = "qup0_se0"; 5382 drive-strength = <6>; 5383 bias-disable; 5384 }; 5385 5386 qup_spi0_data_clk: qup-spi0-data-clk-state { 5387 /* MISO, MOSI, CLK */ 5388 pins = "gpio0", "gpio1", "gpio2"; 5389 function = "qup0_se0"; 5390 drive-strength = <6>; 5391 bias-disable; 5392 }; 5393 5394 qup_spi1_cs: qup-spi1-cs-state { 5395 pins = "gpio7"; 5396 function = "qup0_se1"; 5397 drive-strength = <6>; 5398 bias-disable; 5399 }; 5400 5401 qup_spi1_data_clk: qup-spi1-data-clk-state { 5402 /* MISO, MOSI, CLK */ 5403 pins = "gpio4", "gpio5", "gpio6"; 5404 function = "qup0_se1"; 5405 drive-strength = <6>; 5406 bias-disable; 5407 }; 5408 5409 qup_spi2_cs: qup-spi2-cs-state { 5410 pins = "gpio11"; 5411 function = "qup0_se2"; 5412 drive-strength = <6>; 5413 bias-disable; 5414 }; 5415 5416 qup_spi2_data_clk: qup-spi2-data-clk-state { 5417 /* MISO, MOSI, CLK */ 5418 pins = "gpio8", "gpio9", "gpio10"; 5419 function = "qup0_se2"; 5420 drive-strength = <6>; 5421 bias-disable; 5422 }; 5423 5424 qup_spi3_cs: qup-spi3-cs-state { 5425 pins = "gpio15"; 5426 function = "qup0_se3"; 5427 drive-strength = <6>; 5428 bias-disable; 5429 }; 5430 5431 qup_spi3_data_clk: qup-spi3-data-clk-state { 5432 /* MISO, MOSI, CLK */ 5433 pins = "gpio12", "gpio13", "gpio14"; 5434 function = "qup0_se3"; 5435 drive-strength = <6>; 5436 bias-disable; 5437 }; 5438 5439 qup_spi4_cs: qup-spi4-cs-state { 5440 pins = "gpio19"; 5441 function = "qup0_se4"; 5442 drive-strength = <6>; 5443 bias-disable; 5444 }; 5445 5446 qup_spi4_data_clk: qup-spi4-data-clk-state { 5447 /* MISO, MOSI, CLK */ 5448 pins = "gpio16", "gpio17", "gpio18"; 5449 function = "qup0_se4"; 5450 drive-strength = <6>; 5451 bias-disable; 5452 }; 5453 5454 qup_spi5_cs: qup-spi5-cs-state { 5455 pins = "gpio23"; 5456 function = "qup0_se5"; 5457 drive-strength = <6>; 5458 bias-disable; 5459 }; 5460 5461 qup_spi5_data_clk: qup-spi5-data-clk-state { 5462 /* MISO, MOSI, CLK */ 5463 pins = "gpio20", "gpio21", "gpio22"; 5464 function = "qup0_se5"; 5465 drive-strength = <6>; 5466 bias-disable; 5467 }; 5468 5469 qup_spi6_cs: qup-spi6-cs-state { 5470 pins = "gpio27"; 5471 function = "qup0_se6"; 5472 drive-strength = <6>; 5473 bias-disable; 5474 }; 5475 5476 qup_spi6_data_clk: qup-spi6-data-clk-state { 5477 /* MISO, MOSI, CLK */ 5478 pins = "gpio24", "gpio25", "gpio26"; 5479 function = "qup0_se6"; 5480 drive-strength = <6>; 5481 bias-disable; 5482 }; 5483 5484 qup_spi7_cs: qup-spi7-cs-state { 5485 pins = "gpio13"; 5486 function = "qup0_se7"; 5487 drive-strength = <6>; 5488 bias-disable; 5489 }; 5490 5491 qup_spi7_data_clk: qup-spi7-data-clk-state { 5492 /* MISO, MOSI, CLK */ 5493 pins = "gpio14", "gpio15", "gpio12"; 5494 function = "qup0_se7"; 5495 drive-strength = <6>; 5496 bias-disable; 5497 }; 5498 5499 qup_spi8_cs: qup-spi8-cs-state { 5500 pins = "gpio35"; 5501 function = "qup1_se0"; 5502 drive-strength = <6>; 5503 bias-disable; 5504 }; 5505 5506 qup_spi8_data_clk: qup-spi8-data-clk-state { 5507 /* MISO, MOSI, CLK */ 5508 pins = "gpio32", "gpio33", "gpio34"; 5509 function = "qup1_se0"; 5510 drive-strength = <6>; 5511 bias-disable; 5512 }; 5513 5514 qup_spi9_cs: qup-spi9-cs-state { 5515 pins = "gpio39"; 5516 function = "qup1_se1"; 5517 drive-strength = <6>; 5518 bias-disable; 5519 }; 5520 5521 qup_spi9_data_clk: qup-spi9-data-clk-state { 5522 /* MISO, MOSI, CLK */ 5523 pins = "gpio36", "gpio37", "gpio38"; 5524 function = "qup1_se1"; 5525 drive-strength = <6>; 5526 bias-disable; 5527 }; 5528 5529 qup_spi10_cs: qup-spi10-cs-state { 5530 pins = "gpio43"; 5531 function = "qup1_se2"; 5532 drive-strength = <6>; 5533 bias-disable; 5534 }; 5535 5536 qup_spi10_data_clk: qup-spi10-data-clk-state { 5537 /* MISO, MOSI, CLK */ 5538 pins = "gpio40", "gpio41", "gpio42"; 5539 function = "qup1_se2"; 5540 drive-strength = <6>; 5541 bias-disable; 5542 }; 5543 5544 qup_spi11_cs: qup-spi11-cs-state { 5545 pins = "gpio47"; 5546 function = "qup1_se3"; 5547 drive-strength = <6>; 5548 bias-disable; 5549 }; 5550 5551 qup_spi11_data_clk: qup-spi11-data-clk-state { 5552 /* MISO, MOSI, CLK */ 5553 pins = "gpio44", "gpio45", "gpio46"; 5554 function = "qup1_se3"; 5555 drive-strength = <6>; 5556 bias-disable; 5557 }; 5558 5559 qup_spi12_cs: qup-spi12-cs-state { 5560 pins = "gpio51"; 5561 function = "qup1_se4"; 5562 drive-strength = <6>; 5563 bias-disable; 5564 }; 5565 5566 qup_spi12_data_clk: qup-spi12-data-clk-state { 5567 /* MISO, MOSI, CLK */ 5568 pins = "gpio48", "gpio49", "gpio50"; 5569 function = "qup1_se4"; 5570 drive-strength = <6>; 5571 bias-disable; 5572 }; 5573 5574 qup_spi13_cs: qup-spi13-cs-state { 5575 pins = "gpio55"; 5576 function = "qup1_se5"; 5577 drive-strength = <6>; 5578 bias-disable; 5579 }; 5580 5581 qup_spi13_data_clk: qup-spi13-data-clk-state { 5582 /* MISO, MOSI, CLK */ 5583 pins = "gpio52", "gpio53", "gpio54"; 5584 function = "qup1_se5"; 5585 drive-strength = <6>; 5586 bias-disable; 5587 }; 5588 5589 qup_spi14_cs: qup-spi14-cs-state { 5590 pins = "gpio59"; 5591 function = "qup1_se6"; 5592 drive-strength = <6>; 5593 bias-disable; 5594 }; 5595 5596 qup_spi14_data_clk: qup-spi14-data-clk-state { 5597 /* MISO, MOSI, CLK */ 5598 pins = "gpio56", "gpio57", "gpio58"; 5599 function = "qup1_se6"; 5600 drive-strength = <6>; 5601 bias-disable; 5602 }; 5603 5604 qup_spi15_cs: qup-spi15-cs-state { 5605 pins = "gpio53"; 5606 function = "qup1_se7"; 5607 drive-strength = <6>; 5608 bias-disable; 5609 }; 5610 5611 qup_spi15_data_clk: qup-spi15-data-clk-state { 5612 /* MISO, MOSI, CLK */ 5613 pins = "gpio54", "gpio55", "gpio52"; 5614 function = "qup1_se7"; 5615 drive-strength = <6>; 5616 bias-disable; 5617 }; 5618 5619 qup_spi16_cs: qup-spi16-cs-state { 5620 pins = "gpio67"; 5621 function = "qup2_se0"; 5622 drive-strength = <6>; 5623 bias-disable; 5624 }; 5625 5626 qup_spi16_data_clk: qup-spi16-data-clk-state { 5627 /* MISO, MOSI, CLK */ 5628 pins = "gpio64", "gpio65", "gpio66"; 5629 function = "qup2_se0"; 5630 drive-strength = <6>; 5631 bias-disable; 5632 }; 5633 5634 qup_spi17_cs: qup-spi17-cs-state { 5635 pins = "gpio71"; 5636 function = "qup2_se1"; 5637 drive-strength = <6>; 5638 bias-disable; 5639 }; 5640 5641 qup_spi17_data_clk: qup-spi17-data-clk-state { 5642 /* MISO, MOSI, CLK */ 5643 pins = "gpio68", "gpio69", "gpio70"; 5644 function = "qup2_se1"; 5645 drive-strength = <6>; 5646 bias-disable; 5647 }; 5648 5649 qup_spi18_cs: qup-spi18-cs-state { 5650 pins = "gpio75"; 5651 function = "qup2_se2"; 5652 drive-strength = <6>; 5653 bias-disable; 5654 }; 5655 5656 qup_spi18_data_clk: qup-spi18-data-clk-state { 5657 /* MISO, MOSI, CLK */ 5658 pins = "gpio72", "gpio73", "gpio74"; 5659 function = "qup2_se2"; 5660 drive-strength = <6>; 5661 bias-disable; 5662 }; 5663 5664 qup_spi19_cs: qup-spi19-cs-state { 5665 pins = "gpio79"; 5666 function = "qup2_se3"; 5667 drive-strength = <6>; 5668 bias-disable; 5669 }; 5670 5671 qup_spi19_data_clk: qup-spi19-data-clk-state { 5672 /* MISO, MOSI, CLK */ 5673 pins = "gpio76", "gpio77", "gpio78"; 5674 function = "qup2_se3"; 5675 drive-strength = <6>; 5676 bias-disable; 5677 }; 5678 5679 qup_spi20_cs: qup-spi20-cs-state { 5680 pins = "gpio83"; 5681 function = "qup2_se4"; 5682 drive-strength = <6>; 5683 bias-disable; 5684 }; 5685 5686 qup_spi20_data_clk: qup-spi20-data-clk-state { 5687 /* MISO, MOSI, CLK */ 5688 pins = "gpio80", "gpio81", "gpio82"; 5689 function = "qup2_se4"; 5690 drive-strength = <6>; 5691 bias-disable; 5692 }; 5693 5694 qup_spi21_cs: qup-spi21-cs-state { 5695 pins = "gpio87"; 5696 function = "qup2_se5"; 5697 drive-strength = <6>; 5698 bias-disable; 5699 }; 5700 5701 qup_spi21_data_clk: qup-spi21-data-clk-state { 5702 /* MISO, MOSI, CLK */ 5703 pins = "gpio84", "gpio85", "gpio86"; 5704 function = "qup2_se5"; 5705 drive-strength = <6>; 5706 bias-disable; 5707 }; 5708 5709 qup_spi22_cs: qup-spi22-cs-state { 5710 pins = "gpio91"; 5711 function = "qup2_se6"; 5712 drive-strength = <6>; 5713 bias-disable; 5714 }; 5715 5716 qup_spi22_data_clk: qup-spi22-data-clk-state { 5717 /* MISO, MOSI, CLK */ 5718 pins = "gpio88", "gpio89", "gpio90"; 5719 function = "qup2_se6"; 5720 drive-strength = <6>; 5721 bias-disable; 5722 }; 5723 5724 qup_spi23_cs: qup-spi23-cs-state { 5725 pins = "gpio85"; 5726 function = "qup2_se7"; 5727 drive-strength = <6>; 5728 bias-disable; 5729 }; 5730 5731 qup_spi23_data_clk: qup-spi23-data-clk-state { 5732 /* MISO, MOSI, CLK */ 5733 pins = "gpio86", "gpio87", "gpio84"; 5734 function = "qup2_se7"; 5735 drive-strength = <6>; 5736 bias-disable; 5737 }; 5738 5739 qup_uart2_default: qup-uart2-default-state { 5740 cts-pins { 5741 pins = "gpio8"; 5742 function = "qup0_se2"; 5743 drive-strength = <2>; 5744 bias-disable; 5745 }; 5746 5747 rts-pins { 5748 pins = "gpio9"; 5749 function = "qup0_se2"; 5750 drive-strength = <2>; 5751 bias-disable; 5752 }; 5753 5754 tx-pins { 5755 pins = "gpio10"; 5756 function = "qup0_se2"; 5757 drive-strength = <2>; 5758 bias-disable; 5759 }; 5760 5761 rx-pins { 5762 pins = "gpio11"; 5763 function = "qup0_se2"; 5764 drive-strength = <2>; 5765 bias-disable; 5766 }; 5767 }; 5768 5769 qup_uart21_default: qup-uart21-default-state { 5770 tx-pins { 5771 pins = "gpio86"; 5772 function = "qup2_se5"; 5773 drive-strength = <2>; 5774 bias-disable; 5775 }; 5776 5777 rx-pins { 5778 pins = "gpio87"; 5779 function = "qup2_se5"; 5780 drive-strength = <2>; 5781 bias-disable; 5782 }; 5783 }; 5784 }; 5785 5786 apps_smmu: iommu@15000000 { 5787 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5788 reg = <0 0x15000000 0 0x100000>; 5789 5790 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5842 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5844 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5847 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5848 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5849 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5850 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5851 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5852 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5853 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5854 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5855 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5856 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 5887 5888 #iommu-cells = <2>; 5889 #global-interrupts = <1>; 5890 }; 5891 5892 intc: interrupt-controller@17000000 { 5893 compatible = "arm,gic-v3"; 5894 reg = <0 0x17000000 0 0x10000>, /* GICD */ 5895 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 5896 5897 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5898 5899 #interrupt-cells = <3>; 5900 interrupt-controller; 5901 5902 #redistributor-regions = <1>; 5903 redistributor-stride = <0x0 0x40000>; 5904 5905 #address-cells = <2>; 5906 #size-cells = <2>; 5907 ranges; 5908 5909 gic_its: msi-controller@17040000 { 5910 compatible = "arm,gic-v3-its"; 5911 reg = <0 0x17040000 0 0x40000>; 5912 5913 msi-controller; 5914 #msi-cells = <1>; 5915 5916 status = "disabled"; 5917 }; 5918 }; 5919 5920 apps_rsc: rsc@17500000 { 5921 compatible = "qcom,rpmh-rsc"; 5922 reg = <0 0x17500000 0 0x10000>, 5923 <0 0x17510000 0 0x10000>, 5924 <0 0x17520000 0 0x10000>; 5925 reg-names = "drv-0", "drv-1", "drv-2"; 5926 5927 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5930 qcom,tcs-offset = <0xd00>; 5931 qcom,drv-id = <2>; 5932 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5933 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5934 5935 label = "apps_rsc"; 5936 power-domains = <&SYSTEM_PD>; 5937 5938 apps_bcm_voter: bcm-voter { 5939 compatible = "qcom,bcm-voter"; 5940 }; 5941 5942 rpmhcc: clock-controller { 5943 compatible = "qcom,x1e80100-rpmh-clk"; 5944 5945 clocks = <&xo_board>; 5946 clock-names = "xo"; 5947 5948 #clock-cells = <1>; 5949 }; 5950 5951 rpmhpd: power-controller { 5952 compatible = "qcom,x1e80100-rpmhpd"; 5953 5954 operating-points-v2 = <&rpmhpd_opp_table>; 5955 5956 #power-domain-cells = <1>; 5957 5958 rpmhpd_opp_table: opp-table { 5959 compatible = "operating-points-v2"; 5960 5961 rpmhpd_opp_ret: opp-16 { 5962 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5963 }; 5964 5965 rpmhpd_opp_min_svs: opp-48 { 5966 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5967 }; 5968 5969 rpmhpd_opp_low_svs_d2: opp-52 { 5970 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5971 }; 5972 5973 rpmhpd_opp_low_svs_d1: opp-56 { 5974 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5975 }; 5976 5977 rpmhpd_opp_low_svs_d0: opp-60 { 5978 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5979 }; 5980 5981 rpmhpd_opp_low_svs: opp-64 { 5982 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5983 }; 5984 5985 rpmhpd_opp_low_svs_l1: opp-80 { 5986 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5987 }; 5988 5989 rpmhpd_opp_svs: opp-128 { 5990 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5991 }; 5992 5993 rpmhpd_opp_svs_l0: opp-144 { 5994 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5995 }; 5996 5997 rpmhpd_opp_svs_l1: opp-192 { 5998 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5999 }; 6000 6001 rpmhpd_opp_nom: opp-256 { 6002 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6003 }; 6004 6005 rpmhpd_opp_nom_l1: opp-320 { 6006 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6007 }; 6008 6009 rpmhpd_opp_nom_l2: opp-336 { 6010 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6011 }; 6012 6013 rpmhpd_opp_turbo: opp-384 { 6014 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6015 }; 6016 6017 rpmhpd_opp_turbo_l1: opp-416 { 6018 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6019 }; 6020 }; 6021 }; 6022 }; 6023 6024 timer@17800000 { 6025 compatible = "arm,armv7-timer-mem"; 6026 reg = <0 0x17800000 0 0x1000>; 6027 6028 #address-cells = <2>; 6029 #size-cells = <1>; 6030 ranges = <0 0 0 0 0x20000000>; 6031 6032 frame@17801000 { 6033 reg = <0 0x17801000 0x1000>, 6034 <0 0x17802000 0x1000>; 6035 6036 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6037 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6038 6039 frame-number = <0>; 6040 }; 6041 6042 frame@17803000 { 6043 reg = <0 0x17803000 0x1000>; 6044 6045 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6046 6047 frame-number = <1>; 6048 6049 status = "disabled"; 6050 }; 6051 6052 frame@17805000 { 6053 reg = <0 0x17805000 0x1000>; 6054 6055 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6056 6057 frame-number = <2>; 6058 6059 status = "disabled"; 6060 }; 6061 6062 frame@17807000 { 6063 reg = <0 0x17807000 0x1000>; 6064 6065 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6066 6067 frame-number = <3>; 6068 6069 status = "disabled"; 6070 }; 6071 6072 frame@17809000 { 6073 reg = <0 0x17809000 0x1000>; 6074 6075 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6076 6077 frame-number = <4>; 6078 6079 status = "disabled"; 6080 }; 6081 6082 frame@1780b000 { 6083 reg = <0 0x1780b000 0x1000>; 6084 6085 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6086 6087 frame-number = <5>; 6088 6089 status = "disabled"; 6090 }; 6091 6092 frame@1780d000 { 6093 reg = <0 0x1780d000 0x1000>; 6094 6095 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6096 6097 frame-number = <6>; 6098 6099 status = "disabled"; 6100 }; 6101 }; 6102 6103 pmu@24091000 { 6104 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 6105 reg = <0 0x24091000 0 0x1000>; 6106 6107 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 6108 6109 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 6110 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6111 6112 operating-points-v2 = <&llcc_bwmon_opp_table>; 6113 6114 llcc_bwmon_opp_table: opp-table { 6115 compatible = "operating-points-v2"; 6116 6117 opp-0 { 6118 opp-peak-kBps = <800000>; 6119 }; 6120 6121 opp-1 { 6122 opp-peak-kBps = <2188000>; 6123 }; 6124 6125 opp-2 { 6126 opp-peak-kBps = <3072000>; 6127 }; 6128 6129 opp-3 { 6130 opp-peak-kBps = <6220800>; 6131 }; 6132 6133 opp-4 { 6134 opp-peak-kBps = <6835200>; 6135 }; 6136 6137 opp-5 { 6138 opp-peak-kBps = <8371200>; 6139 }; 6140 6141 opp-6 { 6142 opp-peak-kBps = <10944000>; 6143 }; 6144 6145 opp-7 { 6146 opp-peak-kBps = <12748800>; 6147 }; 6148 6149 opp-8 { 6150 opp-peak-kBps = <14745600>; 6151 }; 6152 6153 opp-9 { 6154 opp-peak-kBps = <16896000>; 6155 }; 6156 }; 6157 }; 6158 6159 /* cluster0 */ 6160 pmu@240b3400 { 6161 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6162 reg = <0 0x240b3400 0 0x600>; 6163 6164 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6165 6166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6167 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6168 6169 operating-points-v2 = <&cpu_bwmon_opp_table>; 6170 6171 cpu_bwmon_opp_table: opp-table { 6172 compatible = "operating-points-v2"; 6173 6174 opp-0 { 6175 opp-peak-kBps = <4800000>; 6176 }; 6177 6178 opp-1 { 6179 opp-peak-kBps = <7464000>; 6180 }; 6181 6182 opp-2 { 6183 opp-peak-kBps = <9600000>; 6184 }; 6185 6186 opp-3 { 6187 opp-peak-kBps = <12896000>; 6188 }; 6189 6190 opp-4 { 6191 opp-peak-kBps = <14928000>; 6192 }; 6193 6194 opp-5 { 6195 opp-peak-kBps = <17064000>; 6196 }; 6197 }; 6198 }; 6199 6200 /* cluster2 */ 6201 pmu@240b5400 { 6202 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6203 reg = <0 0x240b5400 0 0x600>; 6204 6205 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6206 6207 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6208 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6209 6210 operating-points-v2 = <&cpu_bwmon_opp_table>; 6211 }; 6212 6213 /* cluster1 */ 6214 pmu@240b6400 { 6215 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6216 reg = <0 0x240b6400 0 0x600>; 6217 6218 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6219 6220 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6221 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6222 6223 operating-points-v2 = <&cpu_bwmon_opp_table>; 6224 }; 6225 6226 system-cache-controller@25000000 { 6227 compatible = "qcom,x1e80100-llcc"; 6228 reg = <0 0x25000000 0 0x200000>, 6229 <0 0x25200000 0 0x200000>, 6230 <0 0x25400000 0 0x200000>, 6231 <0 0x25600000 0 0x200000>, 6232 <0 0x25800000 0 0x200000>, 6233 <0 0x25a00000 0 0x200000>, 6234 <0 0x25c00000 0 0x200000>, 6235 <0 0x25e00000 0 0x200000>, 6236 <0 0x26000000 0 0x200000>, 6237 <0 0x26200000 0 0x200000>; 6238 reg-names = "llcc0_base", 6239 "llcc1_base", 6240 "llcc2_base", 6241 "llcc3_base", 6242 "llcc4_base", 6243 "llcc5_base", 6244 "llcc6_base", 6245 "llcc7_base", 6246 "llcc_broadcast_base", 6247 "llcc_broadcast_and_base"; 6248 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 6249 }; 6250 6251 remoteproc_cdsp: remoteproc@32300000 { 6252 compatible = "qcom,x1e80100-cdsp-pas"; 6253 reg = <0x0 0x32300000 0x0 0x10000>; 6254 6255 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6256 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 6257 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 6258 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 6259 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 6260 interrupt-names = "wdog", 6261 "fatal", 6262 "ready", 6263 "handover", 6264 "stop-ack"; 6265 6266 clocks = <&rpmhcc RPMH_CXO_CLK>; 6267 clock-names = "xo"; 6268 6269 power-domains = <&rpmhpd RPMHPD_CX>, 6270 <&rpmhpd RPMHPD_MXC>, 6271 <&rpmhpd RPMHPD_NSP>; 6272 power-domain-names = "cx", 6273 "mxc", 6274 "nsp"; 6275 6276 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 6277 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6278 6279 memory-region = <&cdsp_mem>, 6280 <&q6_cdsp_dtb_mem>; 6281 6282 qcom,qmp = <&aoss_qmp>; 6283 6284 qcom,smem-states = <&smp2p_cdsp_out 0>; 6285 qcom,smem-state-names = "stop"; 6286 6287 status = "disabled"; 6288 6289 glink-edge { 6290 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6291 IPCC_MPROC_SIGNAL_GLINK_QMP 6292 IRQ_TYPE_EDGE_RISING>; 6293 mboxes = <&ipcc IPCC_CLIENT_CDSP 6294 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6295 6296 label = "cdsp"; 6297 qcom,remote-pid = <5>; 6298 6299 fastrpc { 6300 compatible = "qcom,fastrpc"; 6301 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6302 label = "cdsp"; 6303 qcom,non-secure-domain; 6304 #address-cells = <1>; 6305 #size-cells = <0>; 6306 6307 compute-cb@1 { 6308 compatible = "qcom,fastrpc-compute-cb"; 6309 reg = <1>; 6310 iommus = <&apps_smmu 0x0c01 0x20>; 6311 dma-coherent; 6312 }; 6313 6314 compute-cb@2 { 6315 compatible = "qcom,fastrpc-compute-cb"; 6316 reg = <2>; 6317 iommus = <&apps_smmu 0x0c02 0x20>; 6318 dma-coherent; 6319 }; 6320 6321 compute-cb@3 { 6322 compatible = "qcom,fastrpc-compute-cb"; 6323 reg = <3>; 6324 iommus = <&apps_smmu 0x0c03 0x20>; 6325 dma-coherent; 6326 }; 6327 6328 compute-cb@4 { 6329 compatible = "qcom,fastrpc-compute-cb"; 6330 reg = <4>; 6331 iommus = <&apps_smmu 0x0c04 0x20>; 6332 dma-coherent; 6333 }; 6334 6335 compute-cb@5 { 6336 compatible = "qcom,fastrpc-compute-cb"; 6337 reg = <5>; 6338 iommus = <&apps_smmu 0x0c05 0x20>; 6339 dma-coherent; 6340 }; 6341 6342 compute-cb@6 { 6343 compatible = "qcom,fastrpc-compute-cb"; 6344 reg = <6>; 6345 iommus = <&apps_smmu 0x0c06 0x20>; 6346 dma-coherent; 6347 }; 6348 6349 compute-cb@7 { 6350 compatible = "qcom,fastrpc-compute-cb"; 6351 reg = <7>; 6352 iommus = <&apps_smmu 0x0c07 0x20>; 6353 dma-coherent; 6354 }; 6355 6356 compute-cb@8 { 6357 compatible = "qcom,fastrpc-compute-cb"; 6358 reg = <8>; 6359 iommus = <&apps_smmu 0x0c08 0x20>; 6360 dma-coherent; 6361 }; 6362 6363 /* note: compute-cb@9 is secure */ 6364 6365 compute-cb@10 { 6366 compatible = "qcom,fastrpc-compute-cb"; 6367 reg = <10>; 6368 iommus = <&apps_smmu 0x0c0c 0x20>; 6369 dma-coherent; 6370 }; 6371 6372 compute-cb@11 { 6373 compatible = "qcom,fastrpc-compute-cb"; 6374 reg = <11>; 6375 iommus = <&apps_smmu 0x0c0d 0x20>; 6376 dma-coherent; 6377 }; 6378 6379 compute-cb@12 { 6380 compatible = "qcom,fastrpc-compute-cb"; 6381 reg = <12>; 6382 iommus = <&apps_smmu 0x0c0e 0x20>; 6383 dma-coherent; 6384 }; 6385 6386 compute-cb@13 { 6387 compatible = "qcom,fastrpc-compute-cb"; 6388 reg = <13>; 6389 iommus = <&apps_smmu 0x0c0f 0x20>; 6390 dma-coherent; 6391 }; 6392 }; 6393 }; 6394 }; 6395 }; 6396 6397 timer { 6398 compatible = "arm,armv8-timer"; 6399 6400 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6401 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6402 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6403 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6404 }; 6405 6406 thermal-zones { 6407 aoss0-thermal { 6408 thermal-sensors = <&tsens0 0>; 6409 6410 trips { 6411 trip-point0 { 6412 temperature = <90000>; 6413 hysteresis = <2000>; 6414 type = "hot"; 6415 }; 6416 6417 aoss0-critical { 6418 temperature = <115000>; 6419 hysteresis = <1000>; 6420 type = "critical"; 6421 }; 6422 }; 6423 }; 6424 6425 cpu0-0-top-thermal { 6426 polling-delay-passive = <250>; 6427 6428 thermal-sensors = <&tsens0 1>; 6429 6430 trips { 6431 trip-point0 { 6432 temperature = <90000>; 6433 hysteresis = <2000>; 6434 type = "passive"; 6435 }; 6436 6437 trip-point1 { 6438 temperature = <95000>; 6439 hysteresis = <2000>; 6440 type = "passive"; 6441 }; 6442 6443 cpu-critical { 6444 temperature = <115000>; 6445 hysteresis = <1000>; 6446 type = "critical"; 6447 }; 6448 }; 6449 }; 6450 6451 cpu0-0-btm-thermal { 6452 polling-delay-passive = <250>; 6453 6454 thermal-sensors = <&tsens0 2>; 6455 6456 trips { 6457 trip-point0 { 6458 temperature = <90000>; 6459 hysteresis = <2000>; 6460 type = "passive"; 6461 }; 6462 6463 trip-point1 { 6464 temperature = <95000>; 6465 hysteresis = <2000>; 6466 type = "passive"; 6467 }; 6468 6469 cpu-critical { 6470 temperature = <115000>; 6471 hysteresis = <1000>; 6472 type = "critical"; 6473 }; 6474 }; 6475 }; 6476 6477 cpu0-1-top-thermal { 6478 polling-delay-passive = <250>; 6479 6480 thermal-sensors = <&tsens0 3>; 6481 6482 trips { 6483 trip-point0 { 6484 temperature = <90000>; 6485 hysteresis = <2000>; 6486 type = "passive"; 6487 }; 6488 6489 trip-point1 { 6490 temperature = <95000>; 6491 hysteresis = <2000>; 6492 type = "passive"; 6493 }; 6494 6495 cpu-critical { 6496 temperature = <115000>; 6497 hysteresis = <1000>; 6498 type = "critical"; 6499 }; 6500 }; 6501 }; 6502 6503 cpu0-1-btm-thermal { 6504 polling-delay-passive = <250>; 6505 6506 thermal-sensors = <&tsens0 4>; 6507 6508 trips { 6509 trip-point0 { 6510 temperature = <90000>; 6511 hysteresis = <2000>; 6512 type = "passive"; 6513 }; 6514 6515 trip-point1 { 6516 temperature = <95000>; 6517 hysteresis = <2000>; 6518 type = "passive"; 6519 }; 6520 6521 cpu-critical { 6522 temperature = <115000>; 6523 hysteresis = <1000>; 6524 type = "critical"; 6525 }; 6526 }; 6527 }; 6528 6529 cpu0-2-top-thermal { 6530 polling-delay-passive = <250>; 6531 6532 thermal-sensors = <&tsens0 5>; 6533 6534 trips { 6535 trip-point0 { 6536 temperature = <90000>; 6537 hysteresis = <2000>; 6538 type = "passive"; 6539 }; 6540 6541 trip-point1 { 6542 temperature = <95000>; 6543 hysteresis = <2000>; 6544 type = "passive"; 6545 }; 6546 6547 cpu-critical { 6548 temperature = <115000>; 6549 hysteresis = <1000>; 6550 type = "critical"; 6551 }; 6552 }; 6553 }; 6554 6555 cpu0-2-btm-thermal { 6556 polling-delay-passive = <250>; 6557 6558 thermal-sensors = <&tsens0 6>; 6559 6560 trips { 6561 trip-point0 { 6562 temperature = <90000>; 6563 hysteresis = <2000>; 6564 type = "passive"; 6565 }; 6566 6567 trip-point1 { 6568 temperature = <95000>; 6569 hysteresis = <2000>; 6570 type = "passive"; 6571 }; 6572 6573 cpu-critical { 6574 temperature = <115000>; 6575 hysteresis = <1000>; 6576 type = "critical"; 6577 }; 6578 }; 6579 }; 6580 6581 cpu0-3-top-thermal { 6582 polling-delay-passive = <250>; 6583 6584 thermal-sensors = <&tsens0 7>; 6585 6586 trips { 6587 trip-point0 { 6588 temperature = <90000>; 6589 hysteresis = <2000>; 6590 type = "passive"; 6591 }; 6592 6593 trip-point1 { 6594 temperature = <95000>; 6595 hysteresis = <2000>; 6596 type = "passive"; 6597 }; 6598 6599 cpu-critical { 6600 temperature = <115000>; 6601 hysteresis = <1000>; 6602 type = "critical"; 6603 }; 6604 }; 6605 }; 6606 6607 cpu0-3-btm-thermal { 6608 polling-delay-passive = <250>; 6609 6610 thermal-sensors = <&tsens0 8>; 6611 6612 trips { 6613 trip-point0 { 6614 temperature = <90000>; 6615 hysteresis = <2000>; 6616 type = "passive"; 6617 }; 6618 6619 trip-point1 { 6620 temperature = <95000>; 6621 hysteresis = <2000>; 6622 type = "passive"; 6623 }; 6624 6625 cpu-critical { 6626 temperature = <115000>; 6627 hysteresis = <1000>; 6628 type = "critical"; 6629 }; 6630 }; 6631 }; 6632 6633 cpuss0-top-thermal { 6634 thermal-sensors = <&tsens0 9>; 6635 6636 trips { 6637 trip-point0 { 6638 temperature = <90000>; 6639 hysteresis = <2000>; 6640 type = "hot"; 6641 }; 6642 6643 cpuss2-critical { 6644 temperature = <115000>; 6645 hysteresis = <1000>; 6646 type = "critical"; 6647 }; 6648 }; 6649 }; 6650 6651 cpuss0-btm-thermal { 6652 thermal-sensors = <&tsens0 10>; 6653 6654 trips { 6655 trip-point0 { 6656 temperature = <90000>; 6657 hysteresis = <2000>; 6658 type = "hot"; 6659 }; 6660 6661 cpuss2-critical { 6662 temperature = <115000>; 6663 hysteresis = <1000>; 6664 type = "critical"; 6665 }; 6666 }; 6667 }; 6668 6669 mem-thermal { 6670 thermal-sensors = <&tsens0 11>; 6671 6672 trips { 6673 trip-point0 { 6674 temperature = <90000>; 6675 hysteresis = <2000>; 6676 type = "hot"; 6677 }; 6678 6679 mem-critical { 6680 temperature = <115000>; 6681 hysteresis = <0>; 6682 type = "critical"; 6683 }; 6684 }; 6685 }; 6686 6687 video-thermal { 6688 thermal-sensors = <&tsens0 12>; 6689 6690 trips { 6691 trip-point0 { 6692 temperature = <90000>; 6693 hysteresis = <2000>; 6694 type = "hot"; 6695 }; 6696 6697 video-critical { 6698 temperature = <115000>; 6699 hysteresis = <1000>; 6700 type = "critical"; 6701 }; 6702 }; 6703 }; 6704 6705 aoss1-thermal { 6706 thermal-sensors = <&tsens1 0>; 6707 6708 trips { 6709 trip-point0 { 6710 temperature = <90000>; 6711 hysteresis = <2000>; 6712 type = "hot"; 6713 }; 6714 6715 aoss0-critical { 6716 temperature = <115000>; 6717 hysteresis = <1000>; 6718 type = "critical"; 6719 }; 6720 }; 6721 }; 6722 6723 cpu1-0-top-thermal { 6724 polling-delay-passive = <250>; 6725 6726 thermal-sensors = <&tsens1 1>; 6727 6728 trips { 6729 trip-point0 { 6730 temperature = <90000>; 6731 hysteresis = <2000>; 6732 type = "passive"; 6733 }; 6734 6735 trip-point1 { 6736 temperature = <95000>; 6737 hysteresis = <2000>; 6738 type = "passive"; 6739 }; 6740 6741 cpu-critical { 6742 temperature = <115000>; 6743 hysteresis = <1000>; 6744 type = "critical"; 6745 }; 6746 }; 6747 }; 6748 6749 cpu1-0-btm-thermal { 6750 polling-delay-passive = <250>; 6751 6752 thermal-sensors = <&tsens1 2>; 6753 6754 trips { 6755 trip-point0 { 6756 temperature = <90000>; 6757 hysteresis = <2000>; 6758 type = "passive"; 6759 }; 6760 6761 trip-point1 { 6762 temperature = <95000>; 6763 hysteresis = <2000>; 6764 type = "passive"; 6765 }; 6766 6767 cpu-critical { 6768 temperature = <115000>; 6769 hysteresis = <1000>; 6770 type = "critical"; 6771 }; 6772 }; 6773 }; 6774 6775 cpu1-1-top-thermal { 6776 polling-delay-passive = <250>; 6777 6778 thermal-sensors = <&tsens1 3>; 6779 6780 trips { 6781 trip-point0 { 6782 temperature = <90000>; 6783 hysteresis = <2000>; 6784 type = "passive"; 6785 }; 6786 6787 trip-point1 { 6788 temperature = <95000>; 6789 hysteresis = <2000>; 6790 type = "passive"; 6791 }; 6792 6793 cpu-critical { 6794 temperature = <115000>; 6795 hysteresis = <1000>; 6796 type = "critical"; 6797 }; 6798 }; 6799 }; 6800 6801 cpu1-1-btm-thermal { 6802 polling-delay-passive = <250>; 6803 6804 thermal-sensors = <&tsens1 4>; 6805 6806 trips { 6807 trip-point0 { 6808 temperature = <90000>; 6809 hysteresis = <2000>; 6810 type = "passive"; 6811 }; 6812 6813 trip-point1 { 6814 temperature = <95000>; 6815 hysteresis = <2000>; 6816 type = "passive"; 6817 }; 6818 6819 cpu-critical { 6820 temperature = <115000>; 6821 hysteresis = <1000>; 6822 type = "critical"; 6823 }; 6824 }; 6825 }; 6826 6827 cpu1-2-top-thermal { 6828 polling-delay-passive = <250>; 6829 6830 thermal-sensors = <&tsens1 5>; 6831 6832 trips { 6833 trip-point0 { 6834 temperature = <90000>; 6835 hysteresis = <2000>; 6836 type = "passive"; 6837 }; 6838 6839 trip-point1 { 6840 temperature = <95000>; 6841 hysteresis = <2000>; 6842 type = "passive"; 6843 }; 6844 6845 cpu-critical { 6846 temperature = <115000>; 6847 hysteresis = <1000>; 6848 type = "critical"; 6849 }; 6850 }; 6851 }; 6852 6853 cpu1-2-btm-thermal { 6854 polling-delay-passive = <250>; 6855 6856 thermal-sensors = <&tsens1 6>; 6857 6858 trips { 6859 trip-point0 { 6860 temperature = <90000>; 6861 hysteresis = <2000>; 6862 type = "passive"; 6863 }; 6864 6865 trip-point1 { 6866 temperature = <95000>; 6867 hysteresis = <2000>; 6868 type = "passive"; 6869 }; 6870 6871 cpu-critical { 6872 temperature = <115000>; 6873 hysteresis = <1000>; 6874 type = "critical"; 6875 }; 6876 }; 6877 }; 6878 6879 cpu1-3-top-thermal { 6880 polling-delay-passive = <250>; 6881 6882 thermal-sensors = <&tsens1 7>; 6883 6884 trips { 6885 trip-point0 { 6886 temperature = <90000>; 6887 hysteresis = <2000>; 6888 type = "passive"; 6889 }; 6890 6891 trip-point1 { 6892 temperature = <95000>; 6893 hysteresis = <2000>; 6894 type = "passive"; 6895 }; 6896 6897 cpu-critical { 6898 temperature = <115000>; 6899 hysteresis = <1000>; 6900 type = "critical"; 6901 }; 6902 }; 6903 }; 6904 6905 cpu1-3-btm-thermal { 6906 polling-delay-passive = <250>; 6907 6908 thermal-sensors = <&tsens1 8>; 6909 6910 trips { 6911 trip-point0 { 6912 temperature = <90000>; 6913 hysteresis = <2000>; 6914 type = "passive"; 6915 }; 6916 6917 trip-point1 { 6918 temperature = <95000>; 6919 hysteresis = <2000>; 6920 type = "passive"; 6921 }; 6922 6923 cpu-critical { 6924 temperature = <115000>; 6925 hysteresis = <1000>; 6926 type = "critical"; 6927 }; 6928 }; 6929 }; 6930 6931 cpuss1-top-thermal { 6932 thermal-sensors = <&tsens1 9>; 6933 6934 trips { 6935 trip-point0 { 6936 temperature = <90000>; 6937 hysteresis = <2000>; 6938 type = "hot"; 6939 }; 6940 6941 cpuss2-critical { 6942 temperature = <115000>; 6943 hysteresis = <1000>; 6944 type = "critical"; 6945 }; 6946 }; 6947 }; 6948 6949 cpuss1-btm-thermal { 6950 thermal-sensors = <&tsens1 10>; 6951 6952 trips { 6953 trip-point0 { 6954 temperature = <90000>; 6955 hysteresis = <2000>; 6956 type = "hot"; 6957 }; 6958 6959 cpuss2-critical { 6960 temperature = <115000>; 6961 hysteresis = <1000>; 6962 type = "critical"; 6963 }; 6964 }; 6965 }; 6966 6967 aoss2-thermal { 6968 thermal-sensors = <&tsens2 0>; 6969 6970 trips { 6971 trip-point0 { 6972 temperature = <90000>; 6973 hysteresis = <2000>; 6974 type = "hot"; 6975 }; 6976 6977 aoss0-critical { 6978 temperature = <115000>; 6979 hysteresis = <1000>; 6980 type = "critical"; 6981 }; 6982 }; 6983 }; 6984 6985 cpu2-0-top-thermal { 6986 polling-delay-passive = <250>; 6987 6988 thermal-sensors = <&tsens2 1>; 6989 6990 trips { 6991 trip-point0 { 6992 temperature = <90000>; 6993 hysteresis = <2000>; 6994 type = "passive"; 6995 }; 6996 6997 trip-point1 { 6998 temperature = <95000>; 6999 hysteresis = <2000>; 7000 type = "passive"; 7001 }; 7002 7003 cpu-critical { 7004 temperature = <115000>; 7005 hysteresis = <1000>; 7006 type = "critical"; 7007 }; 7008 }; 7009 }; 7010 7011 cpu2-0-btm-thermal { 7012 polling-delay-passive = <250>; 7013 7014 thermal-sensors = <&tsens2 2>; 7015 7016 trips { 7017 trip-point0 { 7018 temperature = <90000>; 7019 hysteresis = <2000>; 7020 type = "passive"; 7021 }; 7022 7023 trip-point1 { 7024 temperature = <95000>; 7025 hysteresis = <2000>; 7026 type = "passive"; 7027 }; 7028 7029 cpu-critical { 7030 temperature = <115000>; 7031 hysteresis = <1000>; 7032 type = "critical"; 7033 }; 7034 }; 7035 }; 7036 7037 cpu2-1-top-thermal { 7038 polling-delay-passive = <250>; 7039 7040 thermal-sensors = <&tsens2 3>; 7041 7042 trips { 7043 trip-point0 { 7044 temperature = <90000>; 7045 hysteresis = <2000>; 7046 type = "passive"; 7047 }; 7048 7049 trip-point1 { 7050 temperature = <95000>; 7051 hysteresis = <2000>; 7052 type = "passive"; 7053 }; 7054 7055 cpu-critical { 7056 temperature = <115000>; 7057 hysteresis = <1000>; 7058 type = "critical"; 7059 }; 7060 }; 7061 }; 7062 7063 cpu2-1-btm-thermal { 7064 polling-delay-passive = <250>; 7065 7066 thermal-sensors = <&tsens2 4>; 7067 7068 trips { 7069 trip-point0 { 7070 temperature = <90000>; 7071 hysteresis = <2000>; 7072 type = "passive"; 7073 }; 7074 7075 trip-point1 { 7076 temperature = <95000>; 7077 hysteresis = <2000>; 7078 type = "passive"; 7079 }; 7080 7081 cpu-critical { 7082 temperature = <115000>; 7083 hysteresis = <1000>; 7084 type = "critical"; 7085 }; 7086 }; 7087 }; 7088 7089 cpu2-2-top-thermal { 7090 polling-delay-passive = <250>; 7091 7092 thermal-sensors = <&tsens2 5>; 7093 7094 trips { 7095 trip-point0 { 7096 temperature = <90000>; 7097 hysteresis = <2000>; 7098 type = "passive"; 7099 }; 7100 7101 trip-point1 { 7102 temperature = <95000>; 7103 hysteresis = <2000>; 7104 type = "passive"; 7105 }; 7106 7107 cpu-critical { 7108 temperature = <115000>; 7109 hysteresis = <1000>; 7110 type = "critical"; 7111 }; 7112 }; 7113 }; 7114 7115 cpu2-2-btm-thermal { 7116 polling-delay-passive = <250>; 7117 7118 thermal-sensors = <&tsens2 6>; 7119 7120 trips { 7121 trip-point0 { 7122 temperature = <90000>; 7123 hysteresis = <2000>; 7124 type = "passive"; 7125 }; 7126 7127 trip-point1 { 7128 temperature = <95000>; 7129 hysteresis = <2000>; 7130 type = "passive"; 7131 }; 7132 7133 cpu-critical { 7134 temperature = <115000>; 7135 hysteresis = <1000>; 7136 type = "critical"; 7137 }; 7138 }; 7139 }; 7140 7141 cpu2-3-top-thermal { 7142 polling-delay-passive = <250>; 7143 7144 thermal-sensors = <&tsens2 7>; 7145 7146 trips { 7147 trip-point0 { 7148 temperature = <90000>; 7149 hysteresis = <2000>; 7150 type = "passive"; 7151 }; 7152 7153 trip-point1 { 7154 temperature = <95000>; 7155 hysteresis = <2000>; 7156 type = "passive"; 7157 }; 7158 7159 cpu-critical { 7160 temperature = <115000>; 7161 hysteresis = <1000>; 7162 type = "critical"; 7163 }; 7164 }; 7165 }; 7166 7167 cpu2-3-btm-thermal { 7168 polling-delay-passive = <250>; 7169 7170 thermal-sensors = <&tsens2 8>; 7171 7172 trips { 7173 trip-point0 { 7174 temperature = <90000>; 7175 hysteresis = <2000>; 7176 type = "passive"; 7177 }; 7178 7179 trip-point1 { 7180 temperature = <95000>; 7181 hysteresis = <2000>; 7182 type = "passive"; 7183 }; 7184 7185 cpu-critical { 7186 temperature = <115000>; 7187 hysteresis = <1000>; 7188 type = "critical"; 7189 }; 7190 }; 7191 }; 7192 7193 cpuss2-top-thermal { 7194 thermal-sensors = <&tsens2 9>; 7195 7196 trips { 7197 trip-point0 { 7198 temperature = <90000>; 7199 hysteresis = <2000>; 7200 type = "hot"; 7201 }; 7202 7203 cpuss2-critical { 7204 temperature = <115000>; 7205 hysteresis = <1000>; 7206 type = "critical"; 7207 }; 7208 }; 7209 }; 7210 7211 cpuss2-btm-thermal { 7212 thermal-sensors = <&tsens2 10>; 7213 7214 trips { 7215 trip-point0 { 7216 temperature = <90000>; 7217 hysteresis = <2000>; 7218 type = "hot"; 7219 }; 7220 7221 cpuss2-critical { 7222 temperature = <115000>; 7223 hysteresis = <1000>; 7224 type = "critical"; 7225 }; 7226 }; 7227 }; 7228 7229 aoss3-thermal { 7230 thermal-sensors = <&tsens3 0>; 7231 7232 trips { 7233 trip-point0 { 7234 temperature = <90000>; 7235 hysteresis = <2000>; 7236 type = "hot"; 7237 }; 7238 7239 aoss0-critical { 7240 temperature = <115000>; 7241 hysteresis = <1000>; 7242 type = "critical"; 7243 }; 7244 }; 7245 }; 7246 7247 nsp0-thermal { 7248 thermal-sensors = <&tsens3 1>; 7249 7250 trips { 7251 trip-point0 { 7252 temperature = <90000>; 7253 hysteresis = <2000>; 7254 type = "hot"; 7255 }; 7256 7257 nsp0-critical { 7258 temperature = <115000>; 7259 hysteresis = <1000>; 7260 type = "critical"; 7261 }; 7262 }; 7263 }; 7264 7265 nsp1-thermal { 7266 thermal-sensors = <&tsens3 2>; 7267 7268 trips { 7269 trip-point0 { 7270 temperature = <90000>; 7271 hysteresis = <2000>; 7272 type = "hot"; 7273 }; 7274 7275 nsp1-critical { 7276 temperature = <115000>; 7277 hysteresis = <1000>; 7278 type = "critical"; 7279 }; 7280 }; 7281 }; 7282 7283 nsp2-thermal { 7284 thermal-sensors = <&tsens3 3>; 7285 7286 trips { 7287 trip-point0 { 7288 temperature = <90000>; 7289 hysteresis = <2000>; 7290 type = "hot"; 7291 }; 7292 7293 nsp2-critical { 7294 temperature = <115000>; 7295 hysteresis = <1000>; 7296 type = "critical"; 7297 }; 7298 }; 7299 }; 7300 7301 nsp3-thermal { 7302 thermal-sensors = <&tsens3 4>; 7303 7304 trips { 7305 trip-point0 { 7306 temperature = <90000>; 7307 hysteresis = <2000>; 7308 type = "hot"; 7309 }; 7310 7311 nsp3-critical { 7312 temperature = <115000>; 7313 hysteresis = <1000>; 7314 type = "critical"; 7315 }; 7316 }; 7317 }; 7318 7319 gpuss-0-thermal { 7320 polling-delay-passive = <200>; 7321 7322 thermal-sensors = <&tsens3 5>; 7323 7324 cooling-maps { 7325 map0 { 7326 trip = <&gpuss0_alert0>; 7327 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7328 }; 7329 }; 7330 7331 trips { 7332 gpuss0_alert0: trip-point0 { 7333 temperature = <95000>; 7334 hysteresis = <1000>; 7335 type = "passive"; 7336 }; 7337 7338 gpu-critical { 7339 temperature = <115000>; 7340 hysteresis = <1000>; 7341 type = "critical"; 7342 }; 7343 }; 7344 }; 7345 7346 gpuss-1-thermal { 7347 polling-delay-passive = <200>; 7348 7349 thermal-sensors = <&tsens3 6>; 7350 7351 cooling-maps { 7352 map0 { 7353 trip = <&gpuss1_alert0>; 7354 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7355 }; 7356 }; 7357 7358 trips { 7359 gpuss1_alert0: trip-point0 { 7360 temperature = <95000>; 7361 hysteresis = <1000>; 7362 type = "passive"; 7363 }; 7364 7365 gpu-critical { 7366 temperature = <115000>; 7367 hysteresis = <1000>; 7368 type = "critical"; 7369 }; 7370 }; 7371 }; 7372 7373 gpuss-2-thermal { 7374 polling-delay-passive = <200>; 7375 7376 thermal-sensors = <&tsens3 7>; 7377 7378 cooling-maps { 7379 map0 { 7380 trip = <&gpuss2_alert0>; 7381 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7382 }; 7383 }; 7384 7385 trips { 7386 gpuss2_alert0: trip-point0 { 7387 temperature = <95000>; 7388 hysteresis = <1000>; 7389 type = "passive"; 7390 }; 7391 7392 gpu-critical { 7393 temperature = <115000>; 7394 hysteresis = <1000>; 7395 type = "critical"; 7396 }; 7397 }; 7398 }; 7399 7400 gpuss-3-thermal { 7401 polling-delay-passive = <200>; 7402 7403 thermal-sensors = <&tsens3 8>; 7404 7405 cooling-maps { 7406 map0 { 7407 trip = <&gpuss3_alert0>; 7408 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7409 }; 7410 }; 7411 7412 trips { 7413 gpuss3_alert0: trip-point0 { 7414 temperature = <95000>; 7415 hysteresis = <1000>; 7416 type = "passive"; 7417 }; 7418 7419 gpu-critical { 7420 temperature = <115000>; 7421 hysteresis = <1000>; 7422 type = "critical"; 7423 }; 7424 }; 7425 }; 7426 7427 gpuss-4-thermal { 7428 polling-delay-passive = <200>; 7429 7430 thermal-sensors = <&tsens3 9>; 7431 7432 cooling-maps { 7433 map0 { 7434 trip = <&gpuss4_alert0>; 7435 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7436 }; 7437 }; 7438 7439 trips { 7440 gpuss4_alert0: trip-point0 { 7441 temperature = <95000>; 7442 hysteresis = <1000>; 7443 type = "passive"; 7444 }; 7445 7446 gpu-critical { 7447 temperature = <115000>; 7448 hysteresis = <1000>; 7449 type = "critical"; 7450 }; 7451 }; 7452 }; 7453 7454 gpuss-5-thermal { 7455 polling-delay-passive = <200>; 7456 7457 thermal-sensors = <&tsens3 10>; 7458 7459 cooling-maps { 7460 map0 { 7461 trip = <&gpuss5_alert0>; 7462 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7463 }; 7464 }; 7465 7466 trips { 7467 gpuss5_alert0: trip-point0 { 7468 temperature = <95000>; 7469 hysteresis = <1000>; 7470 type = "passive"; 7471 }; 7472 7473 gpu-critical { 7474 temperature = <115000>; 7475 hysteresis = <1000>; 7476 type = "critical"; 7477 }; 7478 }; 7479 }; 7480 7481 gpuss-6-thermal { 7482 polling-delay-passive = <200>; 7483 7484 thermal-sensors = <&tsens3 11>; 7485 7486 cooling-maps { 7487 map0 { 7488 trip = <&gpuss6_alert0>; 7489 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7490 }; 7491 }; 7492 7493 trips { 7494 gpuss6_alert0: trip-point0 { 7495 temperature = <95000>; 7496 hysteresis = <1000>; 7497 type = "passive"; 7498 }; 7499 7500 gpu-critical { 7501 temperature = <115000>; 7502 hysteresis = <1000>; 7503 type = "critical"; 7504 }; 7505 }; 7506 }; 7507 7508 gpuss-7-thermal { 7509 polling-delay-passive = <200>; 7510 7511 thermal-sensors = <&tsens3 12>; 7512 7513 cooling-maps { 7514 map0 { 7515 trip = <&gpuss7_alert0>; 7516 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7517 }; 7518 }; 7519 7520 trips { 7521 gpuss7_alert0: trip-point0 { 7522 temperature = <95000>; 7523 hysteresis = <1000>; 7524 type = "passive"; 7525 }; 7526 7527 gpu-critical { 7528 temperature = <115000>; 7529 hysteresis = <1000>; 7530 type = "critical"; 7531 }; 7532 }; 7533 }; 7534 7535 camera0-thermal { 7536 thermal-sensors = <&tsens3 13>; 7537 7538 trips { 7539 trip-point0 { 7540 temperature = <90000>; 7541 hysteresis = <2000>; 7542 type = "hot"; 7543 }; 7544 7545 camera0-critical { 7546 temperature = <115000>; 7547 hysteresis = <1000>; 7548 type = "critical"; 7549 }; 7550 }; 7551 }; 7552 7553 camera1-thermal { 7554 thermal-sensors = <&tsens3 14>; 7555 7556 trips { 7557 trip-point0 { 7558 temperature = <90000>; 7559 hysteresis = <2000>; 7560 type = "hot"; 7561 }; 7562 7563 camera0-critical { 7564 temperature = <115000>; 7565 hysteresis = <1000>; 7566 type = "critical"; 7567 }; 7568 }; 7569 }; 7570 }; 7571}; 7572