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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Eagle board with R-Car V3M
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77970.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Eagle board based on r8a77970";
15	compatible = "renesas,eagle", "renesas,r8a77970";
16
17	aliases {
18		i2c0 = &i2c0;
19		i2c1 = &i2c1;
20		i2c2 = &i2c2;
21		i2c3 = &i2c3;
22		i2c4 = &i2c4;
23		serial0 = &scif0;
24		ethernet0 = &avb;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29		stdout-path = "serial0:115200n8";
30	};
31
32	d1p8: regulator-fixed {
33		compatible = "regulator-fixed";
34		regulator-name = "fixed-1.8V";
35		regulator-min-microvolt = <1800000>;
36		regulator-max-microvolt = <1800000>;
37		regulator-boot-on;
38		regulator-always-on;
39	};
40
41	d3p3: regulator-fixed {
42		compatible = "regulator-fixed";
43		regulator-name = "fixed-3.3V";
44		regulator-min-microvolt = <3300000>;
45		regulator-max-microvolt = <3300000>;
46		regulator-boot-on;
47		regulator-always-on;
48	};
49
50	hdmi-out {
51		compatible = "hdmi-connector";
52		type = "a";
53
54		port {
55			hdmi_con_out: endpoint {
56				remote-endpoint = <&adv7511_out>;
57			};
58		};
59	};
60
61	lvds-decoder {
62		compatible = "thine,thc63lvd1024";
63
64		vcc-supply = <&d3p3>;
65
66		ports {
67			#address-cells = <1>;
68			#size-cells = <0>;
69
70			port@0 {
71				reg = <0>;
72				thc63lvd1024_in: endpoint {
73					remote-endpoint = <&lvds0_out>;
74				};
75			};
76
77			port@2 {
78				reg = <2>;
79				thc63lvd1024_out: endpoint {
80					remote-endpoint = <&adv7511_in>;
81				};
82			};
83		};
84	};
85
86	memory@48000000 {
87		device_type = "memory";
88		/* first 128MB is reserved for secure area. */
89		reg = <0x0 0x48000000 0x0 0x38000000>;
90	};
91
92	x1_clk: x1-clock {
93		compatible = "fixed-clock";
94		#clock-cells = <0>;
95		clock-frequency = <148500000>;
96	};
97};
98
99&avb {
100	pinctrl-0 = <&avb_pins>;
101	pinctrl-names = "default";
102
103	renesas,no-ether-link;
104	phy-handle = <&phy0>;
105	rx-internal-delay-ps = <1800>;
106	tx-internal-delay-ps = <2000>;
107	status = "okay";
108
109	phy0: ethernet-phy@0 {
110		compatible = "ethernet-phy-id0022.1622",
111			     "ethernet-phy-ieee802.3-c22";
112		rxc-skew-ps = <1500>;
113		reg = <0>;
114		interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
115		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
116	};
117};
118
119&canfd {
120	pinctrl-0 = <&canfd0_pins>;
121	pinctrl-names = "default";
122	status = "okay";
123
124	channel0 {
125		status = "okay";
126	};
127};
128
129&csi40 {
130	status = "okay";
131
132	ports {
133		port@0 {
134			csi40_in: endpoint {
135				clock-lanes = <0>;
136				data-lanes = <1 2 3 4>;
137				remote-endpoint = <&max9286_out0>;
138			};
139		};
140	};
141};
142
143&du {
144	clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
145	clock-names = "du.0", "dclkin.0";
146	status = "okay";
147};
148
149&extal_clk {
150	clock-frequency = <16666666>;
151};
152
153&extalr_clk {
154	clock-frequency = <32768>;
155};
156
157&i2c0 {
158	pinctrl-0 = <&i2c0_pins>;
159	pinctrl-names = "default";
160
161	status = "okay";
162	clock-frequency = <400000>;
163
164	io_expander: gpio@20 {
165		compatible = "onnn,pca9654";
166		reg = <0x20>;
167		gpio-controller;
168		#gpio-cells = <2>;
169	};
170
171	hdmi@39 {
172		compatible = "adi,adv7511w";
173		reg = <0x39>;
174		interrupt-parent = <&gpio1>;
175		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
176
177		avdd-supply = <&d1p8>;
178		dvdd-supply = <&d1p8>;
179		pvdd-supply = <&d1p8>;
180		dvdd-3v-supply = <&d3p3>;
181		bgvdd-supply = <&d1p8>;
182
183		adi,input-depth = <8>;
184		adi,input-colorspace = "rgb";
185		adi,input-clock = "1x";
186
187		ports {
188			#address-cells = <1>;
189			#size-cells = <0>;
190
191			port@0 {
192				reg = <0>;
193				adv7511_in: endpoint {
194					remote-endpoint = <&thc63lvd1024_out>;
195				};
196			};
197
198			port@1 {
199				reg = <1>;
200				adv7511_out: endpoint {
201					remote-endpoint = <&hdmi_con_out>;
202				};
203			};
204		};
205	};
206};
207
208&i2c3 {
209	pinctrl-0 = <&i2c3_pins>;
210	pinctrl-names = "default";
211
212	status = "okay";
213	clock-frequency = <400000>;
214
215	gmsl0: gmsl-deserializer@48 {
216		compatible = "maxim,max9286";
217		reg = <0x48>;
218
219		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
220		enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
221
222		ports {
223			#address-cells = <1>;
224			#size-cells = <0>;
225
226			port@0 {
227				reg = <0>;
228			};
229
230			port@1 {
231				reg = <1>;
232			};
233
234			port@2 {
235				reg = <2>;
236			};
237
238			port@3 {
239				reg = <3>;
240			};
241
242			port@4 {
243				reg = <4>;
244				max9286_out0: endpoint {
245					clock-lanes = <0>;
246					data-lanes = <1 2 3 4>;
247					remote-endpoint = <&csi40_in>;
248				};
249			};
250		};
251
252		i2c-mux {
253			#address-cells = <1>;
254			#size-cells = <0>;
255
256			i2c@0 {
257				#address-cells = <1>;
258				#size-cells = <0>;
259				reg = <0>;
260
261				status = "disabled";
262			};
263
264			i2c@1 {
265				#address-cells = <1>;
266				#size-cells = <0>;
267				reg = <1>;
268
269				status = "disabled";
270			};
271
272			i2c@2 {
273				#address-cells = <1>;
274				#size-cells = <0>;
275				reg = <2>;
276
277				status = "disabled";
278			};
279
280			i2c@3 {
281				#address-cells = <1>;
282				#size-cells = <0>;
283				reg = <3>;
284
285				status = "disabled";
286			};
287		};
288	};
289};
290
291&lvds0 {
292	status = "okay";
293
294	ports {
295		port@1 {
296			lvds0_out: endpoint {
297				remote-endpoint = <&thc63lvd1024_in>;
298			};
299		};
300	};
301};
302
303&pfc {
304	pinctrl-0 = <&scif_clk_pins>;
305	pinctrl-names = "default";
306
307	avb_pins: avb0 {
308		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
309		function = "avb0";
310	};
311
312	canfd0_pins: canfd0 {
313		groups = "canfd0_data_a";
314		function = "canfd0";
315	};
316
317	i2c0_pins: i2c0 {
318		groups = "i2c0";
319		function = "i2c0";
320	};
321
322	i2c3_pins: i2c3 {
323		groups = "i2c3_a";
324		function = "i2c3";
325	};
326
327	qspi0_pins: qspi0 {
328		groups = "qspi0_ctrl", "qspi0_data4";
329		function = "qspi0";
330	};
331
332	scif0_pins: scif0 {
333		groups = "scif0_data";
334		function = "scif0";
335	};
336
337	scif_clk_pins: scif_clk {
338		groups = "scif_clk_b";
339		function = "scif_clk";
340	};
341};
342
343&rpc {
344	pinctrl-0 = <&qspi0_pins>;
345	pinctrl-names = "default";
346
347	status = "okay";
348
349	flash@0 {
350		compatible = "spansion,s25fs512s", "jedec,spi-nor";
351		reg = <0>;
352		spi-max-frequency = <50000000>;
353		spi-rx-bus-width = <4>;
354
355		partitions {
356			compatible = "fixed-partitions";
357			#address-cells = <1>;
358			#size-cells = <1>;
359
360			bootparam@0 {
361				reg = <0x00000000 0x040000>;
362				read-only;
363			};
364			cr7@40000 {
365				reg = <0x00040000 0x080000>;
366				read-only;
367			};
368			cert_header_sa3@c0000 {
369				reg = <0x000c0000 0x080000>;
370				read-only;
371			};
372			bl2@140000 {
373				reg = <0x00140000 0x040000>;
374				read-only;
375			};
376			cert_header_sa6@180000 {
377				reg = <0x00180000 0x040000>;
378				read-only;
379			};
380			bl31@1c0000 {
381				reg = <0x001c0000 0x460000>;
382				read-only;
383			};
384			uboot@640000 {
385				reg = <0x00640000 0x0c0000>;
386				read-only;
387			};
388			uboot-env@700000 {
389				reg = <0x00700000 0x040000>;
390				read-only;
391			};
392			dtb@740000 {
393				reg = <0x00740000 0x080000>;
394			};
395			kernel@7c0000 {
396				reg = <0x007c0000 0x1400000>;
397			};
398			user@1bc0000 {
399				reg = <0x01bc0000 0x2440000>;
400			};
401		};
402	};
403};
404
405&rwdt {
406	timeout-sec = <60>;
407	status = "okay";
408};
409
410&scif0 {
411	pinctrl-0 = <&scif0_pins>;
412	pinctrl-names = "default";
413
414	status = "okay";
415};
416
417&scif_clk {
418	clock-frequency = <14745600>;
419};
420