1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the V3M Starter Kit board 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77970.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Renesas V3M Starter Kit board"; 15 compatible = "renesas,v3msk", "renesas,r8a77970"; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 serial0 = &scif0; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 hdmi-out { 31 compatible = "hdmi-connector"; 32 type = "a"; 33 34 port { 35 hdmi_con: endpoint { 36 remote-endpoint = <&adv7511_out>; 37 }; 38 }; 39 }; 40 41 lvds-decoder { 42 compatible = "thine,thc63lvd1024"; 43 vcc-supply = <&vcc_d3_3v>; 44 45 ports { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 port@0 { 50 reg = <0>; 51 thc63lvd1024_in: endpoint { 52 remote-endpoint = <&lvds0_out>; 53 }; 54 }; 55 56 port@2 { 57 reg = <2>; 58 thc63lvd1024_out: endpoint { 59 remote-endpoint = <&adv7511_in>; 60 }; 61 }; 62 }; 63 }; 64 65 memory@48000000 { 66 device_type = "memory"; 67 /* first 128MB is reserved for secure area. */ 68 reg = <0x0 0x48000000 0x0 0x78000000>; 69 }; 70 71 osc5_clk: osc5-clock { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <148500000>; 75 }; 76 77 vcc_d1_8v: regulator-0 { 78 compatible = "regulator-fixed"; 79 regulator-name = "VCC_D1.8V"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <1800000>; 82 regulator-boot-on; 83 regulator-always-on; 84 }; 85 86 vcc_d3_3v: regulator-1 { 87 compatible = "regulator-fixed"; 88 regulator-name = "VCC_D3.3V"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-boot-on; 92 regulator-always-on; 93 }; 94 95 vcc_vddq_vin0: regulator-2 { 96 compatible = "regulator-fixed"; 97 regulator-name = "VCC_VDDQ_VIN0"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 regulator-boot-on; 101 regulator-always-on; 102 }; 103}; 104 105&avb { 106 pinctrl-0 = <&avb_pins>; 107 pinctrl-names = "default"; 108 109 renesas,no-ether-link; 110 phy-handle = <&phy0>; 111 rx-internal-delay-ps = <1800>; 112 tx-internal-delay-ps = <2000>; 113 status = "okay"; 114 115 phy0: ethernet-phy@0 { 116 compatible = "ethernet-phy-id0022.1622", 117 "ethernet-phy-ieee802.3-c22"; 118 rxc-skew-ps = <1500>; 119 reg = <0>; 120 interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>; 121 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 122 }; 123}; 124 125&du { 126 clocks = <&cpg CPG_MOD 724>, 127 <&osc5_clk>; 128 clock-names = "du.0", "dclkin.0"; 129 status = "okay"; 130}; 131 132&extal_clk { 133 clock-frequency = <16666666>; 134}; 135 136&extalr_clk { 137 clock-frequency = <32768>; 138}; 139 140&i2c0 { 141 pinctrl-0 = <&i2c0_pins>; 142 pinctrl-names = "default"; 143 144 status = "okay"; 145 clock-frequency = <400000>; 146 147 hdmi@39 { 148 compatible = "adi,adv7511w"; 149 #sound-dai-cells = <0>; 150 reg = <0x39>; 151 interrupt-parent = <&gpio1>; 152 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 153 avdd-supply = <&vcc_d1_8v>; 154 dvdd-supply = <&vcc_d1_8v>; 155 pvdd-supply = <&vcc_d1_8v>; 156 bgvdd-supply = <&vcc_d1_8v>; 157 dvdd-3v-supply = <&vcc_d3_3v>; 158 159 adi,input-depth = <8>; 160 adi,input-colorspace = "rgb"; 161 adi,input-clock = "1x"; 162 163 ports { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 port@0 { 168 reg = <0>; 169 adv7511_in: endpoint { 170 remote-endpoint = <&thc63lvd1024_out>; 171 }; 172 }; 173 174 port@1 { 175 reg = <1>; 176 adv7511_out: endpoint { 177 remote-endpoint = <&hdmi_con>; 178 }; 179 }; 180 }; 181 }; 182}; 183 184&lvds0 { 185 status = "okay"; 186 187 ports { 188 port@1 { 189 lvds0_out: endpoint { 190 remote-endpoint = <&thc63lvd1024_in>; 191 }; 192 }; 193 }; 194}; 195 196&mmc0 { 197 pinctrl-0 = <&mmc_pins>; 198 pinctrl-names = "default"; 199 200 vmmc-supply = <&vcc_d3_3v>; 201 vqmmc-supply = <&vcc_vddq_vin0>; 202 bus-width = <8>; 203 non-removable; 204 status = "okay"; 205}; 206 207&pfc { 208 avb_pins: avb0 { 209 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 210 function = "avb0"; 211 }; 212 213 i2c0_pins: i2c0 { 214 groups = "i2c0"; 215 function = "i2c0"; 216 }; 217 218 mmc_pins: mmc_3_3v { 219 groups = "mmc_data8", "mmc_ctrl"; 220 function = "mmc"; 221 power-source = <3300>; 222 }; 223 224 qspi0_pins: qspi0 { 225 groups = "qspi0_ctrl", "qspi0_data4"; 226 function = "qspi0"; 227 }; 228 229 scif0_pins: scif0 { 230 groups = "scif0_data"; 231 function = "scif0"; 232 }; 233}; 234 235&rpc { 236 pinctrl-0 = <&qspi0_pins>; 237 pinctrl-names = "default"; 238 239 status = "okay"; 240 241 flash@0 { 242 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 243 reg = <0>; 244 spi-max-frequency = <50000000>; 245 spi-rx-bus-width = <4>; 246 247 partitions { 248 compatible = "fixed-partitions"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 bootparam@0 { 253 reg = <0x00000000 0x040000>; 254 read-only; 255 }; 256 cr7@40000 { 257 reg = <0x00040000 0x080000>; 258 read-only; 259 }; 260 cert_header_sa3@c0000 { 261 reg = <0x000c0000 0x080000>; 262 read-only; 263 }; 264 bl2@140000 { 265 reg = <0x00140000 0x040000>; 266 read-only; 267 }; 268 cert_header_sa6@180000 { 269 reg = <0x00180000 0x040000>; 270 read-only; 271 }; 272 bl31@1c0000 { 273 reg = <0x001c0000 0x460000>; 274 read-only; 275 }; 276 uboot@640000 { 277 reg = <0x00640000 0x0c0000>; 278 read-only; 279 }; 280 uboot-env@700000 { 281 reg = <0x00700000 0x040000>; 282 read-only; 283 }; 284 dtb@740000 { 285 reg = <0x00740000 0x080000>; 286 }; 287 kernel@7c0000 { 288 reg = <0x007c0000 0x1400000>; 289 }; 290 user@1bc0000 { 291 reg = <0x01bc0000 0x2440000>; 292 }; 293 }; 294 }; 295}; 296 297&scif0 { 298 pinctrl-0 = <&scif0_pins>; 299 pinctrl-names = "default"; 300 301 status = "okay"; 302}; 303