1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/ { 13 aliases { 14 ethernet0 = ð0; 15 }; 16 17 chosen { 18 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 19 }; 20 21 memory@48000000 { 22 device_type = "memory"; 23 /* first 128MB is reserved for secure area. */ 24 reg = <0x0 0x48000000 0x0 0x38000000>; 25 }; 26 27 reg_1p8v: regulator-1p8v { 28 compatible = "regulator-fixed"; 29 regulator-name = "fixed-1.8V"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 reg_3p3v: regulator-3p3v { 37 compatible = "regulator-fixed"; 38 regulator-name = "fixed-3.3V"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 regulator-boot-on; 42 regulator-always-on; 43 }; 44 45 reg_1p1v: regulator-vdd-core { 46 compatible = "regulator-fixed"; 47 regulator-name = "fixed-1.1V"; 48 regulator-min-microvolt = <1100000>; 49 regulator-max-microvolt = <1100000>; 50 regulator-boot-on; 51 regulator-always-on; 52 }; 53 54 vccq_sdhi0: regulator-vccq-sdhi0 { 55 compatible = "regulator-gpio"; 56 57 regulator-name = "SDHI0 VccQ"; 58 regulator-min-microvolt = <1800000>; 59 regulator-max-microvolt = <3300000>; 60 states = <3300000 1>, <1800000 0>; 61 regulator-boot-on; 62 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 63 regulator-always-on; 64 }; 65 66 /* 32.768kHz crystal */ 67 x2: x2-clock { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 }; 72}; 73 74ð0 { 75 pinctrl-0 = <ð0_pins>; 76 pinctrl-names = "default"; 77 phy-handle = <&phy0>; 78 phy-mode = "rgmii-id"; 79 status = "okay"; 80 81 phy0: ethernet-phy@7 { 82 compatible = "ethernet-phy-id0022.1640", 83 "ethernet-phy-ieee802.3-c22"; 84 reg = <7>; 85 interrupts-extended = <&irqc RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; 86 rxc-skew-psec = <2400>; 87 txc-skew-psec = <2400>; 88 rxdv-skew-psec = <0>; 89 txen-skew-psec = <0>; 90 rxd0-skew-psec = <0>; 91 rxd1-skew-psec = <0>; 92 rxd2-skew-psec = <0>; 93 rxd3-skew-psec = <0>; 94 txd0-skew-psec = <0>; 95 txd1-skew-psec = <0>; 96 txd2-skew-psec = <0>; 97 txd3-skew-psec = <0>; 98 }; 99}; 100 101&extal_clk { 102 clock-frequency = <24000000>; 103}; 104 105&gpu { 106 mali-supply = <®_1p1v>; 107}; 108 109&i2c2 { 110 raa215300: pmic@12 { 111 compatible = "renesas,raa215300"; 112 reg = <0x12>, <0x6f>; 113 reg-names = "main", "rtc"; 114 115 clocks = <&x2>; 116 clock-names = "xin"; 117 }; 118}; 119 120&ostm1 { 121 status = "okay"; 122}; 123 124&ostm2 { 125 status = "okay"; 126}; 127 128&pinctrl { 129 eth0_pins: eth0 { 130 txc { 131 pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */ 132 power-source = <1800>; 133 output-enable; 134 }; 135 136 mux { 137 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ 138 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ 139 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ 140 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ 141 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ 142 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ 143 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ 144 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ 145 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ 146 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ 147 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ 148 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ 149 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 150 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ 151 power-source = <1800>; 152 }; 153 154 irq { 155 pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */ 156 }; 157 }; 158 159 gpio-sd0-pwr-en-hog { 160 gpio-hog; 161 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; 162 output-high; 163 line-name = "gpio_sd0_pwr_en"; 164 }; 165 166 qspi0_pins: qspi0 { 167 qspi0-data { 168 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; 169 power-source = <1800>; 170 }; 171 172 qspi0-ctrl { 173 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; 174 power-source = <1800>; 175 }; 176 }; 177 178 /* 179 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 180 * The below switch logic can be used to select the device between 181 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 182 * SW1[2] should be at OFF position to enable 64 GB eMMC 183 * SW1[2] should be at position ON to enable uSD card CN3 184 */ 185 gpio-sd0-dev-sel-hog { 186 gpio-hog; 187 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; 188 output-high; 189 line-name = "gpio_sd0_dev_sel"; 190 }; 191 192 sdhi0_emmc_pins: sd0emmc { 193 sd0_emmc_data { 194 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 195 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 196 power-source = <1800>; 197 }; 198 199 sd0_emmc_ctrl { 200 pins = "SD0_CLK", "SD0_CMD"; 201 power-source = <1800>; 202 }; 203 204 sd0_emmc_rst { 205 pins = "SD0_RST#"; 206 power-source = <1800>; 207 }; 208 }; 209 210 sdhi0_pins: sd0 { 211 sd0_data { 212 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 213 power-source = <3300>; 214 }; 215 216 sd0_ctrl { 217 pins = "SD0_CLK", "SD0_CMD"; 218 power-source = <3300>; 219 }; 220 221 sd0_mux { 222 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 223 }; 224 }; 225 226 sdhi0_pins_uhs: sd0_uhs { 227 sd0_data_uhs { 228 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 229 power-source = <1800>; 230 }; 231 232 sd0_ctrl_uhs { 233 pins = "SD0_CLK", "SD0_CMD"; 234 power-source = <1800>; 235 }; 236 237 sd0_mux_uhs { 238 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 239 }; 240 }; 241}; 242 243&sbc { 244 pinctrl-0 = <&qspi0_pins>; 245 pinctrl-names = "default"; 246 status = "okay"; 247 248 flash@0 { 249 compatible = "micron,mt25qu512a", "jedec,spi-nor"; 250 reg = <0>; 251 m25p,fast-read; 252 spi-max-frequency = <50000000>; 253 spi-rx-bus-width = <4>; 254 spi-tx-bus-width = <4>; 255 256 partitions { 257 compatible = "fixed-partitions"; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 261 boot@0 { 262 reg = <0x00000000 0x2000000>; 263 read-only; 264 }; 265 user@2000000 { 266 reg = <0x2000000 0x2000000>; 267 }; 268 }; 269 }; 270}; 271 272#if (!SW_SD0_DEV_SEL) 273&sdhi0 { 274 pinctrl-0 = <&sdhi0_pins>; 275 pinctrl-1 = <&sdhi0_pins_uhs>; 276 pinctrl-names = "default", "state_uhs"; 277 278 vmmc-supply = <®_3p3v>; 279 vqmmc-supply = <&vccq_sdhi0>; 280 bus-width = <4>; 281 sd-uhs-sdr50; 282 sd-uhs-sdr104; 283 status = "okay"; 284}; 285#endif 286 287#if SW_SD0_DEV_SEL 288&sdhi0 { 289 pinctrl-0 = <&sdhi0_emmc_pins>; 290 pinctrl-1 = <&sdhi0_emmc_pins>; 291 pinctrl-names = "default", "state_uhs"; 292 293 vmmc-supply = <®_3p3v>; 294 vqmmc-supply = <®_1p8v>; 295 bus-width = <8>; 296 mmc-hs200-1_8v; 297 non-removable; 298 fixed-emmc-driver-type = <1>; 299 status = "okay"; 300}; 301#endif 302 303&wdt0 { 304 status = "okay"; 305 timeout-sec = <60>; 306}; 307 308&wdt1 { 309 status = "okay"; 310 timeout-sec = <60>; 311}; 312