1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cru ARMCLK>; 64 #cooling-cells = <2>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 dynamic-power-coefficient = <120>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 i-cache-size = <0x8000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_cache>; 76 }; 77 78 cpu2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 dynamic-power-coefficient = <120>; 86 enable-method = "psci"; 87 operating-points-v2 = <&cpu0_opp_table>; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_cache>; 95 }; 96 97 cpu3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x3>; 101 clocks = <&cru ARMCLK>; 102 #cooling-cells = <2>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 dynamic-power-coefficient = <120>; 105 enable-method = "psci"; 106 operating-points-v2 = <&cpu0_opp_table>; 107 i-cache-size = <0x8000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <256>; 110 d-cache-size = <0x8000>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_cache>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP: cpu-sleep { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 }; 127 }; 128 129 l2_cache: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 cache-size = <0x40000>; 134 cache-line-size = <64>; 135 cache-sets = <256>; 136 }; 137 }; 138 139 cpu0_opp_table: opp-table-0 { 140 compatible = "operating-points-v2"; 141 opp-shared; 142 143 opp-408000000 { 144 opp-hz = /bits/ 64 <408000000>; 145 opp-microvolt = <950000>; 146 clock-latency-ns = <40000>; 147 opp-suspend; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <950000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-816000000 { 155 opp-hz = /bits/ 64 <816000000>; 156 opp-microvolt = <1000000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-1008000000 { 160 opp-hz = /bits/ 64 <1008000000>; 161 opp-microvolt = <1100000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-1200000000 { 165 opp-hz = /bits/ 64 <1200000000>; 166 opp-microvolt = <1225000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1296000000 { 170 opp-hz = /bits/ 64 <1296000000>; 171 opp-microvolt = <1300000>; 172 clock-latency-ns = <40000>; 173 }; 174 }; 175 176 analog_sound: analog-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <256>; 180 simple-audio-card,name = "Analog"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s1>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&codec>; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 199 }; 200 201 display_subsystem: display-subsystem { 202 compatible = "rockchip,display-subsystem"; 203 ports = <&vop_out>; 204 }; 205 206 hdmi_sound: hdmi-sound { 207 compatible = "simple-audio-card"; 208 simple-audio-card,format = "i2s"; 209 simple-audio-card,mclk-fs = <128>; 210 simple-audio-card,name = "HDMI"; 211 status = "disabled"; 212 213 simple-audio-card,cpu { 214 sound-dai = <&i2s0>; 215 }; 216 217 simple-audio-card,codec { 218 sound-dai = <&hdmi>; 219 }; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 233 }; 234 235 xin24m: xin24m { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <24000000>; 239 clock-output-names = "xin24m"; 240 }; 241 242 i2s0: i2s@ff000000 { 243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 244 reg = <0x0 0xff000000 0x0 0x1000>; 245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 247 clock-names = "i2s_clk", "i2s_hclk"; 248 dmas = <&dmac 11>, <&dmac 12>; 249 dma-names = "tx", "rx"; 250 #sound-dai-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2s1: i2s@ff010000 { 255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff010000 0x0 0x1000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 14>, <&dmac 15>; 261 dma-names = "tx", "rx"; 262 #sound-dai-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2s2: i2s@ff020000 { 267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 268 reg = <0x0 0xff020000 0x0 0x1000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 dmas = <&dmac 0>, <&dmac 1>; 273 dma-names = "tx", "rx"; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spdif: spdif@ff030000 { 279 compatible = "rockchip,rk3328-spdif"; 280 reg = <0x0 0xff030000 0x0 0x1000>; 281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 283 clock-names = "mclk", "hclk"; 284 dmas = <&dmac 10>; 285 dma-names = "tx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spdifm2_tx>; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 pdm: pdm@ff040000 { 293 compatible = "rockchip,pdm"; 294 reg = <0x0 0xff040000 0x0 0x1000>; 295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 296 clock-names = "pdm_clk", "pdm_hclk"; 297 dmas = <&dmac 16>; 298 dma-names = "rx"; 299 pinctrl-names = "default", "sleep"; 300 pinctrl-0 = <&pdmm0_clk 301 &pdmm0_sdi0 302 &pdmm0_sdi1 303 &pdmm0_sdi2 304 &pdmm0_sdi3>; 305 pinctrl-1 = <&pdmm0_clk_sleep 306 &pdmm0_sdi0_sleep 307 &pdmm0_sdi1_sleep 308 &pdmm0_sdi2_sleep 309 &pdmm0_sdi3_sleep>; 310 status = "disabled"; 311 }; 312 313 grf: syscon@ff100000 { 314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 315 reg = <0x0 0xff100000 0x0 0x1000>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,rk3328-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 grf_gpio: gpio { 323 compatible = "rockchip,rk3328-grf-gpio"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 }; 327 328 power: power-controller { 329 compatible = "rockchip,rk3328-power-controller"; 330 #power-domain-cells = <1>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 power-domain@RK3328_PD_HEVC { 335 reg = <RK3328_PD_HEVC>; 336 clocks = <&cru SCLK_VENC_CORE>; 337 #power-domain-cells = <0>; 338 }; 339 power-domain@RK3328_PD_VIDEO { 340 reg = <RK3328_PD_VIDEO>; 341 clocks = <&cru ACLK_RKVDEC>, 342 <&cru HCLK_RKVDEC>, 343 <&cru SCLK_VDEC_CABAC>, 344 <&cru SCLK_VDEC_CORE>; 345 #power-domain-cells = <0>; 346 }; 347 power-domain@RK3328_PD_VPU { 348 reg = <RK3328_PD_VPU>; 349 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 350 #power-domain-cells = <0>; 351 }; 352 }; 353 354 reboot-mode { 355 compatible = "syscon-reboot-mode"; 356 offset = <0x5c8>; 357 mode-normal = <BOOT_NORMAL>; 358 mode-recovery = <BOOT_RECOVERY>; 359 mode-bootloader = <BOOT_FASTBOOT>; 360 mode-loader = <BOOT_BL_DOWNLOAD>; 361 }; 362 }; 363 364 uart0: serial@ff110000 { 365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 366 reg = <0x0 0xff110000 0x0 0x100>; 367 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 369 clock-names = "baudclk", "apb_pclk"; 370 dmas = <&dmac 2>, <&dmac 3>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 374 reg-io-width = <4>; 375 reg-shift = <2>; 376 status = "disabled"; 377 }; 378 379 uart1: serial@ff120000 { 380 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 381 reg = <0x0 0xff120000 0x0 0x100>; 382 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 384 clock-names = "baudclk", "apb_pclk"; 385 dmas = <&dmac 4>, <&dmac 5>; 386 dma-names = "tx", "rx"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 389 reg-io-width = <4>; 390 reg-shift = <2>; 391 status = "disabled"; 392 }; 393 394 uart2: serial@ff130000 { 395 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff130000 0x0 0x100>; 397 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 399 clock-names = "baudclk", "apb_pclk"; 400 dmas = <&dmac 6>, <&dmac 7>; 401 dma-names = "tx", "rx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&uart2m1_xfer>; 404 reg-io-width = <4>; 405 reg-shift = <2>; 406 status = "disabled"; 407 }; 408 409 i2c0: i2c@ff150000 { 410 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 411 reg = <0x0 0xff150000 0x0 0x1000>; 412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 416 clock-names = "i2c", "pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c0_xfer>; 419 status = "disabled"; 420 }; 421 422 i2c1: i2c@ff160000 { 423 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 424 reg = <0x0 0xff160000 0x0 0x1000>; 425 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 429 clock-names = "i2c", "pclk"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&i2c1_xfer>; 432 status = "disabled"; 433 }; 434 435 i2c2: i2c@ff170000 { 436 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 437 reg = <0x0 0xff170000 0x0 0x1000>; 438 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 442 clock-names = "i2c", "pclk"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&i2c2_xfer>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@ff180000 { 449 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 450 reg = <0x0 0xff180000 0x0 0x1000>; 451 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 455 clock-names = "i2c", "pclk"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c3_xfer>; 458 status = "disabled"; 459 }; 460 461 spi0: spi@ff190000 { 462 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 463 reg = <0x0 0xff190000 0x0 0x1000>; 464 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 468 clock-names = "spiclk", "apb_pclk"; 469 dmas = <&dmac 8>, <&dmac 9>; 470 dma-names = "tx", "rx"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 473 status = "disabled"; 474 }; 475 476 wdt: watchdog@ff1a0000 { 477 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 478 reg = <0x0 0xff1a0000 0x0 0x100>; 479 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru PCLK_WDT>; 481 }; 482 483 pwm0: pwm@ff1b0000 { 484 compatible = "rockchip,rk3328-pwm"; 485 reg = <0x0 0xff1b0000 0x0 0x10>; 486 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 487 clock-names = "pwm", "pclk"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pwm0_pin>; 490 #pwm-cells = <3>; 491 status = "disabled"; 492 }; 493 494 pwm1: pwm@ff1b0010 { 495 compatible = "rockchip,rk3328-pwm"; 496 reg = <0x0 0xff1b0010 0x0 0x10>; 497 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 498 clock-names = "pwm", "pclk"; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pwm1_pin>; 501 #pwm-cells = <3>; 502 status = "disabled"; 503 }; 504 505 pwm2: pwm@ff1b0020 { 506 compatible = "rockchip,rk3328-pwm"; 507 reg = <0x0 0xff1b0020 0x0 0x10>; 508 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 509 clock-names = "pwm", "pclk"; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pwm2_pin>; 512 #pwm-cells = <3>; 513 status = "disabled"; 514 }; 515 516 pwm3: pwm@ff1b0030 { 517 compatible = "rockchip,rk3328-pwm"; 518 reg = <0x0 0xff1b0030 0x0 0x10>; 519 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 520 clock-names = "pwm", "pclk"; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pwmir_pin>; 523 #pwm-cells = <3>; 524 status = "disabled"; 525 }; 526 527 dmac: dma-controller@ff1f0000 { 528 compatible = "arm,pl330", "arm,primecell"; 529 reg = <0x0 0xff1f0000 0x0 0x4000>; 530 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 532 arm,pl330-periph-burst; 533 clocks = <&cru ACLK_DMAC>; 534 clock-names = "apb_pclk"; 535 #dma-cells = <1>; 536 }; 537 538 thermal-zones { 539 soc_thermal: soc-thermal { 540 polling-delay-passive = <20>; 541 polling-delay = <1000>; 542 sustainable-power = <1000>; 543 544 thermal-sensors = <&tsadc 0>; 545 546 trips { 547 threshold: trip-point0 { 548 temperature = <70000>; 549 hysteresis = <2000>; 550 type = "passive"; 551 }; 552 target: trip-point1 { 553 temperature = <85000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 soc_crit: soc-crit { 558 temperature = <95000>; 559 hysteresis = <2000>; 560 type = "critical"; 561 }; 562 }; 563 564 cooling-maps { 565 map0 { 566 trip = <&target>; 567 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 568 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 569 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 570 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 571 contribution = <4096>; 572 }; 573 }; 574 }; 575 576 }; 577 578 tsadc: tsadc@ff250000 { 579 compatible = "rockchip,rk3328-tsadc"; 580 reg = <0x0 0xff250000 0x0 0x100>; 581 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 582 assigned-clocks = <&cru SCLK_TSADC>; 583 assigned-clock-rates = <50000>; 584 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 585 clock-names = "tsadc", "apb_pclk"; 586 pinctrl-names = "init", "default", "sleep"; 587 pinctrl-0 = <&otp_pin>; 588 pinctrl-1 = <&otp_out>; 589 pinctrl-2 = <&otp_pin>; 590 resets = <&cru SRST_TSADC>; 591 reset-names = "tsadc-apb"; 592 rockchip,grf = <&grf>; 593 rockchip,hw-tshut-temp = <100000>; 594 #thermal-sensor-cells = <1>; 595 status = "disabled"; 596 }; 597 598 efuse: efuse@ff260000 { 599 compatible = "rockchip,rk3328-efuse"; 600 reg = <0x0 0xff260000 0x0 0x50>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 clocks = <&cru SCLK_EFUSE>; 604 clock-names = "pclk_efuse"; 605 rockchip,efuse-size = <0x20>; 606 607 /* Data cells */ 608 efuse_id: id@7 { 609 reg = <0x07 0x10>; 610 }; 611 cpu_leakage: cpu-leakage@17 { 612 reg = <0x17 0x1>; 613 }; 614 logic_leakage: logic-leakage@19 { 615 reg = <0x19 0x1>; 616 }; 617 efuse_cpu_version: cpu-version@1a { 618 reg = <0x1a 0x1>; 619 bits = <3 3>; 620 }; 621 }; 622 623 saradc: adc@ff280000 { 624 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 625 reg = <0x0 0xff280000 0x0 0x100>; 626 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 627 #io-channel-cells = <1>; 628 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 629 clock-names = "saradc", "apb_pclk"; 630 resets = <&cru SRST_SARADC_P>; 631 reset-names = "saradc-apb"; 632 status = "disabled"; 633 }; 634 635 gpu: gpu@ff300000 { 636 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 637 reg = <0x0 0xff300000 0x0 0x30000>; 638 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "gp", 646 "gpmmu", 647 "pp", 648 "pp0", 649 "ppmmu0", 650 "pp1", 651 "ppmmu1"; 652 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 653 clock-names = "bus", "core"; 654 resets = <&cru SRST_GPU_A>; 655 }; 656 657 h265e_mmu: iommu@ff330200 { 658 compatible = "rockchip,iommu"; 659 reg = <0x0 0xff330200 0 0x100>; 660 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 662 clock-names = "aclk", "iface"; 663 #iommu-cells = <0>; 664 status = "disabled"; 665 }; 666 667 vepu_mmu: iommu@ff340800 { 668 compatible = "rockchip,iommu"; 669 reg = <0x0 0xff340800 0x0 0x40>; 670 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 672 clock-names = "aclk", "iface"; 673 #iommu-cells = <0>; 674 status = "disabled"; 675 }; 676 677 vpu: video-codec@ff350000 { 678 compatible = "rockchip,rk3328-vpu"; 679 reg = <0x0 0xff350000 0x0 0x800>; 680 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "vdpu"; 682 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 683 clock-names = "aclk", "hclk"; 684 iommus = <&vpu_mmu>; 685 power-domains = <&power RK3328_PD_VPU>; 686 }; 687 688 vpu_mmu: iommu@ff350800 { 689 compatible = "rockchip,iommu"; 690 reg = <0x0 0xff350800 0x0 0x40>; 691 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 693 clock-names = "aclk", "iface"; 694 #iommu-cells = <0>; 695 power-domains = <&power RK3328_PD_VPU>; 696 }; 697 698 vdec: video-codec@ff360000 { 699 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 700 reg = <0x0 0xff360000 0x0 0x480>; 701 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 703 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 704 clock-names = "axi", "ahb", "cabac", "core"; 705 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 706 <&cru SCLK_VDEC_CORE>; 707 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 708 iommus = <&vdec_mmu>; 709 power-domains = <&power RK3328_PD_VIDEO>; 710 }; 711 712 vdec_mmu: iommu@ff360480 { 713 compatible = "rockchip,iommu"; 714 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 715 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 717 clock-names = "aclk", "iface"; 718 #iommu-cells = <0>; 719 power-domains = <&power RK3328_PD_VIDEO>; 720 }; 721 722 vop: vop@ff370000 { 723 compatible = "rockchip,rk3328-vop"; 724 reg = <0x0 0xff370000 0x0 0x3efc>; 725 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 727 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 728 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 729 reset-names = "axi", "ahb", "dclk"; 730 iommus = <&vop_mmu>; 731 status = "disabled"; 732 733 vop_out: port { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 737 vop_out_hdmi: endpoint@0 { 738 reg = <0>; 739 remote-endpoint = <&hdmi_in_vop>; 740 }; 741 }; 742 }; 743 744 vop_mmu: iommu@ff373f00 { 745 compatible = "rockchip,iommu"; 746 reg = <0x0 0xff373f00 0x0 0x100>; 747 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 749 clock-names = "aclk", "iface"; 750 #iommu-cells = <0>; 751 status = "disabled"; 752 }; 753 754 hdmi: hdmi@ff3c0000 { 755 compatible = "rockchip,rk3328-dw-hdmi"; 756 reg = <0x0 0xff3c0000 0x0 0x20000>; 757 reg-io-width = <4>; 758 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru PCLK_HDMI>, 760 <&cru SCLK_HDMI_SFC>, 761 <&cru SCLK_RTC32K>; 762 clock-names = "iahb", 763 "isfr", 764 "cec"; 765 phys = <&hdmiphy>; 766 phy-names = "hdmi"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 769 rockchip,grf = <&grf>; 770 #sound-dai-cells = <0>; 771 status = "disabled"; 772 773 ports { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 777 hdmi_in: port@0 { 778 reg = <0>; 779 780 hdmi_in_vop: endpoint { 781 remote-endpoint = <&vop_out_hdmi>; 782 }; 783 }; 784 785 hdmi_out: port@1 { 786 reg = <1>; 787 }; 788 }; 789 }; 790 791 codec: codec@ff410000 { 792 compatible = "rockchip,rk3328-codec"; 793 reg = <0x0 0xff410000 0x0 0x1000>; 794 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 795 clock-names = "pclk", "mclk"; 796 rockchip,grf = <&grf>; 797 #sound-dai-cells = <0>; 798 status = "disabled"; 799 }; 800 801 hdmiphy: phy@ff430000 { 802 compatible = "rockchip,rk3328-hdmi-phy"; 803 reg = <0x0 0xff430000 0x0 0x10000>; 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 806 clock-names = "sysclk", "refoclk", "refpclk"; 807 clock-output-names = "hdmi_phy"; 808 #clock-cells = <0>; 809 nvmem-cells = <&efuse_cpu_version>; 810 nvmem-cell-names = "cpu-version"; 811 #phy-cells = <0>; 812 status = "disabled"; 813 }; 814 815 cru: clock-controller@ff440000 { 816 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 817 reg = <0x0 0xff440000 0x0 0x1000>; 818 rockchip,grf = <&grf>; 819 #clock-cells = <1>; 820 #reset-cells = <1>; 821 assigned-clocks = 822 /* 823 * CPLL should run at 1200, but that is to high for 824 * the initial dividers of most of its children. 825 * We need set cpll child clk div first, 826 * and then set the cpll frequency. 827 */ 828 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 829 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 830 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 831 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 832 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 833 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 834 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 835 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 836 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 837 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 838 <&cru SCLK_WIFI>, <&cru ARMCLK>, 839 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 840 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 841 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 842 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 843 <&cru SCLK_RTC32K>; 844 assigned-clock-parents = 845 <&cru HDMIPHY>, <&cru PLL_APLL>, 846 <&cru PLL_GPLL>, <&xin24m>, 847 <&xin24m>, <&xin24m>; 848 assigned-clock-rates = 849 <0>, <61440000>, 850 <0>, <24000000>, 851 <24000000>, <24000000>, 852 <15000000>, <15000000>, 853 <300000000>, <100000000>, 854 <400000000>, <100000000>, 855 <50000000>, <100000000>, 856 <100000000>, <100000000>, 857 <50000000>, <50000000>, 858 <50000000>, <50000000>, 859 <24000000>, <600000000>, 860 <491520000>, <1200000000>, 861 <150000000>, <75000000>, 862 <75000000>, <150000000>, 863 <75000000>, <75000000>, 864 <32768>; 865 }; 866 867 usb2phy_grf: syscon@ff450000 { 868 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 869 "simple-mfd"; 870 reg = <0x0 0xff450000 0x0 0x10000>; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 874 u2phy: usb2phy@100 { 875 compatible = "rockchip,rk3328-usb2phy"; 876 reg = <0x100 0x10>; 877 clocks = <&xin24m>; 878 clock-names = "phyclk"; 879 clock-output-names = "usb480m_phy"; 880 #clock-cells = <0>; 881 assigned-clocks = <&cru USB480M>; 882 assigned-clock-parents = <&u2phy>; 883 status = "disabled"; 884 885 u2phy_otg: otg-port { 886 #phy-cells = <0>; 887 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 890 interrupt-names = "otg-bvalid", "otg-id", 891 "linestate"; 892 status = "disabled"; 893 }; 894 895 u2phy_host: host-port { 896 #phy-cells = <0>; 897 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "linestate"; 899 status = "disabled"; 900 }; 901 }; 902 }; 903 904 sdmmc: mmc@ff500000 { 905 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 906 reg = <0x0 0xff500000 0x0 0x4000>; 907 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 909 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 910 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 911 fifo-depth = <0x100>; 912 max-frequency = <150000000>; 913 resets = <&cru SRST_MMC0>; 914 reset-names = "reset"; 915 status = "disabled"; 916 }; 917 918 sdio: mmc@ff510000 { 919 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 920 reg = <0x0 0xff510000 0x0 0x4000>; 921 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 923 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 924 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 925 fifo-depth = <0x100>; 926 max-frequency = <150000000>; 927 resets = <&cru SRST_SDIO>; 928 reset-names = "reset"; 929 status = "disabled"; 930 }; 931 932 emmc: mmc@ff520000 { 933 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 934 reg = <0x0 0xff520000 0x0 0x4000>; 935 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 937 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 938 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 939 fifo-depth = <0x100>; 940 max-frequency = <150000000>; 941 resets = <&cru SRST_EMMC>; 942 reset-names = "reset"; 943 status = "disabled"; 944 }; 945 946 gmac2io: ethernet@ff540000 { 947 compatible = "rockchip,rk3328-gmac"; 948 reg = <0x0 0xff540000 0x0 0x10000>; 949 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "macirq"; 951 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 952 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 953 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 954 <&cru PCLK_MAC2IO>; 955 clock-names = "stmmaceth", "mac_clk_rx", 956 "mac_clk_tx", "clk_mac_ref", 957 "clk_mac_refout", "aclk_mac", 958 "pclk_mac"; 959 resets = <&cru SRST_GMAC2IO_A>; 960 reset-names = "stmmaceth"; 961 rockchip,grf = <&grf>; 962 tx-fifo-depth = <2048>; 963 rx-fifo-depth = <4096>; 964 snps,txpbl = <0x4>; 965 status = "disabled"; 966 }; 967 968 gmac2phy: ethernet@ff550000 { 969 compatible = "rockchip,rk3328-gmac"; 970 reg = <0x0 0xff550000 0x0 0x10000>; 971 rockchip,grf = <&grf>; 972 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 973 interrupt-names = "macirq"; 974 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 975 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 976 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 977 <&cru SCLK_MAC2PHY_OUT>; 978 clock-names = "stmmaceth", "mac_clk_rx", 979 "mac_clk_tx", "clk_mac_ref", 980 "aclk_mac", "pclk_mac", 981 "clk_macphy"; 982 resets = <&cru SRST_GMAC2PHY_A>; 983 reset-names = "stmmaceth"; 984 phy-mode = "rmii"; 985 phy-handle = <&phy>; 986 tx-fifo-depth = <2048>; 987 rx-fifo-depth = <4096>; 988 snps,txpbl = <0x4>; 989 clock_in_out = "output"; 990 status = "disabled"; 991 992 mdio { 993 compatible = "snps,dwmac-mdio"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 phy: ethernet-phy@0 { 998 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 999 reg = <0>; 1000 clocks = <&cru SCLK_MAC2PHY_OUT>; 1001 resets = <&cru SRST_MACPHY>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 1004 phy-is-integrated; 1005 }; 1006 }; 1007 }; 1008 1009 usb20_otg: usb@ff580000 { 1010 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 1011 "snps,dwc2"; 1012 reg = <0x0 0xff580000 0x0 0x40000>; 1013 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cru HCLK_OTG>; 1015 clock-names = "otg"; 1016 dr_mode = "otg"; 1017 g-np-tx-fifo-size = <16>; 1018 g-rx-fifo-size = <280>; 1019 g-tx-fifo-size = <256 128 128 64 32 16>; 1020 phys = <&u2phy_otg>; 1021 phy-names = "usb2-phy"; 1022 status = "disabled"; 1023 }; 1024 1025 usb_host0_ehci: usb@ff5c0000 { 1026 compatible = "generic-ehci"; 1027 reg = <0x0 0xff5c0000 0x0 0x10000>; 1028 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1030 phys = <&u2phy_host>; 1031 phy-names = "usb"; 1032 status = "disabled"; 1033 }; 1034 1035 usb_host0_ohci: usb@ff5d0000 { 1036 compatible = "generic-ohci"; 1037 reg = <0x0 0xff5d0000 0x0 0x10000>; 1038 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1040 phys = <&u2phy_host>; 1041 phy-names = "usb"; 1042 status = "disabled"; 1043 }; 1044 1045 sdmmc_ext: mmc@ff5f0000 { 1046 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 1047 reg = <0x0 0xff5f0000 0x0 0x4000>; 1048 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, 1050 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; 1051 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1052 fifo-depth = <0x100>; 1053 max-frequency = <150000000>; 1054 resets = <&cru SRST_SDMMCEXT>; 1055 reset-names = "reset"; 1056 status = "disabled"; 1057 }; 1058 1059 usbdrd3: usb@ff600000 { 1060 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1061 reg = <0x0 0xff600000 0x0 0x100000>; 1062 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1064 <&cru ACLK_USB3OTG>; 1065 clock-names = "ref_clk", "suspend_clk", 1066 "bus_clk"; 1067 dr_mode = "otg"; 1068 phy_type = "utmi_wide"; 1069 snps,dis-del-phy-power-chg-quirk; 1070 snps,dis_enblslpm_quirk; 1071 snps,dis-tx-ipgap-linecheck-quirk; 1072 snps,dis-u2-freeclk-exists-quirk; 1073 snps,dis_u2_susphy_quirk; 1074 snps,dis_u3_susphy_quirk; 1075 status = "disabled"; 1076 }; 1077 1078 gic: interrupt-controller@ff811000 { 1079 compatible = "arm,gic-400"; 1080 #interrupt-cells = <3>; 1081 #address-cells = <0>; 1082 interrupt-controller; 1083 reg = <0x0 0xff811000 0 0x1000>, 1084 <0x0 0xff812000 0 0x2000>, 1085 <0x0 0xff814000 0 0x2000>, 1086 <0x0 0xff816000 0 0x2000>; 1087 interrupts = <GIC_PPI 9 1088 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1089 }; 1090 1091 crypto: crypto@ff060000 { 1092 compatible = "rockchip,rk3328-crypto"; 1093 reg = <0x0 0xff060000 0x0 0x4000>; 1094 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1096 <&cru SCLK_CRYPTO>; 1097 clock-names = "hclk_master", "hclk_slave", "sclk"; 1098 resets = <&cru SRST_CRYPTO>; 1099 reset-names = "crypto-rst"; 1100 }; 1101 1102 pinctrl: pinctrl { 1103 compatible = "rockchip,rk3328-pinctrl"; 1104 rockchip,grf = <&grf>; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 1109 gpio0: gpio@ff210000 { 1110 compatible = "rockchip,gpio-bank"; 1111 reg = <0x0 0xff210000 0x0 0x100>; 1112 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cru PCLK_GPIO0>; 1114 1115 gpio-controller; 1116 #gpio-cells = <2>; 1117 1118 interrupt-controller; 1119 #interrupt-cells = <2>; 1120 }; 1121 1122 gpio1: gpio@ff220000 { 1123 compatible = "rockchip,gpio-bank"; 1124 reg = <0x0 0xff220000 0x0 0x100>; 1125 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&cru PCLK_GPIO1>; 1127 1128 gpio-controller; 1129 #gpio-cells = <2>; 1130 1131 interrupt-controller; 1132 #interrupt-cells = <2>; 1133 }; 1134 1135 gpio2: gpio@ff230000 { 1136 compatible = "rockchip,gpio-bank"; 1137 reg = <0x0 0xff230000 0x0 0x100>; 1138 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&cru PCLK_GPIO2>; 1140 1141 gpio-controller; 1142 #gpio-cells = <2>; 1143 1144 interrupt-controller; 1145 #interrupt-cells = <2>; 1146 }; 1147 1148 gpio3: gpio@ff240000 { 1149 compatible = "rockchip,gpio-bank"; 1150 reg = <0x0 0xff240000 0x0 0x100>; 1151 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&cru PCLK_GPIO3>; 1153 1154 gpio-controller; 1155 #gpio-cells = <2>; 1156 1157 interrupt-controller; 1158 #interrupt-cells = <2>; 1159 }; 1160 1161 pcfg_pull_up: pcfg-pull-up { 1162 bias-pull-up; 1163 }; 1164 1165 pcfg_pull_down: pcfg-pull-down { 1166 bias-pull-down; 1167 }; 1168 1169 pcfg_pull_none: pcfg-pull-none { 1170 bias-disable; 1171 }; 1172 1173 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1174 bias-disable; 1175 drive-strength = <2>; 1176 }; 1177 1178 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1179 bias-pull-up; 1180 drive-strength = <2>; 1181 }; 1182 1183 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1184 bias-pull-up; 1185 drive-strength = <4>; 1186 }; 1187 1188 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1189 bias-disable; 1190 drive-strength = <4>; 1191 }; 1192 1193 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1194 bias-pull-down; 1195 drive-strength = <4>; 1196 }; 1197 1198 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1199 bias-disable; 1200 drive-strength = <8>; 1201 }; 1202 1203 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1204 bias-pull-up; 1205 drive-strength = <8>; 1206 }; 1207 1208 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1209 bias-disable; 1210 drive-strength = <12>; 1211 }; 1212 1213 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1214 bias-pull-up; 1215 drive-strength = <12>; 1216 }; 1217 1218 pcfg_output_high: pcfg-output-high { 1219 output-high; 1220 }; 1221 1222 pcfg_output_low: pcfg-output-low { 1223 output-low; 1224 }; 1225 1226 pcfg_input_high: pcfg-input-high { 1227 bias-pull-up; 1228 input-enable; 1229 }; 1230 1231 pcfg_input: pcfg-input { 1232 input-enable; 1233 }; 1234 1235 i2c0 { 1236 i2c0_xfer: i2c0-xfer { 1237 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1238 <2 RK_PD1 1 &pcfg_pull_none>; 1239 }; 1240 }; 1241 1242 i2c1 { 1243 i2c1_xfer: i2c1-xfer { 1244 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1245 <2 RK_PA5 2 &pcfg_pull_none>; 1246 }; 1247 }; 1248 1249 i2c2 { 1250 i2c2_xfer: i2c2-xfer { 1251 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1252 <2 RK_PB6 1 &pcfg_pull_none>; 1253 }; 1254 }; 1255 1256 i2c3 { 1257 i2c3_xfer: i2c3-xfer { 1258 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1259 <0 RK_PA6 2 &pcfg_pull_none>; 1260 }; 1261 i2c3_pins: i2c3-pins { 1262 rockchip,pins = 1263 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1264 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1265 }; 1266 }; 1267 1268 hdmi_i2c { 1269 hdmii2c_xfer: hdmii2c-xfer { 1270 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1271 <0 RK_PA6 1 &pcfg_pull_none>; 1272 }; 1273 }; 1274 1275 pdm-0 { 1276 pdmm0_clk: pdmm0-clk { 1277 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1278 }; 1279 1280 pdmm0_fsync: pdmm0-fsync { 1281 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1282 }; 1283 1284 pdmm0_sdi0: pdmm0-sdi0 { 1285 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1286 }; 1287 1288 pdmm0_sdi1: pdmm0-sdi1 { 1289 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1290 }; 1291 1292 pdmm0_sdi2: pdmm0-sdi2 { 1293 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1294 }; 1295 1296 pdmm0_sdi3: pdmm0-sdi3 { 1297 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1298 }; 1299 1300 pdmm0_clk_sleep: pdmm0-clk-sleep { 1301 rockchip,pins = 1302 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1303 }; 1304 1305 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1306 rockchip,pins = 1307 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1308 }; 1309 1310 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1311 rockchip,pins = 1312 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1313 }; 1314 1315 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1316 rockchip,pins = 1317 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1318 }; 1319 1320 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1321 rockchip,pins = 1322 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1323 }; 1324 1325 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1326 rockchip,pins = 1327 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1328 }; 1329 }; 1330 1331 tsadc { 1332 otp_pin: otp-pin { 1333 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1334 }; 1335 1336 otp_out: otp-out { 1337 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1338 }; 1339 }; 1340 1341 uart0 { 1342 uart0_xfer: uart0-xfer { 1343 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1344 <1 RK_PB0 1 &pcfg_pull_up>; 1345 }; 1346 1347 uart0_cts: uart0-cts { 1348 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1349 }; 1350 1351 uart0_rts: uart0-rts { 1352 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1353 }; 1354 1355 uart0_rts_pin: uart0-rts-pin { 1356 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1357 }; 1358 }; 1359 1360 uart1 { 1361 uart1_xfer: uart1-xfer { 1362 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1363 <3 RK_PA6 4 &pcfg_pull_up>; 1364 }; 1365 1366 uart1_cts: uart1-cts { 1367 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1368 }; 1369 1370 uart1_rts: uart1-rts { 1371 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1372 }; 1373 1374 uart1_rts_pin: uart1-rts-pin { 1375 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1376 }; 1377 }; 1378 1379 uart2-0 { 1380 uart2m0_xfer: uart2m0-xfer { 1381 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1382 <1 RK_PA1 2 &pcfg_pull_up>; 1383 }; 1384 }; 1385 1386 uart2-1 { 1387 uart2m1_xfer: uart2m1-xfer { 1388 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1389 <2 RK_PA1 1 &pcfg_pull_up>; 1390 }; 1391 }; 1392 1393 spi0-0 { 1394 spi0m0_clk: spi0m0-clk { 1395 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1396 }; 1397 1398 spi0m0_cs0: spi0m0-cs0 { 1399 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1400 }; 1401 1402 spi0m0_tx: spi0m0-tx { 1403 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1404 }; 1405 1406 spi0m0_rx: spi0m0-rx { 1407 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1408 }; 1409 1410 spi0m0_cs1: spi0m0-cs1 { 1411 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1412 }; 1413 }; 1414 1415 spi0-1 { 1416 spi0m1_clk: spi0m1-clk { 1417 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1418 }; 1419 1420 spi0m1_cs0: spi0m1-cs0 { 1421 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1422 }; 1423 1424 spi0m1_tx: spi0m1-tx { 1425 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1426 }; 1427 1428 spi0m1_rx: spi0m1-rx { 1429 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1430 }; 1431 1432 spi0m1_cs1: spi0m1-cs1 { 1433 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1434 }; 1435 }; 1436 1437 spi0-2 { 1438 spi0m2_clk: spi0m2-clk { 1439 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1440 }; 1441 1442 spi0m2_cs0: spi0m2-cs0 { 1443 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1444 }; 1445 1446 spi0m2_tx: spi0m2-tx { 1447 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1448 }; 1449 1450 spi0m2_rx: spi0m2-rx { 1451 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1452 }; 1453 }; 1454 1455 i2s1 { 1456 i2s1_mclk: i2s1-mclk { 1457 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1458 }; 1459 1460 i2s1_sclk: i2s1-sclk { 1461 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1462 }; 1463 1464 i2s1_lrckrx: i2s1-lrckrx { 1465 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1466 }; 1467 1468 i2s1_lrcktx: i2s1-lrcktx { 1469 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1470 }; 1471 1472 i2s1_sdi: i2s1-sdi { 1473 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1474 }; 1475 1476 i2s1_sdo: i2s1-sdo { 1477 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1478 }; 1479 1480 i2s1_sdio1: i2s1-sdio1 { 1481 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1482 }; 1483 1484 i2s1_sdio2: i2s1-sdio2 { 1485 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1486 }; 1487 1488 i2s1_sdio3: i2s1-sdio3 { 1489 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1490 }; 1491 1492 i2s1_sleep: i2s1-sleep { 1493 rockchip,pins = 1494 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1495 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1496 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1497 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1498 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1499 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1500 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1501 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1502 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1503 }; 1504 }; 1505 1506 i2s2-0 { 1507 i2s2m0_mclk: i2s2m0-mclk { 1508 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1509 }; 1510 1511 i2s2m0_sclk: i2s2m0-sclk { 1512 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1513 }; 1514 1515 i2s2m0_lrckrx: i2s2m0-lrckrx { 1516 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1517 }; 1518 1519 i2s2m0_lrcktx: i2s2m0-lrcktx { 1520 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1521 }; 1522 1523 i2s2m0_sdi: i2s2m0-sdi { 1524 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1525 }; 1526 1527 i2s2m0_sdo: i2s2m0-sdo { 1528 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1529 }; 1530 1531 i2s2m0_sleep: i2s2m0-sleep { 1532 rockchip,pins = 1533 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1534 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1535 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1536 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1537 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1538 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1539 }; 1540 }; 1541 1542 i2s2-1 { 1543 i2s2m1_mclk: i2s2m1-mclk { 1544 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1545 }; 1546 1547 i2s2m1_sclk: i2s2m1-sclk { 1548 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1549 }; 1550 1551 i2s2m1_lrckrx: i2sm1-lrckrx { 1552 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1553 }; 1554 1555 i2s2m1_lrcktx: i2s2m1-lrcktx { 1556 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1557 }; 1558 1559 i2s2m1_sdi: i2s2m1-sdi { 1560 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1561 }; 1562 1563 i2s2m1_sdo: i2s2m1-sdo { 1564 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1565 }; 1566 1567 i2s2m1_sleep: i2s2m1-sleep { 1568 rockchip,pins = 1569 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1570 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1571 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1572 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1573 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1574 }; 1575 }; 1576 1577 spdif-0 { 1578 spdifm0_tx: spdifm0-tx { 1579 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1580 }; 1581 }; 1582 1583 spdif-1 { 1584 spdifm1_tx: spdifm1-tx { 1585 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1586 }; 1587 }; 1588 1589 spdif-2 { 1590 spdifm2_tx: spdifm2-tx { 1591 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1592 }; 1593 }; 1594 1595 sdmmc0-0 { 1596 sdmmc0m0_pwren: sdmmc0m0-pwren { 1597 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1598 }; 1599 1600 sdmmc0m0_pin: sdmmc0m0-pin { 1601 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1602 }; 1603 }; 1604 1605 sdmmc0-1 { 1606 sdmmc0m1_pwren: sdmmc0m1-pwren { 1607 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1608 }; 1609 1610 sdmmc0m1_pin: sdmmc0m1-pin { 1611 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1612 }; 1613 }; 1614 1615 sdmmc0 { 1616 sdmmc0_clk: sdmmc0-clk { 1617 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1618 }; 1619 1620 sdmmc0_cmd: sdmmc0-cmd { 1621 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1622 }; 1623 1624 sdmmc0_dectn: sdmmc0-dectn { 1625 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1626 }; 1627 1628 sdmmc0_wrprt: sdmmc0-wrprt { 1629 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1630 }; 1631 1632 sdmmc0_bus1: sdmmc0-bus1 { 1633 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1634 }; 1635 1636 sdmmc0_bus4: sdmmc0-bus4 { 1637 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1638 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1639 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1640 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1641 }; 1642 1643 sdmmc0_pins: sdmmc0-pins { 1644 rockchip,pins = 1645 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1646 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1651 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1652 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1653 }; 1654 }; 1655 1656 sdmmc0ext { 1657 sdmmc0ext_clk: sdmmc0ext-clk { 1658 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1659 }; 1660 1661 sdmmc0ext_cmd: sdmmc0ext-cmd { 1662 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1663 }; 1664 1665 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1666 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1667 }; 1668 1669 sdmmc0ext_dectn: sdmmc0ext-dectn { 1670 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1671 }; 1672 1673 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1674 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1675 }; 1676 1677 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1678 rockchip,pins = 1679 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1680 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1681 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1682 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1683 }; 1684 1685 sdmmc0ext_pins: sdmmc0ext-pins { 1686 rockchip,pins = 1687 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1688 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1689 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1690 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1691 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1692 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1693 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1694 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1695 }; 1696 }; 1697 1698 sdmmc1 { 1699 sdmmc1_clk: sdmmc1-clk { 1700 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1701 }; 1702 1703 sdmmc1_cmd: sdmmc1-cmd { 1704 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1705 }; 1706 1707 sdmmc1_pwren: sdmmc1-pwren { 1708 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1709 }; 1710 1711 sdmmc1_wrprt: sdmmc1-wrprt { 1712 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1713 }; 1714 1715 sdmmc1_dectn: sdmmc1-dectn { 1716 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1717 }; 1718 1719 sdmmc1_bus1: sdmmc1-bus1 { 1720 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1721 }; 1722 1723 sdmmc1_bus4: sdmmc1-bus4 { 1724 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1725 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1726 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1727 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1728 }; 1729 1730 sdmmc1_pins: sdmmc1-pins { 1731 rockchip,pins = 1732 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1733 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1734 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1735 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1736 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1737 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1738 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1739 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1740 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1741 }; 1742 }; 1743 1744 emmc { 1745 emmc_clk: emmc-clk { 1746 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1747 }; 1748 1749 emmc_cmd: emmc-cmd { 1750 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1751 }; 1752 1753 emmc_pwren: emmc-pwren { 1754 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1755 }; 1756 1757 emmc_rstnout: emmc-rstnout { 1758 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1759 }; 1760 1761 emmc_bus1: emmc-bus1 { 1762 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1763 }; 1764 1765 emmc_bus4: emmc-bus4 { 1766 rockchip,pins = 1767 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1768 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1769 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1770 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1771 }; 1772 1773 emmc_bus8: emmc-bus8 { 1774 rockchip,pins = 1775 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1776 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1777 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1778 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1779 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1780 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1781 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1782 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1783 }; 1784 }; 1785 1786 pwm0 { 1787 pwm0_pin: pwm0-pin { 1788 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1789 }; 1790 }; 1791 1792 pwm1 { 1793 pwm1_pin: pwm1-pin { 1794 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1795 }; 1796 }; 1797 1798 pwm2 { 1799 pwm2_pin: pwm2-pin { 1800 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1801 }; 1802 }; 1803 1804 pwmir { 1805 pwmir_pin: pwmir-pin { 1806 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1807 }; 1808 }; 1809 1810 gmac-1 { 1811 rgmiim1_pins: rgmiim1-pins { 1812 rockchip,pins = 1813 /* mac_txclk */ 1814 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1815 /* mac_rxclk */ 1816 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1817 /* mac_mdio */ 1818 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1819 /* mac_txen */ 1820 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1821 /* mac_clk */ 1822 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1823 /* mac_rxdv */ 1824 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1825 /* mac_mdc */ 1826 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1827 /* mac_rxd1 */ 1828 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1829 /* mac_rxd0 */ 1830 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1831 /* mac_txd1 */ 1832 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1833 /* mac_txd0 */ 1834 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1835 /* mac_rxd3 */ 1836 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1837 /* mac_rxd2 */ 1838 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1839 /* mac_txd3 */ 1840 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1841 /* mac_txd2 */ 1842 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1843 1844 /* mac_txclk */ 1845 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1846 /* mac_txen */ 1847 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1848 /* mac_clk */ 1849 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1850 /* mac_txd1 */ 1851 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1852 /* mac_txd0 */ 1853 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1854 /* mac_txd3 */ 1855 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1856 /* mac_txd2 */ 1857 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1858 }; 1859 1860 rmiim1_pins: rmiim1-pins { 1861 rockchip,pins = 1862 /* mac_mdio */ 1863 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1864 /* mac_txen */ 1865 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1866 /* mac_clk */ 1867 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1868 /* mac_rxer */ 1869 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1870 /* mac_rxdv */ 1871 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1872 /* mac_mdc */ 1873 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1874 /* mac_rxd1 */ 1875 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1876 /* mac_rxd0 */ 1877 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1878 /* mac_txd1 */ 1879 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1880 /* mac_txd0 */ 1881 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1882 1883 /* mac_mdio */ 1884 <0 RK_PB3 1 &pcfg_pull_none>, 1885 /* mac_txen */ 1886 <0 RK_PB4 1 &pcfg_pull_none>, 1887 /* mac_clk */ 1888 <0 RK_PD0 1 &pcfg_pull_none>, 1889 /* mac_mdc */ 1890 <0 RK_PC3 1 &pcfg_pull_none>, 1891 /* mac_txd1 */ 1892 <0 RK_PC0 1 &pcfg_pull_none>, 1893 /* mac_txd0 */ 1894 <0 RK_PC1 1 &pcfg_pull_none>; 1895 }; 1896 }; 1897 1898 gmac2phy { 1899 fephyled_speed10: fephyled-speed10 { 1900 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1901 }; 1902 1903 fephyled_duplex: fephyled-duplex { 1904 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1905 }; 1906 1907 fephyled_rxm1: fephyled-rxm1 { 1908 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1909 }; 1910 1911 fephyled_txm1: fephyled-txm1 { 1912 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1913 }; 1914 1915 fephyled_linkm1: fephyled-linkm1 { 1916 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1917 }; 1918 }; 1919 1920 tsadc_pin { 1921 tsadc_int: tsadc-int { 1922 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1923 }; 1924 tsadc_pin: tsadc-pin { 1925 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1926 }; 1927 }; 1928 1929 hdmi_pin { 1930 hdmi_cec: hdmi-cec { 1931 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1932 }; 1933 1934 hdmi_hpd: hdmi-hpd { 1935 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1936 }; 1937 }; 1938 1939 cif-0 { 1940 dvp_d2d9_m0:dvp-d2d9-m0 { 1941 rockchip,pins = 1942 /* cif_d0 */ 1943 <3 RK_PA4 2 &pcfg_pull_none>, 1944 /* cif_d1 */ 1945 <3 RK_PA5 2 &pcfg_pull_none>, 1946 /* cif_d2 */ 1947 <3 RK_PA6 2 &pcfg_pull_none>, 1948 /* cif_d3 */ 1949 <3 RK_PA7 2 &pcfg_pull_none>, 1950 /* cif_d4 */ 1951 <3 RK_PB0 2 &pcfg_pull_none>, 1952 /* cif_d5m0 */ 1953 <3 RK_PB1 2 &pcfg_pull_none>, 1954 /* cif_d6m0 */ 1955 <3 RK_PB2 2 &pcfg_pull_none>, 1956 /* cif_d7m0 */ 1957 <3 RK_PB3 2 &pcfg_pull_none>, 1958 /* cif_href */ 1959 <3 RK_PA1 2 &pcfg_pull_none>, 1960 /* cif_vsync */ 1961 <3 RK_PA0 2 &pcfg_pull_none>, 1962 /* cif_clkoutm0 */ 1963 <3 RK_PA3 2 &pcfg_pull_none>, 1964 /* cif_clkin */ 1965 <3 RK_PA2 2 &pcfg_pull_none>; 1966 }; 1967 }; 1968 1969 cif-1 { 1970 dvp_d2d9_m1:dvp-d2d9-m1 { 1971 rockchip,pins = 1972 /* cif_d0 */ 1973 <3 RK_PA4 2 &pcfg_pull_none>, 1974 /* cif_d1 */ 1975 <3 RK_PA5 2 &pcfg_pull_none>, 1976 /* cif_d2 */ 1977 <3 RK_PA6 2 &pcfg_pull_none>, 1978 /* cif_d3 */ 1979 <3 RK_PA7 2 &pcfg_pull_none>, 1980 /* cif_d4 */ 1981 <3 RK_PB0 2 &pcfg_pull_none>, 1982 /* cif_d5m1 */ 1983 <2 RK_PC0 4 &pcfg_pull_none>, 1984 /* cif_d6m1 */ 1985 <2 RK_PC1 4 &pcfg_pull_none>, 1986 /* cif_d7m1 */ 1987 <2 RK_PC2 4 &pcfg_pull_none>, 1988 /* cif_href */ 1989 <3 RK_PA1 2 &pcfg_pull_none>, 1990 /* cif_vsync */ 1991 <3 RK_PA0 2 &pcfg_pull_none>, 1992 /* cif_clkoutm1 */ 1993 <2 RK_PB7 4 &pcfg_pull_none>, 1994 /* cif_clkin */ 1995 <3 RK_PA2 2 &pcfg_pull_none>; 1996 }; 1997 }; 1998 }; 1999}; 2000