1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASSEMBLY__ 9 #error "Only include this from assembly code" 10 #endif 11 12 #ifndef __ASM_ASSEMBLER_H 13 #define __ASM_ASSEMBLER_H 14 15 #include <linux/export.h> 16 17 #include <asm/alternative.h> 18 #include <asm/asm-bug.h> 19 #include <asm/asm-extable.h> 20 #include <asm/asm-offsets.h> 21 #include <asm/cpufeature.h> 22 #include <asm/cputype.h> 23 #include <asm/debug-monitors.h> 24 #include <asm/page.h> 25 #include <asm/pgtable-hwdef.h> 26 #include <asm/ptrace.h> 27 #include <asm/thread_info.h> 28 29 /* 30 * Provide a wxN alias for each wN register so what we can paste a xN 31 * reference after a 'w' to obtain the 32-bit version. 32 */ 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 34 wx\n .req w\n 35 .endr 36 37 .macro disable_daif 38 msr daifset, #0xf 39 .endm 40 41 /* 42 * Save/restore interrupts. 43 */ 44 .macro save_and_disable_daif, flags 45 mrs \flags, daif 46 msr daifset, #0xf 47 .endm 48 49 .macro save_and_disable_irq, flags 50 mrs \flags, daif 51 msr daifset, #3 52 .endm 53 54 .macro restore_irq, flags 55 msr daif, \flags 56 .endm 57 58 .macro disable_step_tsk, flgs, tmp 59 tbz \flgs, #TIF_SINGLESTEP, 9990f 60 mrs \tmp, mdscr_el1 61 bic \tmp, \tmp, #DBG_MDSCR_SS 62 msr mdscr_el1, \tmp 63 isb // Take effect before a subsequent clear of DAIF.D 64 9990: 65 .endm 66 67 /* call with daif masked */ 68 .macro enable_step_tsk, flgs, tmp 69 tbz \flgs, #TIF_SINGLESTEP, 9990f 70 mrs \tmp, mdscr_el1 71 orr \tmp, \tmp, #DBG_MDSCR_SS 72 msr mdscr_el1, \tmp 73 9990: 74 .endm 75 76 /* 77 * RAS Error Synchronization barrier 78 */ 79 .macro esb 80 #ifdef CONFIG_ARM64_RAS_EXTN 81 hint #16 82 #else 83 nop 84 #endif 85 .endm 86 87 /* 88 * Value prediction barrier 89 */ 90 .macro csdb 91 hint #20 92 .endm 93 94 /* 95 * Clear Branch History instruction 96 */ 97 .macro clearbhb 98 hint #22 99 .endm 100 101 /* 102 * Speculation barrier 103 */ 104 .macro sb 105 alternative_if_not ARM64_HAS_SB 106 dsb nsh 107 isb 108 alternative_else 109 SB_BARRIER_INSN 110 nop 111 alternative_endif 112 .endm 113 114 /* 115 * NOP sequence 116 */ 117 .macro nops, num 118 .rept \num 119 nop 120 .endr 121 .endm 122 123 /* 124 * Register aliases. 125 */ 126 lr .req x30 // link register 127 128 /* 129 * Vector entry 130 */ 131 .macro ventry label 132 .align 7 133 b \label 134 .endm 135 136 /* 137 * Select code when configured for BE. 138 */ 139 #ifdef CONFIG_CPU_BIG_ENDIAN 140 #define CPU_BE(code...) code 141 #else 142 #define CPU_BE(code...) 143 #endif 144 145 /* 146 * Select code when configured for LE. 147 */ 148 #ifdef CONFIG_CPU_BIG_ENDIAN 149 #define CPU_LE(code...) 150 #else 151 #define CPU_LE(code...) code 152 #endif 153 154 /* 155 * Define a macro that constructs a 64-bit value by concatenating two 156 * 32-bit registers. Note that on big endian systems the order of the 157 * registers is swapped. 158 */ 159 #ifndef CONFIG_CPU_BIG_ENDIAN 160 .macro regs_to_64, rd, lbits, hbits 161 #else 162 .macro regs_to_64, rd, hbits, lbits 163 #endif 164 orr \rd, \lbits, \hbits, lsl #32 165 .endm 166 167 /* 168 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where 169 * <symbol> is within the range +/- 4 GB of the PC. 170 */ 171 /* 172 * @dst: destination register (64 bit wide) 173 * @sym: name of the symbol 174 */ 175 .macro adr_l, dst, sym 176 adrp \dst, \sym 177 add \dst, \dst, :lo12:\sym 178 .endm 179 180 /* 181 * @dst: destination register (32 or 64 bit wide) 182 * @sym: name of the symbol 183 * @tmp: optional 64-bit scratch register to be used if <dst> is a 184 * 32-bit wide register, in which case it cannot be used to hold 185 * the address 186 */ 187 .macro ldr_l, dst, sym, tmp= 188 .ifb \tmp 189 adrp \dst, \sym 190 ldr \dst, [\dst, :lo12:\sym] 191 .else 192 adrp \tmp, \sym 193 ldr \dst, [\tmp, :lo12:\sym] 194 .endif 195 .endm 196 197 /* 198 * @src: source register (32 or 64 bit wide) 199 * @sym: name of the symbol 200 * @tmp: mandatory 64-bit scratch register to calculate the address 201 * while <src> needs to be preserved. 202 */ 203 .macro str_l, src, sym, tmp 204 adrp \tmp, \sym 205 str \src, [\tmp, :lo12:\sym] 206 .endm 207 208 /* 209 * @dst: destination register 210 */ 211 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 212 .macro get_this_cpu_offset, dst 213 mrs \dst, tpidr_el2 214 .endm 215 #else 216 .macro get_this_cpu_offset, dst 217 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 218 mrs \dst, tpidr_el1 219 alternative_else 220 mrs \dst, tpidr_el2 221 alternative_endif 222 .endm 223 224 .macro set_this_cpu_offset, src 225 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 226 msr tpidr_el1, \src 227 alternative_else 228 msr tpidr_el2, \src 229 alternative_endif 230 .endm 231 #endif 232 233 /* 234 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP) 235 * @sym: The name of the per-cpu variable 236 * @tmp: scratch register 237 */ 238 .macro adr_this_cpu, dst, sym, tmp 239 adrp \tmp, \sym 240 add \dst, \tmp, #:lo12:\sym 241 get_this_cpu_offset \tmp 242 add \dst, \dst, \tmp 243 .endm 244 245 /* 246 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) 247 * @sym: The name of the per-cpu variable 248 * @tmp: scratch register 249 */ 250 .macro ldr_this_cpu dst, sym, tmp 251 adr_l \dst, \sym 252 get_this_cpu_offset \tmp 253 ldr \dst, [\dst, \tmp] 254 .endm 255 256 /* 257 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) 258 */ 259 .macro vma_vm_mm, rd, rn 260 ldr \rd, [\rn, #VMA_VM_MM] 261 .endm 262 263 /* 264 * read_ctr - read CTR_EL0. If the system has mismatched register fields, 265 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val 266 */ 267 .macro read_ctr, reg 268 #ifndef __KVM_NVHE_HYPERVISOR__ 269 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE 270 mrs \reg, ctr_el0 // read CTR 271 nop 272 alternative_else 273 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL 274 alternative_endif 275 #else 276 alternative_if_not ARM64_KVM_PROTECTED_MODE 277 ASM_BUG() 278 alternative_else_nop_endif 279 alternative_cb ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0 280 movz \reg, #0 281 movk \reg, #0, lsl #16 282 movk \reg, #0, lsl #32 283 movk \reg, #0, lsl #48 284 alternative_cb_end 285 #endif 286 .endm 287 288 289 /* 290 * raw_dcache_line_size - get the minimum D-cache line size on this CPU 291 * from the CTR register. 292 */ 293 .macro raw_dcache_line_size, reg, tmp 294 mrs \tmp, ctr_el0 // read CTR 295 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 296 mov \reg, #4 // bytes per word 297 lsl \reg, \reg, \tmp // actual cache line size 298 .endm 299 300 /* 301 * dcache_line_size - get the safe D-cache line size across all CPUs 302 */ 303 .macro dcache_line_size, reg, tmp 304 read_ctr \tmp 305 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 306 mov \reg, #4 // bytes per word 307 lsl \reg, \reg, \tmp // actual cache line size 308 .endm 309 310 /* 311 * raw_icache_line_size - get the minimum I-cache line size on this CPU 312 * from the CTR register. 313 */ 314 .macro raw_icache_line_size, reg, tmp 315 mrs \tmp, ctr_el0 // read CTR 316 and \tmp, \tmp, #0xf // cache line size encoding 317 mov \reg, #4 // bytes per word 318 lsl \reg, \reg, \tmp // actual cache line size 319 .endm 320 321 /* 322 * icache_line_size - get the safe I-cache line size across all CPUs 323 */ 324 .macro icache_line_size, reg, tmp 325 read_ctr \tmp 326 and \tmp, \tmp, #0xf // cache line size encoding 327 mov \reg, #4 // bytes per word 328 lsl \reg, \reg, \tmp // actual cache line size 329 .endm 330 331 /* 332 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map 333 */ 334 .macro tcr_set_t0sz, valreg, t0sz 335 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH 336 .endm 337 338 /* 339 * tcr_set_t1sz - update TCR.T1SZ 340 */ 341 .macro tcr_set_t1sz, valreg, t1sz 342 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH 343 .endm 344 345 /* 346 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported 347 * ID_AA64MMFR0_EL1.PARange value 348 * 349 * tcr: register with the TCR_ELx value to be updated 350 * pos: IPS or PS bitfield position 351 * tmp{0,1}: temporary registers 352 */ 353 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 354 mrs \tmp0, ID_AA64MMFR0_EL1 355 // Narrow PARange to fit the PS field in TCR_ELx 356 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3 357 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX 358 #ifdef CONFIG_ARM64_LPA2 359 alternative_if_not ARM64_HAS_VA52 360 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48 361 alternative_else_nop_endif 362 #endif 363 cmp \tmp0, \tmp1 364 csel \tmp0, \tmp1, \tmp0, hi 365 bfi \tcr, \tmp0, \pos, #3 366 .endm 367 368 .macro __dcache_op_workaround_clean_cache, op, addr 369 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE 370 dc \op, \addr 371 alternative_else 372 dc civac, \addr 373 alternative_endif 374 .endm 375 376 /* 377 * Macro to perform a data cache maintenance for the interval 378 * [start, end) with dcache line size explicitly provided. 379 * 380 * op: operation passed to dc instruction 381 * domain: domain used in dsb instruciton 382 * start: starting virtual address of the region 383 * end: end virtual address of the region 384 * linesz: dcache line size 385 * fixup: optional label to branch to on user fault 386 * Corrupts: start, end, tmp 387 */ 388 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup 389 sub \tmp, \linesz, #1 390 bic \start, \start, \tmp 391 .Ldcache_op\@: 392 .ifc \op, cvau 393 __dcache_op_workaround_clean_cache \op, \start 394 .else 395 .ifc \op, cvac 396 __dcache_op_workaround_clean_cache \op, \start 397 .else 398 .ifc \op, cvap 399 sys 3, c7, c12, 1, \start // dc cvap 400 .else 401 .ifc \op, cvadp 402 sys 3, c7, c13, 1, \start // dc cvadp 403 .else 404 dc \op, \start 405 .endif 406 .endif 407 .endif 408 .endif 409 add \start, \start, \linesz 410 cmp \start, \end 411 b.lo .Ldcache_op\@ 412 dsb \domain 413 414 _cond_uaccess_extable .Ldcache_op\@, \fixup 415 .endm 416 417 /* 418 * Macro to perform a data cache maintenance for the interval 419 * [start, end) 420 * 421 * op: operation passed to dc instruction 422 * domain: domain used in dsb instruciton 423 * start: starting virtual address of the region 424 * end: end virtual address of the region 425 * fixup: optional label to branch to on user fault 426 * Corrupts: start, end, tmp1, tmp2 427 */ 428 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup 429 dcache_line_size \tmp1, \tmp2 430 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup 431 .endm 432 433 /* 434 * Macro to perform an instruction cache maintenance for the interval 435 * [start, end) 436 * 437 * start, end: virtual addresses describing the region 438 * fixup: optional label to branch to on user fault 439 * Corrupts: tmp1, tmp2 440 */ 441 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup 442 icache_line_size \tmp1, \tmp2 443 sub \tmp2, \tmp1, #1 444 bic \tmp2, \start, \tmp2 445 .Licache_op\@: 446 ic ivau, \tmp2 // invalidate I line PoU 447 add \tmp2, \tmp2, \tmp1 448 cmp \tmp2, \end 449 b.lo .Licache_op\@ 450 dsb ish 451 isb 452 453 _cond_uaccess_extable .Licache_op\@, \fixup 454 .endm 455 456 /* 457 * load_ttbr1 - install @pgtbl as a TTBR1 page table 458 * pgtbl preserved 459 * tmp1/tmp2 clobbered, either may overlap with pgtbl 460 */ 461 .macro load_ttbr1, pgtbl, tmp1, tmp2 462 phys_to_ttbr \tmp1, \pgtbl 463 offset_ttbr1 \tmp1, \tmp2 464 msr ttbr1_el1, \tmp1 465 isb 466 .endm 467 468 /* 469 * To prevent the possibility of old and new partial table walks being visible 470 * in the tlb, switch the ttbr to a zero page when we invalidate the old 471 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i 472 * Even switching to our copied tables will cause a changed output address at 473 * each stage of the walk. 474 */ 475 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2 476 phys_to_ttbr \tmp, \zero_page 477 msr ttbr1_el1, \tmp 478 isb 479 tlbi vmalle1 480 dsb nsh 481 load_ttbr1 \page_table, \tmp, \tmp2 482 .endm 483 484 /* 485 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present 486 */ 487 .macro reset_pmuserenr_el0, tmpreg 488 mrs \tmpreg, id_aa64dfr0_el1 489 ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 490 cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI 491 ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 492 b.eq 9000f // Skip if no PMU present or IMP_DEF 493 msr pmuserenr_el0, xzr // Disable PMU access from EL0 494 9000: 495 .endm 496 497 /* 498 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present 499 */ 500 .macro reset_amuserenr_el0, tmpreg 501 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 502 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 503 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present 504 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 505 .Lskip_\@: 506 .endm 507 /* 508 * copy_page - copy src to dest using temp registers t1-t8 509 */ 510 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 511 9998: ldp \t1, \t2, [\src] 512 ldp \t3, \t4, [\src, #16] 513 ldp \t5, \t6, [\src, #32] 514 ldp \t7, \t8, [\src, #48] 515 add \src, \src, #64 516 stnp \t1, \t2, [\dest] 517 stnp \t3, \t4, [\dest, #16] 518 stnp \t5, \t6, [\dest, #32] 519 stnp \t7, \t8, [\dest, #48] 520 add \dest, \dest, #64 521 tst \src, #(PAGE_SIZE - 1) 522 b.ne 9998b 523 .endm 524 525 /* 526 * Annotate a function as being unsuitable for kprobes. 527 */ 528 #ifdef CONFIG_KPROBES 529 #define NOKPROBE(x) \ 530 .pushsection "_kprobe_blacklist", "aw"; \ 531 .quad x; \ 532 .popsection; 533 #else 534 #define NOKPROBE(x) 535 #endif 536 537 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 538 #define EXPORT_SYMBOL_NOKASAN(name) 539 #else 540 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name) 541 #endif 542 543 /* 544 * Emit a 64-bit absolute little endian symbol reference in a way that 545 * ensures that it will be resolved at build time, even when building a 546 * PIE binary. This requires cooperation from the linker script, which 547 * must emit the lo32/hi32 halves individually. 548 */ 549 .macro le64sym, sym 550 .long \sym\()_lo32 551 .long \sym\()_hi32 552 .endm 553 554 /* 555 * mov_q - move an immediate constant into a 64-bit register using 556 * between 2 and 4 movz/movk instructions (depending on the 557 * magnitude and sign of the operand) 558 */ 559 .macro mov_q, reg, val 560 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) 561 movz \reg, :abs_g1_s:\val 562 .else 563 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) 564 movz \reg, :abs_g2_s:\val 565 .else 566 movz \reg, :abs_g3:\val 567 movk \reg, :abs_g2_nc:\val 568 .endif 569 movk \reg, :abs_g1_nc:\val 570 .endif 571 movk \reg, :abs_g0_nc:\val 572 .endm 573 574 /* 575 * Return the current task_struct. 576 */ 577 .macro get_current_task, rd 578 mrs \rd, sp_el0 579 .endm 580 581 /* 582 * If the kernel is built for 52-bit virtual addressing but the hardware only 583 * supports 48 bits, we cannot program the pgdir address into TTBR1 directly, 584 * but we have to add an offset so that the TTBR1 address corresponds with the 585 * pgdir entry that covers the lowest 48-bit addressable VA. 586 * 587 * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an 588 * additional paging level, and on LPA2/16k pages, we would end up with a root 589 * level table with only 2 entries, which is suboptimal in terms of TLB 590 * utilization, so there we fall back to 47 bits of translation if LPA2 is not 591 * supported. 592 * 593 * orr is used as it can cover the immediate value (and is idempotent). 594 * ttbr: Value of ttbr to set, modified. 595 */ 596 .macro offset_ttbr1, ttbr, tmp 597 #if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2) 598 mrs \tmp, tcr_el1 599 and \tmp, \tmp, #TCR_T1SZ_MASK 600 cmp \tmp, #TCR_T1SZ(VA_BITS_MIN) 601 orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET 602 csel \ttbr, \tmp, \ttbr, eq 603 #endif 604 .endm 605 606 /* 607 * Arrange a physical address in a TTBR register, taking care of 52-bit 608 * addresses. 609 * 610 * phys: physical address, preserved 611 * ttbr: returns the TTBR value 612 */ 613 .macro phys_to_ttbr, ttbr, phys 614 #ifdef CONFIG_ARM64_PA_BITS_52 615 orr \ttbr, \phys, \phys, lsr #46 616 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 617 #else 618 mov \ttbr, \phys 619 #endif 620 .endm 621 622 .macro phys_to_pte, pte, phys 623 #ifdef CONFIG_ARM64_PA_BITS_52 624 orr \pte, \phys, \phys, lsr #PTE_ADDR_HIGH_SHIFT 625 and \pte, \pte, #PHYS_TO_PTE_ADDR_MASK 626 #else 627 mov \pte, \phys 628 #endif 629 .endm 630 631 /* 632 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU. 633 */ 634 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2 635 #ifdef CONFIG_FUJITSU_ERRATUM_010001 636 mrs \tmp1, midr_el1 637 638 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK 639 and \tmp1, \tmp1, \tmp2 640 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001 641 cmp \tmp1, \tmp2 642 b.ne 10f 643 644 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001 645 bic \tcr, \tcr, \tmp2 646 10: 647 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */ 648 .endm 649 650 /** 651 * Errata workaround prior to disable MMU. Insert an ISB immediately prior 652 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. 653 */ 654 .macro pre_disable_mmu_workaround 655 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 656 isb 657 #endif 658 .endm 659 660 /* 661 * frame_push - Push @regcount callee saved registers to the stack, 662 * starting at x19, as well as x29/x30, and set x29 to 663 * the new value of sp. Add @extra bytes of stack space 664 * for locals. 665 */ 666 .macro frame_push, regcount:req, extra 667 __frame st, \regcount, \extra 668 .endm 669 670 /* 671 * frame_pop - Pop the callee saved registers from the stack that were 672 * pushed in the most recent call to frame_push, as well 673 * as x29/x30 and any extra stack space that may have been 674 * allocated. 675 */ 676 .macro frame_pop 677 __frame ld 678 .endm 679 680 .macro __frame_regs, reg1, reg2, op, num 681 .if .Lframe_regcount == \num 682 \op\()r \reg1, [sp, #(\num + 1) * 8] 683 .elseif .Lframe_regcount > \num 684 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] 685 .endif 686 .endm 687 688 .macro __frame, op, regcount, extra=0 689 .ifc \op, st 690 .if (\regcount) < 0 || (\regcount) > 10 691 .error "regcount should be in the range [0 ... 10]" 692 .endif 693 .if ((\extra) % 16) != 0 694 .error "extra should be a multiple of 16 bytes" 695 .endif 696 .ifdef .Lframe_regcount 697 .if .Lframe_regcount != -1 698 .error "frame_push/frame_pop may not be nested" 699 .endif 700 .endif 701 .set .Lframe_regcount, \regcount 702 .set .Lframe_extra, \extra 703 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 704 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! 705 mov x29, sp 706 .endif 707 708 __frame_regs x19, x20, \op, 1 709 __frame_regs x21, x22, \op, 3 710 __frame_regs x23, x24, \op, 5 711 __frame_regs x25, x26, \op, 7 712 __frame_regs x27, x28, \op, 9 713 714 .ifc \op, ld 715 .if .Lframe_regcount == -1 716 .error "frame_push/frame_pop may not be nested" 717 .endif 718 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra 719 .set .Lframe_regcount, -1 720 .endif 721 .endm 722 723 /* 724 * Set SCTLR_ELx to the @reg value, and invalidate the local icache 725 * in the process. This is called when setting the MMU on. 726 */ 727 .macro set_sctlr, sreg, reg 728 msr \sreg, \reg 729 isb 730 /* 731 * Invalidate the local I-cache so that any instructions fetched 732 * speculatively from the PoC are discarded, since they may have 733 * been dynamically patched at the PoU. 734 */ 735 ic iallu 736 dsb nsh 737 isb 738 .endm 739 740 .macro set_sctlr_el1, reg 741 set_sctlr sctlr_el1, \reg 742 .endm 743 744 .macro set_sctlr_el2, reg 745 set_sctlr sctlr_el2, \reg 746 .endm 747 748 /* 749 * Check whether asm code should yield as soon as it is able. This is 750 * the case if we are currently running in task context, and the 751 * TIF_NEED_RESCHED flag is set. (Note that the TIF_NEED_RESCHED flag 752 * is stored negated in the top word of the thread_info::preempt_count 753 * field) 754 */ 755 .macro cond_yield, lbl:req, tmp:req, tmp2 756 #ifdef CONFIG_PREEMPT_VOLUNTARY 757 get_current_task \tmp 758 ldr \tmp, [\tmp, #TSK_TI_PREEMPT] 759 /* 760 * If we are serving a softirq, there is no point in yielding: the 761 * softirq will not be preempted no matter what we do, so we should 762 * run to completion as quickly as we can. The preempt_count field will 763 * have BIT(SOFTIRQ_SHIFT) set in this case, so the zero check will 764 * catch this case too. 765 */ 766 cbz \tmp, \lbl 767 #endif 768 .endm 769 770 /* 771 * Branch Target Identifier (BTI) 772 */ 773 .macro bti, targets 774 .equ .L__bti_targets_c, 34 775 .equ .L__bti_targets_j, 36 776 .equ .L__bti_targets_jc,38 777 hint #.L__bti_targets_\targets 778 .endm 779 780 /* 781 * This macro emits a program property note section identifying 782 * architecture features which require special handling, mainly for 783 * use in assembly files included in the VDSO. 784 */ 785 786 #define NT_GNU_PROPERTY_TYPE_0 5 787 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 788 789 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) 790 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) 791 792 #ifdef CONFIG_ARM64_BTI_KERNEL 793 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \ 794 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \ 795 GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) 796 #endif 797 798 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 799 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 800 .pushsection .note.gnu.property, "a" 801 .align 3 802 .long 2f - 1f 803 .long 6f - 3f 804 .long NT_GNU_PROPERTY_TYPE_0 805 1: .string "GNU" 806 2: 807 .align 3 808 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND 809 .long 5f - 4f 810 4: 811 /* 812 * This is described with an array of char in the Linux API 813 * spec but the text and all other usage (including binutils, 814 * clang and GCC) treat this as a 32 bit value so no swizzling 815 * is required for big endian. 816 */ 817 .long \feat 818 5: 819 .align 3 820 6: 821 .popsection 822 .endm 823 824 #else 825 .macro emit_aarch64_feature_1_and, feat=0 826 .endm 827 828 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */ 829 830 .macro __mitigate_spectre_bhb_loop tmp 831 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 832 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_iter 833 mov \tmp, #32 // Patched to correct the immediate 834 alternative_cb_end 835 .Lspectre_bhb_loop\@: 836 b . + 4 837 subs \tmp, \tmp, #1 838 b.ne .Lspectre_bhb_loop\@ 839 sb 840 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 841 .endm 842 843 .macro mitigate_spectre_bhb_loop tmp 844 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 845 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_mitigation_enable 846 b .L_spectre_bhb_loop_done\@ // Patched to NOP 847 alternative_cb_end 848 __mitigate_spectre_bhb_loop \tmp 849 .L_spectre_bhb_loop_done\@: 850 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 851 .endm 852 853 /* Save/restores x0-x3 to the stack */ 854 .macro __mitigate_spectre_bhb_fw 855 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 856 stp x0, x1, [sp, #-16]! 857 stp x2, x3, [sp, #-16]! 858 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 859 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 860 nop // Patched to SMC/HVC #0 861 alternative_cb_end 862 ldp x2, x3, [sp], #16 863 ldp x0, x1, [sp], #16 864 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 865 .endm 866 867 .macro mitigate_spectre_bhb_clear_insn 868 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 869 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_clearbhb 870 /* Patched to NOP when not supported */ 871 clearbhb 872 isb 873 alternative_cb_end 874 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 875 .endm 876 877 #if defined(__KVM_NVHE_HYPERVISOR__) 878 /* 879 * pKVM uses the module_ops struct to expose services to modules but 880 * doesn't allow fine-grained definition of the license for each export, 881 * and doesn't have a way to check the license of the loaded module. 882 * Given that said module may be proprietary, let's seek GPL compliance 883 * by preventing the accidental export of GPL symbols to hyp modules via 884 * pKVM's module_ops struct. 885 */ 886 #ifdef EXPORT_SYMBOL_GPL 887 #undef EXPORT_SYMBOL_GPL 888 #endif 889 #define EXPORT_SYMBOL_GPL(sym) ASM_BUILD_BUG() 890 #endif 891 #endif /* __ASM_ASSEMBLER_H */ 892