1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Record and handle CPU attributes.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27
28 #include <trace/hooks/cpuinfo.h>
29
30 /*
31 * In case the boot CPU is hotpluggable, we record its initial state and
32 * current state separately. Certain system registers may contain different
33 * values depending on configuration at or after reset.
34 */
35 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
36 static struct cpuinfo_arm64 boot_cpu_data;
37
icache_policy_str(int l1ip)38 static inline const char *icache_policy_str(int l1ip)
39 {
40 switch (l1ip) {
41 case CTR_EL0_L1Ip_VIPT:
42 return "VIPT";
43 case CTR_EL0_L1Ip_PIPT:
44 return "PIPT";
45 default:
46 return "RESERVED/UNKNOWN";
47 }
48 }
49
50 unsigned long __icache_flags;
51
52 static const char *const hwcap_str[] = {
53 [KERNEL_HWCAP_FP] = "fp",
54 [KERNEL_HWCAP_ASIMD] = "asimd",
55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
56 [KERNEL_HWCAP_AES] = "aes",
57 [KERNEL_HWCAP_PMULL] = "pmull",
58 [KERNEL_HWCAP_SHA1] = "sha1",
59 [KERNEL_HWCAP_SHA2] = "sha2",
60 [KERNEL_HWCAP_CRC32] = "crc32",
61 [KERNEL_HWCAP_ATOMICS] = "atomics",
62 [KERNEL_HWCAP_FPHP] = "fphp",
63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
64 [KERNEL_HWCAP_CPUID] = "cpuid",
65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
66 [KERNEL_HWCAP_JSCVT] = "jscvt",
67 [KERNEL_HWCAP_FCMA] = "fcma",
68 [KERNEL_HWCAP_LRCPC] = "lrcpc",
69 [KERNEL_HWCAP_DCPOP] = "dcpop",
70 [KERNEL_HWCAP_SHA3] = "sha3",
71 [KERNEL_HWCAP_SM3] = "sm3",
72 [KERNEL_HWCAP_SM4] = "sm4",
73 [KERNEL_HWCAP_ASIMDDP] = "asimddp",
74 [KERNEL_HWCAP_SHA512] = "sha512",
75 [KERNEL_HWCAP_SVE] = "sve",
76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
77 [KERNEL_HWCAP_DIT] = "dit",
78 [KERNEL_HWCAP_USCAT] = "uscat",
79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
80 [KERNEL_HWCAP_FLAGM] = "flagm",
81 [KERNEL_HWCAP_SSBS] = "ssbs",
82 [KERNEL_HWCAP_SB] = "sb",
83 [KERNEL_HWCAP_PACA] = "paca",
84 [KERNEL_HWCAP_PACG] = "pacg",
85 [KERNEL_HWCAP_DCPODP] = "dcpodp",
86 [KERNEL_HWCAP_SVE2] = "sve2",
87 [KERNEL_HWCAP_SVEAES] = "sveaes",
88 [KERNEL_HWCAP_SVEPMULL] = "svepmull",
89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
90 [KERNEL_HWCAP_SVESHA3] = "svesha3",
91 [KERNEL_HWCAP_SVESM4] = "svesm4",
92 [KERNEL_HWCAP_FLAGM2] = "flagm2",
93 [KERNEL_HWCAP_FRINT] = "frint",
94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
97 [KERNEL_HWCAP_SVEBF16] = "svebf16",
98 [KERNEL_HWCAP_I8MM] = "i8mm",
99 [KERNEL_HWCAP_BF16] = "bf16",
100 [KERNEL_HWCAP_DGH] = "dgh",
101 [KERNEL_HWCAP_RNG] = "rng",
102 [KERNEL_HWCAP_BTI] = "bti",
103 [KERNEL_HWCAP_MTE] = "mte",
104 [KERNEL_HWCAP_ECV] = "ecv",
105 [KERNEL_HWCAP_AFP] = "afp",
106 [KERNEL_HWCAP_RPRES] = "rpres",
107 [KERNEL_HWCAP_MTE3] = "mte3",
108 [KERNEL_HWCAP_SME] = "sme",
109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64",
110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64",
111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32",
112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32",
113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32",
115 [KERNEL_HWCAP_SME_FA64] = "smefa64",
116 [KERNEL_HWCAP_WFXT] = "wfxt",
117 [KERNEL_HWCAP_EBF16] = "ebf16",
118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
119 [KERNEL_HWCAP_CSSC] = "cssc",
120 [KERNEL_HWCAP_RPRFM] = "rprfm",
121 [KERNEL_HWCAP_SVE2P1] = "sve2p1",
122 [KERNEL_HWCAP_SME2] = "sme2",
123 [KERNEL_HWCAP_SME2P1] = "sme2p1",
124 [KERNEL_HWCAP_SME_I16I32] = "smei16i32",
125 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
126 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
127 [KERNEL_HWCAP_SME_F16F16] = "smef16f16",
128 [KERNEL_HWCAP_MOPS] = "mops",
129 [KERNEL_HWCAP_HBC] = "hbc",
130 [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16",
131 [KERNEL_HWCAP_LRCPC3] = "lrcpc3",
132 [KERNEL_HWCAP_LSE128] = "lse128",
133 [KERNEL_HWCAP_FPMR] = "fpmr",
134 [KERNEL_HWCAP_LUT] = "lut",
135 [KERNEL_HWCAP_FAMINMAX] = "faminmax",
136 [KERNEL_HWCAP_F8CVT] = "f8cvt",
137 [KERNEL_HWCAP_F8FMA] = "f8fma",
138 [KERNEL_HWCAP_F8DP4] = "f8dp4",
139 [KERNEL_HWCAP_F8DP2] = "f8dp2",
140 [KERNEL_HWCAP_F8E4M3] = "f8e4m3",
141 [KERNEL_HWCAP_F8E5M2] = "f8e5m2",
142 [KERNEL_HWCAP_SME_LUTV2] = "smelutv2",
143 [KERNEL_HWCAP_SME_F8F16] = "smef8f16",
144 [KERNEL_HWCAP_SME_F8F32] = "smef8f32",
145 [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma",
146 [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4",
147 [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2",
148 [KERNEL_HWCAP_POE] = "poe",
149 };
150
151 #ifdef CONFIG_COMPAT
152 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
153 static const char *const compat_hwcap_str[] = {
154 [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
155 [COMPAT_KERNEL_HWCAP(HALF)] = "half",
156 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
157 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
158 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
159 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
160 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
161 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
162 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
163 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
164 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
165 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
166 [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
167 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
168 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
169 [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
170 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
171 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
172 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
173 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
174 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
175 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
176 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
177 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
178 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
179 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
180 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
181 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
182 };
183
184 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
185 static const char *const compat_hwcap2_str[] = {
186 [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
187 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
188 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
189 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
190 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
191 [COMPAT_KERNEL_HWCAP2(SB)] = "sb",
192 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
193 };
194 #endif /* CONFIG_COMPAT */
195
c_show(struct seq_file * m,void * v)196 static int c_show(struct seq_file *m, void *v)
197 {
198 int i, j;
199 bool compat = personality(current->personality) == PER_LINUX32;
200
201 for_each_online_cpu(i) {
202 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
203 u32 midr = cpuinfo->reg_midr;
204
205 /*
206 * glibc reads /proc/cpuinfo to determine the number of
207 * online processors, looking for lines beginning with
208 * "processor". Give glibc what it expects.
209 */
210 seq_printf(m, "processor\t: %d\n", i);
211 if (compat)
212 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
213 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
214
215 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
216 loops_per_jiffy / (500000UL/HZ),
217 loops_per_jiffy / (5000UL/HZ) % 100);
218
219 /*
220 * Dump out the common processor features in a single line.
221 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
222 * rather than attempting to parse this, but there's a body of
223 * software which does already (at least for 32-bit).
224 */
225 seq_puts(m, "Features\t:");
226 if (compat) {
227 #ifdef CONFIG_COMPAT
228 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
229 if (compat_elf_hwcap & (1 << j)) {
230 /*
231 * Warn once if any feature should not
232 * have been present on arm64 platform.
233 */
234 if (WARN_ON_ONCE(!compat_hwcap_str[j]))
235 continue;
236
237 seq_printf(m, " %s", compat_hwcap_str[j]);
238 }
239 }
240
241 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
242 if (compat_elf_hwcap2 & (1 << j))
243 seq_printf(m, " %s", compat_hwcap2_str[j]);
244 #endif /* CONFIG_COMPAT */
245 } else {
246 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
247 if (cpu_have_feature(j))
248 seq_printf(m, " %s", hwcap_str[j]);
249 }
250 seq_puts(m, "\n");
251
252 seq_printf(m, "CPU implementer\t: 0x%02x\n",
253 MIDR_IMPLEMENTOR(midr));
254 seq_printf(m, "CPU architecture: 8\n");
255 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
256 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
257 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
258 }
259
260 trace_android_rvh_cpuinfo_c_show(m);
261
262 return 0;
263 }
264
c_start(struct seq_file * m,loff_t * pos)265 static void *c_start(struct seq_file *m, loff_t *pos)
266 {
267 return *pos < 1 ? (void *)1 : NULL;
268 }
269
c_next(struct seq_file * m,void * v,loff_t * pos)270 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
271 {
272 ++*pos;
273 return NULL;
274 }
275
c_stop(struct seq_file * m,void * v)276 static void c_stop(struct seq_file *m, void *v)
277 {
278 }
279
280 const struct seq_operations cpuinfo_op = {
281 .start = c_start,
282 .next = c_next,
283 .stop = c_stop,
284 .show = c_show
285 };
286
287
288 static const struct kobj_type cpuregs_kobj_type = {
289 .sysfs_ops = &kobj_sysfs_ops,
290 };
291
292 /*
293 * The ARM ARM uses the phrase "32-bit register" to describe a register
294 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
295 * no statement is made as to whether the upper 32 bits will or will not
296 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
297 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
298 *
299 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
300 * registers, we expose them both as 64 bit values to cater for possible
301 * future expansion without an ABI break.
302 */
303 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
304 #define CPUREGS_ATTR_RO(_name, _field) \
305 static ssize_t _name##_show(struct kobject *kobj, \
306 struct kobj_attribute *attr, char *buf) \
307 { \
308 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
309 \
310 if (info->reg_midr) \
311 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
312 else \
313 return 0; \
314 } \
315 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
316
317 CPUREGS_ATTR_RO(midr_el1, midr);
318 CPUREGS_ATTR_RO(revidr_el1, revidr);
319 CPUREGS_ATTR_RO(smidr_el1, smidr);
320
321 static struct attribute *cpuregs_id_attrs[] = {
322 &cpuregs_attr_midr_el1.attr,
323 &cpuregs_attr_revidr_el1.attr,
324 NULL
325 };
326
327 static const struct attribute_group cpuregs_attr_group = {
328 .attrs = cpuregs_id_attrs,
329 .name = "identification"
330 };
331
332 static struct attribute *sme_cpuregs_id_attrs[] = {
333 &cpuregs_attr_smidr_el1.attr,
334 NULL
335 };
336
337 static const struct attribute_group sme_cpuregs_attr_group = {
338 .attrs = sme_cpuregs_id_attrs,
339 .name = "identification"
340 };
341
cpuid_cpu_online(unsigned int cpu)342 static int cpuid_cpu_online(unsigned int cpu)
343 {
344 int rc;
345 struct device *dev;
346 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
347
348 dev = get_cpu_device(cpu);
349 if (!dev) {
350 rc = -ENODEV;
351 goto out;
352 }
353 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
354 if (rc)
355 goto out;
356 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
357 if (rc)
358 kobject_del(&info->kobj);
359 if (system_supports_sme())
360 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
361 out:
362 return rc;
363 }
364
cpuid_cpu_offline(unsigned int cpu)365 static int cpuid_cpu_offline(unsigned int cpu)
366 {
367 struct device *dev;
368 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
369
370 dev = get_cpu_device(cpu);
371 if (!dev)
372 return -ENODEV;
373 if (info->kobj.parent) {
374 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
375 kobject_del(&info->kobj);
376 }
377
378 return 0;
379 }
380
cpuinfo_regs_init(void)381 static int __init cpuinfo_regs_init(void)
382 {
383 int cpu, ret;
384
385 for_each_possible_cpu(cpu) {
386 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
387
388 kobject_init(&info->kobj, &cpuregs_kobj_type);
389 }
390
391 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
392 cpuid_cpu_online, cpuid_cpu_offline);
393 if (ret < 0) {
394 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
395 return ret;
396 }
397 return 0;
398 }
399 device_initcall(cpuinfo_regs_init);
400
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)401 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
402 {
403 unsigned int cpu = smp_processor_id();
404 u32 l1ip = CTR_L1IP(info->reg_ctr);
405
406 switch (l1ip) {
407 case CTR_EL0_L1Ip_PIPT:
408 break;
409 case CTR_EL0_L1Ip_VIPT:
410 default:
411 /* Assume aliasing */
412 set_bit(ICACHEF_ALIASING, &__icache_flags);
413 break;
414 }
415
416 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
417 }
418
__cpuinfo_store_cpu_32bit(struct cpuinfo_32bit * info)419 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
420 {
421 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
422 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
423 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
424 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
425 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
426 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
427 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
428 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
429 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
430 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
431 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
432 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
433 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
434 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
435 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
436 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
437 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
438 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
439
440 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
441 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
442 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
443 }
444
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)445 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
446 {
447 info->reg_cntfrq = arch_timer_get_cntfrq();
448 /*
449 * Use the effective value of the CTR_EL0 than the raw value
450 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
451 * with the CLIDR_EL1 fields to avoid triggering false warnings
452 * when there is a mismatch across the CPUs. Keep track of the
453 * effective value of the CTR_EL0 in our internal records for
454 * accurate sanity check and feature enablement.
455 */
456 info->reg_ctr = read_cpuid_effective_cachetype();
457 info->reg_dczid = read_cpuid(DCZID_EL0);
458 info->reg_midr = read_cpuid_id();
459 info->reg_revidr = read_cpuid(REVIDR_EL1);
460
461 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
462 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
463 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
464 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
465 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
466 info->reg_id_aa64isar3 = read_cpuid(ID_AA64ISAR3_EL1);
467 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
468 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
469 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
470 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
471 info->reg_id_aa64mmfr4 = read_cpuid(ID_AA64MMFR4_EL1);
472 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
473 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
474 info->reg_id_aa64pfr2 = read_cpuid(ID_AA64PFR2_EL1);
475 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
476 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
477 info->reg_id_aa64fpfr0 = read_cpuid(ID_AA64FPFR0_EL1);
478
479 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
480 info->reg_gmid = read_cpuid(GMID_EL1);
481
482 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
483 __cpuinfo_store_cpu_32bit(&info->aarch32);
484
485 /*
486 * info->reg_mpamidr deferred to {init,update}_cpu_features because we
487 * don't want to read it (and trigger a trap on buggy firmware) if
488 * using an aa64pfr0_el1 override to unconditionally disable MPAM.
489 */
490
491 if (IS_ENABLED(CONFIG_ARM64_SME) &&
492 id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
493 /*
494 * We mask out SMPS since even if the hardware
495 * supports priorities the kernel does not at present
496 * and we block access to them.
497 */
498 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
499 }
500
501 cpuinfo_detect_icache_policy(info);
502 }
503
cpuinfo_store_cpu(void)504 void cpuinfo_store_cpu(void)
505 {
506 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
507 __cpuinfo_store_cpu(info);
508 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
509 }
510
cpuinfo_store_boot_cpu(void)511 void __init cpuinfo_store_boot_cpu(void)
512 {
513 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
514 __cpuinfo_store_cpu(info);
515
516 boot_cpu_data = *info;
517 init_cpu_features(&boot_cpu_data);
518 }
519