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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * AArch64 loadable module support.
4  *
5  * Copyright (C) 2012 ARM Limited
6  *
7  * Author: Will Deacon <will.deacon@arm.com>
8  */
9 
10 #define pr_fmt(fmt) "Modules: " fmt
11 
12 #include <linux/bitops.h>
13 #include <linux/elf.h>
14 #include <linux/ftrace.h>
15 #include <linux/kasan.h>
16 #include <linux/kernel.h>
17 #include <linux/mm.h>
18 #include <linux/moduleloader.h>
19 #include <linux/random.h>
20 #include <linux/scs.h>
21 
22 #include <asm/alternative.h>
23 #include <asm/insn.h>
24 #include <asm/kvm_hyptrace.h>
25 #include <asm/kvm_hypevents_defs.h>
26 #include <asm/scs.h>
27 #include <asm/sections.h>
28 
29 enum aarch64_reloc_op {
30 	RELOC_OP_NONE,
31 	RELOC_OP_ABS,
32 	RELOC_OP_PREL,
33 	RELOC_OP_PAGE,
34 };
35 
do_reloc(enum aarch64_reloc_op reloc_op,__le32 * place,u64 val)36 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
37 {
38 	switch (reloc_op) {
39 	case RELOC_OP_ABS:
40 		return val;
41 	case RELOC_OP_PREL:
42 		return val - (u64)place;
43 	case RELOC_OP_PAGE:
44 		return (val & ~0xfff) - ((u64)place & ~0xfff);
45 	case RELOC_OP_NONE:
46 		return 0;
47 	}
48 
49 	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
50 	return 0;
51 }
52 
reloc_data(enum aarch64_reloc_op op,void * place,u64 val,int len)53 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
54 {
55 	s64 sval = do_reloc(op, place, val);
56 
57 	/*
58 	 * The ELF psABI for AArch64 documents the 16-bit and 32-bit place
59 	 * relative and absolute relocations as having a range of [-2^15, 2^16)
60 	 * or [-2^31, 2^32), respectively. However, in order to be able to
61 	 * detect overflows reliably, we have to choose whether we interpret
62 	 * such quantities as signed or as unsigned, and stick with it.
63 	 * The way we organize our address space requires a signed
64 	 * interpretation of 32-bit relative references, so let's use that
65 	 * for all R_AARCH64_PRELxx relocations. This means our upper
66 	 * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
67 	 */
68 
69 	switch (len) {
70 	case 16:
71 		*(s16 *)place = sval;
72 		switch (op) {
73 		case RELOC_OP_ABS:
74 			if (sval < 0 || sval > U16_MAX)
75 				return -ERANGE;
76 			break;
77 		case RELOC_OP_PREL:
78 			if (sval < S16_MIN || sval > S16_MAX)
79 				return -ERANGE;
80 			break;
81 		default:
82 			pr_err("Invalid 16-bit data relocation (%d)\n", op);
83 			return 0;
84 		}
85 		break;
86 	case 32:
87 		*(s32 *)place = sval;
88 		switch (op) {
89 		case RELOC_OP_ABS:
90 			if (sval < 0 || sval > U32_MAX)
91 				return -ERANGE;
92 			break;
93 		case RELOC_OP_PREL:
94 			if (sval < S32_MIN || sval > S32_MAX)
95 				return -ERANGE;
96 			break;
97 		default:
98 			pr_err("Invalid 32-bit data relocation (%d)\n", op);
99 			return 0;
100 		}
101 		break;
102 	case 64:
103 		*(s64 *)place = sval;
104 		break;
105 	default:
106 		pr_err("Invalid length (%d) for data relocation\n", len);
107 		return 0;
108 	}
109 	return 0;
110 }
111 
112 enum aarch64_insn_movw_imm_type {
113 	AARCH64_INSN_IMM_MOVNZ,
114 	AARCH64_INSN_IMM_MOVKZ,
115 };
116 
reloc_insn_movw(enum aarch64_reloc_op op,__le32 * place,u64 val,int lsb,enum aarch64_insn_movw_imm_type imm_type)117 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
118 			   int lsb, enum aarch64_insn_movw_imm_type imm_type)
119 {
120 	u64 imm;
121 	s64 sval;
122 	u32 insn = le32_to_cpu(*place);
123 
124 	sval = do_reloc(op, place, val);
125 	imm = sval >> lsb;
126 
127 	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
128 		/*
129 		 * For signed MOVW relocations, we have to manipulate the
130 		 * instruction encoding depending on whether or not the
131 		 * immediate is less than zero.
132 		 */
133 		insn &= ~(3 << 29);
134 		if (sval >= 0) {
135 			/* >=0: Set the instruction to MOVZ (opcode 10b). */
136 			insn |= 2 << 29;
137 		} else {
138 			/*
139 			 * <0: Set the instruction to MOVN (opcode 00b).
140 			 *     Since we've masked the opcode already, we
141 			 *     don't need to do anything other than
142 			 *     inverting the new immediate field.
143 			 */
144 			imm = ~imm;
145 		}
146 	}
147 
148 	/* Update the instruction with the new encoding. */
149 	insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
150 	*place = cpu_to_le32(insn);
151 
152 	if (imm > U16_MAX)
153 		return -ERANGE;
154 
155 	return 0;
156 }
157 
reloc_insn_imm(enum aarch64_reloc_op op,__le32 * place,u64 val,int lsb,int len,enum aarch64_insn_imm_type imm_type)158 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
159 			  int lsb, int len, enum aarch64_insn_imm_type imm_type)
160 {
161 	u64 imm, imm_mask;
162 	s64 sval;
163 	u32 insn = le32_to_cpu(*place);
164 
165 	/* Calculate the relocation value. */
166 	sval = do_reloc(op, place, val);
167 	sval >>= lsb;
168 
169 	/* Extract the value bits and shift them to bit 0. */
170 	imm_mask = (BIT(lsb + len) - 1) >> lsb;
171 	imm = sval & imm_mask;
172 
173 	/* Update the instruction's immediate field. */
174 	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
175 	*place = cpu_to_le32(insn);
176 
177 	/*
178 	 * Extract the upper value bits (including the sign bit) and
179 	 * shift them to bit 0.
180 	 */
181 	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
182 
183 	/*
184 	 * Overflow has occurred if the upper bits are not all equal to
185 	 * the sign bit of the value.
186 	 */
187 	if ((u64)(sval + 1) >= 2)
188 		return -ERANGE;
189 
190 	return 0;
191 }
192 
reloc_insn_adrp(struct module * mod,Elf64_Shdr * sechdrs,__le32 * place,u64 val)193 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
194 			   __le32 *place, u64 val)
195 {
196 	u32 insn;
197 
198 	if (!is_forbidden_offset_for_adrp(place))
199 		return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
200 				      AARCH64_INSN_IMM_ADR);
201 
202 	/* patch ADRP to ADR if it is in range */
203 	if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
204 			    AARCH64_INSN_IMM_ADR)) {
205 		insn = le32_to_cpu(*place);
206 		insn &= ~BIT(31);
207 	} else {
208 		/* out of range for ADR -> emit a veneer */
209 		val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
210 		if (!val)
211 			return -ENOEXEC;
212 		insn = aarch64_insn_gen_branch_imm((u64)place, val,
213 						   AARCH64_INSN_BRANCH_NOLINK);
214 	}
215 
216 	*place = cpu_to_le32(insn);
217 	return 0;
218 }
219 
apply_relocate_add(Elf64_Shdr * sechdrs,const char * strtab,unsigned int symindex,unsigned int relsec,struct module * me)220 int apply_relocate_add(Elf64_Shdr *sechdrs,
221 		       const char *strtab,
222 		       unsigned int symindex,
223 		       unsigned int relsec,
224 		       struct module *me)
225 {
226 	unsigned int i;
227 	int ovf;
228 	bool overflow_check;
229 	Elf64_Sym *sym;
230 	void *loc;
231 	u64 val;
232 	Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
233 
234 	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
235 		/* loc corresponds to P in the AArch64 ELF document. */
236 		loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
237 			+ rel[i].r_offset;
238 
239 		/* sym is the ELF symbol we're referring to. */
240 		sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
241 			+ ELF64_R_SYM(rel[i].r_info);
242 
243 		/* val corresponds to (S + A) in the AArch64 ELF document. */
244 		val = sym->st_value + rel[i].r_addend;
245 
246 		/* Check for overflow by default. */
247 		overflow_check = true;
248 
249 		/* Perform the static relocation. */
250 		switch (ELF64_R_TYPE(rel[i].r_info)) {
251 		/* Null relocations. */
252 		case R_ARM_NONE:
253 		case R_AARCH64_NONE:
254 			ovf = 0;
255 			break;
256 
257 		/* Data relocations. */
258 		case R_AARCH64_ABS64:
259 			overflow_check = false;
260 			ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
261 			break;
262 		case R_AARCH64_ABS32:
263 			ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
264 			break;
265 		case R_AARCH64_ABS16:
266 			ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
267 			break;
268 		case R_AARCH64_PREL64:
269 			overflow_check = false;
270 			ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
271 			break;
272 		case R_AARCH64_PREL32:
273 			ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
274 			break;
275 		case R_AARCH64_PREL16:
276 			ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
277 			break;
278 
279 		/* MOVW instruction relocations. */
280 		case R_AARCH64_MOVW_UABS_G0_NC:
281 			overflow_check = false;
282 			fallthrough;
283 		case R_AARCH64_MOVW_UABS_G0:
284 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
285 					      AARCH64_INSN_IMM_MOVKZ);
286 			break;
287 		case R_AARCH64_MOVW_UABS_G1_NC:
288 			overflow_check = false;
289 			fallthrough;
290 		case R_AARCH64_MOVW_UABS_G1:
291 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
292 					      AARCH64_INSN_IMM_MOVKZ);
293 			break;
294 		case R_AARCH64_MOVW_UABS_G2_NC:
295 			overflow_check = false;
296 			fallthrough;
297 		case R_AARCH64_MOVW_UABS_G2:
298 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
299 					      AARCH64_INSN_IMM_MOVKZ);
300 			break;
301 		case R_AARCH64_MOVW_UABS_G3:
302 			/* We're using the top bits so we can't overflow. */
303 			overflow_check = false;
304 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
305 					      AARCH64_INSN_IMM_MOVKZ);
306 			break;
307 		case R_AARCH64_MOVW_SABS_G0:
308 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
309 					      AARCH64_INSN_IMM_MOVNZ);
310 			break;
311 		case R_AARCH64_MOVW_SABS_G1:
312 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
313 					      AARCH64_INSN_IMM_MOVNZ);
314 			break;
315 		case R_AARCH64_MOVW_SABS_G2:
316 			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
317 					      AARCH64_INSN_IMM_MOVNZ);
318 			break;
319 		case R_AARCH64_MOVW_PREL_G0_NC:
320 			overflow_check = false;
321 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
322 					      AARCH64_INSN_IMM_MOVKZ);
323 			break;
324 		case R_AARCH64_MOVW_PREL_G0:
325 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
326 					      AARCH64_INSN_IMM_MOVNZ);
327 			break;
328 		case R_AARCH64_MOVW_PREL_G1_NC:
329 			overflow_check = false;
330 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
331 					      AARCH64_INSN_IMM_MOVKZ);
332 			break;
333 		case R_AARCH64_MOVW_PREL_G1:
334 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
335 					      AARCH64_INSN_IMM_MOVNZ);
336 			break;
337 		case R_AARCH64_MOVW_PREL_G2_NC:
338 			overflow_check = false;
339 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
340 					      AARCH64_INSN_IMM_MOVKZ);
341 			break;
342 		case R_AARCH64_MOVW_PREL_G2:
343 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
344 					      AARCH64_INSN_IMM_MOVNZ);
345 			break;
346 		case R_AARCH64_MOVW_PREL_G3:
347 			/* We're using the top bits so we can't overflow. */
348 			overflow_check = false;
349 			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
350 					      AARCH64_INSN_IMM_MOVNZ);
351 			break;
352 
353 		/* Immediate instruction relocations. */
354 		case R_AARCH64_LD_PREL_LO19:
355 			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
356 					     AARCH64_INSN_IMM_19);
357 			break;
358 		case R_AARCH64_ADR_PREL_LO21:
359 			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
360 					     AARCH64_INSN_IMM_ADR);
361 			break;
362 		case R_AARCH64_ADR_PREL_PG_HI21_NC:
363 			overflow_check = false;
364 			fallthrough;
365 		case R_AARCH64_ADR_PREL_PG_HI21:
366 			ovf = reloc_insn_adrp(me, sechdrs, loc, val);
367 			if (ovf && ovf != -ERANGE)
368 				return ovf;
369 			break;
370 		case R_AARCH64_ADD_ABS_LO12_NC:
371 		case R_AARCH64_LDST8_ABS_LO12_NC:
372 			overflow_check = false;
373 			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
374 					     AARCH64_INSN_IMM_12);
375 			break;
376 		case R_AARCH64_LDST16_ABS_LO12_NC:
377 			overflow_check = false;
378 			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
379 					     AARCH64_INSN_IMM_12);
380 			break;
381 		case R_AARCH64_LDST32_ABS_LO12_NC:
382 			overflow_check = false;
383 			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
384 					     AARCH64_INSN_IMM_12);
385 			break;
386 		case R_AARCH64_LDST64_ABS_LO12_NC:
387 			overflow_check = false;
388 			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
389 					     AARCH64_INSN_IMM_12);
390 			break;
391 		case R_AARCH64_LDST128_ABS_LO12_NC:
392 			overflow_check = false;
393 			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
394 					     AARCH64_INSN_IMM_12);
395 			break;
396 		case R_AARCH64_TSTBR14:
397 			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
398 					     AARCH64_INSN_IMM_14);
399 			break;
400 		case R_AARCH64_CONDBR19:
401 			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
402 					     AARCH64_INSN_IMM_19);
403 			break;
404 		case R_AARCH64_JUMP26:
405 		case R_AARCH64_CALL26:
406 			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
407 					     AARCH64_INSN_IMM_26);
408 			if (ovf == -ERANGE) {
409 				val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
410 				if (!val)
411 					return -ENOEXEC;
412 				ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
413 						     26, AARCH64_INSN_IMM_26);
414 			}
415 			break;
416 
417 		default:
418 			pr_err("module %s: unsupported RELA relocation: %llu\n",
419 			       me->name, ELF64_R_TYPE(rel[i].r_info));
420 			return -ENOEXEC;
421 		}
422 
423 		if (overflow_check && ovf == -ERANGE)
424 			goto overflow;
425 
426 	}
427 
428 	return 0;
429 
430 overflow:
431 	pr_err("module %s: overflow in relocation type %d val %Lx\n",
432 	       me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
433 	return -ENOEXEC;
434 }
435 
__init_plt(struct plt_entry * plt,unsigned long addr)436 static inline void __init_plt(struct plt_entry *plt, unsigned long addr)
437 {
438 	*plt = get_plt_entry(addr, plt);
439 }
440 
module_init_ftrace_plt(const Elf_Ehdr * hdr,const Elf_Shdr * sechdrs,struct module * mod)441 static int module_init_ftrace_plt(const Elf_Ehdr *hdr,
442 				  const Elf_Shdr *sechdrs,
443 				  struct module *mod)
444 {
445 #if defined(CONFIG_DYNAMIC_FTRACE)
446 	const Elf_Shdr *s;
447 	struct plt_entry *plts;
448 
449 	s = find_section(hdr, sechdrs, ".text.ftrace_trampoline");
450 	if (!s)
451 		return -ENOEXEC;
452 
453 	plts = (void *)s->sh_addr;
454 
455 	__init_plt(&plts[FTRACE_PLT_IDX], FTRACE_ADDR);
456 
457 	mod->arch.ftrace_trampolines = plts;
458 #endif
459 	return 0;
460 }
461 
462 #ifdef CONFIG_KVM
find_symbol_table(const Elf_Ehdr * hdr,const Elf_Shdr * sechdrs)463 static const Elf_Shdr *find_symbol_table(const Elf_Ehdr *hdr,
464 					 const Elf_Shdr *sechdrs)
465 {
466 	int idx;
467 
468 	for (idx = 1; idx < hdr->e_shnum; idx++) {
469 		if (sechdrs[idx].sh_type == SHT_SYMTAB)
470 			return &sechdrs[idx];
471 	}
472 
473 	return NULL;
474 }
475 
476 static int
module_init_hyp_imported_sym(const Elf_Ehdr * hdr,const Elf_Shdr * sechdrs,struct module * mod)477 module_init_hyp_imported_sym(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
478 			     struct module *mod)
479 {
480 	struct pkvm_el2_module *hyp_mod = &mod->arch.hyp;
481 	struct pkvm_el2_sym *pkvm_sym;
482 	const Elf_Shdr *symtab = NULL, *s, *se, *orig;
483 	const char *strtab = NULL;
484 	const Elf_Rela *rela;
485 	const Elf_Sym *sym;
486 
487 	INIT_LIST_HEAD(&hyp_mod->ext_symbols);
488 
489 	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
490 		if (s->sh_type != SHT_RELA)
491 			continue;
492 
493 		/* Imported symbols only used in .hyp.text */
494 		orig = &sechdrs[s->sh_info];
495 		if ((void *)orig->sh_addr != hyp_mod->text.start)
496 			continue;
497 
498 		for (rela = (Elf_Rela *)((void *)hdr + s->sh_offset);
499 		     rela < (Elf_Rela *)((void *)hdr + s->sh_offset + s->sh_size); rela++) {
500 			size_t len;
501 
502 			symtab = symtab ? symtab : find_symbol_table(hdr, sechdrs);
503 			if (!symtab)
504 				return -ENOEXEC;
505 			strtab = (const char *)hdr + sechdrs[symtab->sh_link].sh_offset;
506 
507 			sym = (Elf_Sym *)((const char *)hdr + symtab->sh_offset) +
508 				ELF64_R_SYM(rela->r_info);
509 
510 			/* Imported symbols are UNDEF */
511 			if (sym->st_shndx != SHN_UNDEF)
512 				continue;
513 
514 			if (ELF64_R_TYPE(rela->r_info) != R_AARCH64_CALL26) {
515 				pr_warn("Unknown relocation type for imported symbol %s\n",
516 					strtab + sym->st_name);
517 				return -EINVAL;
518 			}
519 
520 			pkvm_sym = kmalloc(sizeof(*pkvm_sym), GFP_KERNEL);
521 			if (!pkvm_sym)
522 				return -ENOMEM;
523 
524 			len = strlen(strtab + sym->st_name);
525 			pkvm_sym->name = kmalloc(len, GFP_KERNEL);
526 			memcpy(pkvm_sym->name, strtab + sym->st_name, len);
527 			pkvm_sym->rela_pos = (void *)orig->sh_addr + rela->r_offset;
528 
529 			list_add(&pkvm_sym->node, &hyp_mod->ext_symbols);
530 		}
531 	}
532 
533 	return 0;
534 }
535 #endif
536 
module_init_hyp(const Elf_Ehdr * hdr,const Elf_Shdr * sechdrs,struct module * mod)537 static int module_init_hyp(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
538 			   struct module *mod)
539 {
540 #ifdef CONFIG_KVM
541 	struct pkvm_el2_module *hyp_mod = &mod->arch.hyp;
542 	const Elf_Shdr *s;
543 
544 	/*
545 	 * If the .hyp.text is missing or empty, this is not a hypervisor
546 	 * module so ignore the rest of it.
547 	 */
548 	s = find_section(hdr, sechdrs, ".hyp.text");
549 	if (!s || !s->sh_size)
550 		return 0;
551 
552 	hyp_mod->text = (struct pkvm_module_section) {
553 		.start	= (void *)s->sh_addr,
554 		.end	= (void *)s->sh_addr + s->sh_size,
555 	};
556 
557 	module_init_hyp_imported_sym(hdr, sechdrs, mod);
558 
559 	s = find_section(hdr, sechdrs, ".hyp.reloc");
560 	if (!s)
561 		return -ENOEXEC;
562 
563 	mod->arch.hyp.relocs = (void *)s->sh_addr;
564 	mod->arch.hyp.nr_relocs = s->sh_size / sizeof(*mod->arch.hyp.relocs);
565 
566 	s = find_section(hdr, sechdrs, ".hyp.bss");
567 	if (s && s->sh_size) {
568 		mod->arch.hyp.bss = (struct pkvm_module_section) {
569 			.start	= (void *)s->sh_addr,
570 			.end	= (void *)s->sh_addr + s->sh_size,
571 		};
572 	}
573 
574 	s = find_section(hdr, sechdrs, ".hyp.rodata");
575 	if (s && s->sh_size) {
576 		mod->arch.hyp.rodata = (struct pkvm_module_section) {
577 			.start	= (void *)s->sh_addr,
578 			.end	= (void *)s->sh_addr + s->sh_size,
579 		};
580 	}
581 
582 	s = find_section(hdr, sechdrs, ".hyp.data");
583 	if (s && s->sh_size) {
584 		mod->arch.hyp.data = (struct pkvm_module_section) {
585 			.start	= (void *)s->sh_addr,
586 			.end	= (void *)s->sh_addr + s->sh_size,
587 		};
588 	}
589 
590 	s = find_section(hdr, sechdrs, ".hyp.event_ids");
591 	if (s && s->sh_size) {
592 		mod->arch.hyp.event_ids = (struct pkvm_module_section) {
593 			.start	= (void *)s->sh_addr,
594 			.end	= (void *)s->sh_addr + s->sh_size,
595 		};
596 	}
597 
598 	s = find_section(hdr, sechdrs, "_hyp_events");
599 	if (s && s->sh_size) {
600 		if (!mod->arch.hyp.event_ids.start) {
601 			WARN(1, "%s: Did you forget define_events.h in the EL2 (hyp) code?",
602 			     mod->name);
603 		} else {
604 			hyp_mod->hyp_events = (void *)s->sh_addr;
605 			hyp_mod->nr_hyp_events = s->sh_size /
606 				sizeof(*hyp_mod->hyp_events);
607 		}
608 	}
609 
610 	s = find_section(hdr, sechdrs, ".hyp.printk_fmts");
611 	if (s && s->sh_size) {
612 		hyp_mod->hyp_printk_fmts = (void *)s->sh_addr;
613 		hyp_mod->nr_hyp_printk_fmts = s->sh_size /
614 			sizeof(*hyp_mod->hyp_printk_fmts);
615 	}
616 
617 	s = find_section(hdr, sechdrs, ".hyp.patchable_function_entries");
618 	if (s && s->sh_size) {
619 		hyp_mod->patchable_function_entries = (struct pkvm_module_section) {
620 			.start	= (void *)s->sh_addr,
621 			.end	= (void *)s->sh_addr + s->sh_size,
622 		};
623 	}
624 
625 #endif
626 	return 0;
627 }
628 
module_finalize(const Elf_Ehdr * hdr,const Elf_Shdr * sechdrs,struct module * me)629 int module_finalize(const Elf_Ehdr *hdr,
630 		    const Elf_Shdr *sechdrs,
631 		    struct module *me)
632 {
633 	int err;
634 	const Elf_Shdr *s;
635 
636 	s = find_section(hdr, sechdrs, ".altinstructions");
637 	if (s)
638 		apply_alternatives_module((void *)s->sh_addr, s->sh_size);
639 
640 	if (scs_is_dynamic()) {
641 		s = find_section(hdr, sechdrs, ".init.eh_frame");
642 		if (s)
643 			__pi_scs_patch((void *)s->sh_addr, s->sh_size);
644 	}
645 
646 	err = module_init_ftrace_plt(hdr, sechdrs, me);
647 	if (err)
648 		return err;
649 
650 	return module_init_hyp(hdr, sechdrs, me);
651 }
652