1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/debugfs.h>
16 #include <linux/kvm_host.h>
17 #include <linux/mm.h>
18 #include <linux/printk.h>
19 #include <linux/uaccess.h>
20
21 #include <asm/arm_pmuv3.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cputype.h>
24 #include <asm/debug-monitors.h>
25 #include <asm/esr.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_emulate.h>
28 #include <asm/kvm_hyp.h>
29 #include <asm/kvm_mmu.h>
30 #include <asm/kvm_nested.h>
31 #include <asm/perf_event.h>
32 #include <asm/sysreg.h>
33
34 #include <trace/events/kvm.h>
35
36 #include "sys_regs.h"
37 #include "vgic/vgic.h"
38
39 #include "trace.h"
40
41 /*
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
49 u64 val);
50
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
52 const struct sys_reg_desc *r)
53 {
54 kvm_inject_undefined(vcpu);
55 return false;
56 }
57
bad_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r,const char * msg)58 static bool bad_trap(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r,
61 const char *msg)
62 {
63 WARN_ONCE(1, "Unexpected %s\n", msg);
64 print_sys_reg_instr(params);
65 return undef_access(vcpu, params, r);
66 }
67
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)68 static bool read_from_write_only(struct kvm_vcpu *vcpu,
69 struct sys_reg_params *params,
70 const struct sys_reg_desc *r)
71 {
72 return bad_trap(vcpu, params, r,
73 "sys_reg read to write-only register");
74 }
75
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)76 static bool write_to_read_only(struct kvm_vcpu *vcpu,
77 struct sys_reg_params *params,
78 const struct sys_reg_desc *r)
79 {
80 return bad_trap(vcpu, params, r,
81 "sys_reg write to read-only register");
82 }
83
84 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
85 #define CSSELR_MAX 14
86
87 /*
88 * Returns the minimum line size for the selected cache, expressed as
89 * Log2(bytes).
90 */
get_min_cache_line_size(bool icache)91 static u8 get_min_cache_line_size(bool icache)
92 {
93 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
94 u8 field;
95
96 if (icache)
97 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
98 else
99 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
100
101 /*
102 * Cache line size is represented as Log2(words) in CTR_EL0.
103 * Log2(bytes) can be derived with the following:
104 *
105 * Log2(words) + 2 = Log2(bytes / 4) + 2
106 * = Log2(bytes) - 2 + 2
107 * = Log2(bytes)
108 */
109 return field + 2;
110 }
111
112 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)113 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
114 {
115 u8 line_size;
116
117 if (vcpu->arch.ccsidr)
118 return vcpu->arch.ccsidr[csselr];
119
120 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
121
122 /*
123 * Fabricate a CCSIDR value as the overriding value does not exist.
124 * The real CCSIDR value will not be used as it can vary by the
125 * physical CPU which the vcpu currently resides in.
126 *
127 * The line size is determined with get_min_cache_line_size(), which
128 * should be valid for all CPUs even if they have different cache
129 * configuration.
130 *
131 * The associativity bits are cleared, meaning the geometry of all data
132 * and unified caches (which are guaranteed to be PIPT and thus
133 * non-aliasing) are 1 set and 1 way.
134 * Guests should not be doing cache operations by set/way at all, and
135 * for this reason, we trap them and attempt to infer the intent, so
136 * that we can flush the entire guest's address space at the appropriate
137 * time. The exposed geometry minimizes the number of the traps.
138 * [If guests should attempt to infer aliasing properties from the
139 * geometry (which is not permitted by the architecture), they would
140 * only do so for virtually indexed caches.]
141 *
142 * We don't check if the cache level exists as it is allowed to return
143 * an UNKNOWN value if not.
144 */
145 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
146 }
147
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)148 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
149 {
150 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
151 u32 *ccsidr = vcpu->arch.ccsidr;
152 u32 i;
153
154 if ((val & CCSIDR_EL1_RES0) ||
155 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
156 return -EINVAL;
157
158 if (!ccsidr) {
159 if (val == get_ccsidr(vcpu, csselr))
160 return 0;
161
162 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
163 if (!ccsidr)
164 return -ENOMEM;
165
166 for (i = 0; i < CSSELR_MAX; i++)
167 ccsidr[i] = get_ccsidr(vcpu, i);
168
169 vcpu->arch.ccsidr = ccsidr;
170 }
171
172 ccsidr[csselr] = val;
173
174 return 0;
175 }
176
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)177 static bool access_rw(struct kvm_vcpu *vcpu,
178 struct sys_reg_params *p,
179 const struct sys_reg_desc *r)
180 {
181 if (p->is_write)
182 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
183 else
184 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
185
186 return true;
187 }
188
189 /*
190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
191 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)192 static bool access_dcsw(struct kvm_vcpu *vcpu,
193 struct sys_reg_params *p,
194 const struct sys_reg_desc *r)
195 {
196 if (!p->is_write)
197 return read_from_write_only(vcpu, p, r);
198
199 /*
200 * Only track S/W ops if we don't have FWB. It still indicates
201 * that the guest is a bit broken (S/W operations should only
202 * be done by firmware, knowing that there is only a single
203 * CPU left in the system, and certainly not from non-secure
204 * software).
205 */
206 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
207 kvm_set_way_flush(vcpu);
208
209 return true;
210 }
211
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)212 static bool access_dcgsw(struct kvm_vcpu *vcpu,
213 struct sys_reg_params *p,
214 const struct sys_reg_desc *r)
215 {
216 if (!kvm_has_mte(vcpu->kvm))
217 return undef_access(vcpu, p, r);
218
219 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
220 return access_dcsw(vcpu, p, r);
221 }
222
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)223 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
224 {
225 switch (r->aarch32_map) {
226 case AA32_LO:
227 *mask = GENMASK_ULL(31, 0);
228 *shift = 0;
229 break;
230 case AA32_HI:
231 *mask = GENMASK_ULL(63, 32);
232 *shift = 32;
233 break;
234 default:
235 *mask = GENMASK_ULL(63, 0);
236 *shift = 0;
237 break;
238 }
239 }
240
241 /*
242 * Generic accessor for VM registers. Only called as long as HCR_TVM
243 * is set. If the guest enables the MMU, we stop trapping the VM
244 * sys_regs and leave it in complete control of the caches.
245 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)246 static bool access_vm_reg(struct kvm_vcpu *vcpu,
247 struct sys_reg_params *p,
248 const struct sys_reg_desc *r)
249 {
250 bool was_enabled = vcpu_has_cache_enabled(vcpu);
251 u64 val, mask, shift;
252
253 if (reg_to_encoding(r) == SYS_TCR2_EL1 &&
254 !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP))
255 return undef_access(vcpu, p, r);
256
257 BUG_ON(!p->is_write);
258
259 get_access_mask(r, &mask, &shift);
260
261 if (~mask) {
262 val = vcpu_read_sys_reg(vcpu, r->reg);
263 val &= ~mask;
264 } else {
265 val = 0;
266 }
267
268 val |= (p->regval & (mask >> shift)) << shift;
269 vcpu_write_sys_reg(vcpu, val, r->reg);
270
271 kvm_toggle_cache(vcpu, was_enabled);
272 return true;
273 }
274
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)275 static bool access_actlr(struct kvm_vcpu *vcpu,
276 struct sys_reg_params *p,
277 const struct sys_reg_desc *r)
278 {
279 u64 mask, shift;
280
281 if (p->is_write)
282 return ignore_write(vcpu, p);
283
284 get_access_mask(r, &mask, &shift);
285 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
286
287 return true;
288 }
289
290 /*
291 * Trap handler for the GICv3 SGI generation system register.
292 * Forward the request to the VGIC emulation.
293 * The cp15_64 code makes sure this automatically works
294 * for both AArch64 and AArch32 accesses.
295 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)296 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
297 struct sys_reg_params *p,
298 const struct sys_reg_desc *r)
299 {
300 bool g1;
301
302 if (!kvm_has_gicv3(vcpu->kvm))
303 return undef_access(vcpu, p, r);
304
305 if (!p->is_write)
306 return read_from_write_only(vcpu, p, r);
307
308 /*
309 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
310 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
311 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
312 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
313 * group.
314 */
315 if (p->Op0 == 0) { /* AArch32 */
316 switch (p->Op1) {
317 default: /* Keep GCC quiet */
318 case 0: /* ICC_SGI1R */
319 g1 = true;
320 break;
321 case 1: /* ICC_ASGI1R */
322 case 2: /* ICC_SGI0R */
323 g1 = false;
324 break;
325 }
326 } else { /* AArch64 */
327 switch (p->Op2) {
328 default: /* Keep GCC quiet */
329 case 5: /* ICC_SGI1R_EL1 */
330 g1 = true;
331 break;
332 case 6: /* ICC_ASGI1R_EL1 */
333 case 7: /* ICC_SGI0R_EL1 */
334 g1 = false;
335 break;
336 }
337 }
338
339 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
340
341 return true;
342 }
343
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)344 static bool access_gic_sre(struct kvm_vcpu *vcpu,
345 struct sys_reg_params *p,
346 const struct sys_reg_desc *r)
347 {
348 if (!kvm_has_gicv3(vcpu->kvm))
349 return undef_access(vcpu, p, r);
350
351 if (p->is_write)
352 return ignore_write(vcpu, p);
353
354 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
355 return true;
356 }
357
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)358 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
359 struct sys_reg_params *p,
360 const struct sys_reg_desc *r)
361 {
362 if (p->is_write)
363 return ignore_write(vcpu, p);
364 else
365 return read_zero(vcpu, p);
366 }
367
368 /*
369 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
370 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
371 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
372 * treat it separately.
373 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)374 static bool trap_loregion(struct kvm_vcpu *vcpu,
375 struct sys_reg_params *p,
376 const struct sys_reg_desc *r)
377 {
378 u32 sr = reg_to_encoding(r);
379
380 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP))
381 return undef_access(vcpu, p, r);
382
383 if (p->is_write && sr == SYS_LORID_EL1)
384 return write_to_read_only(vcpu, p, r);
385
386 return trap_raz_wi(vcpu, p, r);
387 }
388
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)389 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
390 struct sys_reg_params *p,
391 const struct sys_reg_desc *r)
392 {
393 u64 oslsr;
394
395 if (!p->is_write)
396 return read_from_write_only(vcpu, p, r);
397
398 /* Forward the OSLK bit to OSLSR */
399 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK;
400 if (p->regval & OSLAR_EL1_OSLK)
401 oslsr |= OSLSR_EL1_OSLK;
402
403 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
404 return true;
405 }
406
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)407 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
408 struct sys_reg_params *p,
409 const struct sys_reg_desc *r)
410 {
411 if (p->is_write)
412 return write_to_read_only(vcpu, p, r);
413
414 p->regval = __vcpu_sys_reg(vcpu, r->reg);
415 return true;
416 }
417
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)418 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
419 u64 val)
420 {
421 /*
422 * The only modifiable bit is the OSLK bit. Refuse the write if
423 * userspace attempts to change any other bit in the register.
424 */
425 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
426 return -EINVAL;
427
428 __vcpu_sys_reg(vcpu, rd->reg) = val;
429 return 0;
430 }
431
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)432 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
433 struct sys_reg_params *p,
434 const struct sys_reg_desc *r)
435 {
436 if (p->is_write) {
437 return ignore_write(vcpu, p);
438 } else {
439 p->regval = read_sysreg(dbgauthstatus_el1);
440 return true;
441 }
442 }
443
444 /*
445 * We want to avoid world-switching all the DBG registers all the
446 * time:
447 *
448 * - If we've touched any debug register, it is likely that we're
449 * going to touch more of them. It then makes sense to disable the
450 * traps and start doing the save/restore dance
451 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
452 * then mandatory to save/restore the registers, as the guest
453 * depends on them.
454 *
455 * For this, we use a DIRTY bit, indicating the guest has modified the
456 * debug registers, used as follow:
457 *
458 * On guest entry:
459 * - If the dirty bit is set (because we're coming back from trapping),
460 * disable the traps, save host registers, restore guest registers.
461 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
462 * set the dirty bit, disable the traps, save host registers,
463 * restore guest registers.
464 * - Otherwise, enable the traps
465 *
466 * On guest exit:
467 * - If the dirty bit is set, save guest registers, restore host
468 * registers and clear the dirty bit. This ensure that the host can
469 * now use the debug registers.
470 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)471 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
472 struct sys_reg_params *p,
473 const struct sys_reg_desc *r)
474 {
475 access_rw(vcpu, p, r);
476 if (p->is_write)
477 vcpu_set_flag(vcpu, DEBUG_DIRTY);
478
479 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
480
481 return true;
482 }
483
484 /*
485 * reg_to_dbg/dbg_to_reg
486 *
487 * A 32 bit write to a debug register leave top bits alone
488 * A 32 bit read from a debug register only returns the bottom bits
489 *
490 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
491 * switches between host and guest values in future.
492 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)493 static void reg_to_dbg(struct kvm_vcpu *vcpu,
494 struct sys_reg_params *p,
495 const struct sys_reg_desc *rd,
496 u64 *dbg_reg)
497 {
498 u64 mask, shift, val;
499
500 get_access_mask(rd, &mask, &shift);
501
502 val = *dbg_reg;
503 val &= ~mask;
504 val |= (p->regval & (mask >> shift)) << shift;
505 *dbg_reg = val;
506
507 vcpu_set_flag(vcpu, DEBUG_DIRTY);
508 }
509
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)510 static void dbg_to_reg(struct kvm_vcpu *vcpu,
511 struct sys_reg_params *p,
512 const struct sys_reg_desc *rd,
513 u64 *dbg_reg)
514 {
515 u64 mask, shift;
516
517 get_access_mask(rd, &mask, &shift);
518 p->regval = (*dbg_reg & mask) >> shift;
519 }
520
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)521 static bool trap_bvr(struct kvm_vcpu *vcpu,
522 struct sys_reg_params *p,
523 const struct sys_reg_desc *rd)
524 {
525 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
526
527 if (p->is_write)
528 reg_to_dbg(vcpu, p, rd, dbg_reg);
529 else
530 dbg_to_reg(vcpu, p, rd, dbg_reg);
531
532 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
533
534 return true;
535 }
536
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)537 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
538 u64 val)
539 {
540 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
541 return 0;
542 }
543
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)544 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
545 u64 *val)
546 {
547 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
548 return 0;
549 }
550
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)551 static u64 reset_bvr(struct kvm_vcpu *vcpu,
552 const struct sys_reg_desc *rd)
553 {
554 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
555 return rd->val;
556 }
557
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)558 static bool trap_bcr(struct kvm_vcpu *vcpu,
559 struct sys_reg_params *p,
560 const struct sys_reg_desc *rd)
561 {
562 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
563
564 if (p->is_write)
565 reg_to_dbg(vcpu, p, rd, dbg_reg);
566 else
567 dbg_to_reg(vcpu, p, rd, dbg_reg);
568
569 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
570
571 return true;
572 }
573
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)574 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
575 u64 val)
576 {
577 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
578 return 0;
579 }
580
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)581 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
582 u64 *val)
583 {
584 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
585 return 0;
586 }
587
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)588 static u64 reset_bcr(struct kvm_vcpu *vcpu,
589 const struct sys_reg_desc *rd)
590 {
591 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
592 return rd->val;
593 }
594
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)595 static bool trap_wvr(struct kvm_vcpu *vcpu,
596 struct sys_reg_params *p,
597 const struct sys_reg_desc *rd)
598 {
599 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
600
601 if (p->is_write)
602 reg_to_dbg(vcpu, p, rd, dbg_reg);
603 else
604 dbg_to_reg(vcpu, p, rd, dbg_reg);
605
606 trace_trap_reg(__func__, rd->CRm, p->is_write,
607 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
608
609 return true;
610 }
611
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)612 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
613 u64 val)
614 {
615 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
616 return 0;
617 }
618
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)619 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
620 u64 *val)
621 {
622 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
623 return 0;
624 }
625
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)626 static u64 reset_wvr(struct kvm_vcpu *vcpu,
627 const struct sys_reg_desc *rd)
628 {
629 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
630 return rd->val;
631 }
632
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)633 static bool trap_wcr(struct kvm_vcpu *vcpu,
634 struct sys_reg_params *p,
635 const struct sys_reg_desc *rd)
636 {
637 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
638
639 if (p->is_write)
640 reg_to_dbg(vcpu, p, rd, dbg_reg);
641 else
642 dbg_to_reg(vcpu, p, rd, dbg_reg);
643
644 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
645
646 return true;
647 }
648
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)649 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
650 u64 val)
651 {
652 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
653 return 0;
654 }
655
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)656 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
657 u64 *val)
658 {
659 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
660 return 0;
661 }
662
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)663 static u64 reset_wcr(struct kvm_vcpu *vcpu,
664 const struct sys_reg_desc *rd)
665 {
666 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
667 return rd->val;
668 }
669
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)670 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
671 {
672 u64 amair = read_sysreg(amair_el1);
673 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
674 return amair;
675 }
676
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)677 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
678 {
679 u64 actlr = read_sysreg(actlr_el1);
680 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
681 return actlr;
682 }
683
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)684 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
685 {
686 u64 mpidr = calculate_mpidr(vcpu);
687
688 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
689 return mpidr;
690 }
691
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)692 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
693 const struct sys_reg_desc *r)
694 {
695 if (kvm_vcpu_has_pmu(vcpu))
696 return 0;
697
698 return REG_HIDDEN;
699 }
700
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)701 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
702 {
703 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
704 u8 n = vcpu->kvm->arch.pmcr_n;
705
706 if (n)
707 mask |= GENMASK(n - 1, 0);
708
709 reset_unknown(vcpu, r);
710 __vcpu_sys_reg(vcpu, r->reg) &= mask;
711
712 return __vcpu_sys_reg(vcpu, r->reg);
713 }
714
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)715 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
716 {
717 reset_unknown(vcpu, r);
718 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
719
720 return __vcpu_sys_reg(vcpu, r->reg);
721 }
722
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)723 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
724 {
725 /* This thing will UNDEF, who cares about the reset value? */
726 if (!kvm_vcpu_has_pmu(vcpu))
727 return 0;
728
729 reset_unknown(vcpu, r);
730 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm);
731
732 return __vcpu_sys_reg(vcpu, r->reg);
733 }
734
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)735 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
736 {
737 reset_unknown(vcpu, r);
738 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
739
740 return __vcpu_sys_reg(vcpu, r->reg);
741 }
742
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)743 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
744 {
745 u64 pmcr = 0;
746
747 if (!kvm_supports_32bit_el0())
748 pmcr |= ARMV8_PMU_PMCR_LC;
749
750 /*
751 * The value of PMCR.N field is included when the
752 * vCPU register is read via kvm_vcpu_read_pmcr().
753 */
754 __vcpu_sys_reg(vcpu, r->reg) = pmcr;
755
756 return __vcpu_sys_reg(vcpu, r->reg);
757 }
758
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)759 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
760 {
761 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
762 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
763
764 if (!enabled)
765 kvm_inject_undefined(vcpu);
766
767 return !enabled;
768 }
769
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)770 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
771 {
772 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
773 }
774
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)775 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
776 {
777 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
778 }
779
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)780 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
781 {
782 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
783 }
784
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)785 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
786 {
787 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
788 }
789
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)790 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
791 const struct sys_reg_desc *r)
792 {
793 u64 val;
794
795 if (pmu_access_el0_disabled(vcpu))
796 return false;
797
798 if (p->is_write) {
799 /*
800 * Only update writeable bits of PMCR (continuing into
801 * kvm_pmu_handle_pmcr() as well)
802 */
803 val = kvm_vcpu_read_pmcr(vcpu);
804 val &= ~ARMV8_PMU_PMCR_MASK;
805 val |= p->regval & ARMV8_PMU_PMCR_MASK;
806 if (!kvm_supports_32bit_el0())
807 val |= ARMV8_PMU_PMCR_LC;
808 kvm_pmu_handle_pmcr(vcpu, val);
809 } else {
810 /* PMCR.P & PMCR.C are RAZ */
811 val = kvm_vcpu_read_pmcr(vcpu)
812 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
813 p->regval = val;
814 }
815
816 return true;
817 }
818
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)819 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
820 const struct sys_reg_desc *r)
821 {
822 if (pmu_access_event_counter_el0_disabled(vcpu))
823 return false;
824
825 if (p->is_write)
826 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
827 else
828 /* return PMSELR.SEL field */
829 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
830 & PMSELR_EL0_SEL_MASK;
831
832 return true;
833 }
834
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)835 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
836 const struct sys_reg_desc *r)
837 {
838 u64 pmceid, mask, shift;
839
840 BUG_ON(p->is_write);
841
842 if (pmu_access_el0_disabled(vcpu))
843 return false;
844
845 get_access_mask(r, &mask, &shift);
846
847 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
848 pmceid &= mask;
849 pmceid >>= shift;
850
851 p->regval = pmceid;
852
853 return true;
854 }
855
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)856 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
857 {
858 u64 pmcr, val;
859
860 pmcr = kvm_vcpu_read_pmcr(vcpu);
861 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
862 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
863 kvm_inject_undefined(vcpu);
864 return false;
865 }
866
867 return true;
868 }
869
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)870 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
871 u64 *val)
872 {
873 u64 idx;
874
875 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
876 /* PMCCNTR_EL0 */
877 idx = ARMV8_PMU_CYCLE_IDX;
878 else
879 /* PMEVCNTRn_EL0 */
880 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
881
882 *val = kvm_pmu_get_counter_value(vcpu, idx);
883 return 0;
884 }
885
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)886 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
887 struct sys_reg_params *p,
888 const struct sys_reg_desc *r)
889 {
890 u64 idx = ~0UL;
891
892 if (r->CRn == 9 && r->CRm == 13) {
893 if (r->Op2 == 2) {
894 /* PMXEVCNTR_EL0 */
895 if (pmu_access_event_counter_el0_disabled(vcpu))
896 return false;
897
898 idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
899 __vcpu_sys_reg(vcpu, PMSELR_EL0));
900 } else if (r->Op2 == 0) {
901 /* PMCCNTR_EL0 */
902 if (pmu_access_cycle_counter_el0_disabled(vcpu))
903 return false;
904
905 idx = ARMV8_PMU_CYCLE_IDX;
906 }
907 } else if (r->CRn == 0 && r->CRm == 9) {
908 /* PMCCNTR */
909 if (pmu_access_event_counter_el0_disabled(vcpu))
910 return false;
911
912 idx = ARMV8_PMU_CYCLE_IDX;
913 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
914 /* PMEVCNTRn_EL0 */
915 if (pmu_access_event_counter_el0_disabled(vcpu))
916 return false;
917
918 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
919 }
920
921 /* Catch any decoding mistake */
922 WARN_ON(idx == ~0UL);
923
924 if (!pmu_counter_idx_valid(vcpu, idx))
925 return false;
926
927 if (p->is_write) {
928 if (pmu_access_el0_disabled(vcpu))
929 return false;
930
931 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
932 } else {
933 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
934 }
935
936 return true;
937 }
938
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)939 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
940 const struct sys_reg_desc *r)
941 {
942 u64 idx, reg;
943
944 if (pmu_access_el0_disabled(vcpu))
945 return false;
946
947 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
948 /* PMXEVTYPER_EL0 */
949 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
950 reg = PMEVTYPER0_EL0 + idx;
951 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
952 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
953 if (idx == ARMV8_PMU_CYCLE_IDX)
954 reg = PMCCFILTR_EL0;
955 else
956 /* PMEVTYPERn_EL0 */
957 reg = PMEVTYPER0_EL0 + idx;
958 } else {
959 BUG();
960 }
961
962 if (!pmu_counter_idx_valid(vcpu, idx))
963 return false;
964
965 if (p->is_write) {
966 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
967 kvm_vcpu_pmu_restore_guest(vcpu);
968 } else {
969 p->regval = __vcpu_sys_reg(vcpu, reg);
970 }
971
972 return true;
973 }
974
set_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)975 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
976 {
977 bool set;
978
979 val &= kvm_pmu_valid_counter_mask(vcpu);
980
981 switch (r->reg) {
982 case PMOVSSET_EL0:
983 /* CRm[1] being set indicates a SET register, and CLR otherwise */
984 set = r->CRm & 2;
985 break;
986 default:
987 /* Op2[0] being set indicates a SET register, and CLR otherwise */
988 set = r->Op2 & 1;
989 break;
990 }
991
992 if (set)
993 __vcpu_sys_reg(vcpu, r->reg) |= val;
994 else
995 __vcpu_sys_reg(vcpu, r->reg) &= ~val;
996
997 return 0;
998 }
999
get_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1000 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
1001 {
1002 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1003
1004 *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
1005 return 0;
1006 }
1007
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1008 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1009 const struct sys_reg_desc *r)
1010 {
1011 u64 val, mask;
1012
1013 if (pmu_access_el0_disabled(vcpu))
1014 return false;
1015
1016 mask = kvm_pmu_valid_counter_mask(vcpu);
1017 if (p->is_write) {
1018 val = p->regval & mask;
1019 if (r->Op2 & 0x1) {
1020 /* accessing PMCNTENSET_EL0 */
1021 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
1022 kvm_pmu_enable_counter_mask(vcpu, val);
1023 kvm_vcpu_pmu_restore_guest(vcpu);
1024 } else {
1025 /* accessing PMCNTENCLR_EL0 */
1026 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
1027 kvm_pmu_disable_counter_mask(vcpu, val);
1028 }
1029 } else {
1030 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
1031 }
1032
1033 return true;
1034 }
1035
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1036 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1037 const struct sys_reg_desc *r)
1038 {
1039 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1040
1041 if (check_pmu_access_disabled(vcpu, 0))
1042 return false;
1043
1044 if (p->is_write) {
1045 u64 val = p->regval & mask;
1046
1047 if (r->Op2 & 0x1)
1048 /* accessing PMINTENSET_EL1 */
1049 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
1050 else
1051 /* accessing PMINTENCLR_EL1 */
1052 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1053 } else {
1054 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1055 }
1056
1057 return true;
1058 }
1059
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1060 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1061 const struct sys_reg_desc *r)
1062 {
1063 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1064
1065 if (pmu_access_el0_disabled(vcpu))
1066 return false;
1067
1068 if (p->is_write) {
1069 if (r->CRm & 0x2)
1070 /* accessing PMOVSSET_EL0 */
1071 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
1072 else
1073 /* accessing PMOVSCLR_EL0 */
1074 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
1075 } else {
1076 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1077 }
1078
1079 return true;
1080 }
1081
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1082 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1083 const struct sys_reg_desc *r)
1084 {
1085 u64 mask;
1086
1087 if (!p->is_write)
1088 return read_from_write_only(vcpu, p, r);
1089
1090 if (pmu_write_swinc_el0_disabled(vcpu))
1091 return false;
1092
1093 mask = kvm_pmu_valid_counter_mask(vcpu);
1094 kvm_pmu_software_increment(vcpu, p->regval & mask);
1095 return true;
1096 }
1097
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1098 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1099 const struct sys_reg_desc *r)
1100 {
1101 if (p->is_write) {
1102 if (!vcpu_mode_priv(vcpu))
1103 return undef_access(vcpu, p, r);
1104
1105 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1106 p->regval & ARMV8_PMU_USERENR_MASK;
1107 } else {
1108 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1109 & ARMV8_PMU_USERENR_MASK;
1110 }
1111
1112 return true;
1113 }
1114
get_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1115 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1116 u64 *val)
1117 {
1118 *val = kvm_vcpu_read_pmcr(vcpu);
1119 return 0;
1120 }
1121
set_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1122 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1123 u64 val)
1124 {
1125 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
1126 struct kvm *kvm = vcpu->kvm;
1127
1128 mutex_lock(&kvm->arch.config_lock);
1129
1130 /*
1131 * The vCPU can't have more counters than the PMU hardware
1132 * implements. Ignore this error to maintain compatibility
1133 * with the existing KVM behavior.
1134 */
1135 if (!kvm_vm_has_ran_once(kvm) &&
1136 new_n <= kvm_arm_pmu_get_max_counters(kvm))
1137 kvm->arch.pmcr_n = new_n;
1138
1139 mutex_unlock(&kvm->arch.config_lock);
1140
1141 /*
1142 * Ignore writes to RES0 bits, read only bits that are cleared on
1143 * vCPU reset, and writable bits that KVM doesn't support yet.
1144 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
1145 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU.
1146 * But, we leave the bit as it is here, as the vCPU's PMUver might
1147 * be changed later (NOTE: the bit will be cleared on first vCPU run
1148 * if necessary).
1149 */
1150 val &= ARMV8_PMU_PMCR_MASK;
1151
1152 /* The LC bit is RES1 when AArch32 is not supported */
1153 if (!kvm_supports_32bit_el0())
1154 val |= ARMV8_PMU_PMCR_LC;
1155
1156 __vcpu_sys_reg(vcpu, r->reg) = val;
1157 return 0;
1158 }
1159
1160 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1161 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1162 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1163 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1164 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1165 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1166 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1167 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1168 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1169 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1170
1171 #define PMU_SYS_REG(name) \
1172 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1173 .visibility = pmu_visibility
1174
1175 /* Macro to expand the PMEVCNTRn_EL0 register */
1176 #define PMU_PMEVCNTR_EL0(n) \
1177 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
1178 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
1179 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1180
1181 /* Macro to expand the PMEVTYPERn_EL0 register */
1182 #define PMU_PMEVTYPER_EL0(n) \
1183 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
1184 .reset = reset_pmevtyper, \
1185 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1186
1187 /* Macro to expand the AMU counter and type registers*/
1188 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1189 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1190 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1191 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1192
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1193 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1194 const struct sys_reg_desc *rd)
1195 {
1196 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1197 }
1198
1199 /*
1200 * If we land here on a PtrAuth access, that is because we didn't
1201 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1202 * way this happens is when the guest does not have PtrAuth support
1203 * enabled.
1204 */
1205 #define __PTRAUTH_KEY(k) \
1206 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1207 .visibility = ptrauth_visibility}
1208
1209 #define PTRAUTH_KEY(k) \
1210 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1211 __PTRAUTH_KEY(k ## KEYHI_EL1)
1212
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1213 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1214 struct sys_reg_params *p,
1215 const struct sys_reg_desc *r)
1216 {
1217 enum kvm_arch_timers tmr;
1218 enum kvm_arch_timer_regs treg;
1219 u64 reg = reg_to_encoding(r);
1220
1221 switch (reg) {
1222 case SYS_CNTP_TVAL_EL0:
1223 case SYS_AARCH32_CNTP_TVAL:
1224 tmr = TIMER_PTIMER;
1225 treg = TIMER_REG_TVAL;
1226 break;
1227 case SYS_CNTP_CTL_EL0:
1228 case SYS_AARCH32_CNTP_CTL:
1229 tmr = TIMER_PTIMER;
1230 treg = TIMER_REG_CTL;
1231 break;
1232 case SYS_CNTP_CVAL_EL0:
1233 case SYS_AARCH32_CNTP_CVAL:
1234 tmr = TIMER_PTIMER;
1235 treg = TIMER_REG_CVAL;
1236 break;
1237 case SYS_CNTPCT_EL0:
1238 case SYS_CNTPCTSS_EL0:
1239 case SYS_AARCH32_CNTPCT:
1240 tmr = TIMER_PTIMER;
1241 treg = TIMER_REG_CNT;
1242 break;
1243 default:
1244 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1245 return undef_access(vcpu, p, r);
1246 }
1247
1248 if (p->is_write)
1249 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1250 else
1251 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1252
1253 return true;
1254 }
1255
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1256 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1257 s64 new, s64 cur)
1258 {
1259 struct arm64_ftr_bits kvm_ftr = *ftrp;
1260
1261 /* Some features have different safe value type in KVM than host features */
1262 switch (id) {
1263 case SYS_ID_AA64DFR0_EL1:
1264 switch (kvm_ftr.shift) {
1265 case ID_AA64DFR0_EL1_PMUVer_SHIFT:
1266 kvm_ftr.type = FTR_LOWER_SAFE;
1267 break;
1268 case ID_AA64DFR0_EL1_DebugVer_SHIFT:
1269 kvm_ftr.type = FTR_LOWER_SAFE;
1270 break;
1271 }
1272 break;
1273 case SYS_ID_DFR0_EL1:
1274 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1275 kvm_ftr.type = FTR_LOWER_SAFE;
1276 break;
1277 }
1278
1279 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1280 }
1281
1282 /*
1283 * arm64_check_features() - Check if a feature register value constitutes
1284 * a subset of features indicated by the idreg's KVM sanitised limit.
1285 *
1286 * This function will check if each feature field of @val is the "safe" value
1287 * against idreg's KVM sanitised limit return from reset() callback.
1288 * If a field value in @val is the same as the one in limit, it is always
1289 * considered the safe value regardless For register fields that are not in
1290 * writable, only the value in limit is considered the safe value.
1291 *
1292 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1293 */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1294 static int arm64_check_features(struct kvm_vcpu *vcpu,
1295 const struct sys_reg_desc *rd,
1296 u64 val)
1297 {
1298 const struct arm64_ftr_reg *ftr_reg;
1299 const struct arm64_ftr_bits *ftrp = NULL;
1300 u32 id = reg_to_encoding(rd);
1301 u64 writable_mask = rd->val;
1302 u64 limit = rd->reset(vcpu, rd);
1303 u64 mask = 0;
1304
1305 /*
1306 * Hidden and unallocated ID registers may not have a corresponding
1307 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1308 * only safe value is 0.
1309 */
1310 if (sysreg_visible_as_raz(vcpu, rd))
1311 return val ? -E2BIG : 0;
1312
1313 ftr_reg = get_arm64_ftr_reg(id);
1314 if (!ftr_reg)
1315 return -EINVAL;
1316
1317 ftrp = ftr_reg->ftr_bits;
1318
1319 for (; ftrp && ftrp->width; ftrp++) {
1320 s64 f_val, f_lim, safe_val;
1321 u64 ftr_mask;
1322
1323 ftr_mask = arm64_ftr_mask(ftrp);
1324 if ((ftr_mask & writable_mask) != ftr_mask)
1325 continue;
1326
1327 f_val = arm64_ftr_value(ftrp, val);
1328 f_lim = arm64_ftr_value(ftrp, limit);
1329 mask |= ftr_mask;
1330
1331 if (f_val == f_lim)
1332 safe_val = f_val;
1333 else
1334 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1335
1336 if (safe_val != f_val)
1337 return -E2BIG;
1338 }
1339
1340 /* For fields that are not writable, values in limit are the safe values. */
1341 if ((val & ~mask) != (limit & ~mask))
1342 return -E2BIG;
1343
1344 return 0;
1345 }
1346
pmuver_to_perfmon(u8 pmuver)1347 static u8 pmuver_to_perfmon(u8 pmuver)
1348 {
1349 switch (pmuver) {
1350 case ID_AA64DFR0_EL1_PMUVer_IMP:
1351 return ID_DFR0_EL1_PerfMon_PMUv3;
1352 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1353 return ID_DFR0_EL1_PerfMon_IMPDEF;
1354 default:
1355 /* Anything ARMv8.1+ and NI have the same value. For now. */
1356 return pmuver;
1357 }
1358 }
1359
1360 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1361 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1362
1363 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1364 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1365 const struct sys_reg_desc *r)
1366 {
1367 u32 id = reg_to_encoding(r);
1368 u64 val;
1369
1370 if (sysreg_visible_as_raz(vcpu, r))
1371 return 0;
1372
1373 val = read_sanitised_ftr_reg(id);
1374
1375 switch (id) {
1376 case SYS_ID_AA64DFR0_EL1:
1377 val = sanitise_id_aa64dfr0_el1(vcpu, val);
1378 break;
1379 case SYS_ID_AA64PFR0_EL1:
1380 val = sanitise_id_aa64pfr0_el1(vcpu, val);
1381 break;
1382 case SYS_ID_AA64PFR1_EL1:
1383 if (!kvm_has_mte(vcpu->kvm))
1384 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1385
1386 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1387 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
1388 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
1389 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
1390 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
1391 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
1392 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
1393 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2);
1394 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
1395 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac);
1396 break;
1397 case SYS_ID_AA64PFR2_EL1:
1398 /* We only expose FPMR */
1399 val &= ID_AA64PFR2_EL1_FPMR;
1400 break;
1401 case SYS_ID_AA64ISAR1_EL1:
1402 if (!vcpu_has_ptrauth(vcpu))
1403 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1404 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1405 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1406 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1407 break;
1408 case SYS_ID_AA64ISAR2_EL1:
1409 if (!vcpu_has_ptrauth(vcpu))
1410 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1411 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1412 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1413 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1414 break;
1415 case SYS_ID_AA64MMFR2_EL1:
1416 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1417 break;
1418 case SYS_ID_AA64MMFR3_EL1:
1419 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE |
1420 ID_AA64MMFR3_EL1_S1PIE;
1421 break;
1422 case SYS_ID_MMFR4_EL1:
1423 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1424 break;
1425 }
1426
1427 return val;
1428 }
1429
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1430 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1431 const struct sys_reg_desc *r)
1432 {
1433 return __kvm_read_sanitised_id_reg(vcpu, r);
1434 }
1435
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1436 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1437 {
1438 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r));
1439 }
1440
is_feature_id_reg(u32 encoding)1441 static bool is_feature_id_reg(u32 encoding)
1442 {
1443 return (sys_reg_Op0(encoding) == 3 &&
1444 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) &&
1445 sys_reg_CRn(encoding) == 0 &&
1446 sys_reg_CRm(encoding) <= 7);
1447 }
1448
1449 /*
1450 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1451 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID
1452 * registers KVM maintains on a per-VM basis.
1453 */
is_vm_ftr_id_reg(u32 id)1454 static inline bool is_vm_ftr_id_reg(u32 id)
1455 {
1456 if (id == SYS_CTR_EL0)
1457 return true;
1458
1459 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1460 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1461 sys_reg_CRm(id) < 8);
1462 }
1463
is_vcpu_ftr_id_reg(u32 id)1464 static inline bool is_vcpu_ftr_id_reg(u32 id)
1465 {
1466 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id);
1467 }
1468
is_aa32_id_reg(u32 id)1469 static inline bool is_aa32_id_reg(u32 id)
1470 {
1471 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1472 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1473 sys_reg_CRm(id) <= 3);
1474 }
1475
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1476 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1477 const struct sys_reg_desc *r)
1478 {
1479 u32 id = reg_to_encoding(r);
1480
1481 switch (id) {
1482 case SYS_ID_AA64ZFR0_EL1:
1483 if (!vcpu_has_sve(vcpu))
1484 return REG_RAZ;
1485 break;
1486 }
1487
1488 return 0;
1489 }
1490
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1491 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1492 const struct sys_reg_desc *r)
1493 {
1494 /*
1495 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1496 * EL. Promote to RAZ/WI in order to guarantee consistency between
1497 * systems.
1498 */
1499 if (!kvm_supports_32bit_el0())
1500 return REG_RAZ | REG_USER_WI;
1501
1502 return id_visibility(vcpu, r);
1503 }
1504
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1505 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1506 const struct sys_reg_desc *r)
1507 {
1508 return REG_RAZ;
1509 }
1510
1511 /* cpufeature ID register access trap handlers */
1512
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1513 static bool access_id_reg(struct kvm_vcpu *vcpu,
1514 struct sys_reg_params *p,
1515 const struct sys_reg_desc *r)
1516 {
1517 if (p->is_write)
1518 return write_to_read_only(vcpu, p, r);
1519
1520 p->regval = read_id_reg(vcpu, r);
1521
1522 return true;
1523 }
1524
1525 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1526 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1527 const struct sys_reg_desc *rd)
1528 {
1529 if (vcpu_has_sve(vcpu))
1530 return 0;
1531
1532 return REG_HIDDEN;
1533 }
1534
sme_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1535 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu,
1536 const struct sys_reg_desc *rd)
1537 {
1538 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP))
1539 return 0;
1540
1541 return REG_HIDDEN;
1542 }
1543
fp8_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1544 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu,
1545 const struct sys_reg_desc *rd)
1546 {
1547 if (kvm_has_fpmr(vcpu->kvm))
1548 return 0;
1549
1550 return REG_HIDDEN;
1551 }
1552
sanitise_id_aa64pfr0_el1(const struct kvm_vcpu * vcpu,u64 val)1553 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
1554 {
1555 if (!vcpu_has_sve(vcpu))
1556 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
1557
1558 /*
1559 * The default is to expose CSV2 == 1 if the HW isn't affected.
1560 * Although this is a per-CPU feature, we make it global because
1561 * asymmetric systems are just a nuisance.
1562 *
1563 * Userspace can override this as long as it doesn't promise
1564 * the impossible.
1565 */
1566 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1567 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1568 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1569 }
1570 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1571 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1572 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1573 }
1574
1575 if (kvm_vgic_global_state.type == VGIC_V3) {
1576 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1577 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1578 }
1579
1580 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
1581
1582 /*
1583 * MPAM is disabled by default as KVM also needs a set of PARTID to
1584 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some
1585 * older kernels let the guest see the ID bit.
1586 */
1587 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
1588
1589 return val;
1590 }
1591
1592 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \
1593 ({ \
1594 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \
1595 (val) &= ~reg##_##field##_MASK; \
1596 (val) |= FIELD_PREP(reg##_##field##_MASK, \
1597 min(__f_val, \
1598 (u64)SYS_FIELD_VALUE(reg, field, limit))); \
1599 (val); \
1600 })
1601
sanitise_id_aa64dfr0_el1(const struct kvm_vcpu * vcpu,u64 val)1602 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val)
1603 {
1604 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
1605
1606 /*
1607 * Only initialize the PMU version if the vCPU was configured with one.
1608 */
1609 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1610 if (kvm_vcpu_has_pmu(vcpu))
1611 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1612 kvm_arm_pmu_get_pmuver_limit());
1613
1614 /* Hide SPE from guests */
1615 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1616
1617 return val;
1618 }
1619
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1620 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1621 const struct sys_reg_desc *rd,
1622 u64 val)
1623 {
1624 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val);
1625 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
1626
1627 /*
1628 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1629 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1630 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1631 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1632 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1633 *
1634 * At minimum, we're on the hook to allow values that were given to
1635 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1636 * with a more sensible NI. The value of an ID register changing under
1637 * the nose of the guest is unfortunate, but is certainly no more
1638 * surprising than an ill-guided PMU driver poking at impdef system
1639 * registers that end in an UNDEF...
1640 */
1641 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1642 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1643
1644 /*
1645 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a
1646 * nonzero minimum safe value.
1647 */
1648 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP)
1649 return -EINVAL;
1650
1651 return set_id_reg(vcpu, rd, val);
1652 }
1653
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1654 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1655 const struct sys_reg_desc *rd)
1656 {
1657 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1658 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
1659
1660 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1661 if (kvm_vcpu_has_pmu(vcpu))
1662 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
1663
1664 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
1665
1666 return val;
1667 }
1668
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1669 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1670 const struct sys_reg_desc *rd,
1671 u64 val)
1672 {
1673 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
1674 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val);
1675
1676 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1677 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1678 perfmon = 0;
1679 }
1680
1681 /*
1682 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1683 * it doesn't promise more than what the HW gives us on the
1684 * AArch64 side (as everything is emulated with that), and
1685 * that this is a PMUv3.
1686 */
1687 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
1688 return -EINVAL;
1689
1690 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8)
1691 return -EINVAL;
1692
1693 return set_id_reg(vcpu, rd, val);
1694 }
1695
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)1696 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1697 const struct sys_reg_desc *rd, u64 user_val)
1698 {
1699 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1700 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK;
1701
1702 /*
1703 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits
1704 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to
1705 * guests, but didn't add trap handling. KVM doesn't support MPAM and
1706 * always returns an UNDEF for these registers. The guest must see 0
1707 * for this field.
1708 *
1709 * But KVM must also accept values from user-space that were provided
1710 * by KVM. On CPUs that support MPAM, permit user-space to write
1711 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field.
1712 */
1713 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
1714 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
1715
1716 return set_id_reg(vcpu, rd, user_val);
1717 }
1718
set_id_aa64pfr1_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 user_val)1719 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
1720 const struct sys_reg_desc *rd, u64 user_val)
1721 {
1722 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
1723 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK;
1724
1725 /* See set_id_aa64pfr0_el1 for comment about MPAM */
1726 if ((hw_val & mpam_mask) == (user_val & mpam_mask))
1727 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
1728
1729 return set_id_reg(vcpu, rd, user_val);
1730 }
1731
1732 /*
1733 * cpufeature ID register user accessors
1734 *
1735 * For now, these registers are immutable for userspace, so no values
1736 * are stored, and for set_id_reg() we don't allow the effective value
1737 * to be changed.
1738 */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1739 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1740 u64 *val)
1741 {
1742 /*
1743 * Avoid locking if the VM has already started, as the ID registers are
1744 * guaranteed to be invariant at that point.
1745 */
1746 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1747 *val = read_id_reg(vcpu, rd);
1748 return 0;
1749 }
1750
1751 mutex_lock(&vcpu->kvm->arch.config_lock);
1752 *val = read_id_reg(vcpu, rd);
1753 mutex_unlock(&vcpu->kvm->arch.config_lock);
1754
1755 return 0;
1756 }
1757
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1758 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1759 u64 val)
1760 {
1761 u32 id = reg_to_encoding(rd);
1762 int ret;
1763
1764 mutex_lock(&vcpu->kvm->arch.config_lock);
1765
1766 /*
1767 * Once the VM has started the ID registers are immutable. Reject any
1768 * write that does not match the final register value.
1769 */
1770 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1771 if (val != read_id_reg(vcpu, rd))
1772 ret = -EBUSY;
1773 else
1774 ret = 0;
1775
1776 mutex_unlock(&vcpu->kvm->arch.config_lock);
1777 return ret;
1778 }
1779
1780 ret = arm64_check_features(vcpu, rd, val);
1781 if (!ret)
1782 kvm_set_vm_id_reg(vcpu->kvm, id, val);
1783
1784 mutex_unlock(&vcpu->kvm->arch.config_lock);
1785
1786 /*
1787 * arm64_check_features() returns -E2BIG to indicate the register's
1788 * feature set is a superset of the maximally-allowed register value.
1789 * While it would be nice to precisely describe this to userspace, the
1790 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
1791 * writes return -EINVAL.
1792 */
1793 if (ret == -E2BIG)
1794 ret = -EINVAL;
1795 return ret;
1796 }
1797
kvm_set_vm_id_reg(struct kvm * kvm,u32 reg,u64 val)1798 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val)
1799 {
1800 u64 *p = __vm_id_reg(&kvm->arch, reg);
1801
1802 lockdep_assert_held(&kvm->arch.config_lock);
1803
1804 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm))
1805 return;
1806
1807 *p = val;
1808 }
1809
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1810 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1811 u64 *val)
1812 {
1813 *val = 0;
1814 return 0;
1815 }
1816
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1817 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1818 u64 val)
1819 {
1820 return 0;
1821 }
1822
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1823 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1824 const struct sys_reg_desc *r)
1825 {
1826 if (p->is_write)
1827 return write_to_read_only(vcpu, p, r);
1828
1829 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0);
1830 return true;
1831 }
1832
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1833 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1834 const struct sys_reg_desc *r)
1835 {
1836 if (p->is_write)
1837 return write_to_read_only(vcpu, p, r);
1838
1839 p->regval = __vcpu_sys_reg(vcpu, r->reg);
1840 return true;
1841 }
1842
1843 /*
1844 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
1845 * by the physical CPU which the vcpu currently resides in.
1846 */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1847 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1848 {
1849 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1850 u64 clidr;
1851 u8 loc;
1852
1853 if ((ctr_el0 & CTR_EL0_IDC)) {
1854 /*
1855 * Data cache clean to the PoU is not required so LoUU and LoUIS
1856 * will not be set and a unified cache, which will be marked as
1857 * LoC, will be added.
1858 *
1859 * If not DIC, let the unified cache L2 so that an instruction
1860 * cache can be added as L1 later.
1861 */
1862 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
1863 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
1864 } else {
1865 /*
1866 * Data cache clean to the PoU is required so let L1 have a data
1867 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
1868 * it can be marked as LoC too.
1869 */
1870 loc = 1;
1871 clidr = 1 << CLIDR_LOUU_SHIFT;
1872 clidr |= 1 << CLIDR_LOUIS_SHIFT;
1873 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
1874 }
1875
1876 /*
1877 * Instruction cache invalidation to the PoU is required so let L1 have
1878 * an instruction cache. If L1 already has a data cache, it will be
1879 * CACHE_TYPE_SEPARATE.
1880 */
1881 if (!(ctr_el0 & CTR_EL0_DIC))
1882 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
1883
1884 clidr |= loc << CLIDR_LOC_SHIFT;
1885
1886 /*
1887 * Add tag cache unified to data cache. Allocation tags and data are
1888 * unified in a cache line so that it looks valid even if there is only
1889 * one cache line.
1890 */
1891 if (kvm_has_mte(vcpu->kvm))
1892 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
1893
1894 __vcpu_sys_reg(vcpu, r->reg) = clidr;
1895
1896 return __vcpu_sys_reg(vcpu, r->reg);
1897 }
1898
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1899 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1900 u64 val)
1901 {
1902 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1903 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
1904
1905 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
1906 return -EINVAL;
1907
1908 __vcpu_sys_reg(vcpu, rd->reg) = val;
1909
1910 return 0;
1911 }
1912
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1913 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1914 const struct sys_reg_desc *r)
1915 {
1916 int reg = r->reg;
1917
1918 if (p->is_write)
1919 vcpu_write_sys_reg(vcpu, p->regval, reg);
1920 else
1921 p->regval = vcpu_read_sys_reg(vcpu, reg);
1922 return true;
1923 }
1924
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1925 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1926 const struct sys_reg_desc *r)
1927 {
1928 u32 csselr;
1929
1930 if (p->is_write)
1931 return write_to_read_only(vcpu, p, r);
1932
1933 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1934 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
1935 if (csselr < CSSELR_MAX)
1936 p->regval = get_ccsidr(vcpu, csselr);
1937
1938 return true;
1939 }
1940
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1941 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1942 const struct sys_reg_desc *rd)
1943 {
1944 if (kvm_has_mte(vcpu->kvm))
1945 return 0;
1946
1947 return REG_HIDDEN;
1948 }
1949
1950 #define MTE_REG(name) { \
1951 SYS_DESC(SYS_##name), \
1952 .access = undef_access, \
1953 .reset = reset_unknown, \
1954 .reg = name, \
1955 .visibility = mte_visibility, \
1956 }
1957
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1958 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
1959 const struct sys_reg_desc *rd)
1960 {
1961 if (vcpu_has_nv(vcpu))
1962 return 0;
1963
1964 return REG_HIDDEN;
1965 }
1966
bad_vncr_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1967 static bool bad_vncr_trap(struct kvm_vcpu *vcpu,
1968 struct sys_reg_params *p,
1969 const struct sys_reg_desc *r)
1970 {
1971 /*
1972 * We really shouldn't be here, and this is likely the result
1973 * of a misconfigured trap, as this register should target the
1974 * VNCR page, and nothing else.
1975 */
1976 return bad_trap(vcpu, p, r,
1977 "trap of VNCR-backed register");
1978 }
1979
bad_redir_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1980 static bool bad_redir_trap(struct kvm_vcpu *vcpu,
1981 struct sys_reg_params *p,
1982 const struct sys_reg_desc *r)
1983 {
1984 /*
1985 * We really shouldn't be here, and this is likely the result
1986 * of a misconfigured trap, as this register should target the
1987 * corresponding EL1, and nothing else.
1988 */
1989 return bad_trap(vcpu, p, r,
1990 "trap of EL2 register redirected to EL1");
1991 }
1992
1993 #define EL2_REG(name, acc, rst, v) { \
1994 SYS_DESC(SYS_##name), \
1995 .access = acc, \
1996 .reset = rst, \
1997 .reg = name, \
1998 .visibility = el2_visibility, \
1999 .val = v, \
2000 }
2001
2002 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v)
2003 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v)
2004
2005 /*
2006 * Since reset() callback and field val are not used for idregs, they will be
2007 * used for specific purposes for idregs.
2008 * The reset() would return KVM sanitised register value. The value would be the
2009 * same as the host kernel sanitised value if there is no KVM sanitisation.
2010 * The val would be used as a mask indicating writable fields for the idreg.
2011 * Only bits with 1 are writable from userspace. This mask might not be
2012 * necessary in the future whenever all ID registers are enabled as writable
2013 * from userspace.
2014 */
2015
2016 #define ID_DESC(name) \
2017 SYS_DESC(SYS_##name), \
2018 .access = access_id_reg, \
2019 .get_user = get_id_reg \
2020
2021 /* sys_reg_desc initialiser for known cpufeature ID registers */
2022 #define ID_SANITISED(name) { \
2023 ID_DESC(name), \
2024 .set_user = set_id_reg, \
2025 .visibility = id_visibility, \
2026 .reset = kvm_read_sanitised_id_reg, \
2027 .val = 0, \
2028 }
2029
2030 /* sys_reg_desc initialiser for known cpufeature ID registers */
2031 #define AA32_ID_SANITISED(name) { \
2032 ID_DESC(name), \
2033 .set_user = set_id_reg, \
2034 .visibility = aa32_id_visibility, \
2035 .reset = kvm_read_sanitised_id_reg, \
2036 .val = 0, \
2037 }
2038
2039 /* sys_reg_desc initialiser for writable ID registers */
2040 #define ID_WRITABLE(name, mask) { \
2041 ID_DESC(name), \
2042 .set_user = set_id_reg, \
2043 .visibility = id_visibility, \
2044 .reset = kvm_read_sanitised_id_reg, \
2045 .val = mask, \
2046 }
2047
2048 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */
2049 #define ID_FILTERED(sysreg, name, mask) { \
2050 ID_DESC(sysreg), \
2051 .set_user = set_##name, \
2052 .visibility = id_visibility, \
2053 .reset = kvm_read_sanitised_id_reg, \
2054 .val = (mask), \
2055 }
2056
2057 /*
2058 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
2059 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
2060 * (1 <= crm < 8, 0 <= Op2 < 8).
2061 */
2062 #define ID_UNALLOCATED(crm, op2) { \
2063 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2064 .access = access_id_reg, \
2065 .get_user = get_id_reg, \
2066 .set_user = set_id_reg, \
2067 .visibility = raz_visibility, \
2068 .reset = kvm_read_sanitised_id_reg, \
2069 .val = 0, \
2070 }
2071
2072 /*
2073 * sys_reg_desc initialiser for known ID registers that we hide from guests.
2074 * For now, these are exposed just like unallocated ID regs: they appear
2075 * RAZ for the guest.
2076 */
2077 #define ID_HIDDEN(name) { \
2078 ID_DESC(name), \
2079 .set_user = set_id_reg, \
2080 .visibility = raz_visibility, \
2081 .reset = kvm_read_sanitised_id_reg, \
2082 .val = 0, \
2083 }
2084
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2085 static bool access_sp_el1(struct kvm_vcpu *vcpu,
2086 struct sys_reg_params *p,
2087 const struct sys_reg_desc *r)
2088 {
2089 if (p->is_write)
2090 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
2091 else
2092 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
2093
2094 return true;
2095 }
2096
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2097 static bool access_elr(struct kvm_vcpu *vcpu,
2098 struct sys_reg_params *p,
2099 const struct sys_reg_desc *r)
2100 {
2101 if (p->is_write)
2102 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
2103 else
2104 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
2105
2106 return true;
2107 }
2108
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2109 static bool access_spsr(struct kvm_vcpu *vcpu,
2110 struct sys_reg_params *p,
2111 const struct sys_reg_desc *r)
2112 {
2113 if (p->is_write)
2114 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
2115 else
2116 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
2117
2118 return true;
2119 }
2120
access_cntkctl_el12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2121 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu,
2122 struct sys_reg_params *p,
2123 const struct sys_reg_desc *r)
2124 {
2125 if (p->is_write)
2126 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval;
2127 else
2128 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);
2129
2130 return true;
2131 }
2132
reset_hcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2133 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2134 {
2135 u64 val = r->val;
2136
2137 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
2138 val |= HCR_E2H;
2139
2140 return __vcpu_sys_reg(vcpu, r->reg) = val;
2141 }
2142
sve_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2143 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu,
2144 const struct sys_reg_desc *rd)
2145 {
2146 unsigned int r;
2147
2148 r = el2_visibility(vcpu, rd);
2149 if (r)
2150 return r;
2151
2152 return sve_visibility(vcpu, rd);
2153 }
2154
access_zcr_el2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2155 static bool access_zcr_el2(struct kvm_vcpu *vcpu,
2156 struct sys_reg_params *p,
2157 const struct sys_reg_desc *r)
2158 {
2159 unsigned int vq;
2160
2161 if (guest_hyp_sve_traps_enabled(vcpu)) {
2162 kvm_inject_nested_sve_trap(vcpu);
2163 return true;
2164 }
2165
2166 if (!p->is_write) {
2167 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2);
2168 return true;
2169 }
2170
2171 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1;
2172 vq = min(vq, vcpu_sve_max_vq(vcpu));
2173 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2);
2174 return true;
2175 }
2176
s1poe_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2177 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu,
2178 const struct sys_reg_desc *rd)
2179 {
2180 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
2181 return 0;
2182
2183 return REG_HIDDEN;
2184 }
2185
2186 /*
2187 * Architected system registers.
2188 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2189 *
2190 * Debug handling: We do trap most, if not all debug related system
2191 * registers. The implementation is good enough to ensure that a guest
2192 * can use these with minimal performance degradation. The drawback is
2193 * that we don't implement any of the external debug architecture.
2194 * This should be revisited if we ever encounter a more demanding
2195 * guest...
2196 */
2197 static const struct sys_reg_desc sys_reg_descs[] = {
2198 DBG_BCR_BVR_WCR_WVR_EL1(0),
2199 DBG_BCR_BVR_WCR_WVR_EL1(1),
2200 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2201 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2202 DBG_BCR_BVR_WCR_WVR_EL1(2),
2203 DBG_BCR_BVR_WCR_WVR_EL1(3),
2204 DBG_BCR_BVR_WCR_WVR_EL1(4),
2205 DBG_BCR_BVR_WCR_WVR_EL1(5),
2206 DBG_BCR_BVR_WCR_WVR_EL1(6),
2207 DBG_BCR_BVR_WCR_WVR_EL1(7),
2208 DBG_BCR_BVR_WCR_WVR_EL1(8),
2209 DBG_BCR_BVR_WCR_WVR_EL1(9),
2210 DBG_BCR_BVR_WCR_WVR_EL1(10),
2211 DBG_BCR_BVR_WCR_WVR_EL1(11),
2212 DBG_BCR_BVR_WCR_WVR_EL1(12),
2213 DBG_BCR_BVR_WCR_WVR_EL1(13),
2214 DBG_BCR_BVR_WCR_WVR_EL1(14),
2215 DBG_BCR_BVR_WCR_WVR_EL1(15),
2216
2217 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
2218 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
2219 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2220 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
2221 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
2222 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
2223 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
2224 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
2225 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
2226
2227 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
2228 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
2229 // DBGDTR[TR]X_EL0 share the same encoding
2230 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
2231
2232 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
2233
2234 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
2235
2236 /*
2237 * ID regs: all ID_SANITISED() entries here must have corresponding
2238 * entries in arm64_ftr_regs[].
2239 */
2240
2241 /* AArch64 mappings of the AArch32 ID registers */
2242 /* CRm=1 */
2243 AA32_ID_SANITISED(ID_PFR0_EL1),
2244 AA32_ID_SANITISED(ID_PFR1_EL1),
2245 { SYS_DESC(SYS_ID_DFR0_EL1),
2246 .access = access_id_reg,
2247 .get_user = get_id_reg,
2248 .set_user = set_id_dfr0_el1,
2249 .visibility = aa32_id_visibility,
2250 .reset = read_sanitised_id_dfr0_el1,
2251 .val = ID_DFR0_EL1_PerfMon_MASK |
2252 ID_DFR0_EL1_CopDbg_MASK, },
2253 ID_HIDDEN(ID_AFR0_EL1),
2254 AA32_ID_SANITISED(ID_MMFR0_EL1),
2255 AA32_ID_SANITISED(ID_MMFR1_EL1),
2256 AA32_ID_SANITISED(ID_MMFR2_EL1),
2257 AA32_ID_SANITISED(ID_MMFR3_EL1),
2258
2259 /* CRm=2 */
2260 AA32_ID_SANITISED(ID_ISAR0_EL1),
2261 AA32_ID_SANITISED(ID_ISAR1_EL1),
2262 AA32_ID_SANITISED(ID_ISAR2_EL1),
2263 AA32_ID_SANITISED(ID_ISAR3_EL1),
2264 AA32_ID_SANITISED(ID_ISAR4_EL1),
2265 AA32_ID_SANITISED(ID_ISAR5_EL1),
2266 AA32_ID_SANITISED(ID_MMFR4_EL1),
2267 AA32_ID_SANITISED(ID_ISAR6_EL1),
2268
2269 /* CRm=3 */
2270 AA32_ID_SANITISED(MVFR0_EL1),
2271 AA32_ID_SANITISED(MVFR1_EL1),
2272 AA32_ID_SANITISED(MVFR2_EL1),
2273 ID_UNALLOCATED(3,3),
2274 AA32_ID_SANITISED(ID_PFR2_EL1),
2275 ID_HIDDEN(ID_DFR1_EL1),
2276 AA32_ID_SANITISED(ID_MMFR5_EL1),
2277 ID_UNALLOCATED(3,7),
2278
2279 /* AArch64 ID registers */
2280 /* CRm=4 */
2281 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1,
2282 ~(ID_AA64PFR0_EL1_AMU |
2283 ID_AA64PFR0_EL1_MPAM |
2284 ID_AA64PFR0_EL1_SVE |
2285 ID_AA64PFR0_EL1_RAS |
2286 ID_AA64PFR0_EL1_AdvSIMD |
2287 ID_AA64PFR0_EL1_FP)),
2288 { SYS_DESC(SYS_ID_AA64PFR1_EL1),
2289 .access = access_id_reg,
2290 .get_user = get_id_reg,
2291 .set_user = set_id_aa64pfr1_el1,
2292 .reset = kvm_read_sanitised_id_reg,
2293 .val = ~(ID_AA64PFR1_EL1_PFAR |
2294 ID_AA64PFR1_EL1_DF2 |
2295 ID_AA64PFR1_EL1_MTEX |
2296 ID_AA64PFR1_EL1_THE |
2297 ID_AA64PFR1_EL1_GCS |
2298 ID_AA64PFR1_EL1_MTE_frac |
2299 ID_AA64PFR1_EL1_NMI |
2300 ID_AA64PFR1_EL1_RNDR_trap |
2301 ID_AA64PFR1_EL1_SME |
2302 ID_AA64PFR1_EL1_RES0 |
2303 ID_AA64PFR1_EL1_MPAM_frac |
2304 ID_AA64PFR1_EL1_RAS_frac |
2305 ID_AA64PFR1_EL1_MTE), },
2306 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
2307 ID_UNALLOCATED(4,3),
2308 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
2309 ID_HIDDEN(ID_AA64SMFR0_EL1),
2310 ID_UNALLOCATED(4,6),
2311 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0),
2312
2313 /* CRm=5 */
2314 /*
2315 * Prior to FEAT_Debugv8.9, the architecture defines context-aware
2316 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs).
2317 * KVM does not trap + emulate the breakpoint registers, and as such
2318 * cannot support a layout that misaligns with the underlying hardware.
2319 * While it may be possible to describe a subset that aligns with
2320 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for
2321 * simplicity.
2322 *
2323 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking
2324 * of breakpoints for more details.
2325 */
2326 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1,
2327 ID_AA64DFR0_EL1_DoubleLock_MASK |
2328 ID_AA64DFR0_EL1_WRPs_MASK |
2329 ID_AA64DFR0_EL1_PMUVer_MASK |
2330 ID_AA64DFR0_EL1_DebugVer_MASK),
2331 ID_SANITISED(ID_AA64DFR1_EL1),
2332 ID_UNALLOCATED(5,2),
2333 ID_UNALLOCATED(5,3),
2334 ID_HIDDEN(ID_AA64AFR0_EL1),
2335 ID_HIDDEN(ID_AA64AFR1_EL1),
2336 ID_UNALLOCATED(5,6),
2337 ID_UNALLOCATED(5,7),
2338
2339 /* CRm=6 */
2340 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
2341 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
2342 ID_AA64ISAR1_EL1_GPA |
2343 ID_AA64ISAR1_EL1_API |
2344 ID_AA64ISAR1_EL1_APA)),
2345 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
2346 ID_AA64ISAR2_EL1_APA3 |
2347 ID_AA64ISAR2_EL1_GPA3)),
2348 ID_UNALLOCATED(6,3),
2349 ID_UNALLOCATED(6,4),
2350 ID_UNALLOCATED(6,5),
2351 ID_UNALLOCATED(6,6),
2352 ID_UNALLOCATED(6,7),
2353
2354 /* CRm=7 */
2355 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |
2356 ID_AA64MMFR0_EL1_TGRAN4_2 |
2357 ID_AA64MMFR0_EL1_TGRAN64_2 |
2358 ID_AA64MMFR0_EL1_TGRAN16_2 |
2359 ID_AA64MMFR0_EL1_ASIDBITS)),
2360 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
2361 ID_AA64MMFR1_EL1_HCX |
2362 ID_AA64MMFR1_EL1_TWED |
2363 ID_AA64MMFR1_EL1_XNX |
2364 ID_AA64MMFR1_EL1_VH |
2365 ID_AA64MMFR1_EL1_VMIDBits)),
2366 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
2367 ID_AA64MMFR2_EL1_EVT |
2368 ID_AA64MMFR2_EL1_FWB |
2369 ID_AA64MMFR2_EL1_IDS |
2370 ID_AA64MMFR2_EL1_NV |
2371 ID_AA64MMFR2_EL1_CCIDX)),
2372 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX |
2373 ID_AA64MMFR3_EL1_S1PIE |
2374 ID_AA64MMFR3_EL1_S1POE)),
2375 ID_SANITISED(ID_AA64MMFR4_EL1),
2376 ID_UNALLOCATED(7,5),
2377 ID_UNALLOCATED(7,6),
2378 ID_UNALLOCATED(7,7),
2379
2380 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2381 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2382 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2383
2384 MTE_REG(RGSR_EL1),
2385 MTE_REG(GCR_EL1),
2386
2387 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2388 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2389 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2390 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2391 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2392 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2393 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2394 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2395
2396 PTRAUTH_KEY(APIA),
2397 PTRAUTH_KEY(APIB),
2398 PTRAUTH_KEY(APDA),
2399 PTRAUTH_KEY(APDB),
2400 PTRAUTH_KEY(APGA),
2401
2402 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2403 { SYS_DESC(SYS_ELR_EL1), access_elr},
2404
2405 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
2406
2407 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2408 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2409 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2410
2411 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2412 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2413 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2414 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2415 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2416 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2417 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2418 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2419
2420 MTE_REG(TFSR_EL1),
2421 MTE_REG(TFSRE0_EL1),
2422
2423 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2424 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2425
2426 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2427 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2428 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2429 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2430 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2431 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2432 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2433 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2434 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2435 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2436 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2437 /* PMBIDR_EL1 is not trapped */
2438
2439 { PMU_SYS_REG(PMINTENSET_EL1),
2440 .access = access_pminten, .reg = PMINTENSET_EL1,
2441 .get_user = get_pmreg, .set_user = set_pmreg },
2442 { PMU_SYS_REG(PMINTENCLR_EL1),
2443 .access = access_pminten, .reg = PMINTENSET_EL1,
2444 .get_user = get_pmreg, .set_user = set_pmreg },
2445 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2446
2447 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2448 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 },
2449 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 },
2450 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1,
2451 .visibility = s1poe_visibility },
2452 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2453
2454 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2455 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2456 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2457 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2458 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access },
2459 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
2460
2461 { SYS_DESC(SYS_MPAM1_EL1), undef_access },
2462 { SYS_DESC(SYS_MPAM0_EL1), undef_access },
2463 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2464 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2465
2466 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
2467 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
2468 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
2469 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
2470 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
2471 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
2472 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
2473 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
2474 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
2475 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
2476 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
2477 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
2478 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
2479 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
2480 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2481 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2482 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2483 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
2484 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
2485 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
2486 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
2487 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
2488 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2489 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
2490 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
2491
2492 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2493 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2494
2495 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2496
2497 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2498
2499 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2500
2501 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2502 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2503 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 },
2504 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2505 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2506 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2507 ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK |
2508 CTR_EL0_IDC_MASK |
2509 CTR_EL0_DminLine_MASK |
2510 CTR_EL0_IminLine_MASK),
2511 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
2512 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
2513
2514 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
2515 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
2516 { PMU_SYS_REG(PMCNTENSET_EL0),
2517 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2518 .get_user = get_pmreg, .set_user = set_pmreg },
2519 { PMU_SYS_REG(PMCNTENCLR_EL0),
2520 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2521 .get_user = get_pmreg, .set_user = set_pmreg },
2522 { PMU_SYS_REG(PMOVSCLR_EL0),
2523 .access = access_pmovs, .reg = PMOVSSET_EL0,
2524 .get_user = get_pmreg, .set_user = set_pmreg },
2525 /*
2526 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2527 * previously (and pointlessly) advertised in the past...
2528 */
2529 { PMU_SYS_REG(PMSWINC_EL0),
2530 .get_user = get_raz_reg, .set_user = set_wi_reg,
2531 .access = access_pmswinc, .reset = NULL },
2532 { PMU_SYS_REG(PMSELR_EL0),
2533 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2534 { PMU_SYS_REG(PMCEID0_EL0),
2535 .access = access_pmceid, .reset = NULL },
2536 { PMU_SYS_REG(PMCEID1_EL0),
2537 .access = access_pmceid, .reset = NULL },
2538 { PMU_SYS_REG(PMCCNTR_EL0),
2539 .access = access_pmu_evcntr, .reset = reset_unknown,
2540 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2541 { PMU_SYS_REG(PMXEVTYPER_EL0),
2542 .access = access_pmu_evtyper, .reset = NULL },
2543 { PMU_SYS_REG(PMXEVCNTR_EL0),
2544 .access = access_pmu_evcntr, .reset = NULL },
2545 /*
2546 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2547 * in 32bit mode. Here we choose to reset it as zero for consistency.
2548 */
2549 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2550 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2551 { PMU_SYS_REG(PMOVSSET_EL0),
2552 .access = access_pmovs, .reg = PMOVSSET_EL0,
2553 .get_user = get_pmreg, .set_user = set_pmreg },
2554
2555 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0,
2556 .visibility = s1poe_visibility },
2557 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2558 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2559 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2560
2561 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2562
2563 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2564 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2565 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2566 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2567 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2568 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2569 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2570 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2571 AMU_AMEVCNTR0_EL0(0),
2572 AMU_AMEVCNTR0_EL0(1),
2573 AMU_AMEVCNTR0_EL0(2),
2574 AMU_AMEVCNTR0_EL0(3),
2575 AMU_AMEVCNTR0_EL0(4),
2576 AMU_AMEVCNTR0_EL0(5),
2577 AMU_AMEVCNTR0_EL0(6),
2578 AMU_AMEVCNTR0_EL0(7),
2579 AMU_AMEVCNTR0_EL0(8),
2580 AMU_AMEVCNTR0_EL0(9),
2581 AMU_AMEVCNTR0_EL0(10),
2582 AMU_AMEVCNTR0_EL0(11),
2583 AMU_AMEVCNTR0_EL0(12),
2584 AMU_AMEVCNTR0_EL0(13),
2585 AMU_AMEVCNTR0_EL0(14),
2586 AMU_AMEVCNTR0_EL0(15),
2587 AMU_AMEVTYPER0_EL0(0),
2588 AMU_AMEVTYPER0_EL0(1),
2589 AMU_AMEVTYPER0_EL0(2),
2590 AMU_AMEVTYPER0_EL0(3),
2591 AMU_AMEVTYPER0_EL0(4),
2592 AMU_AMEVTYPER0_EL0(5),
2593 AMU_AMEVTYPER0_EL0(6),
2594 AMU_AMEVTYPER0_EL0(7),
2595 AMU_AMEVTYPER0_EL0(8),
2596 AMU_AMEVTYPER0_EL0(9),
2597 AMU_AMEVTYPER0_EL0(10),
2598 AMU_AMEVTYPER0_EL0(11),
2599 AMU_AMEVTYPER0_EL0(12),
2600 AMU_AMEVTYPER0_EL0(13),
2601 AMU_AMEVTYPER0_EL0(14),
2602 AMU_AMEVTYPER0_EL0(15),
2603 AMU_AMEVCNTR1_EL0(0),
2604 AMU_AMEVCNTR1_EL0(1),
2605 AMU_AMEVCNTR1_EL0(2),
2606 AMU_AMEVCNTR1_EL0(3),
2607 AMU_AMEVCNTR1_EL0(4),
2608 AMU_AMEVCNTR1_EL0(5),
2609 AMU_AMEVCNTR1_EL0(6),
2610 AMU_AMEVCNTR1_EL0(7),
2611 AMU_AMEVCNTR1_EL0(8),
2612 AMU_AMEVCNTR1_EL0(9),
2613 AMU_AMEVCNTR1_EL0(10),
2614 AMU_AMEVCNTR1_EL0(11),
2615 AMU_AMEVCNTR1_EL0(12),
2616 AMU_AMEVCNTR1_EL0(13),
2617 AMU_AMEVCNTR1_EL0(14),
2618 AMU_AMEVCNTR1_EL0(15),
2619 AMU_AMEVTYPER1_EL0(0),
2620 AMU_AMEVTYPER1_EL0(1),
2621 AMU_AMEVTYPER1_EL0(2),
2622 AMU_AMEVTYPER1_EL0(3),
2623 AMU_AMEVTYPER1_EL0(4),
2624 AMU_AMEVTYPER1_EL0(5),
2625 AMU_AMEVTYPER1_EL0(6),
2626 AMU_AMEVTYPER1_EL0(7),
2627 AMU_AMEVTYPER1_EL0(8),
2628 AMU_AMEVTYPER1_EL0(9),
2629 AMU_AMEVTYPER1_EL0(10),
2630 AMU_AMEVTYPER1_EL0(11),
2631 AMU_AMEVTYPER1_EL0(12),
2632 AMU_AMEVTYPER1_EL0(13),
2633 AMU_AMEVTYPER1_EL0(14),
2634 AMU_AMEVTYPER1_EL0(15),
2635
2636 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2637 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
2638 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2639 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2640 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
2641
2642 /* PMEVCNTRn_EL0 */
2643 PMU_PMEVCNTR_EL0(0),
2644 PMU_PMEVCNTR_EL0(1),
2645 PMU_PMEVCNTR_EL0(2),
2646 PMU_PMEVCNTR_EL0(3),
2647 PMU_PMEVCNTR_EL0(4),
2648 PMU_PMEVCNTR_EL0(5),
2649 PMU_PMEVCNTR_EL0(6),
2650 PMU_PMEVCNTR_EL0(7),
2651 PMU_PMEVCNTR_EL0(8),
2652 PMU_PMEVCNTR_EL0(9),
2653 PMU_PMEVCNTR_EL0(10),
2654 PMU_PMEVCNTR_EL0(11),
2655 PMU_PMEVCNTR_EL0(12),
2656 PMU_PMEVCNTR_EL0(13),
2657 PMU_PMEVCNTR_EL0(14),
2658 PMU_PMEVCNTR_EL0(15),
2659 PMU_PMEVCNTR_EL0(16),
2660 PMU_PMEVCNTR_EL0(17),
2661 PMU_PMEVCNTR_EL0(18),
2662 PMU_PMEVCNTR_EL0(19),
2663 PMU_PMEVCNTR_EL0(20),
2664 PMU_PMEVCNTR_EL0(21),
2665 PMU_PMEVCNTR_EL0(22),
2666 PMU_PMEVCNTR_EL0(23),
2667 PMU_PMEVCNTR_EL0(24),
2668 PMU_PMEVCNTR_EL0(25),
2669 PMU_PMEVCNTR_EL0(26),
2670 PMU_PMEVCNTR_EL0(27),
2671 PMU_PMEVCNTR_EL0(28),
2672 PMU_PMEVCNTR_EL0(29),
2673 PMU_PMEVCNTR_EL0(30),
2674 /* PMEVTYPERn_EL0 */
2675 PMU_PMEVTYPER_EL0(0),
2676 PMU_PMEVTYPER_EL0(1),
2677 PMU_PMEVTYPER_EL0(2),
2678 PMU_PMEVTYPER_EL0(3),
2679 PMU_PMEVTYPER_EL0(4),
2680 PMU_PMEVTYPER_EL0(5),
2681 PMU_PMEVTYPER_EL0(6),
2682 PMU_PMEVTYPER_EL0(7),
2683 PMU_PMEVTYPER_EL0(8),
2684 PMU_PMEVTYPER_EL0(9),
2685 PMU_PMEVTYPER_EL0(10),
2686 PMU_PMEVTYPER_EL0(11),
2687 PMU_PMEVTYPER_EL0(12),
2688 PMU_PMEVTYPER_EL0(13),
2689 PMU_PMEVTYPER_EL0(14),
2690 PMU_PMEVTYPER_EL0(15),
2691 PMU_PMEVTYPER_EL0(16),
2692 PMU_PMEVTYPER_EL0(17),
2693 PMU_PMEVTYPER_EL0(18),
2694 PMU_PMEVTYPER_EL0(19),
2695 PMU_PMEVTYPER_EL0(20),
2696 PMU_PMEVTYPER_EL0(21),
2697 PMU_PMEVTYPER_EL0(22),
2698 PMU_PMEVTYPER_EL0(23),
2699 PMU_PMEVTYPER_EL0(24),
2700 PMU_PMEVTYPER_EL0(25),
2701 PMU_PMEVTYPER_EL0(26),
2702 PMU_PMEVTYPER_EL0(27),
2703 PMU_PMEVTYPER_EL0(28),
2704 PMU_PMEVTYPER_EL0(29),
2705 PMU_PMEVTYPER_EL0(30),
2706 /*
2707 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
2708 * in 32bit mode. Here we choose to reset it as zero for consistency.
2709 */
2710 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
2711 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2712
2713 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0),
2714 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0),
2715 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2716 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2717 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),
2718 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2719 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2720 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
2721 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
2722 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0),
2723 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
2724 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
2725
2726 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val,
2727 .visibility = sve_el2_visibility, .reg = ZCR_EL2 },
2728
2729 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
2730
2731 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2732 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2733 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2734 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
2735 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
2736
2737 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
2738 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
2739 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
2740 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
2741 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
2742 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
2743 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
2744
2745 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
2746 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi },
2747 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi },
2748 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi },
2749 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi },
2750
2751 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },
2752 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2753 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2754 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
2755 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
2756
2757 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
2758 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2759
2760 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2761 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2762 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access },
2763 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },
2764 { SYS_DESC(SYS_MPAM2_EL2), undef_access },
2765 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },
2766 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },
2767 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },
2768 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },
2769 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },
2770 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },
2771 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },
2772 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },
2773
2774 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2775 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2776 { SYS_DESC(SYS_RMR_EL2), undef_access },
2777
2778 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0),
2779
2780 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2781 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2782
2783 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
2784 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2785
2786 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 },
2787
2788 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
2789 };
2790
handle_at_s1e01(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2791 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2792 const struct sys_reg_desc *r)
2793 {
2794 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2795
2796 __kvm_at_s1e01(vcpu, op, p->regval);
2797
2798 return true;
2799 }
2800
handle_at_s1e2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2801 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2802 const struct sys_reg_desc *r)
2803 {
2804 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2805
2806 /* There is no FGT associated with AT S1E2A :-( */
2807 if (op == OP_AT_S1E2A &&
2808 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) {
2809 kvm_inject_undefined(vcpu);
2810 return false;
2811 }
2812
2813 __kvm_at_s1e2(vcpu, op, p->regval);
2814
2815 return true;
2816 }
2817
handle_at_s12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2818 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2819 const struct sys_reg_desc *r)
2820 {
2821 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2822
2823 __kvm_at_s12(vcpu, op, p->regval);
2824
2825 return true;
2826 }
2827
kvm_supported_tlbi_s12_op(struct kvm_vcpu * vpcu,u32 instr)2828 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr)
2829 {
2830 struct kvm *kvm = vpcu->kvm;
2831 u8 CRm = sys_reg_CRm(instr);
2832
2833 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
2834 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
2835 return false;
2836
2837 if (CRm == TLBI_CRm_nROS &&
2838 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
2839 return false;
2840
2841 return true;
2842 }
2843
handle_alle1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2844 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2845 const struct sys_reg_desc *r)
2846 {
2847 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2848
2849 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
2850 return undef_access(vcpu, p, r);
2851
2852 write_lock(&vcpu->kvm->mmu_lock);
2853
2854 /*
2855 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the
2856 * corresponding VMIDs.
2857 */
2858 kvm_nested_s2_unmap(vcpu->kvm, true);
2859
2860 write_unlock(&vcpu->kvm->mmu_lock);
2861
2862 return true;
2863 }
2864
kvm_supported_tlbi_ipas2_op(struct kvm_vcpu * vpcu,u32 instr)2865 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr)
2866 {
2867 struct kvm *kvm = vpcu->kvm;
2868 u8 CRm = sys_reg_CRm(instr);
2869 u8 Op2 = sys_reg_Op2(instr);
2870
2871 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
2872 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
2873 return false;
2874
2875 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&
2876 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
2877 return false;
2878
2879 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&
2880 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
2881 return false;
2882
2883 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&
2884 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
2885 return false;
2886
2887 return true;
2888 }
2889
2890 /* Only defined here as this is an internal "abstraction" */
2891 union tlbi_info {
2892 struct {
2893 u64 start;
2894 u64 size;
2895 } range;
2896
2897 struct {
2898 u64 addr;
2899 } ipa;
2900
2901 struct {
2902 u64 addr;
2903 u32 encoding;
2904 } va;
2905 };
2906
s2_mmu_unmap_range(struct kvm_s2_mmu * mmu,const union tlbi_info * info)2907 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu,
2908 const union tlbi_info *info)
2909 {
2910 /*
2911 * The unmap operation is allowed to drop the MMU lock and block, which
2912 * means that @mmu could be used for a different context than the one
2913 * currently being invalidated.
2914 *
2915 * This behavior is still safe, as:
2916 *
2917 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating
2918 * the entire MMU before reusing it, which still honors the intent
2919 * of a TLBI.
2920 *
2921 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC
2922 * and ERET to the guest), other vCPUs are allowed to use stale
2923 * translations.
2924 *
2925 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and
2926 * at worst may cause more aborts for shadow stage-2 fills.
2927 *
2928 * Dropping the MMU lock also implies that shadow stage-2 fills could
2929 * happen behind the back of the TLBI. This is still safe, though, as
2930 * the L1 needs to put its stage-2 in a consistent state before doing
2931 * the TLBI.
2932 */
2933 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true);
2934 }
2935
handle_vmalls12e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2936 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2937 const struct sys_reg_desc *r)
2938 {
2939 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2940 u64 limit, vttbr;
2941
2942 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
2943 return undef_access(vcpu, p, r);
2944
2945 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
2946 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm));
2947
2948 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
2949 &(union tlbi_info) {
2950 .range = {
2951 .start = 0,
2952 .size = limit,
2953 },
2954 },
2955 s2_mmu_unmap_range);
2956
2957 return true;
2958 }
2959
handle_ripas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2960 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2961 const struct sys_reg_desc *r)
2962 {
2963 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2964 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
2965 u64 base, range, tg, num, scale;
2966 int shift;
2967
2968 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
2969 return undef_access(vcpu, p, r);
2970
2971 /*
2972 * Because the shadow S2 structure doesn't necessarily reflect that
2973 * of the guest's S2 (different base granule size, for example), we
2974 * decide to ignore TTL and only use the described range.
2975 */
2976 tg = FIELD_GET(GENMASK(47, 46), p->regval);
2977 scale = FIELD_GET(GENMASK(45, 44), p->regval);
2978 num = FIELD_GET(GENMASK(43, 39), p->regval);
2979 base = p->regval & GENMASK(36, 0);
2980
2981 switch(tg) {
2982 case 1:
2983 shift = 12;
2984 break;
2985 case 2:
2986 shift = 14;
2987 break;
2988 case 3:
2989 default: /* IMPDEF: handle tg==0 as 64k */
2990 shift = 16;
2991 break;
2992 }
2993
2994 base <<= shift;
2995 range = __TLBI_RANGE_PAGES(num, scale) << shift;
2996
2997 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
2998 &(union tlbi_info) {
2999 .range = {
3000 .start = base,
3001 .size = range,
3002 },
3003 },
3004 s2_mmu_unmap_range);
3005
3006 return true;
3007 }
3008
s2_mmu_unmap_ipa(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3009 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu,
3010 const union tlbi_info *info)
3011 {
3012 unsigned long max_size;
3013 u64 base_addr;
3014
3015 /*
3016 * We drop a number of things from the supplied value:
3017 *
3018 * - NS bit: we're non-secure only.
3019 *
3020 * - IPA[51:48]: We don't support 52bit IPA just yet...
3021 *
3022 * And of course, adjust the IPA to be on an actual address.
3023 */
3024 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;
3025 max_size = compute_tlb_inval_range(mmu, info->ipa.addr);
3026 base_addr &= ~(max_size - 1);
3027
3028 /*
3029 * See comment in s2_mmu_unmap_range() for why this is allowed to
3030 * reschedule.
3031 */
3032 kvm_stage2_unmap_range(mmu, base_addr, max_size, true);
3033 }
3034
handle_ipas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3035 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3036 const struct sys_reg_desc *r)
3037 {
3038 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3039 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3040
3041 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
3042 return undef_access(vcpu, p, r);
3043
3044 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3045 &(union tlbi_info) {
3046 .ipa = {
3047 .addr = p->regval,
3048 },
3049 },
3050 s2_mmu_unmap_ipa);
3051
3052 return true;
3053 }
3054
s2_mmu_tlbi_s1e1(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3055 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu,
3056 const union tlbi_info *info)
3057 {
3058 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding));
3059 }
3060
handle_tlbi_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3061 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3062 const struct sys_reg_desc *r)
3063 {
3064 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3065 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3066
3067 /*
3068 * If we're here, this is because we've trapped on a EL1 TLBI
3069 * instruction that affects the EL1 translation regime while
3070 * we're running in a context that doesn't allow us to let the
3071 * HW do its thing (aka vEL2):
3072 *
3073 * - HCR_EL2.E2H == 0 : a non-VHE guest
3074 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode
3075 *
3076 * We don't expect these helpers to ever be called when running
3077 * in a vEL1 context.
3078 */
3079
3080 WARN_ON(!vcpu_is_el2(vcpu));
3081
3082 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding))
3083 return undef_access(vcpu, p, r);
3084
3085 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3086 &(union tlbi_info) {
3087 .va = {
3088 .addr = p->regval,
3089 .encoding = sys_encoding,
3090 },
3091 },
3092 s2_mmu_tlbi_s1e1);
3093
3094 return true;
3095 }
3096
3097 #define SYS_INSN(insn, access_fn) \
3098 { \
3099 SYS_DESC(OP_##insn), \
3100 .access = (access_fn), \
3101 }
3102
3103 static struct sys_reg_desc sys_insn_descs[] = {
3104 { SYS_DESC(SYS_DC_ISW), access_dcsw },
3105 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
3106 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
3107
3108 SYS_INSN(AT_S1E1R, handle_at_s1e01),
3109 SYS_INSN(AT_S1E1W, handle_at_s1e01),
3110 SYS_INSN(AT_S1E0R, handle_at_s1e01),
3111 SYS_INSN(AT_S1E0W, handle_at_s1e01),
3112 SYS_INSN(AT_S1E1RP, handle_at_s1e01),
3113 SYS_INSN(AT_S1E1WP, handle_at_s1e01),
3114
3115 { SYS_DESC(SYS_DC_CSW), access_dcsw },
3116 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
3117 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
3118 { SYS_DESC(SYS_DC_CISW), access_dcsw },
3119 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
3120 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
3121
3122 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1),
3123 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1),
3124 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1),
3125 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1),
3126 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1),
3127 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1),
3128
3129 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1),
3130 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1),
3131 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1),
3132 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1),
3133
3134 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1),
3135 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1),
3136 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1),
3137 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1),
3138 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1),
3139 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1),
3140
3141 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1),
3142 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1),
3143 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1),
3144 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1),
3145
3146 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1),
3147 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1),
3148 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1),
3149 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1),
3150
3151 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1),
3152 SYS_INSN(TLBI_VAE1, handle_tlbi_el1),
3153 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1),
3154 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1),
3155 SYS_INSN(TLBI_VALE1, handle_tlbi_el1),
3156 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1),
3157
3158 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1),
3159 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1),
3160 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1),
3161 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1),
3162 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1),
3163 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1),
3164
3165 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1),
3166 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1),
3167 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1),
3168 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1),
3169
3170 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1),
3171 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1),
3172 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1),
3173 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1),
3174 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1),
3175 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1),
3176
3177 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1),
3178 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1),
3179 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1),
3180 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1),
3181
3182 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1),
3183 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1),
3184 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1),
3185 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1),
3186
3187 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1),
3188 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1),
3189 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1),
3190 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1),
3191 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1),
3192 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1),
3193
3194 SYS_INSN(AT_S1E2R, handle_at_s1e2),
3195 SYS_INSN(AT_S1E2W, handle_at_s1e2),
3196 SYS_INSN(AT_S12E1R, handle_at_s12),
3197 SYS_INSN(AT_S12E1W, handle_at_s12),
3198 SYS_INSN(AT_S12E0R, handle_at_s12),
3199 SYS_INSN(AT_S12E0W, handle_at_s12),
3200 SYS_INSN(AT_S1E2A, handle_at_s1e2),
3201
3202 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),
3203 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is),
3204 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is),
3205 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is),
3206
3207 SYS_INSN(TLBI_ALLE2OS, undef_access),
3208 SYS_INSN(TLBI_VAE2OS, undef_access),
3209 SYS_INSN(TLBI_ALLE1OS, handle_alle1is),
3210 SYS_INSN(TLBI_VALE2OS, undef_access),
3211 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is),
3212
3213 SYS_INSN(TLBI_RVAE2IS, undef_access),
3214 SYS_INSN(TLBI_RVALE2IS, undef_access),
3215
3216 SYS_INSN(TLBI_ALLE1IS, handle_alle1is),
3217 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is),
3218 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is),
3219 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is),
3220 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is),
3221 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is),
3222 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is),
3223 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is),
3224 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is),
3225 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is),
3226 SYS_INSN(TLBI_RVAE2OS, undef_access),
3227 SYS_INSN(TLBI_RVALE2OS, undef_access),
3228 SYS_INSN(TLBI_RVAE2, undef_access),
3229 SYS_INSN(TLBI_RVALE2, undef_access),
3230 SYS_INSN(TLBI_ALLE1, handle_alle1is),
3231 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is),
3232
3233 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is),
3234 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is),
3235 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is),
3236 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is),
3237
3238 SYS_INSN(TLBI_ALLE2OSNXS, undef_access),
3239 SYS_INSN(TLBI_VAE2OSNXS, undef_access),
3240 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is),
3241 SYS_INSN(TLBI_VALE2OSNXS, undef_access),
3242 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is),
3243
3244 SYS_INSN(TLBI_RVAE2ISNXS, undef_access),
3245 SYS_INSN(TLBI_RVALE2ISNXS, undef_access),
3246 SYS_INSN(TLBI_ALLE2ISNXS, undef_access),
3247 SYS_INSN(TLBI_VAE2ISNXS, undef_access),
3248
3249 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is),
3250 SYS_INSN(TLBI_VALE2ISNXS, undef_access),
3251 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is),
3252 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is),
3253 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is),
3254 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is),
3255 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is),
3256 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is),
3257 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is),
3258 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is),
3259 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is),
3260 SYS_INSN(TLBI_RVAE2OSNXS, undef_access),
3261 SYS_INSN(TLBI_RVALE2OSNXS, undef_access),
3262 SYS_INSN(TLBI_RVAE2NXS, undef_access),
3263 SYS_INSN(TLBI_RVALE2NXS, undef_access),
3264 SYS_INSN(TLBI_ALLE2NXS, undef_access),
3265 SYS_INSN(TLBI_VAE2NXS, undef_access),
3266 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is),
3267 SYS_INSN(TLBI_VALE2NXS, undef_access),
3268 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is),
3269 };
3270
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3271 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
3272 struct sys_reg_params *p,
3273 const struct sys_reg_desc *r)
3274 {
3275 if (p->is_write) {
3276 return ignore_write(vcpu, p);
3277 } else {
3278 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1);
3279 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP);
3280
3281 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |
3282 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) |
3283 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) |
3284 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) |
3285 (1 << 15) | (el3 << 14) | (el3 << 12));
3286 return true;
3287 }
3288 }
3289
3290 /*
3291 * AArch32 debug register mappings
3292 *
3293 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
3294 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
3295 *
3296 * None of the other registers share their location, so treat them as
3297 * if they were 64bit.
3298 */
3299 #define DBG_BCR_BVR_WCR_WVR(n) \
3300 /* DBGBVRn */ \
3301 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
3302 /* DBGBCRn */ \
3303 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
3304 /* DBGWVRn */ \
3305 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
3306 /* DBGWCRn */ \
3307 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
3308
3309 #define DBGBXVR(n) \
3310 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
3311
3312 /*
3313 * Trapped cp14 registers. We generally ignore most of the external
3314 * debug, on the principle that they don't really make sense to a
3315 * guest. Revisit this one day, would this principle change.
3316 */
3317 static const struct sys_reg_desc cp14_regs[] = {
3318 /* DBGDIDR */
3319 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
3320 /* DBGDTRRXext */
3321 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
3322
3323 DBG_BCR_BVR_WCR_WVR(0),
3324 /* DBGDSCRint */
3325 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
3326 DBG_BCR_BVR_WCR_WVR(1),
3327 /* DBGDCCINT */
3328 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
3329 /* DBGDSCRext */
3330 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
3331 DBG_BCR_BVR_WCR_WVR(2),
3332 /* DBGDTR[RT]Xint */
3333 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
3334 /* DBGDTR[RT]Xext */
3335 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
3336 DBG_BCR_BVR_WCR_WVR(3),
3337 DBG_BCR_BVR_WCR_WVR(4),
3338 DBG_BCR_BVR_WCR_WVR(5),
3339 /* DBGWFAR */
3340 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
3341 /* DBGOSECCR */
3342 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
3343 DBG_BCR_BVR_WCR_WVR(6),
3344 /* DBGVCR */
3345 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
3346 DBG_BCR_BVR_WCR_WVR(7),
3347 DBG_BCR_BVR_WCR_WVR(8),
3348 DBG_BCR_BVR_WCR_WVR(9),
3349 DBG_BCR_BVR_WCR_WVR(10),
3350 DBG_BCR_BVR_WCR_WVR(11),
3351 DBG_BCR_BVR_WCR_WVR(12),
3352 DBG_BCR_BVR_WCR_WVR(13),
3353 DBG_BCR_BVR_WCR_WVR(14),
3354 DBG_BCR_BVR_WCR_WVR(15),
3355
3356 /* DBGDRAR (32bit) */
3357 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
3358
3359 DBGBXVR(0),
3360 /* DBGOSLAR */
3361 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
3362 DBGBXVR(1),
3363 /* DBGOSLSR */
3364 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
3365 DBGBXVR(2),
3366 DBGBXVR(3),
3367 /* DBGOSDLR */
3368 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
3369 DBGBXVR(4),
3370 /* DBGPRCR */
3371 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
3372 DBGBXVR(5),
3373 DBGBXVR(6),
3374 DBGBXVR(7),
3375 DBGBXVR(8),
3376 DBGBXVR(9),
3377 DBGBXVR(10),
3378 DBGBXVR(11),
3379 DBGBXVR(12),
3380 DBGBXVR(13),
3381 DBGBXVR(14),
3382 DBGBXVR(15),
3383
3384 /* DBGDSAR (32bit) */
3385 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
3386
3387 /* DBGDEVID2 */
3388 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
3389 /* DBGDEVID1 */
3390 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
3391 /* DBGDEVID */
3392 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
3393 /* DBGCLAIMSET */
3394 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
3395 /* DBGCLAIMCLR */
3396 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
3397 /* DBGAUTHSTATUS */
3398 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
3399 };
3400
3401 /* Trapped cp14 64bit registers */
3402 static const struct sys_reg_desc cp14_64_regs[] = {
3403 /* DBGDRAR (64bit) */
3404 { Op1( 0), CRm( 1), .access = trap_raz_wi },
3405
3406 /* DBGDSAR (64bit) */
3407 { Op1( 0), CRm( 2), .access = trap_raz_wi },
3408 };
3409
3410 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
3411 AA32(_map), \
3412 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
3413 .visibility = pmu_visibility
3414
3415 /* Macro to expand the PMEVCNTRn register */
3416 #define PMU_PMEVCNTR(n) \
3417 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3418 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3419 .access = access_pmu_evcntr }
3420
3421 /* Macro to expand the PMEVTYPERn register */
3422 #define PMU_PMEVTYPER(n) \
3423 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3424 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3425 .access = access_pmu_evtyper }
3426 /*
3427 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
3428 * depending on the way they are accessed (as a 32bit or a 64bit
3429 * register).
3430 */
3431 static const struct sys_reg_desc cp15_regs[] = {
3432 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3433 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
3434 /* ACTLR */
3435 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
3436 /* ACTLR2 */
3437 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
3438 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
3439 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
3440 /* TTBCR */
3441 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
3442 /* TTBCR2 */
3443 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
3444 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
3445 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
3446 /* DFSR */
3447 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
3448 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
3449 /* ADFSR */
3450 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
3451 /* AIFSR */
3452 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
3453 /* DFAR */
3454 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
3455 /* IFAR */
3456 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
3457
3458 /*
3459 * DC{C,I,CI}SW operations:
3460 */
3461 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
3462 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
3463 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
3464
3465 /* PMU */
3466 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
3467 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
3468 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
3469 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
3470 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
3471 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
3472 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
3473 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
3474 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
3475 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
3476 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
3477 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
3478 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
3479 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
3480 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
3481 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
3482 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
3483 /* PMMIR */
3484 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
3485
3486 /* PRRR/MAIR0 */
3487 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
3488 /* NMRR/MAIR1 */
3489 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
3490 /* AMAIR0 */
3491 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
3492 /* AMAIR1 */
3493 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
3494
3495 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
3496 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
3497 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
3498 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
3499 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
3500 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
3501 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
3502 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
3503 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
3504 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3505 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3506 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
3507 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
3508 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3509 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
3510 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
3511 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
3512 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
3513 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
3514 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
3515 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
3516 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
3517
3518 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
3519
3520 /* Arch Tmers */
3521 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
3522 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
3523
3524 /* PMEVCNTRn */
3525 PMU_PMEVCNTR(0),
3526 PMU_PMEVCNTR(1),
3527 PMU_PMEVCNTR(2),
3528 PMU_PMEVCNTR(3),
3529 PMU_PMEVCNTR(4),
3530 PMU_PMEVCNTR(5),
3531 PMU_PMEVCNTR(6),
3532 PMU_PMEVCNTR(7),
3533 PMU_PMEVCNTR(8),
3534 PMU_PMEVCNTR(9),
3535 PMU_PMEVCNTR(10),
3536 PMU_PMEVCNTR(11),
3537 PMU_PMEVCNTR(12),
3538 PMU_PMEVCNTR(13),
3539 PMU_PMEVCNTR(14),
3540 PMU_PMEVCNTR(15),
3541 PMU_PMEVCNTR(16),
3542 PMU_PMEVCNTR(17),
3543 PMU_PMEVCNTR(18),
3544 PMU_PMEVCNTR(19),
3545 PMU_PMEVCNTR(20),
3546 PMU_PMEVCNTR(21),
3547 PMU_PMEVCNTR(22),
3548 PMU_PMEVCNTR(23),
3549 PMU_PMEVCNTR(24),
3550 PMU_PMEVCNTR(25),
3551 PMU_PMEVCNTR(26),
3552 PMU_PMEVCNTR(27),
3553 PMU_PMEVCNTR(28),
3554 PMU_PMEVCNTR(29),
3555 PMU_PMEVCNTR(30),
3556 /* PMEVTYPERn */
3557 PMU_PMEVTYPER(0),
3558 PMU_PMEVTYPER(1),
3559 PMU_PMEVTYPER(2),
3560 PMU_PMEVTYPER(3),
3561 PMU_PMEVTYPER(4),
3562 PMU_PMEVTYPER(5),
3563 PMU_PMEVTYPER(6),
3564 PMU_PMEVTYPER(7),
3565 PMU_PMEVTYPER(8),
3566 PMU_PMEVTYPER(9),
3567 PMU_PMEVTYPER(10),
3568 PMU_PMEVTYPER(11),
3569 PMU_PMEVTYPER(12),
3570 PMU_PMEVTYPER(13),
3571 PMU_PMEVTYPER(14),
3572 PMU_PMEVTYPER(15),
3573 PMU_PMEVTYPER(16),
3574 PMU_PMEVTYPER(17),
3575 PMU_PMEVTYPER(18),
3576 PMU_PMEVTYPER(19),
3577 PMU_PMEVTYPER(20),
3578 PMU_PMEVTYPER(21),
3579 PMU_PMEVTYPER(22),
3580 PMU_PMEVTYPER(23),
3581 PMU_PMEVTYPER(24),
3582 PMU_PMEVTYPER(25),
3583 PMU_PMEVTYPER(26),
3584 PMU_PMEVTYPER(27),
3585 PMU_PMEVTYPER(28),
3586 PMU_PMEVTYPER(29),
3587 PMU_PMEVTYPER(30),
3588 /* PMCCFILTR */
3589 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
3590
3591 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
3592 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
3593
3594 /* CCSIDR2 */
3595 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
3596
3597 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
3598 };
3599
3600 static const struct sys_reg_desc cp15_64_regs[] = {
3601 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
3602 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
3603 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
3604 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
3605 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
3606 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
3607 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
3608 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
3609 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
3610 };
3611
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)3612 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
3613 bool is_32)
3614 {
3615 unsigned int i;
3616
3617 for (i = 0; i < n; i++) {
3618 if (!is_32 && table[i].reg && !table[i].reset) {
3619 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n",
3620 &table[i], i, table[i].name);
3621 return false;
3622 }
3623
3624 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
3625 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n",
3626 &table[i], i, table[i - 1].name, table[i].name);
3627 return false;
3628 }
3629 }
3630
3631 return true;
3632 }
3633
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)3634 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
3635 {
3636 kvm_inject_undefined(vcpu);
3637 return 1;
3638 }
3639
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)3640 static void perform_access(struct kvm_vcpu *vcpu,
3641 struct sys_reg_params *params,
3642 const struct sys_reg_desc *r)
3643 {
3644 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
3645
3646 /* Check for regs disabled by runtime config */
3647 if (sysreg_hidden(vcpu, r)) {
3648 kvm_inject_undefined(vcpu);
3649 return;
3650 }
3651
3652 /*
3653 * Not having an accessor means that we have configured a trap
3654 * that we don't know how to handle. This certainly qualifies
3655 * as a gross bug that should be fixed right away.
3656 */
3657 BUG_ON(!r->access);
3658
3659 /* Skip instruction if instructed so */
3660 if (likely(r->access(vcpu, params, r)))
3661 kvm_incr_pc(vcpu);
3662 }
3663
3664 /*
3665 * emulate_cp -- tries to match a sys_reg access in a handling table, and
3666 * call the corresponding trap handler.
3667 *
3668 * @params: pointer to the descriptor of the access
3669 * @table: array of trap descriptors
3670 * @num: size of the trap descriptor array
3671 *
3672 * Return true if the access has been handled, false if not.
3673 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)3674 static bool emulate_cp(struct kvm_vcpu *vcpu,
3675 struct sys_reg_params *params,
3676 const struct sys_reg_desc *table,
3677 size_t num)
3678 {
3679 const struct sys_reg_desc *r;
3680
3681 if (!table)
3682 return false; /* Not handled */
3683
3684 r = find_reg(params, table, num);
3685
3686 if (r) {
3687 perform_access(vcpu, params, r);
3688 return true;
3689 }
3690
3691 /* Not handled */
3692 return false;
3693 }
3694
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3695 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
3696 struct sys_reg_params *params)
3697 {
3698 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
3699 int cp = -1;
3700
3701 switch (esr_ec) {
3702 case ESR_ELx_EC_CP15_32:
3703 case ESR_ELx_EC_CP15_64:
3704 cp = 15;
3705 break;
3706 case ESR_ELx_EC_CP14_MR:
3707 case ESR_ELx_EC_CP14_64:
3708 cp = 14;
3709 break;
3710 default:
3711 WARN_ON(1);
3712 }
3713
3714 print_sys_reg_msg(params,
3715 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
3716 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
3717 kvm_inject_undefined(vcpu);
3718 }
3719
3720 /**
3721 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
3722 * @vcpu: The VCPU pointer
3723 * @global: &struct sys_reg_desc
3724 * @nr_global: size of the @global array
3725 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)3726 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
3727 const struct sys_reg_desc *global,
3728 size_t nr_global)
3729 {
3730 struct sys_reg_params params;
3731 u64 esr = kvm_vcpu_get_esr(vcpu);
3732 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3733 int Rt2 = (esr >> 10) & 0x1f;
3734
3735 params.CRm = (esr >> 1) & 0xf;
3736 params.is_write = ((esr & 1) == 0);
3737
3738 params.Op0 = 0;
3739 params.Op1 = (esr >> 16) & 0xf;
3740 params.Op2 = 0;
3741 params.CRn = 0;
3742
3743 /*
3744 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
3745 * backends between AArch32 and AArch64, we get away with it.
3746 */
3747 if (params.is_write) {
3748 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
3749 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
3750 }
3751
3752 /*
3753 * If the table contains a handler, handle the
3754 * potential register operation in the case of a read and return
3755 * with success.
3756 */
3757 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
3758 /* Split up the value between registers for the read side */
3759 if (!params.is_write) {
3760 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
3761 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
3762 }
3763
3764 return 1;
3765 }
3766
3767 unhandled_cp_access(vcpu, ¶ms);
3768 return 1;
3769 }
3770
3771 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
3772
3773 /*
3774 * The CP10 ID registers are architecturally mapped to AArch64 feature
3775 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
3776 * from AArch32.
3777 */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)3778 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
3779 {
3780 u8 reg_id = (esr >> 10) & 0xf;
3781 bool valid;
3782
3783 params->is_write = ((esr & 1) == 0);
3784 params->Op0 = 3;
3785 params->Op1 = 0;
3786 params->CRn = 0;
3787 params->CRm = 3;
3788
3789 /* CP10 ID registers are read-only */
3790 valid = !params->is_write;
3791
3792 switch (reg_id) {
3793 /* MVFR0 */
3794 case 0b0111:
3795 params->Op2 = 0;
3796 break;
3797 /* MVFR1 */
3798 case 0b0110:
3799 params->Op2 = 1;
3800 break;
3801 /* MVFR2 */
3802 case 0b0101:
3803 params->Op2 = 2;
3804 break;
3805 default:
3806 valid = false;
3807 }
3808
3809 if (valid)
3810 return true;
3811
3812 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
3813 params->is_write ? "write" : "read", reg_id);
3814 return false;
3815 }
3816
3817 /**
3818 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
3819 * VFP Register' from AArch32.
3820 * @vcpu: The vCPU pointer
3821 *
3822 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
3823 * Work out the correct AArch64 system register encoding and reroute to the
3824 * AArch64 system register emulation.
3825 */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)3826 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
3827 {
3828 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3829 u64 esr = kvm_vcpu_get_esr(vcpu);
3830 struct sys_reg_params params;
3831
3832 /* UNDEF on any unhandled register access */
3833 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
3834 kvm_inject_undefined(vcpu);
3835 return 1;
3836 }
3837
3838 if (emulate_sys_reg(vcpu, ¶ms))
3839 vcpu_set_reg(vcpu, Rt, params.regval);
3840
3841 return 1;
3842 }
3843
3844 /**
3845 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
3846 * CRn=0, which corresponds to the AArch32 feature
3847 * registers.
3848 * @vcpu: the vCPU pointer
3849 * @params: the system register access parameters.
3850 *
3851 * Our cp15 system register tables do not enumerate the AArch32 feature
3852 * registers. Conveniently, our AArch64 table does, and the AArch32 system
3853 * register encoding can be trivially remapped into the AArch64 for the feature
3854 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
3855 *
3856 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
3857 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
3858 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
3859 * treat undefined registers in this range as RAZ.
3860 */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3861 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
3862 struct sys_reg_params *params)
3863 {
3864 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3865
3866 /* Treat impossible writes to RO registers as UNDEFINED */
3867 if (params->is_write) {
3868 unhandled_cp_access(vcpu, params);
3869 return 1;
3870 }
3871
3872 params->Op0 = 3;
3873
3874 /*
3875 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
3876 * Avoid conflicting with future expansion of AArch64 feature registers
3877 * and simply treat them as RAZ here.
3878 */
3879 if (params->CRm > 3)
3880 params->regval = 0;
3881 else if (!emulate_sys_reg(vcpu, params))
3882 return 1;
3883
3884 vcpu_set_reg(vcpu, Rt, params->regval);
3885 return 1;
3886 }
3887
3888 /**
3889 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
3890 * @vcpu: The VCPU pointer
3891 * @params: &struct sys_reg_params
3892 * @global: &struct sys_reg_desc
3893 * @nr_global: size of the @global array
3894 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)3895 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
3896 struct sys_reg_params *params,
3897 const struct sys_reg_desc *global,
3898 size_t nr_global)
3899 {
3900 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3901
3902 params->regval = vcpu_get_reg(vcpu, Rt);
3903
3904 if (emulate_cp(vcpu, params, global, nr_global)) {
3905 if (!params->is_write)
3906 vcpu_set_reg(vcpu, Rt, params->regval);
3907 return 1;
3908 }
3909
3910 unhandled_cp_access(vcpu, params);
3911 return 1;
3912 }
3913
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)3914 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
3915 {
3916 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
3917 }
3918
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)3919 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
3920 {
3921 struct sys_reg_params params;
3922
3923 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3924
3925 /*
3926 * Certain AArch32 ID registers are handled by rerouting to the AArch64
3927 * system register table. Registers in the ID range where CRm=0 are
3928 * excluded from this scheme as they do not trivially map into AArch64
3929 * system register encodings.
3930 */
3931 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
3932 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
3933
3934 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
3935 }
3936
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)3937 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
3938 {
3939 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
3940 }
3941
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)3942 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
3943 {
3944 struct sys_reg_params params;
3945
3946 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3947
3948 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
3949 }
3950
3951 /**
3952 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
3953 * @vcpu: The VCPU pointer
3954 * @params: Decoded system register parameters
3955 *
3956 * Return: true if the system register access was successful, false otherwise.
3957 */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3958 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
3959 struct sys_reg_params *params)
3960 {
3961 const struct sys_reg_desc *r;
3962
3963 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3964 if (likely(r)) {
3965 perform_access(vcpu, params, r);
3966 return true;
3967 }
3968
3969 print_sys_reg_msg(params,
3970 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
3971 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
3972 kvm_inject_undefined(vcpu);
3973
3974 return false;
3975 }
3976
idregs_debug_find(struct kvm * kvm,u8 pos)3977 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos)
3978 {
3979 unsigned long i, idreg_idx = 0;
3980
3981 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
3982 const struct sys_reg_desc *r = &sys_reg_descs[i];
3983
3984 if (!is_vm_ftr_id_reg(reg_to_encoding(r)))
3985 continue;
3986
3987 if (idreg_idx == pos)
3988 return r;
3989
3990 idreg_idx++;
3991 }
3992
3993 return NULL;
3994 }
3995
idregs_debug_start(struct seq_file * s,loff_t * pos)3996 static void *idregs_debug_start(struct seq_file *s, loff_t *pos)
3997 {
3998 struct kvm *kvm = s->private;
3999 u8 *iter;
4000
4001 mutex_lock(&kvm->arch.config_lock);
4002
4003 iter = &kvm->arch.idreg_debugfs_iter;
4004 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) &&
4005 *iter == (u8)~0) {
4006 *iter = *pos;
4007 if (!idregs_debug_find(kvm, *iter))
4008 iter = NULL;
4009 } else {
4010 iter = ERR_PTR(-EBUSY);
4011 }
4012
4013 mutex_unlock(&kvm->arch.config_lock);
4014
4015 return iter;
4016 }
4017
idregs_debug_next(struct seq_file * s,void * v,loff_t * pos)4018 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos)
4019 {
4020 struct kvm *kvm = s->private;
4021
4022 (*pos)++;
4023
4024 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) {
4025 kvm->arch.idreg_debugfs_iter++;
4026
4027 return &kvm->arch.idreg_debugfs_iter;
4028 }
4029
4030 return NULL;
4031 }
4032
idregs_debug_stop(struct seq_file * s,void * v)4033 static void idregs_debug_stop(struct seq_file *s, void *v)
4034 {
4035 struct kvm *kvm = s->private;
4036
4037 if (IS_ERR(v))
4038 return;
4039
4040 mutex_lock(&kvm->arch.config_lock);
4041
4042 kvm->arch.idreg_debugfs_iter = ~0;
4043
4044 mutex_unlock(&kvm->arch.config_lock);
4045 }
4046
idregs_debug_show(struct seq_file * s,void * v)4047 static int idregs_debug_show(struct seq_file *s, void *v)
4048 {
4049 const struct sys_reg_desc *desc;
4050 struct kvm *kvm = s->private;
4051
4052 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter);
4053
4054 if (!desc->name)
4055 return 0;
4056
4057 seq_printf(s, "%20s:\t%016llx\n",
4058 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc)));
4059
4060 return 0;
4061 }
4062
4063 static const struct seq_operations idregs_debug_sops = {
4064 .start = idregs_debug_start,
4065 .next = idregs_debug_next,
4066 .stop = idregs_debug_stop,
4067 .show = idregs_debug_show,
4068 };
4069
4070 DEFINE_SEQ_ATTRIBUTE(idregs_debug);
4071
kvm_sys_regs_create_debugfs(struct kvm * kvm)4072 void kvm_sys_regs_create_debugfs(struct kvm *kvm)
4073 {
4074 kvm->arch.idreg_debugfs_iter = ~0;
4075
4076 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm,
4077 &idregs_debug_fops);
4078 }
4079
reset_vm_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4080 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg)
4081 {
4082 u32 id = reg_to_encoding(reg);
4083 struct kvm *kvm = vcpu->kvm;
4084
4085 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
4086 return;
4087
4088 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg));
4089 }
4090
reset_vcpu_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4091 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu,
4092 const struct sys_reg_desc *reg)
4093 {
4094 if (kvm_vcpu_initialized(vcpu))
4095 return;
4096
4097 reg->reset(vcpu, reg);
4098 }
4099
4100 /**
4101 * kvm_reset_sys_regs - sets system registers to reset value
4102 * @vcpu: The VCPU pointer
4103 *
4104 * This function finds the right table above and sets the registers on the
4105 * virtual CPU struct to their architecturally defined reset values.
4106 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)4107 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
4108 {
4109 struct kvm *kvm = vcpu->kvm;
4110 unsigned long i;
4111
4112 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4113 const struct sys_reg_desc *r = &sys_reg_descs[i];
4114
4115 if (!r->reset)
4116 continue;
4117
4118 if (is_vm_ftr_id_reg(reg_to_encoding(r)))
4119 reset_vm_ftr_id_reg(vcpu, r);
4120 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r)))
4121 reset_vcpu_ftr_id_reg(vcpu, r);
4122 else
4123 r->reset(vcpu, r);
4124 }
4125
4126 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
4127 }
4128
4129 /**
4130 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction
4131 * trap on a guest execution
4132 * @vcpu: The VCPU pointer
4133 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)4134 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
4135 {
4136 const struct sys_reg_desc *desc = NULL;
4137 struct sys_reg_params params;
4138 unsigned long esr = kvm_vcpu_get_esr(vcpu);
4139 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4140 int sr_idx;
4141
4142 trace_kvm_handle_sys_reg(esr);
4143
4144 if (triage_sysreg_trap(vcpu, &sr_idx))
4145 return 1;
4146
4147 params = esr_sys64_to_params(esr);
4148 params.regval = vcpu_get_reg(vcpu, Rt);
4149
4150 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */
4151 if (params.Op0 == 2 || params.Op0 == 3)
4152 desc = &sys_reg_descs[sr_idx];
4153 else
4154 desc = &sys_insn_descs[sr_idx];
4155
4156 perform_access(vcpu, ¶ms, desc);
4157
4158 /* Read from system register? */
4159 if (!params.is_write &&
4160 (params.Op0 == 2 || params.Op0 == 3))
4161 vcpu_set_reg(vcpu, Rt, params.regval);
4162
4163 return 1;
4164 }
4165
4166 /******************************************************************************
4167 * Userspace API
4168 *****************************************************************************/
4169
index_to_params(u64 id,struct sys_reg_params * params)4170 static bool index_to_params(u64 id, struct sys_reg_params *params)
4171 {
4172 switch (id & KVM_REG_SIZE_MASK) {
4173 case KVM_REG_SIZE_U64:
4174 /* Any unused index bits means it's not valid. */
4175 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
4176 | KVM_REG_ARM_COPROC_MASK
4177 | KVM_REG_ARM64_SYSREG_OP0_MASK
4178 | KVM_REG_ARM64_SYSREG_OP1_MASK
4179 | KVM_REG_ARM64_SYSREG_CRN_MASK
4180 | KVM_REG_ARM64_SYSREG_CRM_MASK
4181 | KVM_REG_ARM64_SYSREG_OP2_MASK))
4182 return false;
4183 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
4184 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
4185 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
4186 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
4187 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
4188 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
4189 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
4190 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
4191 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
4192 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
4193 return true;
4194 default:
4195 return false;
4196 }
4197 }
4198
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)4199 const struct sys_reg_desc *get_reg_by_id(u64 id,
4200 const struct sys_reg_desc table[],
4201 unsigned int num)
4202 {
4203 struct sys_reg_params params;
4204
4205 if (!index_to_params(id, ¶ms))
4206 return NULL;
4207
4208 return find_reg(¶ms, table, num);
4209 }
4210
4211 /* Decode an index value, and find the sys_reg_desc entry. */
4212 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)4213 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
4214 const struct sys_reg_desc table[], unsigned int num)
4215
4216 {
4217 const struct sys_reg_desc *r;
4218
4219 /* We only do sys_reg for now. */
4220 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
4221 return NULL;
4222
4223 r = get_reg_by_id(id, table, num);
4224
4225 /* Not saved in the sys_reg array and not otherwise accessible? */
4226 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
4227 r = NULL;
4228
4229 return r;
4230 }
4231
4232 /*
4233 * These are the invariant sys_reg registers: we let the guest see the
4234 * host versions of these, so they're part of the guest state.
4235 *
4236 * A future CPU may provide a mechanism to present different values to
4237 * the guest, or a future kvm may trap them.
4238 */
4239
4240 #define FUNCTION_INVARIANT(reg) \
4241 static u64 reset_##reg(struct kvm_vcpu *v, \
4242 const struct sys_reg_desc *r) \
4243 { \
4244 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
4245 return ((struct sys_reg_desc *)r)->val; \
4246 }
4247
4248 FUNCTION_INVARIANT(midr_el1)
4249 FUNCTION_INVARIANT(revidr_el1)
4250 FUNCTION_INVARIANT(aidr_el1)
4251
4252 /* ->val is filled in by kvm_sys_reg_table_init() */
4253 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = {
4254 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 },
4255 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 },
4256 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 },
4257 };
4258
get_invariant_sys_reg(u64 id,u64 __user * uaddr)4259 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
4260 {
4261 const struct sys_reg_desc *r;
4262
4263 r = get_reg_by_id(id, invariant_sys_regs,
4264 ARRAY_SIZE(invariant_sys_regs));
4265 if (!r)
4266 return -ENOENT;
4267
4268 return put_user(r->val, uaddr);
4269 }
4270
set_invariant_sys_reg(u64 id,u64 __user * uaddr)4271 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
4272 {
4273 const struct sys_reg_desc *r;
4274 u64 val;
4275
4276 r = get_reg_by_id(id, invariant_sys_regs,
4277 ARRAY_SIZE(invariant_sys_regs));
4278 if (!r)
4279 return -ENOENT;
4280
4281 if (get_user(val, uaddr))
4282 return -EFAULT;
4283
4284 /* This is what we mean by invariant: you can't change it. */
4285 if (r->val != val)
4286 return -EINVAL;
4287
4288 return 0;
4289 }
4290
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4291 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4292 {
4293 u32 val;
4294 u32 __user *uval = uaddr;
4295
4296 /* Fail if we have unknown bits set. */
4297 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4298 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4299 return -ENOENT;
4300
4301 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4302 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4303 if (KVM_REG_SIZE(id) != 4)
4304 return -ENOENT;
4305 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4306 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4307 if (val >= CSSELR_MAX)
4308 return -ENOENT;
4309
4310 return put_user(get_ccsidr(vcpu, val), uval);
4311 default:
4312 return -ENOENT;
4313 }
4314 }
4315
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4316 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4317 {
4318 u32 val, newval;
4319 u32 __user *uval = uaddr;
4320
4321 /* Fail if we have unknown bits set. */
4322 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4323 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4324 return -ENOENT;
4325
4326 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4327 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4328 if (KVM_REG_SIZE(id) != 4)
4329 return -ENOENT;
4330 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4331 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4332 if (val >= CSSELR_MAX)
4333 return -ENOENT;
4334
4335 if (get_user(newval, uval))
4336 return -EFAULT;
4337
4338 return set_ccsidr(vcpu, val, newval);
4339 default:
4340 return -ENOENT;
4341 }
4342 }
4343
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4344 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4345 const struct sys_reg_desc table[], unsigned int num)
4346 {
4347 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4348 const struct sys_reg_desc *r;
4349 u64 val;
4350 int ret;
4351
4352 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4353 if (!r || sysreg_hidden(vcpu, r))
4354 return -ENOENT;
4355
4356 if (r->get_user) {
4357 ret = (r->get_user)(vcpu, r, &val);
4358 } else {
4359 val = __vcpu_sys_reg(vcpu, r->reg);
4360 ret = 0;
4361 }
4362
4363 if (!ret)
4364 ret = put_user(val, uaddr);
4365
4366 return ret;
4367 }
4368
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4369 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4370 {
4371 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4372 int err;
4373
4374 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4375 return demux_c15_get(vcpu, reg->id, uaddr);
4376
4377 err = get_invariant_sys_reg(reg->id, uaddr);
4378 if (err != -ENOENT)
4379 return err;
4380
4381 return kvm_sys_reg_get_user(vcpu, reg,
4382 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4383 }
4384
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4385 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4386 const struct sys_reg_desc table[], unsigned int num)
4387 {
4388 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4389 const struct sys_reg_desc *r;
4390 u64 val;
4391 int ret;
4392
4393 if (get_user(val, uaddr))
4394 return -EFAULT;
4395
4396 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4397 if (!r || sysreg_hidden(vcpu, r))
4398 return -ENOENT;
4399
4400 if (sysreg_user_write_ignore(vcpu, r))
4401 return 0;
4402
4403 if (r->set_user) {
4404 ret = (r->set_user)(vcpu, r, val);
4405 } else {
4406 __vcpu_sys_reg(vcpu, r->reg) = val;
4407 ret = 0;
4408 }
4409
4410 return ret;
4411 }
4412
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4413 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4414 {
4415 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4416 int err;
4417
4418 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4419 return demux_c15_set(vcpu, reg->id, uaddr);
4420
4421 err = set_invariant_sys_reg(reg->id, uaddr);
4422 if (err != -ENOENT)
4423 return err;
4424
4425 return kvm_sys_reg_set_user(vcpu, reg,
4426 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4427 }
4428
num_demux_regs(void)4429 static unsigned int num_demux_regs(void)
4430 {
4431 return CSSELR_MAX;
4432 }
4433
write_demux_regids(u64 __user * uindices)4434 static int write_demux_regids(u64 __user *uindices)
4435 {
4436 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
4437 unsigned int i;
4438
4439 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
4440 for (i = 0; i < CSSELR_MAX; i++) {
4441 if (put_user(val | i, uindices))
4442 return -EFAULT;
4443 uindices++;
4444 }
4445 return 0;
4446 }
4447
sys_reg_to_index(const struct sys_reg_desc * reg)4448 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
4449 {
4450 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
4451 KVM_REG_ARM64_SYSREG |
4452 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
4453 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
4454 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
4455 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
4456 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
4457 }
4458
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)4459 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
4460 {
4461 if (!*uind)
4462 return true;
4463
4464 if (put_user(sys_reg_to_index(reg), *uind))
4465 return false;
4466
4467 (*uind)++;
4468 return true;
4469 }
4470
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)4471 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
4472 const struct sys_reg_desc *rd,
4473 u64 __user **uind,
4474 unsigned int *total)
4475 {
4476 /*
4477 * Ignore registers we trap but don't save,
4478 * and for which no custom user accessor is provided.
4479 */
4480 if (!(rd->reg || rd->get_user))
4481 return 0;
4482
4483 if (sysreg_hidden(vcpu, rd))
4484 return 0;
4485
4486 if (!copy_reg_to_user(rd, uind))
4487 return -EFAULT;
4488
4489 (*total)++;
4490 return 0;
4491 }
4492
4493 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)4494 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
4495 {
4496 const struct sys_reg_desc *i2, *end2;
4497 unsigned int total = 0;
4498 int err;
4499
4500 i2 = sys_reg_descs;
4501 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
4502
4503 while (i2 != end2) {
4504 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
4505 if (err)
4506 return err;
4507 }
4508 return total;
4509 }
4510
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)4511 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
4512 {
4513 return ARRAY_SIZE(invariant_sys_regs)
4514 + num_demux_regs()
4515 + walk_sys_regs(vcpu, (u64 __user *)NULL);
4516 }
4517
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)4518 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
4519 {
4520 unsigned int i;
4521 int err;
4522
4523 /* Then give them all the invariant registers' indices. */
4524 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
4525 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
4526 return -EFAULT;
4527 uindices++;
4528 }
4529
4530 err = walk_sys_regs(vcpu, uindices);
4531 if (err < 0)
4532 return err;
4533 uindices += err;
4534
4535 return write_demux_regids(uindices);
4536 }
4537
4538 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \
4539 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \
4540 sys_reg_Op1(r), \
4541 sys_reg_CRn(r), \
4542 sys_reg_CRm(r), \
4543 sys_reg_Op2(r))
4544
kvm_vm_ioctl_get_reg_writable_masks(struct kvm * kvm,struct reg_mask_range * range)4545 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range)
4546 {
4547 const void *zero_page = page_to_virt(ZERO_PAGE(0));
4548 u64 __user *masks = (u64 __user *)range->addr;
4549
4550 /* Only feature id range is supported, reserved[13] must be zero. */
4551 if (range->range ||
4552 memcmp(range->reserved, zero_page, sizeof(range->reserved)))
4553 return -EINVAL;
4554
4555 /* Wipe the whole thing first */
4556 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64)))
4557 return -EFAULT;
4558
4559 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4560 const struct sys_reg_desc *reg = &sys_reg_descs[i];
4561 u32 encoding = reg_to_encoding(reg);
4562 u64 val;
4563
4564 if (!is_feature_id_reg(encoding) || !reg->set_user)
4565 continue;
4566
4567 if (!reg->val ||
4568 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) {
4569 continue;
4570 }
4571 val = reg->val;
4572
4573 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding))))
4574 return -EFAULT;
4575 }
4576
4577 return 0;
4578 }
4579
vcpu_set_hcr(struct kvm_vcpu * vcpu)4580 static void vcpu_set_hcr(struct kvm_vcpu *vcpu)
4581 {
4582 struct kvm *kvm = vcpu->kvm;
4583
4584 if (has_vhe() || has_hvhe())
4585 vcpu->arch.hcr_el2 |= HCR_E2H;
4586 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
4587 /* route synchronous external abort exceptions to EL2 */
4588 vcpu->arch.hcr_el2 |= HCR_TEA;
4589 /* trap error record accesses */
4590 vcpu->arch.hcr_el2 |= HCR_TERR;
4591 }
4592
4593 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
4594 vcpu->arch.hcr_el2 |= HCR_FWB;
4595
4596 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
4597 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) &&
4598 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0))
4599 vcpu->arch.hcr_el2 |= HCR_TID4;
4600 else
4601 vcpu->arch.hcr_el2 |= HCR_TID2;
4602
4603 if (vcpu_el1_is_32bit(vcpu))
4604 vcpu->arch.hcr_el2 &= ~HCR_RW;
4605
4606 if (kvm_has_mte(vcpu->kvm))
4607 vcpu->arch.hcr_el2 |= HCR_ATA;
4608
4609 /*
4610 * In the absence of FGT, we cannot independently trap TLBI
4611 * Range instructions. This isn't great, but trapping all
4612 * TLBIs would be far worse. Live with it...
4613 */
4614 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4615 vcpu->arch.hcr_el2 |= HCR_TTLBOS;
4616 }
4617
kvm_calculate_traps(struct kvm_vcpu * vcpu)4618 void kvm_calculate_traps(struct kvm_vcpu *vcpu)
4619 {
4620 struct kvm *kvm = vcpu->kvm;
4621
4622 mutex_lock(&kvm->arch.config_lock);
4623 vcpu_set_hcr(vcpu);
4624 vcpu_set_ich_hcr(vcpu);
4625
4626 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
4627 /*
4628 * In general, all HCRX_EL2 bits are gated by a feature.
4629 * The only reason we can set SMPME without checking any
4630 * feature is that its effects are not directly observable
4631 * from the guest.
4632 */
4633 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME;
4634
4635 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP))
4636 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);
4637
4638 if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP))
4639 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En;
4640
4641 if (kvm_has_fpmr(kvm))
4642 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM;
4643 }
4644
4645 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
4646 goto out;
4647
4648 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 |
4649 HFGxTR_EL2_nMAIR2_EL1 |
4650 HFGxTR_EL2_nS2POR_EL1 |
4651 HFGxTR_EL2_nACCDATA_EL1 |
4652 HFGxTR_EL2_nSMPRI_EL1_MASK |
4653 HFGxTR_EL2_nTPIDR2_EL0_MASK);
4654
4655 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4656 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS|
4657 HFGITR_EL2_TLBIRVALE1OS |
4658 HFGITR_EL2_TLBIRVAAE1OS |
4659 HFGITR_EL2_TLBIRVAE1OS |
4660 HFGITR_EL2_TLBIVAALE1OS |
4661 HFGITR_EL2_TLBIVALE1OS |
4662 HFGITR_EL2_TLBIVAAE1OS |
4663 HFGITR_EL2_TLBIASIDE1OS |
4664 HFGITR_EL2_TLBIVAE1OS |
4665 HFGITR_EL2_TLBIVMALLE1OS);
4666
4667 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
4668 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 |
4669 HFGITR_EL2_TLBIRVALE1 |
4670 HFGITR_EL2_TLBIRVAAE1 |
4671 HFGITR_EL2_TLBIRVAE1 |
4672 HFGITR_EL2_TLBIRVAALE1IS|
4673 HFGITR_EL2_TLBIRVALE1IS |
4674 HFGITR_EL2_TLBIRVAAE1IS |
4675 HFGITR_EL2_TLBIRVAE1IS |
4676 HFGITR_EL2_TLBIRVAALE1OS|
4677 HFGITR_EL2_TLBIRVALE1OS |
4678 HFGITR_EL2_TLBIRVAAE1OS |
4679 HFGITR_EL2_TLBIRVAE1OS);
4680
4681 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP))
4682 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A;
4683
4684 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2))
4685 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP |
4686 HFGITR_EL2_ATS1E1WP);
4687
4688 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP))
4689 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 |
4690 HFGxTR_EL2_nPIR_EL1);
4691
4692 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
4693 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
4694 HFGxTR_EL2_nPOR_EL0);
4695
4696 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP))
4697 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 |
4698 HAFGRTR_EL2_RES1);
4699
4700 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
4701 out:
4702 mutex_unlock(&kvm->arch.config_lock);
4703 }
4704
4705 /*
4706 * Perform last adjustments to the ID registers that are implied by the
4707 * configuration outside of the ID regs themselves, as well as any
4708 * initialisation that directly depend on these ID registers (such as
4709 * RES0/RES1 behaviours). This is not the place to configure traps though.
4710 *
4711 * Because this can be called once per CPU, changes must be idempotent.
4712 */
kvm_finalize_sys_regs(struct kvm_vcpu * vcpu)4713 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu)
4714 {
4715 struct kvm *kvm = vcpu->kvm;
4716
4717 guard(mutex)(&kvm->arch.config_lock);
4718
4719 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) &&
4720 irqchip_in_kernel(kvm) &&
4721 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) {
4722 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK;
4723 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK;
4724 }
4725
4726 if (vcpu_has_nv(vcpu)) {
4727 int ret = kvm_init_nv_sysregs(kvm);
4728 if (ret)
4729 return ret;
4730 }
4731
4732 return 0;
4733 }
4734
kvm_sys_reg_table_init(void)4735 int __init kvm_sys_reg_table_init(void)
4736 {
4737 bool valid = true;
4738 unsigned int i;
4739 int ret = 0;
4740
4741 /* Make sure tables are unique and in order. */
4742 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
4743 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
4744 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
4745 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
4746 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
4747 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
4748 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false);
4749
4750 if (!valid)
4751 return -EINVAL;
4752
4753 /* We abuse the reset function to overwrite the table itself. */
4754 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
4755 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
4756
4757 ret = populate_nv_trap_config();
4758
4759 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++)
4760 ret = populate_sysreg_config(sys_reg_descs + i, i);
4761
4762 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++)
4763 ret = populate_sysreg_config(sys_insn_descs + i, i);
4764
4765 return ret;
4766 }
4767