1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015 Regents of the University of California
4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.
5 */
6
7 #ifndef _ASM_RISCV_SBI_H
8 #define _ASM_RISCV_SBI_H
9
10 #include <linux/types.h>
11 #include <linux/cpumask.h>
12 #include <linux/jump_label.h>
13
14 #ifdef CONFIG_RISCV_SBI
15 enum sbi_ext_id {
16 #ifdef CONFIG_RISCV_SBI_V01
17 SBI_EXT_0_1_SET_TIMER = 0x0,
18 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
19 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
20 SBI_EXT_0_1_CLEAR_IPI = 0x3,
21 SBI_EXT_0_1_SEND_IPI = 0x4,
22 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
23 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
24 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
25 SBI_EXT_0_1_SHUTDOWN = 0x8,
26 #endif
27 SBI_EXT_BASE = 0x10,
28 SBI_EXT_TIME = 0x54494D45,
29 SBI_EXT_IPI = 0x735049,
30 SBI_EXT_RFENCE = 0x52464E43,
31 SBI_EXT_HSM = 0x48534D,
32 SBI_EXT_SRST = 0x53525354,
33 SBI_EXT_SUSP = 0x53555350,
34 SBI_EXT_PMU = 0x504D55,
35 SBI_EXT_DBCN = 0x4442434E,
36 SBI_EXT_STA = 0x535441,
37
38 /* Experimentals extensions must lie within this range */
39 SBI_EXT_EXPERIMENTAL_START = 0x08000000,
40 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
41
42 /* Vendor extensions must lie within this range */
43 SBI_EXT_VENDOR_START = 0x09000000,
44 SBI_EXT_VENDOR_END = 0x09FFFFFF,
45 };
46
47 enum sbi_ext_base_fid {
48 SBI_EXT_BASE_GET_SPEC_VERSION = 0,
49 SBI_EXT_BASE_GET_IMP_ID,
50 SBI_EXT_BASE_GET_IMP_VERSION,
51 SBI_EXT_BASE_PROBE_EXT,
52 SBI_EXT_BASE_GET_MVENDORID,
53 SBI_EXT_BASE_GET_MARCHID,
54 SBI_EXT_BASE_GET_MIMPID,
55 };
56
57 enum sbi_ext_time_fid {
58 SBI_EXT_TIME_SET_TIMER = 0,
59 };
60
61 enum sbi_ext_ipi_fid {
62 SBI_EXT_IPI_SEND_IPI = 0,
63 };
64
65 enum sbi_ext_rfence_fid {
66 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
67 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
68 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
69 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
70 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
71 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
72 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
73 };
74
75 enum sbi_ext_hsm_fid {
76 SBI_EXT_HSM_HART_START = 0,
77 SBI_EXT_HSM_HART_STOP,
78 SBI_EXT_HSM_HART_STATUS,
79 SBI_EXT_HSM_HART_SUSPEND,
80 };
81
82 enum sbi_hsm_hart_state {
83 SBI_HSM_STATE_STARTED = 0,
84 SBI_HSM_STATE_STOPPED,
85 SBI_HSM_STATE_START_PENDING,
86 SBI_HSM_STATE_STOP_PENDING,
87 SBI_HSM_STATE_SUSPENDED,
88 SBI_HSM_STATE_SUSPEND_PENDING,
89 SBI_HSM_STATE_RESUME_PENDING,
90 };
91
92 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
93 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
94 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000
95
96 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
97 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
98 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
99 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
100 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
101 SBI_HSM_SUSP_PLAT_BASE)
102 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
103 SBI_HSM_SUSP_BASE_MASK)
104
105 enum sbi_ext_srst_fid {
106 SBI_EXT_SRST_RESET = 0,
107 };
108
109 enum sbi_srst_reset_type {
110 SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
111 SBI_SRST_RESET_TYPE_COLD_REBOOT,
112 SBI_SRST_RESET_TYPE_WARM_REBOOT,
113 };
114
115 enum sbi_srst_reset_reason {
116 SBI_SRST_RESET_REASON_NONE = 0,
117 SBI_SRST_RESET_REASON_SYS_FAILURE,
118 };
119
120 enum sbi_ext_susp_fid {
121 SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
122 };
123
124 enum sbi_ext_susp_sleep_type {
125 SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
126 };
127
128 enum sbi_ext_pmu_fid {
129 SBI_EXT_PMU_NUM_COUNTERS = 0,
130 SBI_EXT_PMU_COUNTER_GET_INFO,
131 SBI_EXT_PMU_COUNTER_CFG_MATCH,
132 SBI_EXT_PMU_COUNTER_START,
133 SBI_EXT_PMU_COUNTER_STOP,
134 SBI_EXT_PMU_COUNTER_FW_READ,
135 SBI_EXT_PMU_COUNTER_FW_READ_HI,
136 SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
137 };
138
139 union sbi_pmu_ctr_info {
140 unsigned long value;
141 struct {
142 unsigned long csr:12;
143 unsigned long width:6;
144 #if __riscv_xlen == 32
145 unsigned long reserved:13;
146 #else
147 unsigned long reserved:45;
148 #endif
149 unsigned long type:1;
150 };
151 };
152
153 /* Data structure to contain the pmu snapshot data */
154 struct riscv_pmu_snapshot_data {
155 u64 ctr_overflow_mask;
156 u64 ctr_values[64];
157 u64 reserved[447];
158 };
159
160 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
161 #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)
162 #define RISCV_PMU_RAW_EVENT_IDX 0x20000
163 #define RISCV_PLAT_FW_EVENT 0xFFFF
164
165 /** General pmu event codes specified in SBI PMU extension */
166 enum sbi_pmu_hw_generic_events_t {
167 SBI_PMU_HW_NO_EVENT = 0,
168 SBI_PMU_HW_CPU_CYCLES = 1,
169 SBI_PMU_HW_INSTRUCTIONS = 2,
170 SBI_PMU_HW_CACHE_REFERENCES = 3,
171 SBI_PMU_HW_CACHE_MISSES = 4,
172 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
173 SBI_PMU_HW_BRANCH_MISSES = 6,
174 SBI_PMU_HW_BUS_CYCLES = 7,
175 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
176 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
177 SBI_PMU_HW_REF_CPU_CYCLES = 10,
178
179 SBI_PMU_HW_GENERAL_MAX,
180 };
181
182 /**
183 * Special "firmware" events provided by the firmware, even if the hardware
184 * does not support performance events. These events are encoded as a raw
185 * event type in Linux kernel perf framework.
186 */
187 enum sbi_pmu_fw_generic_events_t {
188 SBI_PMU_FW_MISALIGNED_LOAD = 0,
189 SBI_PMU_FW_MISALIGNED_STORE = 1,
190 SBI_PMU_FW_ACCESS_LOAD = 2,
191 SBI_PMU_FW_ACCESS_STORE = 3,
192 SBI_PMU_FW_ILLEGAL_INSN = 4,
193 SBI_PMU_FW_SET_TIMER = 5,
194 SBI_PMU_FW_IPI_SENT = 6,
195 SBI_PMU_FW_IPI_RCVD = 7,
196 SBI_PMU_FW_FENCE_I_SENT = 8,
197 SBI_PMU_FW_FENCE_I_RCVD = 9,
198 SBI_PMU_FW_SFENCE_VMA_SENT = 10,
199 SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
200 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
201 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
202
203 SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
204 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
205 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
206 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
207
208 SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
209 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
210 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
211 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
212 SBI_PMU_FW_MAX,
213 };
214
215 /* SBI PMU event types */
216 enum sbi_pmu_event_type {
217 SBI_PMU_EVENT_TYPE_HW = 0x0,
218 SBI_PMU_EVENT_TYPE_CACHE = 0x1,
219 SBI_PMU_EVENT_TYPE_RAW = 0x2,
220 SBI_PMU_EVENT_TYPE_FW = 0xf,
221 };
222
223 /* SBI PMU event types */
224 enum sbi_pmu_ctr_type {
225 SBI_PMU_CTR_TYPE_HW = 0x0,
226 SBI_PMU_CTR_TYPE_FW,
227 };
228
229 /* Helper macros to decode event idx */
230 #define SBI_PMU_EVENT_IDX_OFFSET 20
231 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
232 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
233 #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
234 #define SBI_PMU_EVENT_RAW_IDX 0x20000
235 #define SBI_PMU_FIXED_CTR_MASK 0x07
236
237 #define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
238 #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
239 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
240
241 #define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
242 #define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
243
244 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
245
246 /* Flags defined for config matching function */
247 #define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
248 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
249 #define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
250 #define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
251 #define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
252 #define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
253 #define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
254 #define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
255
256 /* Flags defined for counter start function */
257 #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
258 #define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
259
260 /* Flags defined for counter stop function */
261 #define SBI_PMU_STOP_FLAG_RESET BIT(0)
262 #define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
263
264 enum sbi_ext_dbcn_fid {
265 SBI_EXT_DBCN_CONSOLE_WRITE = 0,
266 SBI_EXT_DBCN_CONSOLE_READ = 1,
267 SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
268 };
269
270 /* SBI STA (steal-time accounting) extension */
271 enum sbi_ext_sta_fid {
272 SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
273 };
274
275 struct sbi_sta_struct {
276 __le32 sequence;
277 __le32 flags;
278 __le64 steal;
279 u8 preempted;
280 u8 pad[47];
281 } __packed;
282
283 #define SBI_SHMEM_DISABLE -1
284
285 /* SBI spec version fields */
286 #define SBI_SPEC_VERSION_DEFAULT 0x1
287 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
288 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
289 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
290
291 /* SBI return error codes */
292 #define SBI_SUCCESS 0
293 #define SBI_ERR_FAILURE -1
294 #define SBI_ERR_NOT_SUPPORTED -2
295 #define SBI_ERR_INVALID_PARAM -3
296 #define SBI_ERR_DENIED -4
297 #define SBI_ERR_INVALID_ADDRESS -5
298 #define SBI_ERR_ALREADY_AVAILABLE -6
299 #define SBI_ERR_ALREADY_STARTED -7
300 #define SBI_ERR_ALREADY_STOPPED -8
301 #define SBI_ERR_NO_SHMEM -9
302
303 extern unsigned long sbi_spec_version;
304 struct sbiret {
305 long error;
306 long value;
307 };
308
309 void sbi_init(void);
310 long __sbi_base_ecall(int fid);
311 struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
312 unsigned long arg2, unsigned long arg3,
313 unsigned long arg4, unsigned long arg5,
314 int fid, int ext);
315 #define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5) \
316 __sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
317
318 #ifdef CONFIG_RISCV_SBI_V01
319 void sbi_console_putchar(int ch);
320 int sbi_console_getchar(void);
321 #else
sbi_console_putchar(int ch)322 static inline void sbi_console_putchar(int ch) { }
sbi_console_getchar(void)323 static inline int sbi_console_getchar(void) { return -ENOENT; }
324 #endif
325 long sbi_get_mvendorid(void);
326 long sbi_get_marchid(void);
327 long sbi_get_mimpid(void);
328 void sbi_set_timer(uint64_t stime_value);
329 void sbi_shutdown(void);
330 void sbi_send_ipi(unsigned int cpu);
331 int sbi_remote_fence_i(const struct cpumask *cpu_mask);
332
333 int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
334 unsigned long start,
335 unsigned long size,
336 unsigned long asid);
337 int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
338 unsigned long start,
339 unsigned long size);
340 int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
341 unsigned long start,
342 unsigned long size,
343 unsigned long vmid);
344 int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
345 unsigned long start,
346 unsigned long size);
347 int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
348 unsigned long start,
349 unsigned long size,
350 unsigned long asid);
351 long sbi_probe_extension(int ext);
352
353 /* Check if current SBI specification version is 0.1 or not */
sbi_spec_is_0_1(void)354 static inline int sbi_spec_is_0_1(void)
355 {
356 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
357 }
358
359 /* Get the major version of SBI */
sbi_major_version(void)360 static inline unsigned long sbi_major_version(void)
361 {
362 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
363 SBI_SPEC_VERSION_MAJOR_MASK;
364 }
365
366 /* Get the minor version of SBI */
sbi_minor_version(void)367 static inline unsigned long sbi_minor_version(void)
368 {
369 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
370 }
371
372 /* Make SBI version */
sbi_mk_version(unsigned long major,unsigned long minor)373 static inline unsigned long sbi_mk_version(unsigned long major,
374 unsigned long minor)
375 {
376 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
377 | (minor & SBI_SPEC_VERSION_MINOR_MASK);
378 }
379
sbi_err_map_linux_errno(int err)380 static inline int sbi_err_map_linux_errno(int err)
381 {
382 switch (err) {
383 case SBI_SUCCESS:
384 return 0;
385 case SBI_ERR_DENIED:
386 return -EPERM;
387 case SBI_ERR_INVALID_PARAM:
388 return -EINVAL;
389 case SBI_ERR_INVALID_ADDRESS:
390 return -EFAULT;
391 case SBI_ERR_NOT_SUPPORTED:
392 case SBI_ERR_FAILURE:
393 default:
394 return -ENOTSUPP;
395 };
396 }
397
398 extern bool sbi_debug_console_available;
399 int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
400 int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
401
402 #else /* CONFIG_RISCV_SBI */
sbi_remote_fence_i(const struct cpumask * cpu_mask)403 static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
sbi_init(void)404 static inline void sbi_init(void) {}
405 #endif /* CONFIG_RISCV_SBI */
406
407 unsigned long riscv_get_mvendorid(void);
408 unsigned long riscv_get_marchid(void);
409 unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
410 unsigned long riscv_cached_marchid(unsigned int cpu_id);
411 unsigned long riscv_cached_mimpid(unsigned int cpu_id);
412
413 #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
414 DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
415 #define riscv_use_sbi_for_rfence() \
416 static_branch_unlikely(&riscv_sbi_for_rfence)
417 void sbi_ipi_init(void);
418 #else
riscv_use_sbi_for_rfence(void)419 static inline bool riscv_use_sbi_for_rfence(void) { return false; }
sbi_ipi_init(void)420 static inline void sbi_ipi_init(void) { }
421 #endif
422
423 #endif /* _ASM_RISCV_SBI_H */
424