1 /*
2 * Performance events - AMD IBS
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
5 *
6 * For licencing details see kernel-base/COPYING
7 */
8
9 #include <linux/perf_event.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/ptrace.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/sched/clock.h>
16
17 #include <asm/apic.h>
18
19 #include "../perf_event.h"
20
21 static u32 ibs_caps;
22
23 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
24
25 #include <linux/kprobes.h>
26 #include <linux/hardirq.h>
27
28 #include <asm/nmi.h>
29 #include <asm/amd-ibs.h>
30
31 #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
32 #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
33
34
35 /*
36 * IBS states:
37 *
38 * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
39 * and any further add()s must fail.
40 *
41 * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
42 * complicated by the fact that the IBS hardware can send late NMIs (ie. after
43 * we've cleared the EN bit).
44 *
45 * In order to consume these late NMIs we have the STOPPED state, any NMI that
46 * happens after we've cleared the EN state will clear this bit and report the
47 * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
48 * someone else can consume our BIT and our NMI will go unhandled).
49 *
50 * And since we cannot set/clear this separate bit together with the EN bit,
51 * there are races; if we cleared STARTED early, an NMI could land in
52 * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
53 * could happen if the period is small enough), and consume our STOPPED bit
54 * and trigger streams of unhandled NMIs.
55 *
56 * If, however, we clear STARTED late, an NMI can hit between clearing the
57 * EN bit and clearing STARTED, still see STARTED set and process the event.
58 * If this event will have the VALID bit clear, we bail properly, but this
59 * is not a given. With VALID set we can end up calling pmu::stop() again
60 * (the throttle logic) and trigger the WARNs in there.
61 *
62 * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
63 * nesting, and clear STARTED late, so that we have a well defined state over
64 * the clearing of the EN bit.
65 *
66 * XXX: we could probably be using !atomic bitops for all this.
67 */
68
69 enum ibs_states {
70 IBS_ENABLED = 0,
71 IBS_STARTED = 1,
72 IBS_STOPPING = 2,
73 IBS_STOPPED = 3,
74
75 IBS_MAX_STATES,
76 };
77
78 struct cpu_perf_ibs {
79 struct perf_event *event;
80 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
81 };
82
83 struct perf_ibs {
84 struct pmu pmu;
85 unsigned int msr;
86 u64 config_mask;
87 u64 cnt_mask;
88 u64 enable_mask;
89 u64 valid_mask;
90 u64 max_period;
91 unsigned long offset_mask[1];
92 int offset_max;
93 unsigned int fetch_count_reset_broken : 1;
94 unsigned int fetch_ignore_if_zero_rip : 1;
95 struct cpu_perf_ibs __percpu *pcpu;
96
97 u64 (*get_count)(u64 config);
98 };
99
100 static int
perf_event_set_period(struct hw_perf_event * hwc,u64 min,u64 max,u64 * hw_period)101 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
102 {
103 s64 left = local64_read(&hwc->period_left);
104 s64 period = hwc->sample_period;
105 int overflow = 0;
106
107 /*
108 * If we are way outside a reasonable range then just skip forward:
109 */
110 if (unlikely(left <= -period)) {
111 left = period;
112 local64_set(&hwc->period_left, left);
113 hwc->last_period = period;
114 overflow = 1;
115 }
116
117 if (unlikely(left < (s64)min)) {
118 left += period;
119 local64_set(&hwc->period_left, left);
120 hwc->last_period = period;
121 overflow = 1;
122 }
123
124 /*
125 * If the hw period that triggers the sw overflow is too short
126 * we might hit the irq handler. This biases the results.
127 * Thus we shorten the next-to-last period and set the last
128 * period to the max period.
129 */
130 if (left > max) {
131 left -= max;
132 if (left > max)
133 left = max;
134 else if (left < min)
135 left = min;
136 }
137
138 *hw_period = (u64)left;
139
140 return overflow;
141 }
142
143 static int
perf_event_try_update(struct perf_event * event,u64 new_raw_count,int width)144 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
145 {
146 struct hw_perf_event *hwc = &event->hw;
147 int shift = 64 - width;
148 u64 prev_raw_count;
149 u64 delta;
150
151 /*
152 * Careful: an NMI might modify the previous event value.
153 *
154 * Our tactic to handle this is to first atomically read and
155 * exchange a new raw count - then add that new-prev delta
156 * count to the generic event atomically:
157 */
158 prev_raw_count = local64_read(&hwc->prev_count);
159 if (!local64_try_cmpxchg(&hwc->prev_count,
160 &prev_raw_count, new_raw_count))
161 return 0;
162
163 /*
164 * Now we have the new raw value and have updated the prev
165 * timestamp already. We can now calculate the elapsed delta
166 * (event-)time and add that to the generic event.
167 *
168 * Careful, not all hw sign-extends above the physical width
169 * of the count.
170 */
171 delta = (new_raw_count << shift) - (prev_raw_count << shift);
172 delta >>= shift;
173
174 local64_add(delta, &event->count);
175 local64_sub(delta, &hwc->period_left);
176
177 return 1;
178 }
179
180 static struct perf_ibs perf_ibs_fetch;
181 static struct perf_ibs perf_ibs_op;
182
get_ibs_pmu(int type)183 static struct perf_ibs *get_ibs_pmu(int type)
184 {
185 if (perf_ibs_fetch.pmu.type == type)
186 return &perf_ibs_fetch;
187 if (perf_ibs_op.pmu.type == type)
188 return &perf_ibs_op;
189 return NULL;
190 }
191
192 /*
193 * core pmu config -> IBS config
194 *
195 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
196 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
197 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
198 *
199 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
200 * MSRC001_1033) is used to select either cycle or micro-ops counting
201 * mode.
202 */
core_pmu_ibs_config(struct perf_event * event,u64 * config)203 static int core_pmu_ibs_config(struct perf_event *event, u64 *config)
204 {
205 switch (event->attr.type) {
206 case PERF_TYPE_HARDWARE:
207 switch (event->attr.config) {
208 case PERF_COUNT_HW_CPU_CYCLES:
209 *config = 0;
210 return 0;
211 }
212 break;
213 case PERF_TYPE_RAW:
214 switch (event->attr.config) {
215 case 0x0076:
216 *config = 0;
217 return 0;
218 case 0x00C1:
219 *config = IBS_OP_CNT_CTL;
220 return 0;
221 }
222 break;
223 default:
224 return -ENOENT;
225 }
226
227 return -EOPNOTSUPP;
228 }
229
230 /*
231 * The rip of IBS samples has skid 0. Thus, IBS supports precise
232 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
233 * rip is invalid when IBS was not able to record the rip correctly.
234 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
235 */
forward_event_to_ibs(struct perf_event * event)236 int forward_event_to_ibs(struct perf_event *event)
237 {
238 u64 config = 0;
239
240 if (!event->attr.precise_ip || event->attr.precise_ip > 2)
241 return -EOPNOTSUPP;
242
243 if (!core_pmu_ibs_config(event, &config)) {
244 event->attr.type = perf_ibs_op.pmu.type;
245 event->attr.config = config;
246 }
247 return -ENOENT;
248 }
249
250 /*
251 * Grouping of IBS events is not possible since IBS can have only
252 * one event active at any point in time.
253 */
validate_group(struct perf_event * event)254 static int validate_group(struct perf_event *event)
255 {
256 struct perf_event *sibling;
257
258 if (event->group_leader == event)
259 return 0;
260
261 if (event->group_leader->pmu == event->pmu)
262 return -EINVAL;
263
264 for_each_sibling_event(sibling, event->group_leader) {
265 if (sibling->pmu == event->pmu)
266 return -EINVAL;
267 }
268 return 0;
269 }
270
perf_ibs_init(struct perf_event * event)271 static int perf_ibs_init(struct perf_event *event)
272 {
273 struct hw_perf_event *hwc = &event->hw;
274 struct perf_ibs *perf_ibs;
275 u64 config;
276 int ret;
277
278 perf_ibs = get_ibs_pmu(event->attr.type);
279 if (!perf_ibs)
280 return -ENOENT;
281
282 config = event->attr.config;
283
284 if (event->pmu != &perf_ibs->pmu)
285 return -ENOENT;
286
287 if (config & ~perf_ibs->config_mask)
288 return -EINVAL;
289
290 if (has_branch_stack(event))
291 return -EOPNOTSUPP;
292
293 ret = validate_group(event);
294 if (ret)
295 return ret;
296
297 if (hwc->sample_period) {
298 if (config & perf_ibs->cnt_mask)
299 /* raw max_cnt may not be set */
300 return -EINVAL;
301 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
302 /*
303 * lower 4 bits can not be set in ibs max cnt,
304 * but allowing it in case we adjust the
305 * sample period to set a frequency.
306 */
307 return -EINVAL;
308 hwc->sample_period &= ~0x0FULL;
309 if (!hwc->sample_period)
310 hwc->sample_period = 0x10;
311 } else {
312 u64 period = 0;
313
314 if (perf_ibs == &perf_ibs_op) {
315 period = (config & IBS_OP_MAX_CNT) << 4;
316 if (ibs_caps & IBS_CAPS_OPCNTEXT)
317 period |= config & IBS_OP_MAX_CNT_EXT_MASK;
318 } else {
319 period = (config & IBS_FETCH_MAX_CNT) << 4;
320 }
321
322 config &= ~perf_ibs->cnt_mask;
323 event->attr.sample_period = period;
324 hwc->sample_period = period;
325 }
326
327 if (!hwc->sample_period)
328 return -EINVAL;
329
330 /*
331 * If we modify hwc->sample_period, we also need to update
332 * hwc->last_period and hwc->period_left.
333 */
334 hwc->last_period = hwc->sample_period;
335 local64_set(&hwc->period_left, hwc->sample_period);
336
337 hwc->config_base = perf_ibs->msr;
338 hwc->config = config;
339
340 return 0;
341 }
342
perf_ibs_set_period(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 * period)343 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
344 struct hw_perf_event *hwc, u64 *period)
345 {
346 int overflow;
347
348 /* ignore lower 4 bits in min count: */
349 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
350 local64_set(&hwc->prev_count, 0);
351
352 return overflow;
353 }
354
get_ibs_fetch_count(u64 config)355 static u64 get_ibs_fetch_count(u64 config)
356 {
357 union ibs_fetch_ctl fetch_ctl = (union ibs_fetch_ctl)config;
358
359 return fetch_ctl.fetch_cnt << 4;
360 }
361
get_ibs_op_count(u64 config)362 static u64 get_ibs_op_count(u64 config)
363 {
364 union ibs_op_ctl op_ctl = (union ibs_op_ctl)config;
365 u64 count = 0;
366
367 /*
368 * If the internal 27-bit counter rolled over, the count is MaxCnt
369 * and the lower 7 bits of CurCnt are randomized.
370 * Otherwise CurCnt has the full 27-bit current counter value.
371 */
372 if (op_ctl.op_val) {
373 count = op_ctl.opmaxcnt << 4;
374 if (ibs_caps & IBS_CAPS_OPCNTEXT)
375 count += op_ctl.opmaxcnt_ext << 20;
376 } else if (ibs_caps & IBS_CAPS_RDWROPCNT) {
377 count = op_ctl.opcurcnt;
378 }
379
380 return count;
381 }
382
383 static void
perf_ibs_event_update(struct perf_ibs * perf_ibs,struct perf_event * event,u64 * config)384 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
385 u64 *config)
386 {
387 u64 count = perf_ibs->get_count(*config);
388
389 /*
390 * Set width to 64 since we do not overflow on max width but
391 * instead on max count. In perf_ibs_set_period() we clear
392 * prev count manually on overflow.
393 */
394 while (!perf_event_try_update(event, count, 64)) {
395 rdmsrl(event->hw.config_base, *config);
396 count = perf_ibs->get_count(*config);
397 }
398 }
399
perf_ibs_enable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)400 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
401 struct hw_perf_event *hwc, u64 config)
402 {
403 u64 tmp = hwc->config | config;
404
405 if (perf_ibs->fetch_count_reset_broken)
406 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
407
408 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
409 }
410
411 /*
412 * Erratum #420 Instruction-Based Sampling Engine May Generate
413 * Interrupt that Cannot Be Cleared:
414 *
415 * Must clear counter mask first, then clear the enable bit. See
416 * Revision Guide for AMD Family 10h Processors, Publication #41322.
417 */
perf_ibs_disable_event(struct perf_ibs * perf_ibs,struct hw_perf_event * hwc,u64 config)418 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
419 struct hw_perf_event *hwc, u64 config)
420 {
421 config &= ~perf_ibs->cnt_mask;
422 if (boot_cpu_data.x86 == 0x10)
423 wrmsrl(hwc->config_base, config);
424 config &= ~perf_ibs->enable_mask;
425 wrmsrl(hwc->config_base, config);
426 }
427
428 /*
429 * We cannot restore the ibs pmu state, so we always needs to update
430 * the event while stopping it and then reset the state when starting
431 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
432 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
433 */
perf_ibs_start(struct perf_event * event,int flags)434 static void perf_ibs_start(struct perf_event *event, int flags)
435 {
436 struct hw_perf_event *hwc = &event->hw;
437 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
438 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
439 u64 period, config = 0;
440
441 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
442 return;
443
444 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
445 hwc->state = 0;
446
447 perf_ibs_set_period(perf_ibs, hwc, &period);
448 if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {
449 config |= period & IBS_OP_MAX_CNT_EXT_MASK;
450 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
451 }
452 config |= period >> 4;
453
454 /*
455 * Set STARTED before enabling the hardware, such that a subsequent NMI
456 * must observe it.
457 */
458 set_bit(IBS_STARTED, pcpu->state);
459 clear_bit(IBS_STOPPING, pcpu->state);
460 perf_ibs_enable_event(perf_ibs, hwc, config);
461
462 perf_event_update_userpage(event);
463 }
464
perf_ibs_stop(struct perf_event * event,int flags)465 static void perf_ibs_stop(struct perf_event *event, int flags)
466 {
467 struct hw_perf_event *hwc = &event->hw;
468 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
469 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
470 u64 config;
471 int stopping;
472
473 if (test_and_set_bit(IBS_STOPPING, pcpu->state))
474 return;
475
476 stopping = test_bit(IBS_STARTED, pcpu->state);
477
478 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
479 return;
480
481 rdmsrl(hwc->config_base, config);
482
483 if (stopping) {
484 /*
485 * Set STOPPED before disabling the hardware, such that it
486 * must be visible to NMIs the moment we clear the EN bit,
487 * at which point we can generate an !VALID sample which
488 * we need to consume.
489 */
490 set_bit(IBS_STOPPED, pcpu->state);
491 perf_ibs_disable_event(perf_ibs, hwc, config);
492 /*
493 * Clear STARTED after disabling the hardware; if it were
494 * cleared before an NMI hitting after the clear but before
495 * clearing the EN bit might think it a spurious NMI and not
496 * handle it.
497 *
498 * Clearing it after, however, creates the problem of the NMI
499 * handler seeing STARTED but not having a valid sample.
500 */
501 clear_bit(IBS_STARTED, pcpu->state);
502 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
503 hwc->state |= PERF_HES_STOPPED;
504 }
505
506 if (hwc->state & PERF_HES_UPTODATE)
507 return;
508
509 /*
510 * Clear valid bit to not count rollovers on update, rollovers
511 * are only updated in the irq handler.
512 */
513 config &= ~perf_ibs->valid_mask;
514
515 perf_ibs_event_update(perf_ibs, event, &config);
516 hwc->state |= PERF_HES_UPTODATE;
517 }
518
perf_ibs_add(struct perf_event * event,int flags)519 static int perf_ibs_add(struct perf_event *event, int flags)
520 {
521 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
522 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
523
524 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
525 return -ENOSPC;
526
527 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
528
529 pcpu->event = event;
530
531 if (flags & PERF_EF_START)
532 perf_ibs_start(event, PERF_EF_RELOAD);
533
534 return 0;
535 }
536
perf_ibs_del(struct perf_event * event,int flags)537 static void perf_ibs_del(struct perf_event *event, int flags)
538 {
539 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
540 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
541
542 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
543 return;
544
545 perf_ibs_stop(event, PERF_EF_UPDATE);
546
547 pcpu->event = NULL;
548
549 perf_event_update_userpage(event);
550 }
551
perf_ibs_read(struct perf_event * event)552 static void perf_ibs_read(struct perf_event *event) { }
553
554 /*
555 * We need to initialize with empty group if all attributes in the
556 * group are dynamic.
557 */
558 static struct attribute *attrs_empty[] = {
559 NULL,
560 };
561
562 static struct attribute_group empty_format_group = {
563 .name = "format",
564 .attrs = attrs_empty,
565 };
566
567 static struct attribute_group empty_caps_group = {
568 .name = "caps",
569 .attrs = attrs_empty,
570 };
571
572 static const struct attribute_group *empty_attr_groups[] = {
573 &empty_format_group,
574 &empty_caps_group,
575 NULL,
576 };
577
578 PMU_FORMAT_ATTR(rand_en, "config:57");
579 PMU_FORMAT_ATTR(cnt_ctl, "config:19");
580 PMU_EVENT_ATTR_STRING(l3missonly, fetch_l3missonly, "config:59");
581 PMU_EVENT_ATTR_STRING(l3missonly, op_l3missonly, "config:16");
582 PMU_EVENT_ATTR_STRING(zen4_ibs_extensions, zen4_ibs_extensions, "1");
583
584 static umode_t
zen4_ibs_extensions_is_visible(struct kobject * kobj,struct attribute * attr,int i)585 zen4_ibs_extensions_is_visible(struct kobject *kobj, struct attribute *attr, int i)
586 {
587 return ibs_caps & IBS_CAPS_ZEN4 ? attr->mode : 0;
588 }
589
590 static struct attribute *rand_en_attrs[] = {
591 &format_attr_rand_en.attr,
592 NULL,
593 };
594
595 static struct attribute *fetch_l3missonly_attrs[] = {
596 &fetch_l3missonly.attr.attr,
597 NULL,
598 };
599
600 static struct attribute *zen4_ibs_extensions_attrs[] = {
601 &zen4_ibs_extensions.attr.attr,
602 NULL,
603 };
604
605 static struct attribute_group group_rand_en = {
606 .name = "format",
607 .attrs = rand_en_attrs,
608 };
609
610 static struct attribute_group group_fetch_l3missonly = {
611 .name = "format",
612 .attrs = fetch_l3missonly_attrs,
613 .is_visible = zen4_ibs_extensions_is_visible,
614 };
615
616 static struct attribute_group group_zen4_ibs_extensions = {
617 .name = "caps",
618 .attrs = zen4_ibs_extensions_attrs,
619 .is_visible = zen4_ibs_extensions_is_visible,
620 };
621
622 static const struct attribute_group *fetch_attr_groups[] = {
623 &group_rand_en,
624 &empty_caps_group,
625 NULL,
626 };
627
628 static const struct attribute_group *fetch_attr_update[] = {
629 &group_fetch_l3missonly,
630 &group_zen4_ibs_extensions,
631 NULL,
632 };
633
634 static umode_t
cnt_ctl_is_visible(struct kobject * kobj,struct attribute * attr,int i)635 cnt_ctl_is_visible(struct kobject *kobj, struct attribute *attr, int i)
636 {
637 return ibs_caps & IBS_CAPS_OPCNT ? attr->mode : 0;
638 }
639
640 static struct attribute *cnt_ctl_attrs[] = {
641 &format_attr_cnt_ctl.attr,
642 NULL,
643 };
644
645 static struct attribute *op_l3missonly_attrs[] = {
646 &op_l3missonly.attr.attr,
647 NULL,
648 };
649
650 static struct attribute_group group_cnt_ctl = {
651 .name = "format",
652 .attrs = cnt_ctl_attrs,
653 .is_visible = cnt_ctl_is_visible,
654 };
655
656 static struct attribute_group group_op_l3missonly = {
657 .name = "format",
658 .attrs = op_l3missonly_attrs,
659 .is_visible = zen4_ibs_extensions_is_visible,
660 };
661
662 static const struct attribute_group *op_attr_update[] = {
663 &group_cnt_ctl,
664 &group_op_l3missonly,
665 &group_zen4_ibs_extensions,
666 NULL,
667 };
668
669 static struct perf_ibs perf_ibs_fetch = {
670 .pmu = {
671 .task_ctx_nr = perf_hw_context,
672
673 .event_init = perf_ibs_init,
674 .add = perf_ibs_add,
675 .del = perf_ibs_del,
676 .start = perf_ibs_start,
677 .stop = perf_ibs_stop,
678 .read = perf_ibs_read,
679 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
680 },
681 .msr = MSR_AMD64_IBSFETCHCTL,
682 .config_mask = IBS_FETCH_CONFIG_MASK,
683 .cnt_mask = IBS_FETCH_MAX_CNT,
684 .enable_mask = IBS_FETCH_ENABLE,
685 .valid_mask = IBS_FETCH_VAL,
686 .max_period = IBS_FETCH_MAX_CNT << 4,
687 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
688 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
689
690 .get_count = get_ibs_fetch_count,
691 };
692
693 static struct perf_ibs perf_ibs_op = {
694 .pmu = {
695 .task_ctx_nr = perf_hw_context,
696
697 .event_init = perf_ibs_init,
698 .add = perf_ibs_add,
699 .del = perf_ibs_del,
700 .start = perf_ibs_start,
701 .stop = perf_ibs_stop,
702 .read = perf_ibs_read,
703 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
704 },
705 .msr = MSR_AMD64_IBSOPCTL,
706 .config_mask = IBS_OP_CONFIG_MASK,
707 .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
708 IBS_OP_CUR_CNT_RAND,
709 .enable_mask = IBS_OP_ENABLE,
710 .valid_mask = IBS_OP_VAL,
711 .max_period = IBS_OP_MAX_CNT << 4,
712 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
713 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
714
715 .get_count = get_ibs_op_count,
716 };
717
perf_ibs_get_mem_op(union ibs_op_data3 * op_data3,struct perf_sample_data * data)718 static void perf_ibs_get_mem_op(union ibs_op_data3 *op_data3,
719 struct perf_sample_data *data)
720 {
721 union perf_mem_data_src *data_src = &data->data_src;
722
723 data_src->mem_op = PERF_MEM_OP_NA;
724
725 if (op_data3->ld_op)
726 data_src->mem_op = PERF_MEM_OP_LOAD;
727 else if (op_data3->st_op)
728 data_src->mem_op = PERF_MEM_OP_STORE;
729 }
730
731 /*
732 * Processors having CPUID_Fn8000001B_EAX[11] aka IBS_CAPS_ZEN4 has
733 * more fine granular DataSrc encodings. Others have coarse.
734 */
perf_ibs_data_src(union ibs_op_data2 * op_data2)735 static u8 perf_ibs_data_src(union ibs_op_data2 *op_data2)
736 {
737 if (ibs_caps & IBS_CAPS_ZEN4)
738 return (op_data2->data_src_hi << 3) | op_data2->data_src_lo;
739
740 return op_data2->data_src_lo;
741 }
742
743 #define L(x) (PERF_MEM_S(LVL, x) | PERF_MEM_S(LVL, HIT))
744 #define LN(x) PERF_MEM_S(LVLNUM, x)
745 #define REM PERF_MEM_S(REMOTE, REMOTE)
746 #define HOPS(x) PERF_MEM_S(HOPS, x)
747
748 static u64 g_data_src[8] = {
749 [IBS_DATA_SRC_LOC_CACHE] = L(L3) | L(REM_CCE1) | LN(ANY_CACHE) | HOPS(0),
750 [IBS_DATA_SRC_DRAM] = L(LOC_RAM) | LN(RAM),
751 [IBS_DATA_SRC_REM_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
752 [IBS_DATA_SRC_IO] = L(IO) | LN(IO),
753 };
754
755 #define RMT_NODE_BITS (1 << IBS_DATA_SRC_DRAM)
756 #define RMT_NODE_APPLICABLE(x) (RMT_NODE_BITS & (1 << x))
757
758 static u64 g_zen4_data_src[32] = {
759 [IBS_DATA_SRC_EXT_LOC_CACHE] = L(L3) | LN(L3),
760 [IBS_DATA_SRC_EXT_NEAR_CCX_CACHE] = L(REM_CCE1) | LN(ANY_CACHE) | REM | HOPS(0),
761 [IBS_DATA_SRC_EXT_DRAM] = L(LOC_RAM) | LN(RAM),
762 [IBS_DATA_SRC_EXT_FAR_CCX_CACHE] = L(REM_CCE2) | LN(ANY_CACHE) | REM | HOPS(1),
763 [IBS_DATA_SRC_EXT_PMEM] = LN(PMEM),
764 [IBS_DATA_SRC_EXT_IO] = L(IO) | LN(IO),
765 [IBS_DATA_SRC_EXT_EXT_MEM] = LN(CXL),
766 };
767
768 #define ZEN4_RMT_NODE_BITS ((1 << IBS_DATA_SRC_EXT_DRAM) | \
769 (1 << IBS_DATA_SRC_EXT_PMEM) | \
770 (1 << IBS_DATA_SRC_EXT_EXT_MEM))
771 #define ZEN4_RMT_NODE_APPLICABLE(x) (ZEN4_RMT_NODE_BITS & (1 << x))
772
perf_ibs_get_mem_lvl(union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3,struct perf_sample_data * data)773 static __u64 perf_ibs_get_mem_lvl(union ibs_op_data2 *op_data2,
774 union ibs_op_data3 *op_data3,
775 struct perf_sample_data *data)
776 {
777 union perf_mem_data_src *data_src = &data->data_src;
778 u8 ibs_data_src = perf_ibs_data_src(op_data2);
779
780 data_src->mem_lvl = 0;
781 data_src->mem_lvl_num = 0;
782
783 /*
784 * DcMiss, L2Miss, DataSrc, DcMissLat etc. are all invalid for Uncached
785 * memory accesses. So, check DcUcMemAcc bit early.
786 */
787 if (op_data3->dc_uc_mem_acc && ibs_data_src != IBS_DATA_SRC_EXT_IO)
788 return L(UNC) | LN(UNC);
789
790 /* L1 Hit */
791 if (op_data3->dc_miss == 0)
792 return L(L1) | LN(L1);
793
794 /* L2 Hit */
795 if (op_data3->l2_miss == 0) {
796 /* Erratum #1293 */
797 if (boot_cpu_data.x86 != 0x19 || boot_cpu_data.x86_model > 0xF ||
798 !(op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc))
799 return L(L2) | LN(L2);
800 }
801
802 /*
803 * OP_DATA2 is valid only for load ops. Skip all checks which
804 * uses OP_DATA2[DataSrc].
805 */
806 if (data_src->mem_op != PERF_MEM_OP_LOAD)
807 goto check_mab;
808
809 if (ibs_caps & IBS_CAPS_ZEN4) {
810 u64 val = g_zen4_data_src[ibs_data_src];
811
812 if (!val)
813 goto check_mab;
814
815 /* HOPS_1 because IBS doesn't provide remote socket detail */
816 if (op_data2->rmt_node && ZEN4_RMT_NODE_APPLICABLE(ibs_data_src)) {
817 if (ibs_data_src == IBS_DATA_SRC_EXT_DRAM)
818 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
819 else
820 val |= REM | HOPS(1);
821 }
822
823 return val;
824 } else {
825 u64 val = g_data_src[ibs_data_src];
826
827 if (!val)
828 goto check_mab;
829
830 /* HOPS_1 because IBS doesn't provide remote socket detail */
831 if (op_data2->rmt_node && RMT_NODE_APPLICABLE(ibs_data_src)) {
832 if (ibs_data_src == IBS_DATA_SRC_DRAM)
833 val = L(REM_RAM1) | LN(RAM) | REM | HOPS(1);
834 else
835 val |= REM | HOPS(1);
836 }
837
838 return val;
839 }
840
841 check_mab:
842 /*
843 * MAB (Miss Address Buffer) Hit. MAB keeps track of outstanding
844 * DC misses. However, such data may come from any level in mem
845 * hierarchy. IBS provides detail about both MAB as well as actual
846 * DataSrc simultaneously. Prioritize DataSrc over MAB, i.e. set
847 * MAB only when IBS fails to provide DataSrc.
848 */
849 if (op_data3->dc_miss_no_mab_alloc)
850 return L(LFB) | LN(LFB);
851
852 /* Don't set HIT with NA */
853 return PERF_MEM_S(LVL, NA) | LN(NA);
854 }
855
perf_ibs_cache_hit_st_valid(void)856 static bool perf_ibs_cache_hit_st_valid(void)
857 {
858 /* 0: Uninitialized, 1: Valid, -1: Invalid */
859 static int cache_hit_st_valid;
860
861 if (unlikely(!cache_hit_st_valid)) {
862 if (boot_cpu_data.x86 == 0x19 &&
863 (boot_cpu_data.x86_model <= 0xF ||
864 (boot_cpu_data.x86_model >= 0x20 &&
865 boot_cpu_data.x86_model <= 0x5F))) {
866 cache_hit_st_valid = -1;
867 } else {
868 cache_hit_st_valid = 1;
869 }
870 }
871
872 return cache_hit_st_valid == 1;
873 }
874
perf_ibs_get_mem_snoop(union ibs_op_data2 * op_data2,struct perf_sample_data * data)875 static void perf_ibs_get_mem_snoop(union ibs_op_data2 *op_data2,
876 struct perf_sample_data *data)
877 {
878 union perf_mem_data_src *data_src = &data->data_src;
879 u8 ibs_data_src;
880
881 data_src->mem_snoop = PERF_MEM_SNOOP_NA;
882
883 if (!perf_ibs_cache_hit_st_valid() ||
884 data_src->mem_op != PERF_MEM_OP_LOAD ||
885 data_src->mem_lvl & PERF_MEM_LVL_L1 ||
886 data_src->mem_lvl & PERF_MEM_LVL_L2 ||
887 op_data2->cache_hit_st)
888 return;
889
890 ibs_data_src = perf_ibs_data_src(op_data2);
891
892 if (ibs_caps & IBS_CAPS_ZEN4) {
893 if (ibs_data_src == IBS_DATA_SRC_EXT_LOC_CACHE ||
894 ibs_data_src == IBS_DATA_SRC_EXT_NEAR_CCX_CACHE ||
895 ibs_data_src == IBS_DATA_SRC_EXT_FAR_CCX_CACHE)
896 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
897 } else if (ibs_data_src == IBS_DATA_SRC_LOC_CACHE) {
898 data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
899 }
900 }
901
perf_ibs_get_tlb_lvl(union ibs_op_data3 * op_data3,struct perf_sample_data * data)902 static void perf_ibs_get_tlb_lvl(union ibs_op_data3 *op_data3,
903 struct perf_sample_data *data)
904 {
905 union perf_mem_data_src *data_src = &data->data_src;
906
907 data_src->mem_dtlb = PERF_MEM_TLB_NA;
908
909 if (!op_data3->dc_lin_addr_valid)
910 return;
911
912 if (!op_data3->dc_l1tlb_miss) {
913 data_src->mem_dtlb = PERF_MEM_TLB_L1 | PERF_MEM_TLB_HIT;
914 return;
915 }
916
917 if (!op_data3->dc_l2tlb_miss) {
918 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_HIT;
919 return;
920 }
921
922 data_src->mem_dtlb = PERF_MEM_TLB_L2 | PERF_MEM_TLB_MISS;
923 }
924
perf_ibs_get_mem_lock(union ibs_op_data3 * op_data3,struct perf_sample_data * data)925 static void perf_ibs_get_mem_lock(union ibs_op_data3 *op_data3,
926 struct perf_sample_data *data)
927 {
928 union perf_mem_data_src *data_src = &data->data_src;
929
930 data_src->mem_lock = PERF_MEM_LOCK_NA;
931
932 if (op_data3->dc_locked_op)
933 data_src->mem_lock = PERF_MEM_LOCK_LOCKED;
934 }
935
936 #define ibs_op_msr_idx(msr) (msr - MSR_AMD64_IBSOPCTL)
937
perf_ibs_get_data_src(struct perf_ibs_data * ibs_data,struct perf_sample_data * data,union ibs_op_data2 * op_data2,union ibs_op_data3 * op_data3)938 static void perf_ibs_get_data_src(struct perf_ibs_data *ibs_data,
939 struct perf_sample_data *data,
940 union ibs_op_data2 *op_data2,
941 union ibs_op_data3 *op_data3)
942 {
943 union perf_mem_data_src *data_src = &data->data_src;
944
945 data_src->val |= perf_ibs_get_mem_lvl(op_data2, op_data3, data);
946 perf_ibs_get_mem_snoop(op_data2, data);
947 perf_ibs_get_tlb_lvl(op_data3, data);
948 perf_ibs_get_mem_lock(op_data3, data);
949 }
950
perf_ibs_get_op_data2(struct perf_ibs_data * ibs_data,union ibs_op_data3 * op_data3)951 static __u64 perf_ibs_get_op_data2(struct perf_ibs_data *ibs_data,
952 union ibs_op_data3 *op_data3)
953 {
954 __u64 val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA2)];
955
956 /* Erratum #1293 */
957 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model <= 0xF &&
958 (op_data3->sw_pf || op_data3->dc_miss_no_mab_alloc)) {
959 /*
960 * OP_DATA2 has only two fields on Zen3: DataSrc and RmtNode.
961 * DataSrc=0 is 'No valid status' and RmtNode is invalid when
962 * DataSrc=0.
963 */
964 val = 0;
965 }
966 return val;
967 }
968
perf_ibs_parse_ld_st_data(__u64 sample_type,struct perf_ibs_data * ibs_data,struct perf_sample_data * data)969 static void perf_ibs_parse_ld_st_data(__u64 sample_type,
970 struct perf_ibs_data *ibs_data,
971 struct perf_sample_data *data)
972 {
973 union ibs_op_data3 op_data3;
974 union ibs_op_data2 op_data2;
975 union ibs_op_data op_data;
976
977 data->data_src.val = PERF_MEM_NA;
978 op_data3.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA3)];
979
980 perf_ibs_get_mem_op(&op_data3, data);
981 if (data->data_src.mem_op != PERF_MEM_OP_LOAD &&
982 data->data_src.mem_op != PERF_MEM_OP_STORE)
983 return;
984
985 op_data2.val = perf_ibs_get_op_data2(ibs_data, &op_data3);
986
987 if (sample_type & PERF_SAMPLE_DATA_SRC) {
988 perf_ibs_get_data_src(ibs_data, data, &op_data2, &op_data3);
989 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
990 }
991
992 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE && op_data3.dc_miss &&
993 data->data_src.mem_op == PERF_MEM_OP_LOAD) {
994 op_data.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA)];
995
996 if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
997 data->weight.var1_dw = op_data3.dc_miss_lat;
998 data->weight.var2_w = op_data.tag_to_ret_ctr;
999 } else if (sample_type & PERF_SAMPLE_WEIGHT) {
1000 data->weight.full = op_data3.dc_miss_lat;
1001 }
1002 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1003 }
1004
1005 if (sample_type & PERF_SAMPLE_ADDR && op_data3.dc_lin_addr_valid) {
1006 data->addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCLINAD)];
1007 data->sample_flags |= PERF_SAMPLE_ADDR;
1008 }
1009
1010 if (sample_type & PERF_SAMPLE_PHYS_ADDR && op_data3.dc_phy_addr_valid) {
1011 data->phys_addr = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSDCPHYSAD)];
1012 data->sample_flags |= PERF_SAMPLE_PHYS_ADDR;
1013 }
1014 }
1015
perf_ibs_get_offset_max(struct perf_ibs * perf_ibs,u64 sample_type,int check_rip)1016 static int perf_ibs_get_offset_max(struct perf_ibs *perf_ibs, u64 sample_type,
1017 int check_rip)
1018 {
1019 if (sample_type & PERF_SAMPLE_RAW ||
1020 (perf_ibs == &perf_ibs_op &&
1021 (sample_type & PERF_SAMPLE_DATA_SRC ||
1022 sample_type & PERF_SAMPLE_WEIGHT_TYPE ||
1023 sample_type & PERF_SAMPLE_ADDR ||
1024 sample_type & PERF_SAMPLE_PHYS_ADDR)))
1025 return perf_ibs->offset_max;
1026 else if (check_rip)
1027 return 3;
1028 return 1;
1029 }
1030
perf_ibs_handle_irq(struct perf_ibs * perf_ibs,struct pt_regs * iregs)1031 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
1032 {
1033 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
1034 struct perf_event *event = pcpu->event;
1035 struct hw_perf_event *hwc;
1036 struct perf_sample_data data;
1037 struct perf_raw_record raw;
1038 struct pt_regs regs;
1039 struct perf_ibs_data ibs_data;
1040 int offset, size, check_rip, offset_max, throttle = 0;
1041 unsigned int msr;
1042 u64 *buf, *config, period, new_config = 0;
1043
1044 if (!test_bit(IBS_STARTED, pcpu->state)) {
1045 fail:
1046 /*
1047 * Catch spurious interrupts after stopping IBS: After
1048 * disabling IBS there could be still incoming NMIs
1049 * with samples that even have the valid bit cleared.
1050 * Mark all this NMIs as handled.
1051 */
1052 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
1053 return 1;
1054
1055 return 0;
1056 }
1057
1058 if (WARN_ON_ONCE(!event))
1059 goto fail;
1060
1061 hwc = &event->hw;
1062 msr = hwc->config_base;
1063 buf = ibs_data.regs;
1064 rdmsrl(msr, *buf);
1065 if (!(*buf++ & perf_ibs->valid_mask))
1066 goto fail;
1067
1068 config = &ibs_data.regs[0];
1069 perf_ibs_event_update(perf_ibs, event, config);
1070 perf_sample_data_init(&data, 0, hwc->last_period);
1071 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
1072 goto out; /* no sw counter overflow */
1073
1074 ibs_data.caps = ibs_caps;
1075 size = 1;
1076 offset = 1;
1077 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
1078
1079 offset_max = perf_ibs_get_offset_max(perf_ibs, event->attr.sample_type, check_rip);
1080
1081 do {
1082 rdmsrl(msr + offset, *buf++);
1083 size++;
1084 offset = find_next_bit(perf_ibs->offset_mask,
1085 perf_ibs->offset_max,
1086 offset + 1);
1087 } while (offset < offset_max);
1088 /*
1089 * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately
1090 * depending on their availability.
1091 * Can't add to offset_max as they are staggered
1092 */
1093 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1094 if (perf_ibs == &perf_ibs_op) {
1095 if (ibs_caps & IBS_CAPS_BRNTRGT) {
1096 rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
1097 size++;
1098 }
1099 if (ibs_caps & IBS_CAPS_OPDATA4) {
1100 rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
1101 size++;
1102 }
1103 }
1104 if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
1105 rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);
1106 size++;
1107 }
1108 }
1109 ibs_data.size = sizeof(u64) * size;
1110
1111 regs = *iregs;
1112 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
1113 regs.flags &= ~PERF_EFLAGS_EXACT;
1114 } else {
1115 /* Workaround for erratum #1197 */
1116 if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))
1117 goto out;
1118
1119 set_linear_ip(®s, ibs_data.regs[1]);
1120 regs.flags |= PERF_EFLAGS_EXACT;
1121 }
1122
1123 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
1124 raw = (struct perf_raw_record){
1125 .frag = {
1126 .size = sizeof(u32) + ibs_data.size,
1127 .data = ibs_data.data,
1128 },
1129 };
1130 perf_sample_save_raw_data(&data, event, &raw);
1131 }
1132
1133 if (perf_ibs == &perf_ibs_op)
1134 perf_ibs_parse_ld_st_data(event->attr.sample_type, &ibs_data, &data);
1135
1136 /*
1137 * rip recorded by IbsOpRip will not be consistent with rsp and rbp
1138 * recorded as part of interrupt regs. Thus we need to use rip from
1139 * interrupt regs while unwinding call stack.
1140 */
1141 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
1142 perf_sample_save_callchain(&data, event, iregs);
1143
1144 throttle = perf_event_overflow(event, &data, ®s);
1145 out:
1146 if (throttle) {
1147 perf_ibs_stop(event, 0);
1148 } else {
1149 if (perf_ibs == &perf_ibs_op) {
1150 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1151 new_config = period & IBS_OP_MAX_CNT_EXT_MASK;
1152 period &= ~IBS_OP_MAX_CNT_EXT_MASK;
1153 }
1154 if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))
1155 new_config |= *config & IBS_OP_CUR_CNT_RAND;
1156 }
1157 new_config |= period >> 4;
1158
1159 perf_ibs_enable_event(perf_ibs, hwc, new_config);
1160 }
1161
1162 perf_event_update_userpage(event);
1163
1164 return 1;
1165 }
1166
1167 static int
perf_ibs_nmi_handler(unsigned int cmd,struct pt_regs * regs)1168 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1169 {
1170 u64 stamp = sched_clock();
1171 int handled = 0;
1172
1173 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
1174 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
1175
1176 if (handled)
1177 inc_irq_stat(apic_perf_irqs);
1178
1179 perf_sample_event_took(sched_clock() - stamp);
1180
1181 return handled;
1182 }
1183 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
1184
perf_ibs_pmu_init(struct perf_ibs * perf_ibs,char * name)1185 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
1186 {
1187 struct cpu_perf_ibs __percpu *pcpu;
1188 int ret;
1189
1190 pcpu = alloc_percpu(struct cpu_perf_ibs);
1191 if (!pcpu)
1192 return -ENOMEM;
1193
1194 perf_ibs->pcpu = pcpu;
1195
1196 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
1197 if (ret) {
1198 perf_ibs->pcpu = NULL;
1199 free_percpu(pcpu);
1200 }
1201
1202 return ret;
1203 }
1204
perf_ibs_fetch_init(void)1205 static __init int perf_ibs_fetch_init(void)
1206 {
1207 /*
1208 * Some chips fail to reset the fetch count when it is written; instead
1209 * they need a 0-1 transition of IbsFetchEn.
1210 */
1211 if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)
1212 perf_ibs_fetch.fetch_count_reset_broken = 1;
1213
1214 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
1215 perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
1216
1217 if (ibs_caps & IBS_CAPS_ZEN4)
1218 perf_ibs_fetch.config_mask |= IBS_FETCH_L3MISSONLY;
1219
1220 perf_ibs_fetch.pmu.attr_groups = fetch_attr_groups;
1221 perf_ibs_fetch.pmu.attr_update = fetch_attr_update;
1222
1223 return perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
1224 }
1225
perf_ibs_op_init(void)1226 static __init int perf_ibs_op_init(void)
1227 {
1228 if (ibs_caps & IBS_CAPS_OPCNT)
1229 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
1230
1231 if (ibs_caps & IBS_CAPS_OPCNTEXT) {
1232 perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK;
1233 perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK;
1234 perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK |
1235 IBS_OP_CUR_CNT_EXT_MASK);
1236 }
1237
1238 if (ibs_caps & IBS_CAPS_ZEN4)
1239 perf_ibs_op.config_mask |= IBS_OP_L3MISSONLY;
1240
1241 perf_ibs_op.pmu.attr_groups = empty_attr_groups;
1242 perf_ibs_op.pmu.attr_update = op_attr_update;
1243
1244 return perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
1245 }
1246
perf_event_ibs_init(void)1247 static __init int perf_event_ibs_init(void)
1248 {
1249 int ret;
1250
1251 ret = perf_ibs_fetch_init();
1252 if (ret)
1253 return ret;
1254
1255 ret = perf_ibs_op_init();
1256 if (ret)
1257 goto err_op;
1258
1259 ret = register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
1260 if (ret)
1261 goto err_nmi;
1262
1263 pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
1264 return 0;
1265
1266 err_nmi:
1267 perf_pmu_unregister(&perf_ibs_op.pmu);
1268 free_percpu(perf_ibs_op.pcpu);
1269 perf_ibs_op.pcpu = NULL;
1270 err_op:
1271 perf_pmu_unregister(&perf_ibs_fetch.pmu);
1272 free_percpu(perf_ibs_fetch.pcpu);
1273 perf_ibs_fetch.pcpu = NULL;
1274
1275 return ret;
1276 }
1277
1278 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
1279
perf_event_ibs_init(void)1280 static __init int perf_event_ibs_init(void)
1281 {
1282 return 0;
1283 }
1284
1285 #endif
1286
1287 /* IBS - apic initialization, for perf and oprofile */
1288
__get_ibs_caps(void)1289 static __init u32 __get_ibs_caps(void)
1290 {
1291 u32 caps;
1292 unsigned int max_level;
1293
1294 if (!boot_cpu_has(X86_FEATURE_IBS))
1295 return 0;
1296
1297 /* check IBS cpuid feature flags */
1298 max_level = cpuid_eax(0x80000000);
1299 if (max_level < IBS_CPUID_FEATURES)
1300 return IBS_CAPS_DEFAULT;
1301
1302 caps = cpuid_eax(IBS_CPUID_FEATURES);
1303 if (!(caps & IBS_CAPS_AVAIL))
1304 /* cpuid flags not valid */
1305 return IBS_CAPS_DEFAULT;
1306
1307 return caps;
1308 }
1309
get_ibs_caps(void)1310 u32 get_ibs_caps(void)
1311 {
1312 return ibs_caps;
1313 }
1314
1315 EXPORT_SYMBOL(get_ibs_caps);
1316
get_eilvt(int offset)1317 static inline int get_eilvt(int offset)
1318 {
1319 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
1320 }
1321
put_eilvt(int offset)1322 static inline int put_eilvt(int offset)
1323 {
1324 return !setup_APIC_eilvt(offset, 0, 0, 1);
1325 }
1326
1327 /*
1328 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
1329 */
ibs_eilvt_valid(void)1330 static inline int ibs_eilvt_valid(void)
1331 {
1332 int offset;
1333 u64 val;
1334 int valid = 0;
1335
1336 preempt_disable();
1337
1338 rdmsrl(MSR_AMD64_IBSCTL, val);
1339 offset = val & IBSCTL_LVT_OFFSET_MASK;
1340
1341 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
1342 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
1343 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1344 goto out;
1345 }
1346
1347 if (!get_eilvt(offset)) {
1348 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
1349 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
1350 goto out;
1351 }
1352
1353 valid = 1;
1354 out:
1355 preempt_enable();
1356
1357 return valid;
1358 }
1359
setup_ibs_ctl(int ibs_eilvt_off)1360 static int setup_ibs_ctl(int ibs_eilvt_off)
1361 {
1362 struct pci_dev *cpu_cfg;
1363 int nodes;
1364 u32 value = 0;
1365
1366 nodes = 0;
1367 cpu_cfg = NULL;
1368 do {
1369 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
1370 PCI_DEVICE_ID_AMD_10H_NB_MISC,
1371 cpu_cfg);
1372 if (!cpu_cfg)
1373 break;
1374 ++nodes;
1375 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
1376 | IBSCTL_LVT_OFFSET_VALID);
1377 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
1378 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
1379 pci_dev_put(cpu_cfg);
1380 pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
1381 value);
1382 return -EINVAL;
1383 }
1384 } while (1);
1385
1386 if (!nodes) {
1387 pr_debug("No CPU node configured for IBS\n");
1388 return -ENODEV;
1389 }
1390
1391 return 0;
1392 }
1393
1394 /*
1395 * This runs only on the current cpu. We try to find an LVT offset and
1396 * setup the local APIC. For this we must disable preemption. On
1397 * success we initialize all nodes with this offset. This updates then
1398 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
1399 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
1400 * is using the new offset.
1401 */
force_ibs_eilvt_setup(void)1402 static void force_ibs_eilvt_setup(void)
1403 {
1404 int offset;
1405 int ret;
1406
1407 preempt_disable();
1408 /* find the next free available EILVT entry, skip offset 0 */
1409 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
1410 if (get_eilvt(offset))
1411 break;
1412 }
1413 preempt_enable();
1414
1415 if (offset == APIC_EILVT_NR_MAX) {
1416 pr_debug("No EILVT entry available\n");
1417 return;
1418 }
1419
1420 ret = setup_ibs_ctl(offset);
1421 if (ret)
1422 goto out;
1423
1424 if (!ibs_eilvt_valid())
1425 goto out;
1426
1427 pr_info("LVT offset %d assigned\n", offset);
1428
1429 return;
1430 out:
1431 preempt_disable();
1432 put_eilvt(offset);
1433 preempt_enable();
1434 return;
1435 }
1436
ibs_eilvt_setup(void)1437 static void ibs_eilvt_setup(void)
1438 {
1439 /*
1440 * Force LVT offset assignment for family 10h: The offsets are
1441 * not assigned by the BIOS for this family, so the OS is
1442 * responsible for doing it. If the OS assignment fails, fall
1443 * back to BIOS settings and try to setup this.
1444 */
1445 if (boot_cpu_data.x86 == 0x10)
1446 force_ibs_eilvt_setup();
1447 }
1448
get_ibs_lvt_offset(void)1449 static inline int get_ibs_lvt_offset(void)
1450 {
1451 u64 val;
1452
1453 rdmsrl(MSR_AMD64_IBSCTL, val);
1454 if (!(val & IBSCTL_LVT_OFFSET_VALID))
1455 return -EINVAL;
1456
1457 return val & IBSCTL_LVT_OFFSET_MASK;
1458 }
1459
setup_APIC_ibs(void)1460 static void setup_APIC_ibs(void)
1461 {
1462 int offset;
1463
1464 offset = get_ibs_lvt_offset();
1465 if (offset < 0)
1466 goto failed;
1467
1468 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
1469 return;
1470 failed:
1471 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
1472 smp_processor_id());
1473 }
1474
clear_APIC_ibs(void)1475 static void clear_APIC_ibs(void)
1476 {
1477 int offset;
1478
1479 offset = get_ibs_lvt_offset();
1480 if (offset >= 0)
1481 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
1482 }
1483
x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)1484 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
1485 {
1486 setup_APIC_ibs();
1487 return 0;
1488 }
1489
1490 #ifdef CONFIG_PM
1491
perf_ibs_suspend(void)1492 static int perf_ibs_suspend(void)
1493 {
1494 clear_APIC_ibs();
1495 return 0;
1496 }
1497
perf_ibs_resume(void)1498 static void perf_ibs_resume(void)
1499 {
1500 ibs_eilvt_setup();
1501 setup_APIC_ibs();
1502 }
1503
1504 static struct syscore_ops perf_ibs_syscore_ops = {
1505 .resume = perf_ibs_resume,
1506 .suspend = perf_ibs_suspend,
1507 };
1508
perf_ibs_pm_init(void)1509 static void perf_ibs_pm_init(void)
1510 {
1511 register_syscore_ops(&perf_ibs_syscore_ops);
1512 }
1513
1514 #else
1515
perf_ibs_pm_init(void)1516 static inline void perf_ibs_pm_init(void) { }
1517
1518 #endif
1519
x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)1520 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
1521 {
1522 clear_APIC_ibs();
1523 return 0;
1524 }
1525
amd_ibs_init(void)1526 static __init int amd_ibs_init(void)
1527 {
1528 u32 caps;
1529
1530 caps = __get_ibs_caps();
1531 if (!caps)
1532 return -ENODEV; /* ibs not supported by the cpu */
1533
1534 ibs_eilvt_setup();
1535
1536 if (!ibs_eilvt_valid())
1537 return -EINVAL;
1538
1539 perf_ibs_pm_init();
1540
1541 ibs_caps = caps;
1542 /* make ibs_caps visible to other cpus: */
1543 smp_mb();
1544 /*
1545 * x86_pmu_amd_ibs_starting_cpu will be called from core on
1546 * all online cpus.
1547 */
1548 cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1549 "perf/x86/amd/ibs:starting",
1550 x86_pmu_amd_ibs_starting_cpu,
1551 x86_pmu_amd_ibs_dying_cpu);
1552
1553 return perf_event_ibs_init();
1554 }
1555
1556 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1557 device_initcall(amd_ibs_init);
1558