1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26
27 #include "../perf_event.h"
28
29 /*
30 * Intel PerfMon, used on Core and later.
31 */
32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
33 {
34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 };
43
44 static struct event_constraint intel_core_event_constraints[] __read_mostly =
45 {
46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
52 EVENT_CONSTRAINT_END
53 };
54
55 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
56 {
57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
70 EVENT_CONSTRAINT_END
71 };
72
73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
74 {
75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
86 EVENT_CONSTRAINT_END
87 };
88
89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
90 {
91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
94 EVENT_EXTRA_END
95 };
96
97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
98 {
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
106 EVENT_CONSTRAINT_END
107 };
108
109 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
110 {
111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123
124 /*
125 * When HT is off these events can only run on the bottom 4 counters
126 * When HT is on, they are impacted by the HT bug and require EXCL access
127 */
128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
132
133 EVENT_CONSTRAINT_END
134 };
135
136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
137 {
138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151
152 /*
153 * When HT is off these events can only run on the bottom 4 counters
154 * When HT is on, they are impacted by the HT bug and require EXCL access
155 */
156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
160
161 EVENT_CONSTRAINT_END
162 };
163
164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
165 {
166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
170 EVENT_EXTRA_END
171 };
172
173 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
174 {
175 EVENT_CONSTRAINT_END
176 };
177
178 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
179 {
180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
183 EVENT_CONSTRAINT_END
184 };
185
186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
187 {
188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
192 FIXED_EVENT_CONSTRAINT(0x0500, 4),
193 FIXED_EVENT_CONSTRAINT(0x0600, 5),
194 FIXED_EVENT_CONSTRAINT(0x0700, 6),
195 FIXED_EVENT_CONSTRAINT(0x0800, 7),
196 FIXED_EVENT_CONSTRAINT(0x0900, 8),
197 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
198 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
199 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
200 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
201 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
202 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
203 FIXED_EVENT_CONSTRAINT(0x1000, 15),
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
208 {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
212 EVENT_CONSTRAINT_END
213 };
214
215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
220 EVENT_CONSTRAINT_END
221 };
222
223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
231 EVENT_CONSTRAINT_END
232 };
233
234 static struct event_constraint intel_skl_event_constraints[] = {
235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
239
240 /*
241 * when HT is off, these can only run on the bottom 4 counters
242 */
243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
248
249 EVENT_CONSTRAINT_END
250 };
251
252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
255 EVENT_EXTRA_END
256 };
257
258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
263 EVENT_EXTRA_END
264 };
265
266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
271 EVENT_EXTRA_END
272 };
273
274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
278 /*
279 * Note the low 8 bits eventsel code is not a continuous field, containing
280 * some #GPing bits. These are masked out.
281 */
282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
283 EVENT_EXTRA_END
284 };
285
286 static struct event_constraint intel_icl_event_constraints[] = {
287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
309 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
311 EVENT_CONSTRAINT_END
312 };
313
314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
319 EVENT_EXTRA_END
320 };
321
322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
329 EVENT_EXTRA_END
330 };
331
332 static struct event_constraint intel_glc_event_constraints[] = {
333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
347
348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
350 /*
351 * Generally event codes < 0x90 are restricted to counters 0-3.
352 * The 0x2E and 0x3C are exception, which has no restriction.
353 */
354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
355
356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
362 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
364 /*
365 * Generally event codes >= 0x90 are likely to have no restrictions.
366 * The exception are defined as above.
367 */
368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
369
370 EVENT_CONSTRAINT_END
371 };
372
373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
381 EVENT_EXTRA_END
382 };
383
384 static struct event_constraint intel_lnc_event_constraints[] = {
385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
399
400 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
401
402 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
403 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
404 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
405 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
406
407 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
408 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
409
410 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
411 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
412 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
413 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
414 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
415 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
416 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
417 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
418
419 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
420
421 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
422
423 EVENT_CONSTRAINT_END
424 };
425
426 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
427 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
428 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
429 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
430 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
431 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
432 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
433 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
434 EVENT_EXTRA_END
435 };
436
437 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
438 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
439 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
440
441 static struct attribute *nhm_mem_events_attrs[] = {
442 EVENT_PTR(mem_ld_nhm),
443 NULL,
444 };
445
446 /*
447 * topdown events for Intel Core CPUs.
448 *
449 * The events are all in slots, which is a free slot in a 4 wide
450 * pipeline. Some events are already reported in slots, for cycle
451 * events we multiply by the pipeline width (4).
452 *
453 * With Hyper Threading on, topdown metrics are either summed or averaged
454 * between the threads of a core: (count_t0 + count_t1).
455 *
456 * For the average case the metric is always scaled to pipeline width,
457 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
458 */
459
460 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
461 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
462 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
463 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
464 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
465 "event=0xe,umask=0x1"); /* uops_issued.any */
466 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
467 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
468 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
469 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
470 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
471 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
472 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
473 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
474 "4", "2");
475
476 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
477 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
478 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
479 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
480 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
481 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
482 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
483 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
484 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
485
486 static struct attribute *snb_events_attrs[] = {
487 EVENT_PTR(td_slots_issued),
488 EVENT_PTR(td_slots_retired),
489 EVENT_PTR(td_fetch_bubbles),
490 EVENT_PTR(td_total_slots),
491 EVENT_PTR(td_total_slots_scale),
492 EVENT_PTR(td_recovery_bubbles),
493 EVENT_PTR(td_recovery_bubbles_scale),
494 NULL,
495 };
496
497 static struct attribute *snb_mem_events_attrs[] = {
498 EVENT_PTR(mem_ld_snb),
499 EVENT_PTR(mem_st_snb),
500 NULL,
501 };
502
503 static struct event_constraint intel_hsw_event_constraints[] = {
504 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
505 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
506 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
507 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
508 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
509 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
510 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
511 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
512 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
513 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
514 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
515 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
516
517 /*
518 * When HT is off these events can only run on the bottom 4 counters
519 * When HT is on, they are impacted by the HT bug and require EXCL access
520 */
521 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
522 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
523 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
524 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
525
526 EVENT_CONSTRAINT_END
527 };
528
529 static struct event_constraint intel_bdw_event_constraints[] = {
530 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
531 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
532 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
533 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
534 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
535 /*
536 * when HT is off, these can only run on the bottom 4 counters
537 */
538 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
539 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
540 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
541 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
542 EVENT_CONSTRAINT_END
543 };
544
intel_pmu_event_map(int hw_event)545 static u64 intel_pmu_event_map(int hw_event)
546 {
547 return intel_perfmon_event_map[hw_event];
548 }
549
550 static __initconst const u64 glc_hw_cache_event_ids
551 [PERF_COUNT_HW_CACHE_MAX]
552 [PERF_COUNT_HW_CACHE_OP_MAX]
553 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
554 {
555 [ C(L1D ) ] = {
556 [ C(OP_READ) ] = {
557 [ C(RESULT_ACCESS) ] = 0x81d0,
558 [ C(RESULT_MISS) ] = 0xe124,
559 },
560 [ C(OP_WRITE) ] = {
561 [ C(RESULT_ACCESS) ] = 0x82d0,
562 },
563 },
564 [ C(L1I ) ] = {
565 [ C(OP_READ) ] = {
566 [ C(RESULT_MISS) ] = 0xe424,
567 },
568 [ C(OP_WRITE) ] = {
569 [ C(RESULT_ACCESS) ] = -1,
570 [ C(RESULT_MISS) ] = -1,
571 },
572 },
573 [ C(LL ) ] = {
574 [ C(OP_READ) ] = {
575 [ C(RESULT_ACCESS) ] = 0x12a,
576 [ C(RESULT_MISS) ] = 0x12a,
577 },
578 [ C(OP_WRITE) ] = {
579 [ C(RESULT_ACCESS) ] = 0x12a,
580 [ C(RESULT_MISS) ] = 0x12a,
581 },
582 },
583 [ C(DTLB) ] = {
584 [ C(OP_READ) ] = {
585 [ C(RESULT_ACCESS) ] = 0x81d0,
586 [ C(RESULT_MISS) ] = 0xe12,
587 },
588 [ C(OP_WRITE) ] = {
589 [ C(RESULT_ACCESS) ] = 0x82d0,
590 [ C(RESULT_MISS) ] = 0xe13,
591 },
592 },
593 [ C(ITLB) ] = {
594 [ C(OP_READ) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = 0xe11,
597 },
598 [ C(OP_WRITE) ] = {
599 [ C(RESULT_ACCESS) ] = -1,
600 [ C(RESULT_MISS) ] = -1,
601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = -1,
604 [ C(RESULT_MISS) ] = -1,
605 },
606 },
607 [ C(BPU ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x4c4,
610 [ C(RESULT_MISS) ] = 0x4c5,
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = -1,
618 [ C(RESULT_MISS) ] = -1,
619 },
620 },
621 [ C(NODE) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0x12a,
624 [ C(RESULT_MISS) ] = 0x12a,
625 },
626 },
627 };
628
629 static __initconst const u64 glc_hw_cache_extra_regs
630 [PERF_COUNT_HW_CACHE_MAX]
631 [PERF_COUNT_HW_CACHE_OP_MAX]
632 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
633 {
634 [ C(LL ) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x10001,
637 [ C(RESULT_MISS) ] = 0x3fbfc00001,
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
641 [ C(RESULT_MISS) ] = 0x3f3fc00002,
642 },
643 },
644 [ C(NODE) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_ACCESS) ] = 0x10c000001,
647 [ C(RESULT_MISS) ] = 0x3fb3000001,
648 },
649 },
650 };
651
652 /*
653 * Notes on the events:
654 * - data reads do not include code reads (comparable to earlier tables)
655 * - data counts include speculative execution (except L1 write, dtlb, bpu)
656 * - remote node access includes remote memory, remote cache, remote mmio.
657 * - prefetches are not included in the counts.
658 * - icache miss does not include decoded icache
659 */
660
661 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
662 #define SKL_DEMAND_RFO BIT_ULL(1)
663 #define SKL_ANY_RESPONSE BIT_ULL(16)
664 #define SKL_SUPPLIER_NONE BIT_ULL(17)
665 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
666 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
667 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
668 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
669 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
670 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
671 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
672 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
673 #define SKL_SPL_HIT BIT_ULL(30)
674 #define SKL_SNOOP_NONE BIT_ULL(31)
675 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
676 #define SKL_SNOOP_MISS BIT_ULL(33)
677 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
678 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
679 #define SKL_SNOOP_HITM BIT_ULL(36)
680 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
681 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
682 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
683 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
684 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
685 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
686 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
687 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
688 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
689 SKL_SNOOP_HITM|SKL_SPL_HIT)
690 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
691 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
692 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
693 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
694 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
695
696 static __initconst const u64 skl_hw_cache_event_ids
697 [PERF_COUNT_HW_CACHE_MAX]
698 [PERF_COUNT_HW_CACHE_OP_MAX]
699 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
700 {
701 [ C(L1D ) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
704 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
708 [ C(RESULT_MISS) ] = 0x0,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
713 },
714 },
715 [ C(L1I ) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x0,
718 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = 0x0,
726 [ C(RESULT_MISS) ] = 0x0,
727 },
728 },
729 [ C(LL ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
732 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
736 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = 0x0,
740 [ C(RESULT_MISS) ] = 0x0,
741 },
742 },
743 [ C(DTLB) ] = {
744 [ C(OP_READ) ] = {
745 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
746 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
747 },
748 [ C(OP_WRITE) ] = {
749 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
750 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
751 },
752 [ C(OP_PREFETCH) ] = {
753 [ C(RESULT_ACCESS) ] = 0x0,
754 [ C(RESULT_MISS) ] = 0x0,
755 },
756 },
757 [ C(ITLB) ] = {
758 [ C(OP_READ) ] = {
759 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
760 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
761 },
762 [ C(OP_WRITE) ] = {
763 [ C(RESULT_ACCESS) ] = -1,
764 [ C(RESULT_MISS) ] = -1,
765 },
766 [ C(OP_PREFETCH) ] = {
767 [ C(RESULT_ACCESS) ] = -1,
768 [ C(RESULT_MISS) ] = -1,
769 },
770 },
771 [ C(BPU ) ] = {
772 [ C(OP_READ) ] = {
773 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
774 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
775 },
776 [ C(OP_WRITE) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
779 },
780 [ C(OP_PREFETCH) ] = {
781 [ C(RESULT_ACCESS) ] = -1,
782 [ C(RESULT_MISS) ] = -1,
783 },
784 },
785 [ C(NODE) ] = {
786 [ C(OP_READ) ] = {
787 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
788 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
789 },
790 [ C(OP_WRITE) ] = {
791 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
792 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
793 },
794 [ C(OP_PREFETCH) ] = {
795 [ C(RESULT_ACCESS) ] = 0x0,
796 [ C(RESULT_MISS) ] = 0x0,
797 },
798 },
799 };
800
801 static __initconst const u64 skl_hw_cache_extra_regs
802 [PERF_COUNT_HW_CACHE_MAX]
803 [PERF_COUNT_HW_CACHE_OP_MAX]
804 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
805 {
806 [ C(LL ) ] = {
807 [ C(OP_READ) ] = {
808 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
809 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
810 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
811 SKL_L3_MISS|SKL_ANY_SNOOP|
812 SKL_SUPPLIER_NONE,
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
816 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
817 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
818 SKL_L3_MISS|SKL_ANY_SNOOP|
819 SKL_SUPPLIER_NONE,
820 },
821 [ C(OP_PREFETCH) ] = {
822 [ C(RESULT_ACCESS) ] = 0x0,
823 [ C(RESULT_MISS) ] = 0x0,
824 },
825 },
826 [ C(NODE) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
829 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
830 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
831 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
832 },
833 [ C(OP_WRITE) ] = {
834 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
835 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
837 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
838 },
839 [ C(OP_PREFETCH) ] = {
840 [ C(RESULT_ACCESS) ] = 0x0,
841 [ C(RESULT_MISS) ] = 0x0,
842 },
843 },
844 };
845
846 #define SNB_DMND_DATA_RD (1ULL << 0)
847 #define SNB_DMND_RFO (1ULL << 1)
848 #define SNB_DMND_IFETCH (1ULL << 2)
849 #define SNB_DMND_WB (1ULL << 3)
850 #define SNB_PF_DATA_RD (1ULL << 4)
851 #define SNB_PF_RFO (1ULL << 5)
852 #define SNB_PF_IFETCH (1ULL << 6)
853 #define SNB_LLC_DATA_RD (1ULL << 7)
854 #define SNB_LLC_RFO (1ULL << 8)
855 #define SNB_LLC_IFETCH (1ULL << 9)
856 #define SNB_BUS_LOCKS (1ULL << 10)
857 #define SNB_STRM_ST (1ULL << 11)
858 #define SNB_OTHER (1ULL << 15)
859 #define SNB_RESP_ANY (1ULL << 16)
860 #define SNB_NO_SUPP (1ULL << 17)
861 #define SNB_LLC_HITM (1ULL << 18)
862 #define SNB_LLC_HITE (1ULL << 19)
863 #define SNB_LLC_HITS (1ULL << 20)
864 #define SNB_LLC_HITF (1ULL << 21)
865 #define SNB_LOCAL (1ULL << 22)
866 #define SNB_REMOTE (0xffULL << 23)
867 #define SNB_SNP_NONE (1ULL << 31)
868 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
869 #define SNB_SNP_MISS (1ULL << 33)
870 #define SNB_NO_FWD (1ULL << 34)
871 #define SNB_SNP_FWD (1ULL << 35)
872 #define SNB_HITM (1ULL << 36)
873 #define SNB_NON_DRAM (1ULL << 37)
874
875 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
876 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
877 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
878
879 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
880 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
881 SNB_HITM)
882
883 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
884 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
885
886 #define SNB_L3_ACCESS SNB_RESP_ANY
887 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
888
889 static __initconst const u64 snb_hw_cache_extra_regs
890 [PERF_COUNT_HW_CACHE_MAX]
891 [PERF_COUNT_HW_CACHE_OP_MAX]
892 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
893 {
894 [ C(LL ) ] = {
895 [ C(OP_READ) ] = {
896 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
897 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
898 },
899 [ C(OP_WRITE) ] = {
900 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
901 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
902 },
903 [ C(OP_PREFETCH) ] = {
904 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
905 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
906 },
907 },
908 [ C(NODE) ] = {
909 [ C(OP_READ) ] = {
910 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
911 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
912 },
913 [ C(OP_WRITE) ] = {
914 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
915 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
916 },
917 [ C(OP_PREFETCH) ] = {
918 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
919 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
920 },
921 },
922 };
923
924 static __initconst const u64 snb_hw_cache_event_ids
925 [PERF_COUNT_HW_CACHE_MAX]
926 [PERF_COUNT_HW_CACHE_OP_MAX]
927 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
928 {
929 [ C(L1D) ] = {
930 [ C(OP_READ) ] = {
931 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
932 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
933 },
934 [ C(OP_WRITE) ] = {
935 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
936 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
937 },
938 [ C(OP_PREFETCH) ] = {
939 [ C(RESULT_ACCESS) ] = 0x0,
940 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
941 },
942 },
943 [ C(L1I ) ] = {
944 [ C(OP_READ) ] = {
945 [ C(RESULT_ACCESS) ] = 0x0,
946 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
947 },
948 [ C(OP_WRITE) ] = {
949 [ C(RESULT_ACCESS) ] = -1,
950 [ C(RESULT_MISS) ] = -1,
951 },
952 [ C(OP_PREFETCH) ] = {
953 [ C(RESULT_ACCESS) ] = 0x0,
954 [ C(RESULT_MISS) ] = 0x0,
955 },
956 },
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
962 [ C(RESULT_MISS) ] = 0x01b7,
963 },
964 [ C(OP_WRITE) ] = {
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
984 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033
1034 };
1035
1036 /*
1037 * Notes on the events:
1038 * - data reads do not include code reads (comparable to earlier tables)
1039 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1040 * - remote node access includes remote memory, remote cache, remote mmio.
1041 * - prefetches are not included in the counts because they are not
1042 * reliably counted.
1043 */
1044
1045 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1046 #define HSW_DEMAND_RFO BIT_ULL(1)
1047 #define HSW_ANY_RESPONSE BIT_ULL(16)
1048 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1049 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1050 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1051 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1052 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1053 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1054 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1055 HSW_L3_MISS_REMOTE_HOP2P)
1056 #define HSW_SNOOP_NONE BIT_ULL(31)
1057 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1058 #define HSW_SNOOP_MISS BIT_ULL(33)
1059 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1060 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1061 #define HSW_SNOOP_HITM BIT_ULL(36)
1062 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1063 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1064 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1065 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1066 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1067 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1068 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1069 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1070 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1071 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1072 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1073
1074 #define BDW_L3_MISS_LOCAL BIT(26)
1075 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1076 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1077 HSW_L3_MISS_REMOTE_HOP2P)
1078
1079
1080 static __initconst const u64 hsw_hw_cache_event_ids
1081 [PERF_COUNT_HW_CACHE_MAX]
1082 [PERF_COUNT_HW_CACHE_OP_MAX]
1083 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1084 {
1085 [ C(L1D ) ] = {
1086 [ C(OP_READ) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1088 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1089 },
1090 [ C(OP_WRITE) ] = {
1091 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1092 [ C(RESULT_MISS) ] = 0x0,
1093 },
1094 [ C(OP_PREFETCH) ] = {
1095 [ C(RESULT_ACCESS) ] = 0x0,
1096 [ C(RESULT_MISS) ] = 0x0,
1097 },
1098 },
1099 [ C(L1I ) ] = {
1100 [ C(OP_READ) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0,
1102 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1103 },
1104 [ C(OP_WRITE) ] = {
1105 [ C(RESULT_ACCESS) ] = -1,
1106 [ C(RESULT_MISS) ] = -1,
1107 },
1108 [ C(OP_PREFETCH) ] = {
1109 [ C(RESULT_ACCESS) ] = 0x0,
1110 [ C(RESULT_MISS) ] = 0x0,
1111 },
1112 },
1113 [ C(LL ) ] = {
1114 [ C(OP_READ) ] = {
1115 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1116 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1117 },
1118 [ C(OP_WRITE) ] = {
1119 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1120 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1121 },
1122 [ C(OP_PREFETCH) ] = {
1123 [ C(RESULT_ACCESS) ] = 0x0,
1124 [ C(RESULT_MISS) ] = 0x0,
1125 },
1126 },
1127 [ C(DTLB) ] = {
1128 [ C(OP_READ) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1130 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1131 },
1132 [ C(OP_WRITE) ] = {
1133 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1134 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1135 },
1136 [ C(OP_PREFETCH) ] = {
1137 [ C(RESULT_ACCESS) ] = 0x0,
1138 [ C(RESULT_MISS) ] = 0x0,
1139 },
1140 },
1141 [ C(ITLB) ] = {
1142 [ C(OP_READ) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1144 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1145 },
1146 [ C(OP_WRITE) ] = {
1147 [ C(RESULT_ACCESS) ] = -1,
1148 [ C(RESULT_MISS) ] = -1,
1149 },
1150 [ C(OP_PREFETCH) ] = {
1151 [ C(RESULT_ACCESS) ] = -1,
1152 [ C(RESULT_MISS) ] = -1,
1153 },
1154 },
1155 [ C(BPU ) ] = {
1156 [ C(OP_READ) ] = {
1157 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1158 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1159 },
1160 [ C(OP_WRITE) ] = {
1161 [ C(RESULT_ACCESS) ] = -1,
1162 [ C(RESULT_MISS) ] = -1,
1163 },
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = -1,
1166 [ C(RESULT_MISS) ] = -1,
1167 },
1168 },
1169 [ C(NODE) ] = {
1170 [ C(OP_READ) ] = {
1171 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1172 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1173 },
1174 [ C(OP_WRITE) ] = {
1175 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1176 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1177 },
1178 [ C(OP_PREFETCH) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x0,
1180 [ C(RESULT_MISS) ] = 0x0,
1181 },
1182 },
1183 };
1184
1185 static __initconst const u64 hsw_hw_cache_extra_regs
1186 [PERF_COUNT_HW_CACHE_MAX]
1187 [PERF_COUNT_HW_CACHE_OP_MAX]
1188 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1189 {
1190 [ C(LL ) ] = {
1191 [ C(OP_READ) ] = {
1192 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1193 HSW_LLC_ACCESS,
1194 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1195 HSW_L3_MISS|HSW_ANY_SNOOP,
1196 },
1197 [ C(OP_WRITE) ] = {
1198 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1199 HSW_LLC_ACCESS,
1200 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1201 HSW_L3_MISS|HSW_ANY_SNOOP,
1202 },
1203 [ C(OP_PREFETCH) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x0,
1205 [ C(RESULT_MISS) ] = 0x0,
1206 },
1207 },
1208 [ C(NODE) ] = {
1209 [ C(OP_READ) ] = {
1210 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1211 HSW_L3_MISS_LOCAL_DRAM|
1212 HSW_SNOOP_DRAM,
1213 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1214 HSW_L3_MISS_REMOTE|
1215 HSW_SNOOP_DRAM,
1216 },
1217 [ C(OP_WRITE) ] = {
1218 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1219 HSW_L3_MISS_LOCAL_DRAM|
1220 HSW_SNOOP_DRAM,
1221 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1222 HSW_L3_MISS_REMOTE|
1223 HSW_SNOOP_DRAM,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x0,
1227 [ C(RESULT_MISS) ] = 0x0,
1228 },
1229 },
1230 };
1231
1232 static __initconst const u64 westmere_hw_cache_event_ids
1233 [PERF_COUNT_HW_CACHE_MAX]
1234 [PERF_COUNT_HW_CACHE_OP_MAX]
1235 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1236 {
1237 [ C(L1D) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1240 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1244 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1248 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1249 },
1250 },
1251 [ C(L1I ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1254 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = -1,
1258 [ C(RESULT_MISS) ] = -1,
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x0,
1262 [ C(RESULT_MISS) ] = 0x0,
1263 },
1264 },
1265 [ C(LL ) ] = {
1266 [ C(OP_READ) ] = {
1267 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1268 [ C(RESULT_ACCESS) ] = 0x01b7,
1269 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1270 [ C(RESULT_MISS) ] = 0x01b7,
1271 },
1272 /*
1273 * Use RFO, not WRITEBACK, because a write miss would typically occur
1274 * on RFO.
1275 */
1276 [ C(OP_WRITE) ] = {
1277 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1278 [ C(RESULT_ACCESS) ] = 0x01b7,
1279 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1280 [ C(RESULT_MISS) ] = 0x01b7,
1281 },
1282 [ C(OP_PREFETCH) ] = {
1283 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1284 [ C(RESULT_ACCESS) ] = 0x01b7,
1285 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1286 [ C(RESULT_MISS) ] = 0x01b7,
1287 },
1288 },
1289 [ C(DTLB) ] = {
1290 [ C(OP_READ) ] = {
1291 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1292 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1293 },
1294 [ C(OP_WRITE) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1296 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1297 },
1298 [ C(OP_PREFETCH) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x0,
1300 [ C(RESULT_MISS) ] = 0x0,
1301 },
1302 },
1303 [ C(ITLB) ] = {
1304 [ C(OP_READ) ] = {
1305 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1306 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1307 },
1308 [ C(OP_WRITE) ] = {
1309 [ C(RESULT_ACCESS) ] = -1,
1310 [ C(RESULT_MISS) ] = -1,
1311 },
1312 [ C(OP_PREFETCH) ] = {
1313 [ C(RESULT_ACCESS) ] = -1,
1314 [ C(RESULT_MISS) ] = -1,
1315 },
1316 },
1317 [ C(BPU ) ] = {
1318 [ C(OP_READ) ] = {
1319 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1320 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1321 },
1322 [ C(OP_WRITE) ] = {
1323 [ C(RESULT_ACCESS) ] = -1,
1324 [ C(RESULT_MISS) ] = -1,
1325 },
1326 [ C(OP_PREFETCH) ] = {
1327 [ C(RESULT_ACCESS) ] = -1,
1328 [ C(RESULT_MISS) ] = -1,
1329 },
1330 },
1331 [ C(NODE) ] = {
1332 [ C(OP_READ) ] = {
1333 [ C(RESULT_ACCESS) ] = 0x01b7,
1334 [ C(RESULT_MISS) ] = 0x01b7,
1335 },
1336 [ C(OP_WRITE) ] = {
1337 [ C(RESULT_ACCESS) ] = 0x01b7,
1338 [ C(RESULT_MISS) ] = 0x01b7,
1339 },
1340 [ C(OP_PREFETCH) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 [ C(RESULT_MISS) ] = 0x01b7,
1343 },
1344 },
1345 };
1346
1347 /*
1348 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1349 * See IA32 SDM Vol 3B 30.6.1.3
1350 */
1351
1352 #define NHM_DMND_DATA_RD (1 << 0)
1353 #define NHM_DMND_RFO (1 << 1)
1354 #define NHM_DMND_IFETCH (1 << 2)
1355 #define NHM_DMND_WB (1 << 3)
1356 #define NHM_PF_DATA_RD (1 << 4)
1357 #define NHM_PF_DATA_RFO (1 << 5)
1358 #define NHM_PF_IFETCH (1 << 6)
1359 #define NHM_OFFCORE_OTHER (1 << 7)
1360 #define NHM_UNCORE_HIT (1 << 8)
1361 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1362 #define NHM_OTHER_CORE_HITM (1 << 10)
1363 /* reserved */
1364 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1365 #define NHM_REMOTE_DRAM (1 << 13)
1366 #define NHM_LOCAL_DRAM (1 << 14)
1367 #define NHM_NON_DRAM (1 << 15)
1368
1369 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1370 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1371
1372 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1373 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1374 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1375
1376 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1377 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1378 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1379
1380 static __initconst const u64 nehalem_hw_cache_extra_regs
1381 [PERF_COUNT_HW_CACHE_MAX]
1382 [PERF_COUNT_HW_CACHE_OP_MAX]
1383 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1384 {
1385 [ C(LL ) ] = {
1386 [ C(OP_READ) ] = {
1387 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1388 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1389 },
1390 [ C(OP_WRITE) ] = {
1391 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1392 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1393 },
1394 [ C(OP_PREFETCH) ] = {
1395 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1396 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1397 },
1398 },
1399 [ C(NODE) ] = {
1400 [ C(OP_READ) ] = {
1401 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1402 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1403 },
1404 [ C(OP_WRITE) ] = {
1405 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1406 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1407 },
1408 [ C(OP_PREFETCH) ] = {
1409 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1410 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1411 },
1412 },
1413 };
1414
1415 static __initconst const u64 nehalem_hw_cache_event_ids
1416 [PERF_COUNT_HW_CACHE_MAX]
1417 [PERF_COUNT_HW_CACHE_OP_MAX]
1418 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1419 {
1420 [ C(L1D) ] = {
1421 [ C(OP_READ) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1423 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1424 },
1425 [ C(OP_WRITE) ] = {
1426 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1427 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1428 },
1429 [ C(OP_PREFETCH) ] = {
1430 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1431 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1432 },
1433 },
1434 [ C(L1I ) ] = {
1435 [ C(OP_READ) ] = {
1436 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1437 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1438 },
1439 [ C(OP_WRITE) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1442 },
1443 [ C(OP_PREFETCH) ] = {
1444 [ C(RESULT_ACCESS) ] = 0x0,
1445 [ C(RESULT_MISS) ] = 0x0,
1446 },
1447 },
1448 [ C(LL ) ] = {
1449 [ C(OP_READ) ] = {
1450 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1451 [ C(RESULT_ACCESS) ] = 0x01b7,
1452 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1453 [ C(RESULT_MISS) ] = 0x01b7,
1454 },
1455 /*
1456 * Use RFO, not WRITEBACK, because a write miss would typically occur
1457 * on RFO.
1458 */
1459 [ C(OP_WRITE) ] = {
1460 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1461 [ C(RESULT_ACCESS) ] = 0x01b7,
1462 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1463 [ C(RESULT_MISS) ] = 0x01b7,
1464 },
1465 [ C(OP_PREFETCH) ] = {
1466 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1467 [ C(RESULT_ACCESS) ] = 0x01b7,
1468 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1469 [ C(RESULT_MISS) ] = 0x01b7,
1470 },
1471 },
1472 [ C(DTLB) ] = {
1473 [ C(OP_READ) ] = {
1474 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1475 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1476 },
1477 [ C(OP_WRITE) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1479 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1480 },
1481 [ C(OP_PREFETCH) ] = {
1482 [ C(RESULT_ACCESS) ] = 0x0,
1483 [ C(RESULT_MISS) ] = 0x0,
1484 },
1485 },
1486 [ C(ITLB) ] = {
1487 [ C(OP_READ) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1489 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1490 },
1491 [ C(OP_WRITE) ] = {
1492 [ C(RESULT_ACCESS) ] = -1,
1493 [ C(RESULT_MISS) ] = -1,
1494 },
1495 [ C(OP_PREFETCH) ] = {
1496 [ C(RESULT_ACCESS) ] = -1,
1497 [ C(RESULT_MISS) ] = -1,
1498 },
1499 },
1500 [ C(BPU ) ] = {
1501 [ C(OP_READ) ] = {
1502 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1503 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1504 },
1505 [ C(OP_WRITE) ] = {
1506 [ C(RESULT_ACCESS) ] = -1,
1507 [ C(RESULT_MISS) ] = -1,
1508 },
1509 [ C(OP_PREFETCH) ] = {
1510 [ C(RESULT_ACCESS) ] = -1,
1511 [ C(RESULT_MISS) ] = -1,
1512 },
1513 },
1514 [ C(NODE) ] = {
1515 [ C(OP_READ) ] = {
1516 [ C(RESULT_ACCESS) ] = 0x01b7,
1517 [ C(RESULT_MISS) ] = 0x01b7,
1518 },
1519 [ C(OP_WRITE) ] = {
1520 [ C(RESULT_ACCESS) ] = 0x01b7,
1521 [ C(RESULT_MISS) ] = 0x01b7,
1522 },
1523 [ C(OP_PREFETCH) ] = {
1524 [ C(RESULT_ACCESS) ] = 0x01b7,
1525 [ C(RESULT_MISS) ] = 0x01b7,
1526 },
1527 },
1528 };
1529
1530 static __initconst const u64 core2_hw_cache_event_ids
1531 [PERF_COUNT_HW_CACHE_MAX]
1532 [PERF_COUNT_HW_CACHE_OP_MAX]
1533 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1534 {
1535 [ C(L1D) ] = {
1536 [ C(OP_READ) ] = {
1537 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1538 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1539 },
1540 [ C(OP_WRITE) ] = {
1541 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1542 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1543 },
1544 [ C(OP_PREFETCH) ] = {
1545 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1546 [ C(RESULT_MISS) ] = 0,
1547 },
1548 },
1549 [ C(L1I ) ] = {
1550 [ C(OP_READ) ] = {
1551 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1552 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1553 },
1554 [ C(OP_WRITE) ] = {
1555 [ C(RESULT_ACCESS) ] = -1,
1556 [ C(RESULT_MISS) ] = -1,
1557 },
1558 [ C(OP_PREFETCH) ] = {
1559 [ C(RESULT_ACCESS) ] = 0,
1560 [ C(RESULT_MISS) ] = 0,
1561 },
1562 },
1563 [ C(LL ) ] = {
1564 [ C(OP_READ) ] = {
1565 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1566 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1567 },
1568 [ C(OP_WRITE) ] = {
1569 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1570 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1571 },
1572 [ C(OP_PREFETCH) ] = {
1573 [ C(RESULT_ACCESS) ] = 0,
1574 [ C(RESULT_MISS) ] = 0,
1575 },
1576 },
1577 [ C(DTLB) ] = {
1578 [ C(OP_READ) ] = {
1579 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1580 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1581 },
1582 [ C(OP_WRITE) ] = {
1583 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1584 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1585 },
1586 [ C(OP_PREFETCH) ] = {
1587 [ C(RESULT_ACCESS) ] = 0,
1588 [ C(RESULT_MISS) ] = 0,
1589 },
1590 },
1591 [ C(ITLB) ] = {
1592 [ C(OP_READ) ] = {
1593 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1594 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1595 },
1596 [ C(OP_WRITE) ] = {
1597 [ C(RESULT_ACCESS) ] = -1,
1598 [ C(RESULT_MISS) ] = -1,
1599 },
1600 [ C(OP_PREFETCH) ] = {
1601 [ C(RESULT_ACCESS) ] = -1,
1602 [ C(RESULT_MISS) ] = -1,
1603 },
1604 },
1605 [ C(BPU ) ] = {
1606 [ C(OP_READ) ] = {
1607 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1608 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1609 },
1610 [ C(OP_WRITE) ] = {
1611 [ C(RESULT_ACCESS) ] = -1,
1612 [ C(RESULT_MISS) ] = -1,
1613 },
1614 [ C(OP_PREFETCH) ] = {
1615 [ C(RESULT_ACCESS) ] = -1,
1616 [ C(RESULT_MISS) ] = -1,
1617 },
1618 },
1619 };
1620
1621 static __initconst const u64 atom_hw_cache_event_ids
1622 [PERF_COUNT_HW_CACHE_MAX]
1623 [PERF_COUNT_HW_CACHE_OP_MAX]
1624 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1625 {
1626 [ C(L1D) ] = {
1627 [ C(OP_READ) ] = {
1628 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1629 [ C(RESULT_MISS) ] = 0,
1630 },
1631 [ C(OP_WRITE) ] = {
1632 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1633 [ C(RESULT_MISS) ] = 0,
1634 },
1635 [ C(OP_PREFETCH) ] = {
1636 [ C(RESULT_ACCESS) ] = 0x0,
1637 [ C(RESULT_MISS) ] = 0,
1638 },
1639 },
1640 [ C(L1I ) ] = {
1641 [ C(OP_READ) ] = {
1642 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1643 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1644 },
1645 [ C(OP_WRITE) ] = {
1646 [ C(RESULT_ACCESS) ] = -1,
1647 [ C(RESULT_MISS) ] = -1,
1648 },
1649 [ C(OP_PREFETCH) ] = {
1650 [ C(RESULT_ACCESS) ] = 0,
1651 [ C(RESULT_MISS) ] = 0,
1652 },
1653 },
1654 [ C(LL ) ] = {
1655 [ C(OP_READ) ] = {
1656 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1657 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1658 },
1659 [ C(OP_WRITE) ] = {
1660 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1661 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1662 },
1663 [ C(OP_PREFETCH) ] = {
1664 [ C(RESULT_ACCESS) ] = 0,
1665 [ C(RESULT_MISS) ] = 0,
1666 },
1667 },
1668 [ C(DTLB) ] = {
1669 [ C(OP_READ) ] = {
1670 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1671 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1672 },
1673 [ C(OP_WRITE) ] = {
1674 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1675 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1676 },
1677 [ C(OP_PREFETCH) ] = {
1678 [ C(RESULT_ACCESS) ] = 0,
1679 [ C(RESULT_MISS) ] = 0,
1680 },
1681 },
1682 [ C(ITLB) ] = {
1683 [ C(OP_READ) ] = {
1684 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1685 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1686 },
1687 [ C(OP_WRITE) ] = {
1688 [ C(RESULT_ACCESS) ] = -1,
1689 [ C(RESULT_MISS) ] = -1,
1690 },
1691 [ C(OP_PREFETCH) ] = {
1692 [ C(RESULT_ACCESS) ] = -1,
1693 [ C(RESULT_MISS) ] = -1,
1694 },
1695 },
1696 [ C(BPU ) ] = {
1697 [ C(OP_READ) ] = {
1698 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1699 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1700 },
1701 [ C(OP_WRITE) ] = {
1702 [ C(RESULT_ACCESS) ] = -1,
1703 [ C(RESULT_MISS) ] = -1,
1704 },
1705 [ C(OP_PREFETCH) ] = {
1706 [ C(RESULT_ACCESS) ] = -1,
1707 [ C(RESULT_MISS) ] = -1,
1708 },
1709 },
1710 };
1711
1712 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1713 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1714 /* no_alloc_cycles.not_delivered */
1715 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1716 "event=0xca,umask=0x50");
1717 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1718 /* uops_retired.all */
1719 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1720 "event=0xc2,umask=0x10");
1721 /* uops_retired.all */
1722 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1723 "event=0xc2,umask=0x10");
1724
1725 static struct attribute *slm_events_attrs[] = {
1726 EVENT_PTR(td_total_slots_slm),
1727 EVENT_PTR(td_total_slots_scale_slm),
1728 EVENT_PTR(td_fetch_bubbles_slm),
1729 EVENT_PTR(td_fetch_bubbles_scale_slm),
1730 EVENT_PTR(td_slots_issued_slm),
1731 EVENT_PTR(td_slots_retired_slm),
1732 NULL
1733 };
1734
1735 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1736 {
1737 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1738 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1739 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1740 EVENT_EXTRA_END
1741 };
1742
1743 #define SLM_DMND_READ SNB_DMND_DATA_RD
1744 #define SLM_DMND_WRITE SNB_DMND_RFO
1745 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1746
1747 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1748 #define SLM_LLC_ACCESS SNB_RESP_ANY
1749 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1750
1751 static __initconst const u64 slm_hw_cache_extra_regs
1752 [PERF_COUNT_HW_CACHE_MAX]
1753 [PERF_COUNT_HW_CACHE_OP_MAX]
1754 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1755 {
1756 [ C(LL ) ] = {
1757 [ C(OP_READ) ] = {
1758 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1759 [ C(RESULT_MISS) ] = 0,
1760 },
1761 [ C(OP_WRITE) ] = {
1762 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1763 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1764 },
1765 [ C(OP_PREFETCH) ] = {
1766 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1767 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1768 },
1769 },
1770 };
1771
1772 static __initconst const u64 slm_hw_cache_event_ids
1773 [PERF_COUNT_HW_CACHE_MAX]
1774 [PERF_COUNT_HW_CACHE_OP_MAX]
1775 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1776 {
1777 [ C(L1D) ] = {
1778 [ C(OP_READ) ] = {
1779 [ C(RESULT_ACCESS) ] = 0,
1780 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1781 },
1782 [ C(OP_WRITE) ] = {
1783 [ C(RESULT_ACCESS) ] = 0,
1784 [ C(RESULT_MISS) ] = 0,
1785 },
1786 [ C(OP_PREFETCH) ] = {
1787 [ C(RESULT_ACCESS) ] = 0,
1788 [ C(RESULT_MISS) ] = 0,
1789 },
1790 },
1791 [ C(L1I ) ] = {
1792 [ C(OP_READ) ] = {
1793 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1794 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1795 },
1796 [ C(OP_WRITE) ] = {
1797 [ C(RESULT_ACCESS) ] = -1,
1798 [ C(RESULT_MISS) ] = -1,
1799 },
1800 [ C(OP_PREFETCH) ] = {
1801 [ C(RESULT_ACCESS) ] = 0,
1802 [ C(RESULT_MISS) ] = 0,
1803 },
1804 },
1805 [ C(LL ) ] = {
1806 [ C(OP_READ) ] = {
1807 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1808 [ C(RESULT_ACCESS) ] = 0x01b7,
1809 [ C(RESULT_MISS) ] = 0,
1810 },
1811 [ C(OP_WRITE) ] = {
1812 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1813 [ C(RESULT_ACCESS) ] = 0x01b7,
1814 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1815 [ C(RESULT_MISS) ] = 0x01b7,
1816 },
1817 [ C(OP_PREFETCH) ] = {
1818 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1819 [ C(RESULT_ACCESS) ] = 0x01b7,
1820 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1821 [ C(RESULT_MISS) ] = 0x01b7,
1822 },
1823 },
1824 [ C(DTLB) ] = {
1825 [ C(OP_READ) ] = {
1826 [ C(RESULT_ACCESS) ] = 0,
1827 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1828 },
1829 [ C(OP_WRITE) ] = {
1830 [ C(RESULT_ACCESS) ] = 0,
1831 [ C(RESULT_MISS) ] = 0,
1832 },
1833 [ C(OP_PREFETCH) ] = {
1834 [ C(RESULT_ACCESS) ] = 0,
1835 [ C(RESULT_MISS) ] = 0,
1836 },
1837 },
1838 [ C(ITLB) ] = {
1839 [ C(OP_READ) ] = {
1840 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1841 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1842 },
1843 [ C(OP_WRITE) ] = {
1844 [ C(RESULT_ACCESS) ] = -1,
1845 [ C(RESULT_MISS) ] = -1,
1846 },
1847 [ C(OP_PREFETCH) ] = {
1848 [ C(RESULT_ACCESS) ] = -1,
1849 [ C(RESULT_MISS) ] = -1,
1850 },
1851 },
1852 [ C(BPU ) ] = {
1853 [ C(OP_READ) ] = {
1854 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1855 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1856 },
1857 [ C(OP_WRITE) ] = {
1858 [ C(RESULT_ACCESS) ] = -1,
1859 [ C(RESULT_MISS) ] = -1,
1860 },
1861 [ C(OP_PREFETCH) ] = {
1862 [ C(RESULT_ACCESS) ] = -1,
1863 [ C(RESULT_MISS) ] = -1,
1864 },
1865 },
1866 };
1867
1868 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1869 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1870 /* UOPS_NOT_DELIVERED.ANY */
1871 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1872 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1873 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1874 /* UOPS_RETIRED.ANY */
1875 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1876 /* UOPS_ISSUED.ANY */
1877 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1878
1879 static struct attribute *glm_events_attrs[] = {
1880 EVENT_PTR(td_total_slots_glm),
1881 EVENT_PTR(td_total_slots_scale_glm),
1882 EVENT_PTR(td_fetch_bubbles_glm),
1883 EVENT_PTR(td_recovery_bubbles_glm),
1884 EVENT_PTR(td_slots_issued_glm),
1885 EVENT_PTR(td_slots_retired_glm),
1886 NULL
1887 };
1888
1889 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1890 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1891 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1892 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1893 EVENT_EXTRA_END
1894 };
1895
1896 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1897 #define GLM_DEMAND_RFO BIT_ULL(1)
1898 #define GLM_ANY_RESPONSE BIT_ULL(16)
1899 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1900 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1901 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1902 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1903 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1904 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1905 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1906
1907 static __initconst const u64 glm_hw_cache_event_ids
1908 [PERF_COUNT_HW_CACHE_MAX]
1909 [PERF_COUNT_HW_CACHE_OP_MAX]
1910 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1911 [C(L1D)] = {
1912 [C(OP_READ)] = {
1913 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1914 [C(RESULT_MISS)] = 0x0,
1915 },
1916 [C(OP_WRITE)] = {
1917 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1918 [C(RESULT_MISS)] = 0x0,
1919 },
1920 [C(OP_PREFETCH)] = {
1921 [C(RESULT_ACCESS)] = 0x0,
1922 [C(RESULT_MISS)] = 0x0,
1923 },
1924 },
1925 [C(L1I)] = {
1926 [C(OP_READ)] = {
1927 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1928 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1929 },
1930 [C(OP_WRITE)] = {
1931 [C(RESULT_ACCESS)] = -1,
1932 [C(RESULT_MISS)] = -1,
1933 },
1934 [C(OP_PREFETCH)] = {
1935 [C(RESULT_ACCESS)] = 0x0,
1936 [C(RESULT_MISS)] = 0x0,
1937 },
1938 },
1939 [C(LL)] = {
1940 [C(OP_READ)] = {
1941 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1942 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1943 },
1944 [C(OP_WRITE)] = {
1945 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1946 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1947 },
1948 [C(OP_PREFETCH)] = {
1949 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1950 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1951 },
1952 },
1953 [C(DTLB)] = {
1954 [C(OP_READ)] = {
1955 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1956 [C(RESULT_MISS)] = 0x0,
1957 },
1958 [C(OP_WRITE)] = {
1959 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1960 [C(RESULT_MISS)] = 0x0,
1961 },
1962 [C(OP_PREFETCH)] = {
1963 [C(RESULT_ACCESS)] = 0x0,
1964 [C(RESULT_MISS)] = 0x0,
1965 },
1966 },
1967 [C(ITLB)] = {
1968 [C(OP_READ)] = {
1969 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1970 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1971 },
1972 [C(OP_WRITE)] = {
1973 [C(RESULT_ACCESS)] = -1,
1974 [C(RESULT_MISS)] = -1,
1975 },
1976 [C(OP_PREFETCH)] = {
1977 [C(RESULT_ACCESS)] = -1,
1978 [C(RESULT_MISS)] = -1,
1979 },
1980 },
1981 [C(BPU)] = {
1982 [C(OP_READ)] = {
1983 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1984 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1985 },
1986 [C(OP_WRITE)] = {
1987 [C(RESULT_ACCESS)] = -1,
1988 [C(RESULT_MISS)] = -1,
1989 },
1990 [C(OP_PREFETCH)] = {
1991 [C(RESULT_ACCESS)] = -1,
1992 [C(RESULT_MISS)] = -1,
1993 },
1994 },
1995 };
1996
1997 static __initconst const u64 glm_hw_cache_extra_regs
1998 [PERF_COUNT_HW_CACHE_MAX]
1999 [PERF_COUNT_HW_CACHE_OP_MAX]
2000 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2001 [C(LL)] = {
2002 [C(OP_READ)] = {
2003 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2004 GLM_LLC_ACCESS,
2005 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2006 GLM_LLC_MISS,
2007 },
2008 [C(OP_WRITE)] = {
2009 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2010 GLM_LLC_ACCESS,
2011 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2012 GLM_LLC_MISS,
2013 },
2014 [C(OP_PREFETCH)] = {
2015 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2016 GLM_LLC_ACCESS,
2017 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2018 GLM_LLC_MISS,
2019 },
2020 },
2021 };
2022
2023 static __initconst const u64 glp_hw_cache_event_ids
2024 [PERF_COUNT_HW_CACHE_MAX]
2025 [PERF_COUNT_HW_CACHE_OP_MAX]
2026 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2027 [C(L1D)] = {
2028 [C(OP_READ)] = {
2029 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2030 [C(RESULT_MISS)] = 0x0,
2031 },
2032 [C(OP_WRITE)] = {
2033 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2034 [C(RESULT_MISS)] = 0x0,
2035 },
2036 [C(OP_PREFETCH)] = {
2037 [C(RESULT_ACCESS)] = 0x0,
2038 [C(RESULT_MISS)] = 0x0,
2039 },
2040 },
2041 [C(L1I)] = {
2042 [C(OP_READ)] = {
2043 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2044 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2045 },
2046 [C(OP_WRITE)] = {
2047 [C(RESULT_ACCESS)] = -1,
2048 [C(RESULT_MISS)] = -1,
2049 },
2050 [C(OP_PREFETCH)] = {
2051 [C(RESULT_ACCESS)] = 0x0,
2052 [C(RESULT_MISS)] = 0x0,
2053 },
2054 },
2055 [C(LL)] = {
2056 [C(OP_READ)] = {
2057 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2058 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2059 },
2060 [C(OP_WRITE)] = {
2061 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2062 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2063 },
2064 [C(OP_PREFETCH)] = {
2065 [C(RESULT_ACCESS)] = 0x0,
2066 [C(RESULT_MISS)] = 0x0,
2067 },
2068 },
2069 [C(DTLB)] = {
2070 [C(OP_READ)] = {
2071 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2072 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2073 },
2074 [C(OP_WRITE)] = {
2075 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2076 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2077 },
2078 [C(OP_PREFETCH)] = {
2079 [C(RESULT_ACCESS)] = 0x0,
2080 [C(RESULT_MISS)] = 0x0,
2081 },
2082 },
2083 [C(ITLB)] = {
2084 [C(OP_READ)] = {
2085 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2086 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2087 },
2088 [C(OP_WRITE)] = {
2089 [C(RESULT_ACCESS)] = -1,
2090 [C(RESULT_MISS)] = -1,
2091 },
2092 [C(OP_PREFETCH)] = {
2093 [C(RESULT_ACCESS)] = -1,
2094 [C(RESULT_MISS)] = -1,
2095 },
2096 },
2097 [C(BPU)] = {
2098 [C(OP_READ)] = {
2099 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2100 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2101 },
2102 [C(OP_WRITE)] = {
2103 [C(RESULT_ACCESS)] = -1,
2104 [C(RESULT_MISS)] = -1,
2105 },
2106 [C(OP_PREFETCH)] = {
2107 [C(RESULT_ACCESS)] = -1,
2108 [C(RESULT_MISS)] = -1,
2109 },
2110 },
2111 };
2112
2113 static __initconst const u64 glp_hw_cache_extra_regs
2114 [PERF_COUNT_HW_CACHE_MAX]
2115 [PERF_COUNT_HW_CACHE_OP_MAX]
2116 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2117 [C(LL)] = {
2118 [C(OP_READ)] = {
2119 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2120 GLM_LLC_ACCESS,
2121 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2122 GLM_LLC_MISS,
2123 },
2124 [C(OP_WRITE)] = {
2125 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2126 GLM_LLC_ACCESS,
2127 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2128 GLM_LLC_MISS,
2129 },
2130 [C(OP_PREFETCH)] = {
2131 [C(RESULT_ACCESS)] = 0x0,
2132 [C(RESULT_MISS)] = 0x0,
2133 },
2134 },
2135 };
2136
2137 #define TNT_LOCAL_DRAM BIT_ULL(26)
2138 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2139 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2140 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2141 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2142 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2143 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2144
2145 static __initconst const u64 tnt_hw_cache_extra_regs
2146 [PERF_COUNT_HW_CACHE_MAX]
2147 [PERF_COUNT_HW_CACHE_OP_MAX]
2148 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2149 [C(LL)] = {
2150 [C(OP_READ)] = {
2151 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2152 TNT_LLC_ACCESS,
2153 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2154 TNT_LLC_MISS,
2155 },
2156 [C(OP_WRITE)] = {
2157 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2158 TNT_LLC_ACCESS,
2159 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2160 TNT_LLC_MISS,
2161 },
2162 [C(OP_PREFETCH)] = {
2163 [C(RESULT_ACCESS)] = 0x0,
2164 [C(RESULT_MISS)] = 0x0,
2165 },
2166 },
2167 };
2168
2169 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2170 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2171 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2172 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2173
2174 static struct attribute *tnt_events_attrs[] = {
2175 EVENT_PTR(td_fe_bound_tnt),
2176 EVENT_PTR(td_retiring_tnt),
2177 EVENT_PTR(td_bad_spec_tnt),
2178 EVENT_PTR(td_be_bound_tnt),
2179 NULL,
2180 };
2181
2182 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2183 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2184 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2185 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2186 EVENT_EXTRA_END
2187 };
2188
2189 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2190 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2191
2192 static struct attribute *grt_mem_attrs[] = {
2193 EVENT_PTR(mem_ld_grt),
2194 EVENT_PTR(mem_st_grt),
2195 NULL
2196 };
2197
2198 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2199 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2200 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2201 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2202 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2203 EVENT_EXTRA_END
2204 };
2205
2206 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2207 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2208
2209 static struct attribute *cmt_events_attrs[] = {
2210 EVENT_PTR(td_fe_bound_tnt),
2211 EVENT_PTR(td_retiring_cmt),
2212 EVENT_PTR(td_bad_spec_cmt),
2213 EVENT_PTR(td_be_bound_tnt),
2214 NULL
2215 };
2216
2217 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2218 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2219 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2220 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2221 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2222 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2223 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2224 EVENT_EXTRA_END
2225 };
2226
2227 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2228 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2229 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2230 #define KNL_MCDRAM_FAR BIT_ULL(22)
2231 #define KNL_DDR_LOCAL BIT_ULL(23)
2232 #define KNL_DDR_FAR BIT_ULL(24)
2233 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2234 KNL_DDR_LOCAL | KNL_DDR_FAR)
2235 #define KNL_L2_READ SLM_DMND_READ
2236 #define KNL_L2_WRITE SLM_DMND_WRITE
2237 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2238 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2239 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2240 KNL_DRAM_ANY | SNB_SNP_ANY | \
2241 SNB_NON_DRAM)
2242
2243 static __initconst const u64 knl_hw_cache_extra_regs
2244 [PERF_COUNT_HW_CACHE_MAX]
2245 [PERF_COUNT_HW_CACHE_OP_MAX]
2246 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2247 [C(LL)] = {
2248 [C(OP_READ)] = {
2249 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2250 [C(RESULT_MISS)] = 0,
2251 },
2252 [C(OP_WRITE)] = {
2253 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2254 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2255 },
2256 [C(OP_PREFETCH)] = {
2257 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2258 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2259 },
2260 },
2261 };
2262
2263 /*
2264 * Used from PMIs where the LBRs are already disabled.
2265 *
2266 * This function could be called consecutively. It is required to remain in
2267 * disabled state if called consecutively.
2268 *
2269 * During consecutive calls, the same disable value will be written to related
2270 * registers, so the PMU state remains unchanged.
2271 *
2272 * intel_bts events don't coexist with intel PMU's BTS events because of
2273 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2274 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2275 *
2276 * Avoid PEBS_ENABLE MSR access in PMIs.
2277 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2278 * It doesn't matter if the PEBS is enabled or not.
2279 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2280 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2281 * However, there are some cases which may change PEBS status, e.g. PMI
2282 * throttle. The PEBS_ENABLE should be updated where the status changes.
2283 */
__intel_pmu_disable_all(bool bts)2284 static __always_inline void __intel_pmu_disable_all(bool bts)
2285 {
2286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2287
2288 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2289
2290 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2291 intel_pmu_disable_bts();
2292 }
2293
intel_pmu_disable_all(void)2294 static __always_inline void intel_pmu_disable_all(void)
2295 {
2296 __intel_pmu_disable_all(true);
2297 intel_pmu_pebs_disable_all();
2298 intel_pmu_lbr_disable_all();
2299 }
2300
__intel_pmu_enable_all(int added,bool pmi)2301 static void __intel_pmu_enable_all(int added, bool pmi)
2302 {
2303 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2304 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2305
2306 intel_pmu_lbr_enable_all(pmi);
2307
2308 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2309 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2310 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2311 }
2312
2313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2314 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2315
2316 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2317 struct perf_event *event =
2318 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2319
2320 if (WARN_ON_ONCE(!event))
2321 return;
2322
2323 intel_pmu_enable_bts(event->hw.config);
2324 }
2325 }
2326
intel_pmu_enable_all(int added)2327 static void intel_pmu_enable_all(int added)
2328 {
2329 intel_pmu_pebs_enable_all();
2330 __intel_pmu_enable_all(added, false);
2331 }
2332
2333 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2334 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2335 unsigned int cnt, unsigned long flags)
2336 {
2337 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2338
2339 intel_pmu_lbr_read();
2340 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2341
2342 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2343 intel_pmu_enable_all(0);
2344 local_irq_restore(flags);
2345 return cnt;
2346 }
2347
2348 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2349 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2350 {
2351 unsigned long flags;
2352
2353 /* must not have branches... */
2354 local_irq_save(flags);
2355 __intel_pmu_disable_all(false); /* we don't care about BTS */
2356 __intel_pmu_lbr_disable();
2357 /* ... until here */
2358 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2359 }
2360
2361 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2362 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2363 {
2364 unsigned long flags;
2365
2366 /* must not have branches... */
2367 local_irq_save(flags);
2368 __intel_pmu_disable_all(false); /* we don't care about BTS */
2369 __intel_pmu_arch_lbr_disable();
2370 /* ... until here */
2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2372 }
2373
2374 /*
2375 * Workaround for:
2376 * Intel Errata AAK100 (model 26)
2377 * Intel Errata AAP53 (model 30)
2378 * Intel Errata BD53 (model 44)
2379 *
2380 * The official story:
2381 * These chips need to be 'reset' when adding counters by programming the
2382 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2383 * in sequence on the same PMC or on different PMCs.
2384 *
2385 * In practice it appears some of these events do in fact count, and
2386 * we need to program all 4 events.
2387 */
intel_pmu_nhm_workaround(void)2388 static void intel_pmu_nhm_workaround(void)
2389 {
2390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2391 static const unsigned long nhm_magic[4] = {
2392 0x4300B5,
2393 0x4300D2,
2394 0x4300B1,
2395 0x4300B1
2396 };
2397 struct perf_event *event;
2398 int i;
2399
2400 /*
2401 * The Errata requires below steps:
2402 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2403 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2404 * the corresponding PMCx;
2405 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2406 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2407 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2408 */
2409
2410 /*
2411 * The real steps we choose are a little different from above.
2412 * A) To reduce MSR operations, we don't run step 1) as they
2413 * are already cleared before this function is called;
2414 * B) Call x86_perf_event_update to save PMCx before configuring
2415 * PERFEVTSELx with magic number;
2416 * C) With step 5), we do clear only when the PERFEVTSELx is
2417 * not used currently.
2418 * D) Call x86_perf_event_set_period to restore PMCx;
2419 */
2420
2421 /* We always operate 4 pairs of PERF Counters */
2422 for (i = 0; i < 4; i++) {
2423 event = cpuc->events[i];
2424 if (event)
2425 static_call(x86_pmu_update)(event);
2426 }
2427
2428 for (i = 0; i < 4; i++) {
2429 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2430 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2431 }
2432
2433 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2434 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2435
2436 for (i = 0; i < 4; i++) {
2437 event = cpuc->events[i];
2438
2439 if (event) {
2440 static_call(x86_pmu_set_period)(event);
2441 __x86_pmu_enable_event(&event->hw,
2442 ARCH_PERFMON_EVENTSEL_ENABLE);
2443 } else
2444 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2445 }
2446 }
2447
intel_pmu_nhm_enable_all(int added)2448 static void intel_pmu_nhm_enable_all(int added)
2449 {
2450 if (added)
2451 intel_pmu_nhm_workaround();
2452 intel_pmu_enable_all(added);
2453 }
2454
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2455 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2456 {
2457 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2458
2459 if (cpuc->tfa_shadow != val) {
2460 cpuc->tfa_shadow = val;
2461 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2462 }
2463 }
2464
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2465 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2466 {
2467 /*
2468 * We're going to use PMC3, make sure TFA is set before we touch it.
2469 */
2470 if (cntr == 3)
2471 intel_set_tfa(cpuc, true);
2472 }
2473
intel_tfa_pmu_enable_all(int added)2474 static void intel_tfa_pmu_enable_all(int added)
2475 {
2476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2477
2478 /*
2479 * If we find PMC3 is no longer used when we enable the PMU, we can
2480 * clear TFA.
2481 */
2482 if (!test_bit(3, cpuc->active_mask))
2483 intel_set_tfa(cpuc, false);
2484
2485 intel_pmu_enable_all(added);
2486 }
2487
intel_pmu_get_status(void)2488 static inline u64 intel_pmu_get_status(void)
2489 {
2490 u64 status;
2491
2492 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2493
2494 return status;
2495 }
2496
intel_pmu_ack_status(u64 ack)2497 static inline void intel_pmu_ack_status(u64 ack)
2498 {
2499 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2500 }
2501
event_is_checkpointed(struct perf_event * event)2502 static inline bool event_is_checkpointed(struct perf_event *event)
2503 {
2504 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2505 }
2506
intel_set_masks(struct perf_event * event,int idx)2507 static inline void intel_set_masks(struct perf_event *event, int idx)
2508 {
2509 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2510
2511 if (event->attr.exclude_host)
2512 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2513 if (event->attr.exclude_guest)
2514 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2515 if (event_is_checkpointed(event))
2516 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2517 }
2518
intel_clear_masks(struct perf_event * event,int idx)2519 static inline void intel_clear_masks(struct perf_event *event, int idx)
2520 {
2521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2522
2523 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2524 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2525 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2526 }
2527
intel_pmu_disable_fixed(struct perf_event * event)2528 static void intel_pmu_disable_fixed(struct perf_event *event)
2529 {
2530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2531 struct hw_perf_event *hwc = &event->hw;
2532 int idx = hwc->idx;
2533 u64 mask;
2534
2535 if (is_topdown_idx(idx)) {
2536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2537
2538 /*
2539 * When there are other active TopDown events,
2540 * don't disable the fixed counter 3.
2541 */
2542 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2543 return;
2544 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2545 }
2546
2547 intel_clear_masks(event, idx);
2548
2549 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2550 cpuc->fixed_ctrl_val &= ~mask;
2551 }
2552
intel_pmu_disable_event(struct perf_event * event)2553 static void intel_pmu_disable_event(struct perf_event *event)
2554 {
2555 struct hw_perf_event *hwc = &event->hw;
2556 int idx = hwc->idx;
2557
2558 switch (idx) {
2559 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2560 intel_clear_masks(event, idx);
2561 x86_pmu_disable_event(event);
2562 break;
2563 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2564 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2565 intel_pmu_disable_fixed(event);
2566 break;
2567 case INTEL_PMC_IDX_FIXED_BTS:
2568 intel_pmu_disable_bts();
2569 intel_pmu_drain_bts_buffer();
2570 return;
2571 case INTEL_PMC_IDX_FIXED_VLBR:
2572 intel_clear_masks(event, idx);
2573 break;
2574 default:
2575 intel_clear_masks(event, idx);
2576 pr_warn("Failed to disable the event with invalid index %d\n",
2577 idx);
2578 return;
2579 }
2580
2581 /*
2582 * Needs to be called after x86_pmu_disable_event,
2583 * so we don't trigger the event without PEBS bit set.
2584 */
2585 if (unlikely(event->attr.precise_ip))
2586 intel_pmu_pebs_disable(event);
2587 }
2588
intel_pmu_assign_event(struct perf_event * event,int idx)2589 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2590 {
2591 if (is_pebs_pt(event))
2592 perf_report_aux_output_id(event, idx);
2593 }
2594
intel_pmu_needs_branch_stack(struct perf_event * event)2595 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
2596 {
2597 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
2598 }
2599
intel_pmu_del_event(struct perf_event * event)2600 static void intel_pmu_del_event(struct perf_event *event)
2601 {
2602 if (intel_pmu_needs_branch_stack(event))
2603 intel_pmu_lbr_del(event);
2604 if (event->attr.precise_ip)
2605 intel_pmu_pebs_del(event);
2606 }
2607
icl_set_topdown_event_period(struct perf_event * event)2608 static int icl_set_topdown_event_period(struct perf_event *event)
2609 {
2610 struct hw_perf_event *hwc = &event->hw;
2611 s64 left = local64_read(&hwc->period_left);
2612
2613 /*
2614 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2615 * Software should start both registers, PERF_METRICS and fixed
2616 * counter 3, from zero.
2617 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2618 * After that, both MSRs will be cleared for each read.
2619 * Don't need to clear them again.
2620 */
2621 if (left == x86_pmu.max_period) {
2622 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2623 wrmsrl(MSR_PERF_METRICS, 0);
2624 hwc->saved_slots = 0;
2625 hwc->saved_metric = 0;
2626 }
2627
2628 if ((hwc->saved_slots) && is_slots_event(event)) {
2629 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2630 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2631 }
2632
2633 perf_event_update_userpage(event);
2634
2635 return 0;
2636 }
2637
2638 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2639
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2640 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2641 {
2642 u32 val;
2643
2644 /*
2645 * The metric is reported as an 8bit integer fraction
2646 * summing up to 0xff.
2647 * slots-in-metric = (Metric / 0xff) * slots
2648 */
2649 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2650 return mul_u64_u32_div(slots, val, 0xff);
2651 }
2652
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2653 static u64 icl_get_topdown_value(struct perf_event *event,
2654 u64 slots, u64 metrics)
2655 {
2656 int idx = event->hw.idx;
2657 u64 delta;
2658
2659 if (is_metric_idx(idx))
2660 delta = icl_get_metrics_event_value(metrics, slots, idx);
2661 else
2662 delta = slots;
2663
2664 return delta;
2665 }
2666
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2667 static void __icl_update_topdown_event(struct perf_event *event,
2668 u64 slots, u64 metrics,
2669 u64 last_slots, u64 last_metrics)
2670 {
2671 u64 delta, last = 0;
2672
2673 delta = icl_get_topdown_value(event, slots, metrics);
2674 if (last_slots)
2675 last = icl_get_topdown_value(event, last_slots, last_metrics);
2676
2677 /*
2678 * The 8bit integer fraction of metric may be not accurate,
2679 * especially when the changes is very small.
2680 * For example, if only a few bad_spec happens, the fraction
2681 * may be reduced from 1 to 0. If so, the bad_spec event value
2682 * will be 0 which is definitely less than the last value.
2683 * Avoid update event->count for this case.
2684 */
2685 if (delta > last) {
2686 delta -= last;
2687 local64_add(delta, &event->count);
2688 }
2689 }
2690
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)2691 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2692 u64 metrics, int metric_end)
2693 {
2694 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2695 struct perf_event *other;
2696 int idx;
2697
2698 event->hw.saved_slots = slots;
2699 event->hw.saved_metric = metrics;
2700
2701 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2702 if (!is_topdown_idx(idx))
2703 continue;
2704 other = cpuc->events[idx];
2705 other->hw.saved_slots = slots;
2706 other->hw.saved_metric = metrics;
2707 }
2708 }
2709
2710 /*
2711 * Update all active Topdown events.
2712 *
2713 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2714 * modify by a NMI. PMU has to be disabled before calling this function.
2715 */
2716
intel_update_topdown_event(struct perf_event * event,int metric_end)2717 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2718 {
2719 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2720 struct perf_event *other;
2721 u64 slots, metrics;
2722 bool reset = true;
2723 int idx;
2724
2725 /* read Fixed counter 3 */
2726 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2727 if (!slots)
2728 return 0;
2729
2730 /* read PERF_METRICS */
2731 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2732
2733 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2734 if (!is_topdown_idx(idx))
2735 continue;
2736 other = cpuc->events[idx];
2737 __icl_update_topdown_event(other, slots, metrics,
2738 event ? event->hw.saved_slots : 0,
2739 event ? event->hw.saved_metric : 0);
2740 }
2741
2742 /*
2743 * Check and update this event, which may have been cleared
2744 * in active_mask e.g. x86_pmu_stop()
2745 */
2746 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2747 __icl_update_topdown_event(event, slots, metrics,
2748 event->hw.saved_slots,
2749 event->hw.saved_metric);
2750
2751 /*
2752 * In x86_pmu_stop(), the event is cleared in active_mask first,
2753 * then drain the delta, which indicates context switch for
2754 * counting.
2755 * Save metric and slots for context switch.
2756 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2757 * Because the values will be restored in next schedule in.
2758 */
2759 update_saved_topdown_regs(event, slots, metrics, metric_end);
2760 reset = false;
2761 }
2762
2763 if (reset) {
2764 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2765 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2766 wrmsrl(MSR_PERF_METRICS, 0);
2767 if (event)
2768 update_saved_topdown_regs(event, 0, 0, metric_end);
2769 }
2770
2771 return slots;
2772 }
2773
icl_update_topdown_event(struct perf_event * event)2774 static u64 icl_update_topdown_event(struct perf_event *event)
2775 {
2776 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2777 x86_pmu.num_topdown_events - 1);
2778 }
2779
2780 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);
2781
intel_pmu_read_event(struct perf_event * event)2782 static void intel_pmu_read_event(struct perf_event *event)
2783 {
2784 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN)) {
2785 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2786 bool pmu_enabled = cpuc->enabled;
2787
2788 /* Only need to call update_topdown_event() once for group read. */
2789 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
2790 return;
2791
2792 cpuc->enabled = 0;
2793 if (pmu_enabled)
2794 intel_pmu_disable_all();
2795
2796 if (is_topdown_count(event))
2797 static_call(intel_pmu_update_topdown_event)(event);
2798 else
2799 intel_pmu_drain_pebs_buffer();
2800
2801 cpuc->enabled = pmu_enabled;
2802 if (pmu_enabled)
2803 intel_pmu_enable_all(0);
2804
2805 return;
2806 }
2807
2808 x86_perf_event_update(event);
2809 }
2810
intel_pmu_enable_fixed(struct perf_event * event)2811 static void intel_pmu_enable_fixed(struct perf_event *event)
2812 {
2813 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2814 struct hw_perf_event *hwc = &event->hw;
2815 u64 mask, bits = 0;
2816 int idx = hwc->idx;
2817
2818 if (is_topdown_idx(idx)) {
2819 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2820 /*
2821 * When there are other active TopDown events,
2822 * don't enable the fixed counter 3 again.
2823 */
2824 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2825 return;
2826
2827 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2828 }
2829
2830 intel_set_masks(event, idx);
2831
2832 /*
2833 * Enable IRQ generation (0x8), if not PEBS,
2834 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2835 * if requested:
2836 */
2837 if (!event->attr.precise_ip)
2838 bits |= INTEL_FIXED_0_ENABLE_PMI;
2839 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2840 bits |= INTEL_FIXED_0_USER;
2841 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2842 bits |= INTEL_FIXED_0_KERNEL;
2843
2844 /*
2845 * ANY bit is supported in v3 and up
2846 */
2847 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2848 bits |= INTEL_FIXED_0_ANYTHREAD;
2849
2850 idx -= INTEL_PMC_IDX_FIXED;
2851 bits = intel_fixed_bits_by_idx(idx, bits);
2852 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2853
2854 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2855 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2856 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2857 }
2858
2859 cpuc->fixed_ctrl_val &= ~mask;
2860 cpuc->fixed_ctrl_val |= bits;
2861 }
2862
intel_pmu_enable_event(struct perf_event * event)2863 static void intel_pmu_enable_event(struct perf_event *event)
2864 {
2865 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
2866 struct hw_perf_event *hwc = &event->hw;
2867 int idx = hwc->idx;
2868
2869 if (unlikely(event->attr.precise_ip))
2870 intel_pmu_pebs_enable(event);
2871
2872 switch (idx) {
2873 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2874 if (branch_sample_counters(event))
2875 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
2876 intel_set_masks(event, idx);
2877 __x86_pmu_enable_event(hwc, enable_mask);
2878 break;
2879 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2880 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2881 intel_pmu_enable_fixed(event);
2882 break;
2883 case INTEL_PMC_IDX_FIXED_BTS:
2884 if (!__this_cpu_read(cpu_hw_events.enabled))
2885 return;
2886 intel_pmu_enable_bts(hwc->config);
2887 break;
2888 case INTEL_PMC_IDX_FIXED_VLBR:
2889 intel_set_masks(event, idx);
2890 break;
2891 default:
2892 pr_warn("Failed to enable the event with invalid index %d\n",
2893 idx);
2894 }
2895 }
2896
intel_pmu_add_event(struct perf_event * event)2897 static void intel_pmu_add_event(struct perf_event *event)
2898 {
2899 if (event->attr.precise_ip)
2900 intel_pmu_pebs_add(event);
2901 if (intel_pmu_needs_branch_stack(event))
2902 intel_pmu_lbr_add(event);
2903 }
2904
2905 /*
2906 * Save and restart an expired event. Called by NMI contexts,
2907 * so it has to be careful about preempting normal event ops:
2908 */
intel_pmu_save_and_restart(struct perf_event * event)2909 int intel_pmu_save_and_restart(struct perf_event *event)
2910 {
2911 static_call(x86_pmu_update)(event);
2912 /*
2913 * For a checkpointed counter always reset back to 0. This
2914 * avoids a situation where the counter overflows, aborts the
2915 * transaction and is then set back to shortly before the
2916 * overflow, and overflows and aborts again.
2917 */
2918 if (unlikely(event_is_checkpointed(event))) {
2919 /* No race with NMIs because the counter should not be armed */
2920 wrmsrl(event->hw.event_base, 0);
2921 local64_set(&event->hw.prev_count, 0);
2922 }
2923 return static_call(x86_pmu_set_period)(event);
2924 }
2925
intel_pmu_set_period(struct perf_event * event)2926 static int intel_pmu_set_period(struct perf_event *event)
2927 {
2928 if (unlikely(is_topdown_count(event)))
2929 return static_call(intel_pmu_set_topdown_event_period)(event);
2930
2931 return x86_perf_event_set_period(event);
2932 }
2933
intel_pmu_update(struct perf_event * event)2934 static u64 intel_pmu_update(struct perf_event *event)
2935 {
2936 if (unlikely(is_topdown_count(event)))
2937 return static_call(intel_pmu_update_topdown_event)(event);
2938
2939 return x86_perf_event_update(event);
2940 }
2941
intel_pmu_reset(void)2942 static void intel_pmu_reset(void)
2943 {
2944 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2945 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2946 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
2947 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
2948 unsigned long flags;
2949 int idx;
2950
2951 if (!*(u64 *)cntr_mask)
2952 return;
2953
2954 local_irq_save(flags);
2955
2956 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2957
2958 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
2959 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2960 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2961 }
2962 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
2963 if (fixed_counter_disabled(idx, cpuc->pmu))
2964 continue;
2965 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
2966 }
2967
2968 if (ds)
2969 ds->bts_index = ds->bts_buffer_base;
2970
2971 /* Ack all overflows and disable fixed counters */
2972 if (x86_pmu.version >= 2) {
2973 intel_pmu_ack_status(intel_pmu_get_status());
2974 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2975 }
2976
2977 /* Reset LBRs and LBR freezing */
2978 if (x86_pmu.lbr_nr) {
2979 update_debugctlmsr(get_debugctlmsr() &
2980 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2981 }
2982
2983 local_irq_restore(flags);
2984 }
2985
2986 /*
2987 * We may be running with guest PEBS events created by KVM, and the
2988 * PEBS records are logged into the guest's DS and invisible to host.
2989 *
2990 * In the case of guest PEBS overflow, we only trigger a fake event
2991 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
2992 * The guest will then vm-entry and check the guest DS area to read
2993 * the guest PEBS records.
2994 *
2995 * The contents and other behavior of the guest event do not matter.
2996 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)2997 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
2998 struct perf_sample_data *data)
2999 {
3000 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3001 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3002 struct perf_event *event = NULL;
3003 int bit;
3004
3005 if (!unlikely(perf_guest_state()))
3006 return;
3007
3008 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3009 !guest_pebs_idxs)
3010 return;
3011
3012 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3013 event = cpuc->events[bit];
3014 if (!event->attr.precise_ip)
3015 continue;
3016
3017 perf_sample_data_init(data, 0, event->hw.last_period);
3018 if (perf_event_overflow(event, data, regs))
3019 x86_pmu_stop(event, 0);
3020
3021 /* Inject one fake event is enough. */
3022 break;
3023 }
3024 }
3025
handle_pmi_common(struct pt_regs * regs,u64 status)3026 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3027 {
3028 struct perf_sample_data data;
3029 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3030 int bit;
3031 int handled = 0;
3032 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3033
3034 inc_irq_stat(apic_perf_irqs);
3035
3036 /*
3037 * Ignore a range of extra bits in status that do not indicate
3038 * overflow by themselves.
3039 */
3040 status &= ~(GLOBAL_STATUS_COND_CHG |
3041 GLOBAL_STATUS_ASIF |
3042 GLOBAL_STATUS_LBRS_FROZEN);
3043 if (!status)
3044 return 0;
3045 /*
3046 * In case multiple PEBS events are sampled at the same time,
3047 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3048 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3049 * having their bits set in the status register. This is a sign
3050 * that there was at least one PEBS record pending at the time
3051 * of the PMU interrupt. PEBS counters must only be processed
3052 * via the drain_pebs() calls and not via the regular sample
3053 * processing loop coming after that the function, otherwise
3054 * phony regular samples may be generated in the sampling buffer
3055 * not marked with the EXACT tag. Another possibility is to have
3056 * one PEBS event and at least one non-PEBS event which overflows
3057 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3058 * not be set, yet the overflow status bit for the PEBS counter will
3059 * be on Skylake.
3060 *
3061 * To avoid this problem, we systematically ignore the PEBS-enabled
3062 * counters from the GLOBAL_STATUS mask and we always process PEBS
3063 * events via drain_pebs().
3064 */
3065 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3066
3067 /*
3068 * PEBS overflow sets bit 62 in the global status register
3069 */
3070 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3071 u64 pebs_enabled = cpuc->pebs_enabled;
3072
3073 handled++;
3074 x86_pmu_handle_guest_pebs(regs, &data);
3075 static_call(x86_pmu_drain_pebs)(regs, &data);
3076 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
3077
3078 /*
3079 * PMI throttle may be triggered, which stops the PEBS event.
3080 * Although cpuc->pebs_enabled is updated accordingly, the
3081 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3082 * cpuc->enabled has been forced to 0 in PMI.
3083 * Update the MSR if pebs_enabled is changed.
3084 */
3085 if (pebs_enabled != cpuc->pebs_enabled)
3086 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3087 }
3088
3089 /*
3090 * Intel PT
3091 */
3092 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3093 handled++;
3094 if (!perf_guest_handle_intel_pt_intr())
3095 intel_pt_interrupt();
3096 }
3097
3098 /*
3099 * Intel Perf metrics
3100 */
3101 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3102 handled++;
3103 static_call(intel_pmu_update_topdown_event)(NULL);
3104 }
3105
3106 /*
3107 * Checkpointed counters can lead to 'spurious' PMIs because the
3108 * rollback caused by the PMI will have cleared the overflow status
3109 * bit. Therefore always force probe these counters.
3110 */
3111 status |= cpuc->intel_cp_status;
3112
3113 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3114 struct perf_event *event = cpuc->events[bit];
3115
3116 handled++;
3117
3118 if (!test_bit(bit, cpuc->active_mask))
3119 continue;
3120
3121 if (!intel_pmu_save_and_restart(event))
3122 continue;
3123
3124 perf_sample_data_init(&data, 0, event->hw.last_period);
3125
3126 if (has_branch_stack(event))
3127 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3128
3129 if (perf_event_overflow(event, &data, regs))
3130 x86_pmu_stop(event, 0);
3131 }
3132
3133 return handled;
3134 }
3135
3136 /*
3137 * This handler is triggered by the local APIC, so the APIC IRQ handling
3138 * rules apply:
3139 */
intel_pmu_handle_irq(struct pt_regs * regs)3140 static int intel_pmu_handle_irq(struct pt_regs *regs)
3141 {
3142 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3143 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3144 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3145 int loops;
3146 u64 status;
3147 int handled;
3148 int pmu_enabled;
3149
3150 /*
3151 * Save the PMU state.
3152 * It needs to be restored when leaving the handler.
3153 */
3154 pmu_enabled = cpuc->enabled;
3155 /*
3156 * In general, the early ACK is only applied for old platforms.
3157 * For the big core starts from Haswell, the late ACK should be
3158 * applied.
3159 * For the small core after Tremont, we have to do the ACK right
3160 * before re-enabling counters, which is in the middle of the
3161 * NMI handler.
3162 */
3163 if (!late_ack && !mid_ack)
3164 apic_write(APIC_LVTPC, APIC_DM_NMI);
3165 intel_bts_disable_local();
3166 cpuc->enabled = 0;
3167 __intel_pmu_disable_all(true);
3168 handled = intel_pmu_drain_bts_buffer();
3169 handled += intel_bts_interrupt();
3170 status = intel_pmu_get_status();
3171 if (!status)
3172 goto done;
3173
3174 loops = 0;
3175 again:
3176 intel_pmu_lbr_read();
3177 intel_pmu_ack_status(status);
3178 if (++loops > 100) {
3179 static bool warned;
3180
3181 if (!warned) {
3182 WARN(1, "perfevents: irq loop stuck!\n");
3183 perf_event_print_debug();
3184 warned = true;
3185 }
3186 intel_pmu_reset();
3187 goto done;
3188 }
3189
3190 handled += handle_pmi_common(regs, status);
3191
3192 /*
3193 * Repeat if there is more work to be done:
3194 */
3195 status = intel_pmu_get_status();
3196 if (status)
3197 goto again;
3198
3199 done:
3200 if (mid_ack)
3201 apic_write(APIC_LVTPC, APIC_DM_NMI);
3202 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3203 cpuc->enabled = pmu_enabled;
3204 if (pmu_enabled)
3205 __intel_pmu_enable_all(0, true);
3206 intel_bts_enable_local();
3207
3208 /*
3209 * Only unmask the NMI after the overflow counters
3210 * have been reset. This avoids spurious NMIs on
3211 * Haswell CPUs.
3212 */
3213 if (late_ack)
3214 apic_write(APIC_LVTPC, APIC_DM_NMI);
3215 return handled;
3216 }
3217
3218 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)3219 intel_bts_constraints(struct perf_event *event)
3220 {
3221 if (unlikely(intel_pmu_has_bts(event)))
3222 return &bts_constraint;
3223
3224 return NULL;
3225 }
3226
3227 /*
3228 * Note: matches a fake event, like Fixed2.
3229 */
3230 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)3231 intel_vlbr_constraints(struct perf_event *event)
3232 {
3233 struct event_constraint *c = &vlbr_constraint;
3234
3235 if (unlikely(constraint_match(c, event->hw.config))) {
3236 event->hw.flags |= c->flags;
3237 return c;
3238 }
3239
3240 return NULL;
3241 }
3242
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)3243 static int intel_alt_er(struct cpu_hw_events *cpuc,
3244 int idx, u64 config)
3245 {
3246 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3247 int alt_idx = idx;
3248
3249 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3250 return idx;
3251
3252 if (idx == EXTRA_REG_RSP_0)
3253 alt_idx = EXTRA_REG_RSP_1;
3254
3255 if (idx == EXTRA_REG_RSP_1)
3256 alt_idx = EXTRA_REG_RSP_0;
3257
3258 if (config & ~extra_regs[alt_idx].valid_mask)
3259 return idx;
3260
3261 return alt_idx;
3262 }
3263
intel_fixup_er(struct perf_event * event,int idx)3264 static void intel_fixup_er(struct perf_event *event, int idx)
3265 {
3266 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3267 event->hw.extra_reg.idx = idx;
3268
3269 if (idx == EXTRA_REG_RSP_0) {
3270 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3271 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3272 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3273 } else if (idx == EXTRA_REG_RSP_1) {
3274 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3275 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3276 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3277 }
3278 }
3279
3280 /*
3281 * manage allocation of shared extra msr for certain events
3282 *
3283 * sharing can be:
3284 * per-cpu: to be shared between the various events on a single PMU
3285 * per-core: per-cpu + shared by HT threads
3286 */
3287 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)3288 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3289 struct perf_event *event,
3290 struct hw_perf_event_extra *reg)
3291 {
3292 struct event_constraint *c = &emptyconstraint;
3293 struct er_account *era;
3294 unsigned long flags;
3295 int idx = reg->idx;
3296
3297 /*
3298 * reg->alloc can be set due to existing state, so for fake cpuc we
3299 * need to ignore this, otherwise we might fail to allocate proper fake
3300 * state for this extra reg constraint. Also see the comment below.
3301 */
3302 if (reg->alloc && !cpuc->is_fake)
3303 return NULL; /* call x86_get_event_constraint() */
3304
3305 again:
3306 era = &cpuc->shared_regs->regs[idx];
3307 /*
3308 * we use spin_lock_irqsave() to avoid lockdep issues when
3309 * passing a fake cpuc
3310 */
3311 raw_spin_lock_irqsave(&era->lock, flags);
3312
3313 if (!atomic_read(&era->ref) || era->config == reg->config) {
3314
3315 /*
3316 * If its a fake cpuc -- as per validate_{group,event}() we
3317 * shouldn't touch event state and we can avoid doing so
3318 * since both will only call get_event_constraints() once
3319 * on each event, this avoids the need for reg->alloc.
3320 *
3321 * Not doing the ER fixup will only result in era->reg being
3322 * wrong, but since we won't actually try and program hardware
3323 * this isn't a problem either.
3324 */
3325 if (!cpuc->is_fake) {
3326 if (idx != reg->idx)
3327 intel_fixup_er(event, idx);
3328
3329 /*
3330 * x86_schedule_events() can call get_event_constraints()
3331 * multiple times on events in the case of incremental
3332 * scheduling(). reg->alloc ensures we only do the ER
3333 * allocation once.
3334 */
3335 reg->alloc = 1;
3336 }
3337
3338 /* lock in msr value */
3339 era->config = reg->config;
3340 era->reg = reg->reg;
3341
3342 /* one more user */
3343 atomic_inc(&era->ref);
3344
3345 /*
3346 * need to call x86_get_event_constraint()
3347 * to check if associated event has constraints
3348 */
3349 c = NULL;
3350 } else {
3351 idx = intel_alt_er(cpuc, idx, reg->config);
3352 if (idx != reg->idx) {
3353 raw_spin_unlock_irqrestore(&era->lock, flags);
3354 goto again;
3355 }
3356 }
3357 raw_spin_unlock_irqrestore(&era->lock, flags);
3358
3359 return c;
3360 }
3361
3362 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3363 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3364 struct hw_perf_event_extra *reg)
3365 {
3366 struct er_account *era;
3367
3368 /*
3369 * Only put constraint if extra reg was actually allocated. Also takes
3370 * care of event which do not use an extra shared reg.
3371 *
3372 * Also, if this is a fake cpuc we shouldn't touch any event state
3373 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3374 * either since it'll be thrown out.
3375 */
3376 if (!reg->alloc || cpuc->is_fake)
3377 return;
3378
3379 era = &cpuc->shared_regs->regs[reg->idx];
3380
3381 /* one fewer user */
3382 atomic_dec(&era->ref);
3383
3384 /* allocate again next time */
3385 reg->alloc = 0;
3386 }
3387
3388 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3389 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3390 struct perf_event *event)
3391 {
3392 struct event_constraint *c = NULL, *d;
3393 struct hw_perf_event_extra *xreg, *breg;
3394
3395 xreg = &event->hw.extra_reg;
3396 if (xreg->idx != EXTRA_REG_NONE) {
3397 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3398 if (c == &emptyconstraint)
3399 return c;
3400 }
3401 breg = &event->hw.branch_reg;
3402 if (breg->idx != EXTRA_REG_NONE) {
3403 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3404 if (d == &emptyconstraint) {
3405 __intel_shared_reg_put_constraints(cpuc, xreg);
3406 c = d;
3407 }
3408 }
3409 return c;
3410 }
3411
3412 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3413 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3414 struct perf_event *event)
3415 {
3416 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3417 struct event_constraint *c;
3418
3419 if (event_constraints) {
3420 for_each_event_constraint(c, event_constraints) {
3421 if (constraint_match(c, event->hw.config)) {
3422 event->hw.flags |= c->flags;
3423 return c;
3424 }
3425 }
3426 }
3427
3428 return &hybrid_var(cpuc->pmu, unconstrained);
3429 }
3430
3431 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3432 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3433 struct perf_event *event)
3434 {
3435 struct event_constraint *c;
3436
3437 c = intel_vlbr_constraints(event);
3438 if (c)
3439 return c;
3440
3441 c = intel_bts_constraints(event);
3442 if (c)
3443 return c;
3444
3445 c = intel_shared_regs_constraints(cpuc, event);
3446 if (c)
3447 return c;
3448
3449 c = intel_pebs_constraints(event);
3450 if (c)
3451 return c;
3452
3453 return x86_get_event_constraints(cpuc, idx, event);
3454 }
3455
3456 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3457 intel_start_scheduling(struct cpu_hw_events *cpuc)
3458 {
3459 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3460 struct intel_excl_states *xl;
3461 int tid = cpuc->excl_thread_id;
3462
3463 /*
3464 * nothing needed if in group validation mode
3465 */
3466 if (cpuc->is_fake || !is_ht_workaround_enabled())
3467 return;
3468
3469 /*
3470 * no exclusion needed
3471 */
3472 if (WARN_ON_ONCE(!excl_cntrs))
3473 return;
3474
3475 xl = &excl_cntrs->states[tid];
3476
3477 xl->sched_started = true;
3478 /*
3479 * lock shared state until we are done scheduling
3480 * in stop_event_scheduling()
3481 * makes scheduling appear as a transaction
3482 */
3483 raw_spin_lock(&excl_cntrs->lock);
3484 }
3485
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3486 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3487 {
3488 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3489 struct event_constraint *c = cpuc->event_constraint[idx];
3490 struct intel_excl_states *xl;
3491 int tid = cpuc->excl_thread_id;
3492
3493 if (cpuc->is_fake || !is_ht_workaround_enabled())
3494 return;
3495
3496 if (WARN_ON_ONCE(!excl_cntrs))
3497 return;
3498
3499 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3500 return;
3501
3502 xl = &excl_cntrs->states[tid];
3503
3504 lockdep_assert_held(&excl_cntrs->lock);
3505
3506 if (c->flags & PERF_X86_EVENT_EXCL)
3507 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3508 else
3509 xl->state[cntr] = INTEL_EXCL_SHARED;
3510 }
3511
3512 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3513 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3514 {
3515 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3516 struct intel_excl_states *xl;
3517 int tid = cpuc->excl_thread_id;
3518
3519 /*
3520 * nothing needed if in group validation mode
3521 */
3522 if (cpuc->is_fake || !is_ht_workaround_enabled())
3523 return;
3524 /*
3525 * no exclusion needed
3526 */
3527 if (WARN_ON_ONCE(!excl_cntrs))
3528 return;
3529
3530 xl = &excl_cntrs->states[tid];
3531
3532 xl->sched_started = false;
3533 /*
3534 * release shared state lock (acquired in intel_start_scheduling())
3535 */
3536 raw_spin_unlock(&excl_cntrs->lock);
3537 }
3538
3539 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3540 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3541 {
3542 WARN_ON_ONCE(!cpuc->constraint_list);
3543
3544 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3545 struct event_constraint *cx;
3546
3547 /*
3548 * grab pre-allocated constraint entry
3549 */
3550 cx = &cpuc->constraint_list[idx];
3551
3552 /*
3553 * initialize dynamic constraint
3554 * with static constraint
3555 */
3556 *cx = *c;
3557
3558 /*
3559 * mark constraint as dynamic
3560 */
3561 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3562 c = cx;
3563 }
3564
3565 return c;
3566 }
3567
3568 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3569 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3570 int idx, struct event_constraint *c)
3571 {
3572 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3573 struct intel_excl_states *xlo;
3574 int tid = cpuc->excl_thread_id;
3575 int is_excl, i, w;
3576
3577 /*
3578 * validating a group does not require
3579 * enforcing cross-thread exclusion
3580 */
3581 if (cpuc->is_fake || !is_ht_workaround_enabled())
3582 return c;
3583
3584 /*
3585 * no exclusion needed
3586 */
3587 if (WARN_ON_ONCE(!excl_cntrs))
3588 return c;
3589
3590 /*
3591 * because we modify the constraint, we need
3592 * to make a copy. Static constraints come
3593 * from static const tables.
3594 *
3595 * only needed when constraint has not yet
3596 * been cloned (marked dynamic)
3597 */
3598 c = dyn_constraint(cpuc, c, idx);
3599
3600 /*
3601 * From here on, the constraint is dynamic.
3602 * Either it was just allocated above, or it
3603 * was allocated during a earlier invocation
3604 * of this function
3605 */
3606
3607 /*
3608 * state of sibling HT
3609 */
3610 xlo = &excl_cntrs->states[tid ^ 1];
3611
3612 /*
3613 * event requires exclusive counter access
3614 * across HT threads
3615 */
3616 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3617 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3618 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3619 if (!cpuc->n_excl++)
3620 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3621 }
3622
3623 /*
3624 * Modify static constraint with current dynamic
3625 * state of thread
3626 *
3627 * EXCLUSIVE: sibling counter measuring exclusive event
3628 * SHARED : sibling counter measuring non-exclusive event
3629 * UNUSED : sibling counter unused
3630 */
3631 w = c->weight;
3632 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3633 /*
3634 * exclusive event in sibling counter
3635 * our corresponding counter cannot be used
3636 * regardless of our event
3637 */
3638 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3639 __clear_bit(i, c->idxmsk);
3640 w--;
3641 continue;
3642 }
3643 /*
3644 * if measuring an exclusive event, sibling
3645 * measuring non-exclusive, then counter cannot
3646 * be used
3647 */
3648 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3649 __clear_bit(i, c->idxmsk);
3650 w--;
3651 continue;
3652 }
3653 }
3654
3655 /*
3656 * if we return an empty mask, then switch
3657 * back to static empty constraint to avoid
3658 * the cost of freeing later on
3659 */
3660 if (!w)
3661 c = &emptyconstraint;
3662
3663 c->weight = w;
3664
3665 return c;
3666 }
3667
3668 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3669 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3670 struct perf_event *event)
3671 {
3672 struct event_constraint *c1, *c2;
3673
3674 c1 = cpuc->event_constraint[idx];
3675
3676 /*
3677 * first time only
3678 * - static constraint: no change across incremental scheduling calls
3679 * - dynamic constraint: handled by intel_get_excl_constraints()
3680 */
3681 c2 = __intel_get_event_constraints(cpuc, idx, event);
3682 if (c1) {
3683 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3684 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3685 c1->weight = c2->weight;
3686 c2 = c1;
3687 }
3688
3689 if (cpuc->excl_cntrs)
3690 return intel_get_excl_constraints(cpuc, event, idx, c2);
3691
3692 /* Not all counters support the branch counter feature. */
3693 if (branch_sample_counters(event)) {
3694 c2 = dyn_constraint(cpuc, c2, idx);
3695 c2->idxmsk64 &= x86_pmu.lbr_counters;
3696 c2->weight = hweight64(c2->idxmsk64);
3697 }
3698
3699 return c2;
3700 }
3701
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3702 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3703 struct perf_event *event)
3704 {
3705 struct hw_perf_event *hwc = &event->hw;
3706 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3707 int tid = cpuc->excl_thread_id;
3708 struct intel_excl_states *xl;
3709
3710 /*
3711 * nothing needed if in group validation mode
3712 */
3713 if (cpuc->is_fake)
3714 return;
3715
3716 if (WARN_ON_ONCE(!excl_cntrs))
3717 return;
3718
3719 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3720 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3721 if (!--cpuc->n_excl)
3722 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3723 }
3724
3725 /*
3726 * If event was actually assigned, then mark the counter state as
3727 * unused now.
3728 */
3729 if (hwc->idx >= 0) {
3730 xl = &excl_cntrs->states[tid];
3731
3732 /*
3733 * put_constraint may be called from x86_schedule_events()
3734 * which already has the lock held so here make locking
3735 * conditional.
3736 */
3737 if (!xl->sched_started)
3738 raw_spin_lock(&excl_cntrs->lock);
3739
3740 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3741
3742 if (!xl->sched_started)
3743 raw_spin_unlock(&excl_cntrs->lock);
3744 }
3745 }
3746
3747 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3748 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3749 struct perf_event *event)
3750 {
3751 struct hw_perf_event_extra *reg;
3752
3753 reg = &event->hw.extra_reg;
3754 if (reg->idx != EXTRA_REG_NONE)
3755 __intel_shared_reg_put_constraints(cpuc, reg);
3756
3757 reg = &event->hw.branch_reg;
3758 if (reg->idx != EXTRA_REG_NONE)
3759 __intel_shared_reg_put_constraints(cpuc, reg);
3760 }
3761
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3762 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3763 struct perf_event *event)
3764 {
3765 intel_put_shared_regs_event_constraints(cpuc, event);
3766
3767 /*
3768 * is PMU has exclusive counter restrictions, then
3769 * all events are subject to and must call the
3770 * put_excl_constraints() routine
3771 */
3772 if (cpuc->excl_cntrs)
3773 intel_put_excl_constraints(cpuc, event);
3774 }
3775
intel_pebs_aliases_core2(struct perf_event * event)3776 static void intel_pebs_aliases_core2(struct perf_event *event)
3777 {
3778 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3779 /*
3780 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3781 * (0x003c) so that we can use it with PEBS.
3782 *
3783 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3784 * PEBS capable. However we can use INST_RETIRED.ANY_P
3785 * (0x00c0), which is a PEBS capable event, to get the same
3786 * count.
3787 *
3788 * INST_RETIRED.ANY_P counts the number of cycles that retires
3789 * CNTMASK instructions. By setting CNTMASK to a value (16)
3790 * larger than the maximum number of instructions that can be
3791 * retired per cycle (4) and then inverting the condition, we
3792 * count all cycles that retire 16 or less instructions, which
3793 * is every cycle.
3794 *
3795 * Thereby we gain a PEBS capable cycle counter.
3796 */
3797 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3798
3799 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3800 event->hw.config = alt_config;
3801 }
3802 }
3803
intel_pebs_aliases_snb(struct perf_event * event)3804 static void intel_pebs_aliases_snb(struct perf_event *event)
3805 {
3806 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3807 /*
3808 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3809 * (0x003c) so that we can use it with PEBS.
3810 *
3811 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3812 * PEBS capable. However we can use UOPS_RETIRED.ALL
3813 * (0x01c2), which is a PEBS capable event, to get the same
3814 * count.
3815 *
3816 * UOPS_RETIRED.ALL counts the number of cycles that retires
3817 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3818 * larger than the maximum number of micro-ops that can be
3819 * retired per cycle (4) and then inverting the condition, we
3820 * count all cycles that retire 16 or less micro-ops, which
3821 * is every cycle.
3822 *
3823 * Thereby we gain a PEBS capable cycle counter.
3824 */
3825 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3826
3827 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3828 event->hw.config = alt_config;
3829 }
3830 }
3831
intel_pebs_aliases_precdist(struct perf_event * event)3832 static void intel_pebs_aliases_precdist(struct perf_event *event)
3833 {
3834 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3835 /*
3836 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3837 * (0x003c) so that we can use it with PEBS.
3838 *
3839 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3840 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3841 * (0x01c0), which is a PEBS capable event, to get the same
3842 * count.
3843 *
3844 * The PREC_DIST event has special support to minimize sample
3845 * shadowing effects. One drawback is that it can be
3846 * only programmed on counter 1, but that seems like an
3847 * acceptable trade off.
3848 */
3849 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3850
3851 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3852 event->hw.config = alt_config;
3853 }
3854 }
3855
intel_pebs_aliases_ivb(struct perf_event * event)3856 static void intel_pebs_aliases_ivb(struct perf_event *event)
3857 {
3858 if (event->attr.precise_ip < 3)
3859 return intel_pebs_aliases_snb(event);
3860 return intel_pebs_aliases_precdist(event);
3861 }
3862
intel_pebs_aliases_skl(struct perf_event * event)3863 static void intel_pebs_aliases_skl(struct perf_event *event)
3864 {
3865 if (event->attr.precise_ip < 3)
3866 return intel_pebs_aliases_core2(event);
3867 return intel_pebs_aliases_precdist(event);
3868 }
3869
intel_pmu_large_pebs_flags(struct perf_event * event)3870 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3871 {
3872 unsigned long flags = x86_pmu.large_pebs_flags;
3873
3874 if (event->attr.use_clockid)
3875 flags &= ~PERF_SAMPLE_TIME;
3876 if (!event->attr.exclude_kernel)
3877 flags &= ~PERF_SAMPLE_REGS_USER;
3878 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3879 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3880 return flags;
3881 }
3882
intel_pmu_bts_config(struct perf_event * event)3883 static int intel_pmu_bts_config(struct perf_event *event)
3884 {
3885 struct perf_event_attr *attr = &event->attr;
3886
3887 if (unlikely(intel_pmu_has_bts(event))) {
3888 /* BTS is not supported by this architecture. */
3889 if (!x86_pmu.bts_active)
3890 return -EOPNOTSUPP;
3891
3892 /* BTS is currently only allowed for user-mode. */
3893 if (!attr->exclude_kernel)
3894 return -EOPNOTSUPP;
3895
3896 /* BTS is not allowed for precise events. */
3897 if (attr->precise_ip)
3898 return -EOPNOTSUPP;
3899
3900 /* disallow bts if conflicting events are present */
3901 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3902 return -EBUSY;
3903
3904 event->destroy = hw_perf_lbr_event_destroy;
3905 }
3906
3907 return 0;
3908 }
3909
core_pmu_hw_config(struct perf_event * event)3910 static int core_pmu_hw_config(struct perf_event *event)
3911 {
3912 int ret = x86_pmu_hw_config(event);
3913
3914 if (ret)
3915 return ret;
3916
3917 return intel_pmu_bts_config(event);
3918 }
3919
3920 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3921 ((x86_pmu.num_topdown_events - 1) << 8))
3922
is_available_metric_event(struct perf_event * event)3923 static bool is_available_metric_event(struct perf_event *event)
3924 {
3925 return is_metric_event(event) &&
3926 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3927 }
3928
is_mem_loads_event(struct perf_event * event)3929 static inline bool is_mem_loads_event(struct perf_event *event)
3930 {
3931 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3932 }
3933
is_mem_loads_aux_event(struct perf_event * event)3934 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3935 {
3936 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3937 }
3938
require_mem_loads_aux_event(struct perf_event * event)3939 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3940 {
3941 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3942 return false;
3943
3944 if (is_hybrid())
3945 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
3946
3947 return true;
3948 }
3949
intel_pmu_has_cap(struct perf_event * event,int idx)3950 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3951 {
3952 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3953
3954 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3955 }
3956
intel_pmu_freq_start_period(struct perf_event * event)3957 static u64 intel_pmu_freq_start_period(struct perf_event *event)
3958 {
3959 int type = event->attr.type;
3960 u64 config, factor;
3961 s64 start;
3962
3963 /*
3964 * The 127 is the lowest possible recommended SAV (sample after value)
3965 * for a 4000 freq (default freq), according to the event list JSON file.
3966 * Also, assume the workload is idle 50% time.
3967 */
3968 factor = 64 * 4000;
3969 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
3970 goto end;
3971
3972 /*
3973 * The estimation of the start period in the freq mode is
3974 * based on the below assumption.
3975 *
3976 * For a cycles or an instructions event, 1GHZ of the
3977 * underlying platform, 1 IPC. The workload is idle 50% time.
3978 * The start period = 1,000,000,000 * 1 / freq / 2.
3979 * = 500,000,000 / freq
3980 *
3981 * Usually, the branch-related events occur less than the
3982 * instructions event. According to the Intel event list JSON
3983 * file, the SAV (sample after value) of a branch-related event
3984 * is usually 1/4 of an instruction event.
3985 * The start period of branch-related events = 125,000,000 / freq.
3986 *
3987 * The cache-related events occurs even less. The SAV is usually
3988 * 1/20 of an instruction event.
3989 * The start period of cache-related events = 25,000,000 / freq.
3990 */
3991 config = event->attr.config & PERF_HW_EVENT_MASK;
3992 if (type == PERF_TYPE_HARDWARE) {
3993 switch (config) {
3994 case PERF_COUNT_HW_CPU_CYCLES:
3995 case PERF_COUNT_HW_INSTRUCTIONS:
3996 case PERF_COUNT_HW_BUS_CYCLES:
3997 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
3998 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
3999 case PERF_COUNT_HW_REF_CPU_CYCLES:
4000 factor = 500000000;
4001 break;
4002 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4003 case PERF_COUNT_HW_BRANCH_MISSES:
4004 factor = 125000000;
4005 break;
4006 case PERF_COUNT_HW_CACHE_REFERENCES:
4007 case PERF_COUNT_HW_CACHE_MISSES:
4008 factor = 25000000;
4009 break;
4010 default:
4011 goto end;
4012 }
4013 }
4014
4015 if (type == PERF_TYPE_HW_CACHE)
4016 factor = 25000000;
4017 end:
4018 /*
4019 * Usually, a prime or a number with less factors (close to prime)
4020 * is chosen as an SAV, which makes it less likely that the sampling
4021 * period synchronizes with some periodic event in the workload.
4022 * Minus 1 to make it at least avoiding values near power of twos
4023 * for the default freq.
4024 */
4025 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4026
4027 if (start > x86_pmu.max_period)
4028 start = x86_pmu.max_period;
4029
4030 if (x86_pmu.limit_period)
4031 x86_pmu.limit_period(event, &start);
4032
4033 return start;
4034 }
4035
intel_pmu_hw_config(struct perf_event * event)4036 static int intel_pmu_hw_config(struct perf_event *event)
4037 {
4038 int ret = x86_pmu_hw_config(event);
4039
4040 if (ret)
4041 return ret;
4042
4043 ret = intel_pmu_bts_config(event);
4044 if (ret)
4045 return ret;
4046
4047 if (event->attr.freq && event->attr.sample_freq) {
4048 event->hw.sample_period = intel_pmu_freq_start_period(event);
4049 event->hw.last_period = event->hw.sample_period;
4050 local64_set(&event->hw.period_left, event->hw.sample_period);
4051 }
4052
4053 if (event->attr.precise_ip) {
4054 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4055 return -EINVAL;
4056
4057 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4058 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4059 if (!(event->attr.sample_type &
4060 ~intel_pmu_large_pebs_flags(event))) {
4061 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4062 event->attach_state |= PERF_ATTACH_SCHED_CB;
4063 }
4064 }
4065 if (x86_pmu.pebs_aliases)
4066 x86_pmu.pebs_aliases(event);
4067 }
4068
4069 if (needs_branch_stack(event)) {
4070 /* Avoid branch stack setup for counting events in SAMPLE READ */
4071 if (is_sampling_event(event) ||
4072 !(event->attr.sample_type & PERF_SAMPLE_READ))
4073 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4074 }
4075
4076 if (branch_sample_counters(event)) {
4077 struct perf_event *leader, *sibling;
4078 int num = 0;
4079
4080 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4081 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4082 return -EINVAL;
4083
4084 /*
4085 * The branch counter logging is not supported in the call stack
4086 * mode yet, since we cannot simply flush the LBR during e.g.,
4087 * multiplexing. Also, there is no obvious usage with the call
4088 * stack mode. Simply forbids it for now.
4089 *
4090 * If any events in the group enable the branch counter logging
4091 * feature, the group is treated as a branch counter logging
4092 * group, which requires the extra space to store the counters.
4093 */
4094 leader = event->group_leader;
4095 if (branch_sample_call_stack(leader))
4096 return -EINVAL;
4097 if (branch_sample_counters(leader))
4098 num++;
4099 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4100
4101 for_each_sibling_event(sibling, leader) {
4102 if (branch_sample_call_stack(sibling))
4103 return -EINVAL;
4104 if (branch_sample_counters(sibling))
4105 num++;
4106 }
4107
4108 if (num > fls(x86_pmu.lbr_counters))
4109 return -EINVAL;
4110 /*
4111 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
4112 * require any branch stack setup.
4113 * Clear the bit to avoid unnecessary branch stack setup.
4114 */
4115 if (0 == (event->attr.branch_sample_type &
4116 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
4117 PERF_SAMPLE_BRANCH_COUNTERS)))
4118 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4119
4120 /*
4121 * Force the leader to be a LBR event. So LBRs can be reset
4122 * with the leader event. See intel_pmu_lbr_del() for details.
4123 */
4124 if (!intel_pmu_needs_branch_stack(leader))
4125 return -EINVAL;
4126 }
4127
4128 if (intel_pmu_needs_branch_stack(event)) {
4129 ret = intel_pmu_setup_lbr_filter(event);
4130 if (ret)
4131 return ret;
4132 event->attach_state |= PERF_ATTACH_SCHED_CB;
4133
4134 /*
4135 * BTS is set up earlier in this path, so don't account twice
4136 */
4137 if (!unlikely(intel_pmu_has_bts(event))) {
4138 /* disallow lbr if conflicting events are present */
4139 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4140 return -EBUSY;
4141
4142 event->destroy = hw_perf_lbr_event_destroy;
4143 }
4144 }
4145
4146 if (event->attr.aux_output) {
4147 if (!event->attr.precise_ip)
4148 return -EINVAL;
4149
4150 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
4151 }
4152
4153 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
4154 (event->attr.type == PERF_TYPE_HW_CACHE))
4155 return 0;
4156
4157 /*
4158 * Config Topdown slots and metric events
4159 *
4160 * The slots event on Fixed Counter 3 can support sampling,
4161 * which will be handled normally in x86_perf_event_update().
4162 *
4163 * Metric events don't support sampling and require being paired
4164 * with a slots event as group leader. When the slots event
4165 * is used in a metrics group, it too cannot support sampling.
4166 */
4167 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
4168 if (event->attr.config1 || event->attr.config2)
4169 return -EINVAL;
4170
4171 /*
4172 * The TopDown metrics events and slots event don't
4173 * support any filters.
4174 */
4175 if (event->attr.config & X86_ALL_EVENT_FLAGS)
4176 return -EINVAL;
4177
4178 if (is_available_metric_event(event)) {
4179 struct perf_event *leader = event->group_leader;
4180
4181 /* The metric events don't support sampling. */
4182 if (is_sampling_event(event))
4183 return -EINVAL;
4184
4185 /* The metric events require a slots group leader. */
4186 if (!is_slots_event(leader))
4187 return -EINVAL;
4188
4189 /*
4190 * The leader/SLOTS must not be a sampling event for
4191 * metric use; hardware requires it starts at 0 when used
4192 * in conjunction with MSR_PERF_METRICS.
4193 */
4194 if (is_sampling_event(leader))
4195 return -EINVAL;
4196
4197 event->event_caps |= PERF_EV_CAP_SIBLING;
4198 /*
4199 * Only once we have a METRICs sibling do we
4200 * need TopDown magic.
4201 */
4202 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4203 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4204 }
4205 }
4206
4207 /*
4208 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
4209 * doesn't function quite right. As a work-around it needs to always be
4210 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
4211 * The actual count of this second event is irrelevant it just needs
4212 * to be active to make the first event function correctly.
4213 *
4214 * In a group, the auxiliary event must be in front of the load latency
4215 * event. The rule is to simplify the implementation of the check.
4216 * That's because perf cannot have a complete group at the moment.
4217 */
4218 if (require_mem_loads_aux_event(event) &&
4219 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
4220 is_mem_loads_event(event)) {
4221 struct perf_event *leader = event->group_leader;
4222 struct perf_event *sibling = NULL;
4223
4224 /*
4225 * When this memload event is also the first event (no group
4226 * exists yet), then there is no aux event before it.
4227 */
4228 if (leader == event)
4229 return -ENODATA;
4230
4231 if (!is_mem_loads_aux_event(leader)) {
4232 for_each_sibling_event(sibling, leader) {
4233 if (is_mem_loads_aux_event(sibling))
4234 break;
4235 }
4236 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4237 return -ENODATA;
4238 }
4239 }
4240
4241 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4242 return 0;
4243
4244 if (x86_pmu.version < 3)
4245 return -EINVAL;
4246
4247 ret = perf_allow_cpu(&event->attr);
4248 if (ret)
4249 return ret;
4250
4251 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4252
4253 return 0;
4254 }
4255
4256 /*
4257 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4258 * The host perf context helps to prepare the values of the real hardware for
4259 * a set of msrs that need to be switched atomically in a vmx transaction.
4260 *
4261 * For example, the pseudocode needed to add a new msr should look like:
4262 *
4263 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4264 * .msr = the hardware msr address,
4265 * .host = the value the hardware has when it doesn't run a guest,
4266 * .guest = the value the hardware has when it runs a guest,
4267 * };
4268 *
4269 * These values have nothing to do with the emulated values the guest sees
4270 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4271 * specifically in the intel_pmu_{get,set}_msr().
4272 */
intel_guest_get_msrs(int * nr,void * data)4273 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4274 {
4275 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4276 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4277 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4278 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4279 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4280 int global_ctrl, pebs_enable;
4281
4282 /*
4283 * In addition to obeying exclude_guest/exclude_host, remove bits being
4284 * used for PEBS when running a guest, because PEBS writes to virtual
4285 * addresses (not physical addresses).
4286 */
4287 *nr = 0;
4288 global_ctrl = (*nr)++;
4289 arr[global_ctrl] = (struct perf_guest_switch_msr){
4290 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4291 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4292 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
4293 };
4294
4295 if (!x86_pmu.pebs)
4296 return arr;
4297
4298 /*
4299 * If PMU counter has PEBS enabled it is not enough to
4300 * disable counter on a guest entry since PEBS memory
4301 * write can overshoot guest entry and corrupt guest
4302 * memory. Disabling PEBS solves the problem.
4303 *
4304 * Don't do this if the CPU already enforces it.
4305 */
4306 if (x86_pmu.pebs_no_isolation) {
4307 arr[(*nr)++] = (struct perf_guest_switch_msr){
4308 .msr = MSR_IA32_PEBS_ENABLE,
4309 .host = cpuc->pebs_enabled,
4310 .guest = 0,
4311 };
4312 return arr;
4313 }
4314
4315 if (!kvm_pmu || !x86_pmu.pebs_ept)
4316 return arr;
4317
4318 arr[(*nr)++] = (struct perf_guest_switch_msr){
4319 .msr = MSR_IA32_DS_AREA,
4320 .host = (unsigned long)cpuc->ds,
4321 .guest = kvm_pmu->ds_area,
4322 };
4323
4324 if (x86_pmu.intel_cap.pebs_baseline) {
4325 arr[(*nr)++] = (struct perf_guest_switch_msr){
4326 .msr = MSR_PEBS_DATA_CFG,
4327 .host = cpuc->active_pebs_data_cfg,
4328 .guest = kvm_pmu->pebs_data_cfg,
4329 };
4330 }
4331
4332 pebs_enable = (*nr)++;
4333 arr[pebs_enable] = (struct perf_guest_switch_msr){
4334 .msr = MSR_IA32_PEBS_ENABLE,
4335 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4336 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable,
4337 };
4338
4339 if (arr[pebs_enable].host) {
4340 /* Disable guest PEBS if host PEBS is enabled. */
4341 arr[pebs_enable].guest = 0;
4342 } else {
4343 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4344 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4345 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4346 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4347 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4348 }
4349
4350 return arr;
4351 }
4352
core_guest_get_msrs(int * nr,void * data)4353 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4354 {
4355 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4356 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4357 int idx;
4358
4359 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4360 struct perf_event *event = cpuc->events[idx];
4361
4362 arr[idx].msr = x86_pmu_config_addr(idx);
4363 arr[idx].host = arr[idx].guest = 0;
4364
4365 if (!test_bit(idx, cpuc->active_mask))
4366 continue;
4367
4368 arr[idx].host = arr[idx].guest =
4369 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4370
4371 if (event->attr.exclude_host)
4372 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4373 else if (event->attr.exclude_guest)
4374 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4375 }
4376
4377 *nr = x86_pmu_max_num_counters(cpuc->pmu);
4378 return arr;
4379 }
4380
core_pmu_enable_event(struct perf_event * event)4381 static void core_pmu_enable_event(struct perf_event *event)
4382 {
4383 if (!event->attr.exclude_host)
4384 x86_pmu_enable_event(event);
4385 }
4386
core_pmu_enable_all(int added)4387 static void core_pmu_enable_all(int added)
4388 {
4389 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4390 int idx;
4391
4392 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4393 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4394
4395 if (!test_bit(idx, cpuc->active_mask) ||
4396 cpuc->events[idx]->attr.exclude_host)
4397 continue;
4398
4399 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4400 }
4401 }
4402
hsw_hw_config(struct perf_event * event)4403 static int hsw_hw_config(struct perf_event *event)
4404 {
4405 int ret = intel_pmu_hw_config(event);
4406
4407 if (ret)
4408 return ret;
4409 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4410 return 0;
4411 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4412
4413 /*
4414 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4415 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4416 * this combination.
4417 */
4418 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4419 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4420 event->attr.precise_ip > 0))
4421 return -EOPNOTSUPP;
4422
4423 if (event_is_checkpointed(event)) {
4424 /*
4425 * Sampling of checkpointed events can cause situations where
4426 * the CPU constantly aborts because of a overflow, which is
4427 * then checkpointed back and ignored. Forbid checkpointing
4428 * for sampling.
4429 *
4430 * But still allow a long sampling period, so that perf stat
4431 * from KVM works.
4432 */
4433 if (event->attr.sample_period > 0 &&
4434 event->attr.sample_period < 0x7fffffff)
4435 return -EOPNOTSUPP;
4436 }
4437 return 0;
4438 }
4439
4440 static struct event_constraint counter0_constraint =
4441 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4442
4443 static struct event_constraint counter1_constraint =
4444 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4445
4446 static struct event_constraint counter0_1_constraint =
4447 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4448
4449 static struct event_constraint counter2_constraint =
4450 EVENT_CONSTRAINT(0, 0x4, 0);
4451
4452 static struct event_constraint fixed0_constraint =
4453 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4454
4455 static struct event_constraint fixed0_counter0_constraint =
4456 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4457
4458 static struct event_constraint fixed0_counter0_1_constraint =
4459 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4460
4461 static struct event_constraint counters_1_7_constraint =
4462 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4463
4464 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4465 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4466 struct perf_event *event)
4467 {
4468 struct event_constraint *c;
4469
4470 c = intel_get_event_constraints(cpuc, idx, event);
4471
4472 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4473 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4474 if (c->idxmsk64 & (1U << 2))
4475 return &counter2_constraint;
4476 return &emptyconstraint;
4477 }
4478
4479 return c;
4480 }
4481
4482 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4483 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4484 struct perf_event *event)
4485 {
4486 /*
4487 * Fixed counter 0 has less skid.
4488 * Force instruction:ppp in Fixed counter 0
4489 */
4490 if ((event->attr.precise_ip == 3) &&
4491 constraint_match(&fixed0_constraint, event->hw.config))
4492 return &fixed0_constraint;
4493
4494 return hsw_get_event_constraints(cpuc, idx, event);
4495 }
4496
4497 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4498 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4499 struct perf_event *event)
4500 {
4501 struct event_constraint *c;
4502
4503 c = icl_get_event_constraints(cpuc, idx, event);
4504
4505 /*
4506 * The :ppp indicates the Precise Distribution (PDist) facility, which
4507 * is only supported on the GP counter 0. If a :ppp event which is not
4508 * available on the GP counter 0, error out.
4509 * Exception: Instruction PDIR is only available on the fixed counter 0.
4510 */
4511 if ((event->attr.precise_ip == 3) &&
4512 !constraint_match(&fixed0_constraint, event->hw.config)) {
4513 if (c->idxmsk64 & BIT_ULL(0))
4514 return &counter0_constraint;
4515
4516 return &emptyconstraint;
4517 }
4518
4519 return c;
4520 }
4521
4522 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4523 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4524 struct perf_event *event)
4525 {
4526 struct event_constraint *c;
4527
4528 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4529 if (event->attr.precise_ip == 3)
4530 return &counter0_constraint;
4531
4532 c = intel_get_event_constraints(cpuc, idx, event);
4533
4534 return c;
4535 }
4536
4537 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4538 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4539 struct perf_event *event)
4540 {
4541 struct event_constraint *c;
4542
4543 c = intel_get_event_constraints(cpuc, idx, event);
4544
4545 /*
4546 * :ppp means to do reduced skid PEBS,
4547 * which is available on PMC0 and fixed counter 0.
4548 */
4549 if (event->attr.precise_ip == 3) {
4550 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4551 if (constraint_match(&fixed0_constraint, event->hw.config))
4552 return &fixed0_counter0_constraint;
4553
4554 return &counter0_constraint;
4555 }
4556
4557 return c;
4558 }
4559
4560 static bool allow_tsx_force_abort = true;
4561
4562 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4563 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4564 struct perf_event *event)
4565 {
4566 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4567
4568 /*
4569 * Without TFA we must not use PMC3.
4570 */
4571 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4572 c = dyn_constraint(cpuc, c, idx);
4573 c->idxmsk64 &= ~(1ULL << 3);
4574 c->weight--;
4575 }
4576
4577 return c;
4578 }
4579
4580 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4581 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4582 struct perf_event *event)
4583 {
4584 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4585
4586 if (pmu->pmu_type == hybrid_big)
4587 return glc_get_event_constraints(cpuc, idx, event);
4588 else if (pmu->pmu_type == hybrid_small)
4589 return tnt_get_event_constraints(cpuc, idx, event);
4590
4591 WARN_ON(1);
4592 return &emptyconstraint;
4593 }
4594
4595 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4596 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4597 struct perf_event *event)
4598 {
4599 struct event_constraint *c;
4600
4601 c = intel_get_event_constraints(cpuc, idx, event);
4602
4603 /*
4604 * The :ppp indicates the Precise Distribution (PDist) facility, which
4605 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
4606 * If a :ppp event which is not available on the above eligible counters,
4607 * error out.
4608 */
4609 if (event->attr.precise_ip == 3) {
4610 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
4611 if (constraint_match(&fixed0_constraint, event->hw.config)) {
4612 /* The fixed counter 0 doesn't support LBR event logging. */
4613 if (branch_sample_counters(event))
4614 return &counter0_1_constraint;
4615 else
4616 return &fixed0_counter0_1_constraint;
4617 }
4618
4619 switch (c->idxmsk64 & 0x3ull) {
4620 case 0x1:
4621 return &counter0_constraint;
4622 case 0x2:
4623 return &counter1_constraint;
4624 case 0x3:
4625 return &counter0_1_constraint;
4626 }
4627 return &emptyconstraint;
4628 }
4629
4630 return c;
4631 }
4632
4633 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4634 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4635 struct perf_event *event)
4636 {
4637 struct event_constraint *c;
4638
4639 c = glc_get_event_constraints(cpuc, idx, event);
4640
4641 /* The Retire Latency is not supported by the fixed counter 0. */
4642 if (event->attr.precise_ip &&
4643 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
4644 constraint_match(&fixed0_constraint, event->hw.config)) {
4645 /*
4646 * The Instruction PDIR is only available
4647 * on the fixed counter 0. Error out for this case.
4648 */
4649 if (event->attr.precise_ip == 3)
4650 return &emptyconstraint;
4651 return &counters_1_7_constraint;
4652 }
4653
4654 return c;
4655 }
4656
4657 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4658 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4659 struct perf_event *event)
4660 {
4661 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4662
4663 if (pmu->pmu_type == hybrid_big)
4664 return rwc_get_event_constraints(cpuc, idx, event);
4665 if (pmu->pmu_type == hybrid_small)
4666 return cmt_get_event_constraints(cpuc, idx, event);
4667
4668 WARN_ON(1);
4669 return &emptyconstraint;
4670 }
4671
adl_hw_config(struct perf_event * event)4672 static int adl_hw_config(struct perf_event *event)
4673 {
4674 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4675
4676 if (pmu->pmu_type == hybrid_big)
4677 return hsw_hw_config(event);
4678 else if (pmu->pmu_type == hybrid_small)
4679 return intel_pmu_hw_config(event);
4680
4681 WARN_ON(1);
4682 return -EOPNOTSUPP;
4683 }
4684
adl_get_hybrid_cpu_type(void)4685 static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
4686 {
4687 return HYBRID_INTEL_CORE;
4688 }
4689
erratum_hsw11(struct perf_event * event)4690 static inline bool erratum_hsw11(struct perf_event *event)
4691 {
4692 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4693 X86_CONFIG(.event=0xc0, .umask=0x01);
4694 }
4695
4696 /*
4697 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
4698 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
4699 *
4700 * The message 'interrupt took too long' can be observed on any counter which
4701 * was armed with a period < 32 and two events expired in the same NMI.
4702 * A minimum period of 32 is enforced for the rest of the events.
4703 */
hsw_limit_period(struct perf_event * event,s64 * left)4704 static void hsw_limit_period(struct perf_event *event, s64 *left)
4705 {
4706 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
4707 }
4708
4709 /*
4710 * Broadwell:
4711 *
4712 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4713 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4714 * the two to enforce a minimum period of 128 (the smallest value that has bits
4715 * 0-5 cleared and >= 100).
4716 *
4717 * Because of how the code in x86_perf_event_set_period() works, the truncation
4718 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4719 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4720 *
4721 * Therefore the effective (average) period matches the requested period,
4722 * despite coarser hardware granularity.
4723 */
bdw_limit_period(struct perf_event * event,s64 * left)4724 static void bdw_limit_period(struct perf_event *event, s64 *left)
4725 {
4726 if (erratum_hsw11(event)) {
4727 if (*left < 128)
4728 *left = 128;
4729 *left &= ~0x3fULL;
4730 }
4731 }
4732
nhm_limit_period(struct perf_event * event,s64 * left)4733 static void nhm_limit_period(struct perf_event *event, s64 *left)
4734 {
4735 *left = max(*left, 32LL);
4736 }
4737
glc_limit_period(struct perf_event * event,s64 * left)4738 static void glc_limit_period(struct perf_event *event, s64 *left)
4739 {
4740 if (event->attr.precise_ip == 3)
4741 *left = max(*left, 128LL);
4742 }
4743
4744 PMU_FORMAT_ATTR(event, "config:0-7" );
4745 PMU_FORMAT_ATTR(umask, "config:8-15" );
4746 PMU_FORMAT_ATTR(edge, "config:18" );
4747 PMU_FORMAT_ATTR(pc, "config:19" );
4748 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4749 PMU_FORMAT_ATTR(inv, "config:23" );
4750 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4751 PMU_FORMAT_ATTR(in_tx, "config:32" );
4752 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
4753 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
4754
umask2_show(struct device * dev,struct device_attribute * attr,char * page)4755 static ssize_t umask2_show(struct device *dev,
4756 struct device_attribute *attr,
4757 char *page)
4758 {
4759 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
4760
4761 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
4762 return sprintf(page, "config:8-15,40-47\n");
4763
4764 /* Roll back to the old format if umask2 is not supported. */
4765 return sprintf(page, "config:8-15\n");
4766 }
4767
4768 static struct device_attribute format_attr_umask2 =
4769 __ATTR(umask, 0444, umask2_show, NULL);
4770
4771 static struct attribute *format_evtsel_ext_attrs[] = {
4772 &format_attr_umask2.attr,
4773 &format_attr_eq.attr,
4774 NULL
4775 };
4776
4777 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)4778 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4779 {
4780 struct device *dev = kobj_to_dev(kobj);
4781 u64 mask;
4782
4783 /*
4784 * The umask and umask2 have different formats but share the
4785 * same attr name. In update mode, the previous value of the
4786 * umask is unconditionally removed before is_visible. If
4787 * umask2 format is not enumerated, it's impossible to roll
4788 * back to the old format.
4789 * Does the check in umask2_show rather than is_visible.
4790 */
4791 if (i == 0)
4792 return attr->mode;
4793
4794 mask = hybrid(dev_get_drvdata(dev), config_mask);
4795 if (i == 1)
4796 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
4797
4798 return 0;
4799 }
4800
4801 static struct attribute *intel_arch_formats_attr[] = {
4802 &format_attr_event.attr,
4803 &format_attr_umask.attr,
4804 &format_attr_edge.attr,
4805 &format_attr_pc.attr,
4806 &format_attr_inv.attr,
4807 &format_attr_cmask.attr,
4808 NULL,
4809 };
4810
intel_event_sysfs_show(char * page,u64 config)4811 ssize_t intel_event_sysfs_show(char *page, u64 config)
4812 {
4813 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4814
4815 return x86_event_sysfs_show(page, config, event);
4816 }
4817
allocate_shared_regs(int cpu)4818 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4819 {
4820 struct intel_shared_regs *regs;
4821 int i;
4822
4823 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4824 GFP_KERNEL, cpu_to_node(cpu));
4825 if (regs) {
4826 /*
4827 * initialize the locks to keep lockdep happy
4828 */
4829 for (i = 0; i < EXTRA_REG_MAX; i++)
4830 raw_spin_lock_init(®s->regs[i].lock);
4831
4832 regs->core_id = -1;
4833 }
4834 return regs;
4835 }
4836
allocate_excl_cntrs(int cpu)4837 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4838 {
4839 struct intel_excl_cntrs *c;
4840
4841 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4842 GFP_KERNEL, cpu_to_node(cpu));
4843 if (c) {
4844 raw_spin_lock_init(&c->lock);
4845 c->core_id = -1;
4846 }
4847 return c;
4848 }
4849
4850
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4851 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4852 {
4853 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4854
4855 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4856 cpuc->shared_regs = allocate_shared_regs(cpu);
4857 if (!cpuc->shared_regs)
4858 goto err;
4859 }
4860
4861 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) {
4862 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4863
4864 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4865 if (!cpuc->constraint_list)
4866 goto err_shared_regs;
4867 }
4868
4869 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4870 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4871 if (!cpuc->excl_cntrs)
4872 goto err_constraint_list;
4873
4874 cpuc->excl_thread_id = 0;
4875 }
4876
4877 return 0;
4878
4879 err_constraint_list:
4880 kfree(cpuc->constraint_list);
4881 cpuc->constraint_list = NULL;
4882
4883 err_shared_regs:
4884 kfree(cpuc->shared_regs);
4885 cpuc->shared_regs = NULL;
4886
4887 err:
4888 return -ENOMEM;
4889 }
4890
intel_pmu_cpu_prepare(int cpu)4891 static int intel_pmu_cpu_prepare(int cpu)
4892 {
4893 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4894 }
4895
flip_smm_bit(void * data)4896 static void flip_smm_bit(void *data)
4897 {
4898 unsigned long set = *(unsigned long *)data;
4899
4900 if (set > 0) {
4901 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4902 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4903 } else {
4904 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4905 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4906 }
4907 }
4908
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)4909 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
4910 u64 *fixed_cntr_mask,
4911 u64 *intel_ctrl)
4912 {
4913 unsigned int bit;
4914
4915 bit = fls64(*cntr_mask);
4916 if (bit > INTEL_PMC_MAX_GENERIC) {
4917 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4918 bit, INTEL_PMC_MAX_GENERIC);
4919 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
4920 }
4921 *intel_ctrl = *cntr_mask;
4922
4923 bit = fls64(*fixed_cntr_mask);
4924 if (bit > INTEL_PMC_MAX_FIXED) {
4925 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4926 bit, INTEL_PMC_MAX_FIXED);
4927 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
4928 }
4929
4930 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
4931 }
4932
4933 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
4934 u64 cntr_mask,
4935 u64 fixed_cntr_mask,
4936 u64 intel_ctrl);
4937
4938 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
4939
intel_pmu_broken_perf_cap(void)4940 static inline bool intel_pmu_broken_perf_cap(void)
4941 {
4942 /* The Perf Metric (Bit 15) is always cleared */
4943 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
4944 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
4945 return true;
4946
4947 return false;
4948 }
4949
update_pmu_cap(struct x86_hybrid_pmu * pmu)4950 static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
4951 {
4952 unsigned int cntr, fixed_cntr, ecx, edx;
4953 union cpuid35_eax eax;
4954 union cpuid35_ebx ebx;
4955
4956 cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx);
4957
4958 if (ebx.split.umask2)
4959 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2;
4960 if (ebx.split.eq)
4961 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
4962
4963 if (eax.split.cntr_subleaf) {
4964 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
4965 &cntr, &fixed_cntr, &ecx, &edx);
4966 pmu->cntr_mask64 = cntr;
4967 pmu->fixed_cntr_mask64 = fixed_cntr;
4968 }
4969
4970 if (!intel_pmu_broken_perf_cap()) {
4971 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
4972 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities);
4973 }
4974 }
4975
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)4976 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
4977 {
4978 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
4979 &pmu->intel_ctrl);
4980 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
4981 pmu->unconstrained = (struct event_constraint)
4982 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
4983 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
4984
4985 if (pmu->intel_cap.perf_metrics)
4986 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
4987 else
4988 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4989
4990 intel_pmu_check_event_constraints(pmu->event_constraints,
4991 pmu->cntr_mask64,
4992 pmu->fixed_cntr_mask64,
4993 pmu->intel_ctrl);
4994
4995 intel_pmu_check_extra_regs(pmu->extra_regs);
4996 }
4997
find_hybrid_pmu_for_cpu(void)4998 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
4999 {
5000 u8 cpu_type = get_this_hybrid_cpu_type();
5001 int i;
5002
5003 /*
5004 * This is running on a CPU model that is known to have hybrid
5005 * configurations. But the CPU told us it is not hybrid, shame
5006 * on it. There should be a fixup function provided for these
5007 * troublesome CPUs (->get_hybrid_cpu_type).
5008 */
5009 if (cpu_type == HYBRID_INTEL_NONE) {
5010 if (x86_pmu.get_hybrid_cpu_type)
5011 cpu_type = x86_pmu.get_hybrid_cpu_type();
5012 else
5013 return NULL;
5014 }
5015
5016 /*
5017 * This essentially just maps between the 'hybrid_cpu_type'
5018 * and 'hybrid_pmu_type' enums:
5019 */
5020 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5021 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
5022
5023 if (cpu_type == HYBRID_INTEL_CORE &&
5024 pmu_type == hybrid_big)
5025 return &x86_pmu.hybrid_pmu[i];
5026 if (cpu_type == HYBRID_INTEL_ATOM &&
5027 pmu_type == hybrid_small)
5028 return &x86_pmu.hybrid_pmu[i];
5029 }
5030
5031 return NULL;
5032 }
5033
init_hybrid_pmu(int cpu)5034 static bool init_hybrid_pmu(int cpu)
5035 {
5036 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5037 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
5038
5039 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
5040 cpuc->pmu = NULL;
5041 return false;
5042 }
5043
5044 /* Only check and dump the PMU information for the first CPU */
5045 if (!cpumask_empty(&pmu->supported_cpus))
5046 goto end;
5047
5048 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
5049 update_pmu_cap(pmu);
5050
5051 intel_pmu_check_hybrid_pmus(pmu);
5052
5053 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask))
5054 return false;
5055
5056 pr_info("%s PMU driver: ", pmu->name);
5057
5058 pr_cont("\n");
5059
5060 x86_pmu_show_pmu_cap(&pmu->pmu);
5061
5062 end:
5063 cpumask_set_cpu(cpu, &pmu->supported_cpus);
5064 cpuc->pmu = &pmu->pmu;
5065
5066 return true;
5067 }
5068
intel_pmu_cpu_starting(int cpu)5069 static void intel_pmu_cpu_starting(int cpu)
5070 {
5071 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5072 int core_id = topology_core_id(cpu);
5073 int i;
5074
5075 if (is_hybrid() && !init_hybrid_pmu(cpu))
5076 return;
5077
5078 init_debug_store_on_cpu(cpu);
5079 /*
5080 * Deal with CPUs that don't clear their LBRs on power-up, and that may
5081 * even boot with LBRs enabled.
5082 */
5083 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
5084 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
5085 intel_pmu_lbr_reset();
5086
5087 cpuc->lbr_sel = NULL;
5088
5089 if (x86_pmu.flags & PMU_FL_TFA) {
5090 WARN_ON_ONCE(cpuc->tfa_shadow);
5091 cpuc->tfa_shadow = ~0ULL;
5092 intel_set_tfa(cpuc, false);
5093 }
5094
5095 if (x86_pmu.version > 1)
5096 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
5097
5098 /*
5099 * Disable perf metrics if any added CPU doesn't support it.
5100 *
5101 * Turn off the check for a hybrid architecture, because the
5102 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
5103 * the architecture features. The perf metrics is a model-specific
5104 * feature for now. The corresponding bit should always be 0 on
5105 * a hybrid platform, e.g., Alder Lake.
5106 */
5107 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
5108 union perf_capabilities perf_cap;
5109
5110 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
5111 if (!perf_cap.perf_metrics) {
5112 x86_pmu.intel_cap.perf_metrics = 0;
5113 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5114 }
5115 }
5116
5117 if (!cpuc->shared_regs)
5118 return;
5119
5120 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
5121 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5122 struct intel_shared_regs *pc;
5123
5124 pc = per_cpu(cpu_hw_events, i).shared_regs;
5125 if (pc && pc->core_id == core_id) {
5126 cpuc->kfree_on_online[0] = cpuc->shared_regs;
5127 cpuc->shared_regs = pc;
5128 break;
5129 }
5130 }
5131 cpuc->shared_regs->core_id = core_id;
5132 cpuc->shared_regs->refcnt++;
5133 }
5134
5135 if (x86_pmu.lbr_sel_map)
5136 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
5137
5138 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5139 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5140 struct cpu_hw_events *sibling;
5141 struct intel_excl_cntrs *c;
5142
5143 sibling = &per_cpu(cpu_hw_events, i);
5144 c = sibling->excl_cntrs;
5145 if (c && c->core_id == core_id) {
5146 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
5147 cpuc->excl_cntrs = c;
5148 if (!sibling->excl_thread_id)
5149 cpuc->excl_thread_id = 1;
5150 break;
5151 }
5152 }
5153 cpuc->excl_cntrs->core_id = core_id;
5154 cpuc->excl_cntrs->refcnt++;
5155 }
5156 }
5157
free_excl_cntrs(struct cpu_hw_events * cpuc)5158 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
5159 {
5160 struct intel_excl_cntrs *c;
5161
5162 c = cpuc->excl_cntrs;
5163 if (c) {
5164 if (c->core_id == -1 || --c->refcnt == 0)
5165 kfree(c);
5166 cpuc->excl_cntrs = NULL;
5167 }
5168
5169 kfree(cpuc->constraint_list);
5170 cpuc->constraint_list = NULL;
5171 }
5172
intel_pmu_cpu_dying(int cpu)5173 static void intel_pmu_cpu_dying(int cpu)
5174 {
5175 fini_debug_store_on_cpu(cpu);
5176 }
5177
intel_cpuc_finish(struct cpu_hw_events * cpuc)5178 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
5179 {
5180 struct intel_shared_regs *pc;
5181
5182 pc = cpuc->shared_regs;
5183 if (pc) {
5184 if (pc->core_id == -1 || --pc->refcnt == 0)
5185 kfree(pc);
5186 cpuc->shared_regs = NULL;
5187 }
5188
5189 free_excl_cntrs(cpuc);
5190 }
5191
intel_pmu_cpu_dead(int cpu)5192 static void intel_pmu_cpu_dead(int cpu)
5193 {
5194 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5195
5196 intel_cpuc_finish(cpuc);
5197
5198 if (is_hybrid() && cpuc->pmu)
5199 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
5200 }
5201
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)5202 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
5203 bool sched_in)
5204 {
5205 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
5206 intel_pmu_lbr_sched_task(pmu_ctx, sched_in);
5207 }
5208
intel_pmu_swap_task_ctx(struct perf_event_pmu_context * prev_epc,struct perf_event_pmu_context * next_epc)5209 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
5210 struct perf_event_pmu_context *next_epc)
5211 {
5212 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
5213 }
5214
intel_pmu_check_period(struct perf_event * event,u64 value)5215 static int intel_pmu_check_period(struct perf_event *event, u64 value)
5216 {
5217 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
5218 }
5219
intel_aux_output_init(void)5220 static void intel_aux_output_init(void)
5221 {
5222 /* Refer also intel_pmu_aux_output_match() */
5223 if (x86_pmu.intel_cap.pebs_output_pt_available)
5224 x86_pmu.assign = intel_pmu_assign_event;
5225 }
5226
intel_pmu_aux_output_match(struct perf_event * event)5227 static int intel_pmu_aux_output_match(struct perf_event *event)
5228 {
5229 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
5230 if (!x86_pmu.intel_cap.pebs_output_pt_available)
5231 return 0;
5232
5233 return is_intel_pt_event(event);
5234 }
5235
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)5236 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
5237 {
5238 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
5239
5240 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
5241 }
5242
5243 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5244
5245 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5246
5247 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5248
5249 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
5250
5251 static struct attribute *intel_arch3_formats_attr[] = {
5252 &format_attr_event.attr,
5253 &format_attr_umask.attr,
5254 &format_attr_edge.attr,
5255 &format_attr_pc.attr,
5256 &format_attr_any.attr,
5257 &format_attr_inv.attr,
5258 &format_attr_cmask.attr,
5259 NULL,
5260 };
5261
5262 static struct attribute *hsw_format_attr[] = {
5263 &format_attr_in_tx.attr,
5264 &format_attr_in_tx_cp.attr,
5265 &format_attr_offcore_rsp.attr,
5266 &format_attr_ldlat.attr,
5267 NULL
5268 };
5269
5270 static struct attribute *nhm_format_attr[] = {
5271 &format_attr_offcore_rsp.attr,
5272 &format_attr_ldlat.attr,
5273 NULL
5274 };
5275
5276 static struct attribute *slm_format_attr[] = {
5277 &format_attr_offcore_rsp.attr,
5278 NULL
5279 };
5280
5281 static struct attribute *cmt_format_attr[] = {
5282 &format_attr_offcore_rsp.attr,
5283 &format_attr_ldlat.attr,
5284 &format_attr_snoop_rsp.attr,
5285 NULL
5286 };
5287
5288 static struct attribute *skl_format_attr[] = {
5289 &format_attr_frontend.attr,
5290 NULL,
5291 };
5292
5293 static __initconst const struct x86_pmu core_pmu = {
5294 .name = "core",
5295 .handle_irq = x86_pmu_handle_irq,
5296 .disable_all = x86_pmu_disable_all,
5297 .enable_all = core_pmu_enable_all,
5298 .enable = core_pmu_enable_event,
5299 .disable = x86_pmu_disable_event,
5300 .hw_config = core_pmu_hw_config,
5301 .schedule_events = x86_schedule_events,
5302 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5303 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5304 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5305 .event_map = intel_pmu_event_map,
5306 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5307 .apic = 1,
5308 .large_pebs_flags = LARGE_PEBS_FLAGS,
5309
5310 /*
5311 * Intel PMCs cannot be accessed sanely above 32-bit width,
5312 * so we install an artificial 1<<31 period regardless of
5313 * the generic event period:
5314 */
5315 .max_period = (1ULL<<31) - 1,
5316 .get_event_constraints = intel_get_event_constraints,
5317 .put_event_constraints = intel_put_event_constraints,
5318 .event_constraints = intel_core_event_constraints,
5319 .guest_get_msrs = core_guest_get_msrs,
5320 .format_attrs = intel_arch_formats_attr,
5321 .events_sysfs_show = intel_event_sysfs_show,
5322
5323 /*
5324 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
5325 * together with PMU version 1 and thus be using core_pmu with
5326 * shared_regs. We need following callbacks here to allocate
5327 * it properly.
5328 */
5329 .cpu_prepare = intel_pmu_cpu_prepare,
5330 .cpu_starting = intel_pmu_cpu_starting,
5331 .cpu_dying = intel_pmu_cpu_dying,
5332 .cpu_dead = intel_pmu_cpu_dead,
5333
5334 .check_period = intel_pmu_check_period,
5335
5336 .lbr_reset = intel_pmu_lbr_reset_64,
5337 .lbr_read = intel_pmu_lbr_read_64,
5338 .lbr_save = intel_pmu_lbr_save,
5339 .lbr_restore = intel_pmu_lbr_restore,
5340 };
5341
5342 static __initconst const struct x86_pmu intel_pmu = {
5343 .name = "Intel",
5344 .handle_irq = intel_pmu_handle_irq,
5345 .disable_all = intel_pmu_disable_all,
5346 .enable_all = intel_pmu_enable_all,
5347 .enable = intel_pmu_enable_event,
5348 .disable = intel_pmu_disable_event,
5349 .add = intel_pmu_add_event,
5350 .del = intel_pmu_del_event,
5351 .read = intel_pmu_read_event,
5352 .set_period = intel_pmu_set_period,
5353 .update = intel_pmu_update,
5354 .hw_config = intel_pmu_hw_config,
5355 .schedule_events = x86_schedule_events,
5356 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5357 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5358 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5359 .event_map = intel_pmu_event_map,
5360 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5361 .apic = 1,
5362 .large_pebs_flags = LARGE_PEBS_FLAGS,
5363 /*
5364 * Intel PMCs cannot be accessed sanely above 32 bit width,
5365 * so we install an artificial 1<<31 period regardless of
5366 * the generic event period:
5367 */
5368 .max_period = (1ULL << 31) - 1,
5369 .get_event_constraints = intel_get_event_constraints,
5370 .put_event_constraints = intel_put_event_constraints,
5371 .pebs_aliases = intel_pebs_aliases_core2,
5372
5373 .format_attrs = intel_arch3_formats_attr,
5374 .events_sysfs_show = intel_event_sysfs_show,
5375
5376 .cpu_prepare = intel_pmu_cpu_prepare,
5377 .cpu_starting = intel_pmu_cpu_starting,
5378 .cpu_dying = intel_pmu_cpu_dying,
5379 .cpu_dead = intel_pmu_cpu_dead,
5380
5381 .guest_get_msrs = intel_guest_get_msrs,
5382 .sched_task = intel_pmu_sched_task,
5383 .swap_task_ctx = intel_pmu_swap_task_ctx,
5384
5385 .check_period = intel_pmu_check_period,
5386
5387 .aux_output_match = intel_pmu_aux_output_match,
5388
5389 .lbr_reset = intel_pmu_lbr_reset_64,
5390 .lbr_read = intel_pmu_lbr_read_64,
5391 .lbr_save = intel_pmu_lbr_save,
5392 .lbr_restore = intel_pmu_lbr_restore,
5393
5394 /*
5395 * SMM has access to all 4 rings and while traditionally SMM code only
5396 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
5397 *
5398 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
5399 * between SMM or not, this results in what should be pure userspace
5400 * counters including SMM data.
5401 *
5402 * This is a clear privilege issue, therefore globally disable
5403 * counting SMM by default.
5404 */
5405 .attr_freeze_on_smi = 1,
5406 };
5407
intel_clovertown_quirk(void)5408 static __init void intel_clovertown_quirk(void)
5409 {
5410 /*
5411 * PEBS is unreliable due to:
5412 *
5413 * AJ67 - PEBS may experience CPL leaks
5414 * AJ68 - PEBS PMI may be delayed by one event
5415 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
5416 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
5417 *
5418 * AJ67 could be worked around by restricting the OS/USR flags.
5419 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
5420 *
5421 * AJ106 could possibly be worked around by not allowing LBR
5422 * usage from PEBS, including the fixup.
5423 * AJ68 could possibly be worked around by always programming
5424 * a pebs_event_reset[0] value and coping with the lost events.
5425 *
5426 * But taken together it might just make sense to not enable PEBS on
5427 * these chips.
5428 */
5429 pr_warn("PEBS disabled due to CPU errata\n");
5430 x86_pmu.pebs = 0;
5431 x86_pmu.pebs_constraints = NULL;
5432 }
5433
5434 static const struct x86_cpu_desc isolation_ucodes[] = {
5435 INTEL_CPU_DESC(INTEL_HASWELL, 3, 0x0000001f),
5436 INTEL_CPU_DESC(INTEL_HASWELL_L, 1, 0x0000001e),
5437 INTEL_CPU_DESC(INTEL_HASWELL_G, 1, 0x00000015),
5438 INTEL_CPU_DESC(INTEL_HASWELL_X, 2, 0x00000037),
5439 INTEL_CPU_DESC(INTEL_HASWELL_X, 4, 0x0000000a),
5440 INTEL_CPU_DESC(INTEL_BROADWELL, 4, 0x00000023),
5441 INTEL_CPU_DESC(INTEL_BROADWELL_G, 1, 0x00000014),
5442 INTEL_CPU_DESC(INTEL_BROADWELL_D, 2, 0x00000010),
5443 INTEL_CPU_DESC(INTEL_BROADWELL_D, 3, 0x07000009),
5444 INTEL_CPU_DESC(INTEL_BROADWELL_D, 4, 0x0f000009),
5445 INTEL_CPU_DESC(INTEL_BROADWELL_D, 5, 0x0e000002),
5446 INTEL_CPU_DESC(INTEL_BROADWELL_X, 1, 0x0b000014),
5447 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 3, 0x00000021),
5448 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 4, 0x00000000),
5449 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 5, 0x00000000),
5450 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 6, 0x00000000),
5451 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 7, 0x00000000),
5452 INTEL_CPU_DESC(INTEL_SKYLAKE_X, 11, 0x00000000),
5453 INTEL_CPU_DESC(INTEL_SKYLAKE_L, 3, 0x0000007c),
5454 INTEL_CPU_DESC(INTEL_SKYLAKE, 3, 0x0000007c),
5455 INTEL_CPU_DESC(INTEL_KABYLAKE, 9, 0x0000004e),
5456 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 9, 0x0000004e),
5457 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 10, 0x0000004e),
5458 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 11, 0x0000004e),
5459 INTEL_CPU_DESC(INTEL_KABYLAKE_L, 12, 0x0000004e),
5460 INTEL_CPU_DESC(INTEL_KABYLAKE, 10, 0x0000004e),
5461 INTEL_CPU_DESC(INTEL_KABYLAKE, 11, 0x0000004e),
5462 INTEL_CPU_DESC(INTEL_KABYLAKE, 12, 0x0000004e),
5463 INTEL_CPU_DESC(INTEL_KABYLAKE, 13, 0x0000004e),
5464 {}
5465 };
5466
intel_check_pebs_isolation(void)5467 static void intel_check_pebs_isolation(void)
5468 {
5469 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
5470 }
5471
intel_pebs_isolation_quirk(void)5472 static __init void intel_pebs_isolation_quirk(void)
5473 {
5474 WARN_ON_ONCE(x86_pmu.check_microcode);
5475 x86_pmu.check_microcode = intel_check_pebs_isolation;
5476 intel_check_pebs_isolation();
5477 }
5478
5479 static const struct x86_cpu_desc pebs_ucodes[] = {
5480 INTEL_CPU_DESC(INTEL_SANDYBRIDGE, 7, 0x00000028),
5481 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 6, 0x00000618),
5482 INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X, 7, 0x0000070c),
5483 {}
5484 };
5485
intel_snb_pebs_broken(void)5486 static bool intel_snb_pebs_broken(void)
5487 {
5488 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
5489 }
5490
intel_snb_check_microcode(void)5491 static void intel_snb_check_microcode(void)
5492 {
5493 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
5494 return;
5495
5496 /*
5497 * Serialized by the microcode lock..
5498 */
5499 if (x86_pmu.pebs_broken) {
5500 pr_info("PEBS enabled due to microcode update\n");
5501 x86_pmu.pebs_broken = 0;
5502 } else {
5503 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
5504 x86_pmu.pebs_broken = 1;
5505 }
5506 }
5507
is_lbr_from(unsigned long msr)5508 static bool is_lbr_from(unsigned long msr)
5509 {
5510 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
5511
5512 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
5513 }
5514
5515 /*
5516 * Under certain circumstances, access certain MSR may cause #GP.
5517 * The function tests if the input MSR can be safely accessed.
5518 */
check_msr(unsigned long msr,u64 mask)5519 static bool check_msr(unsigned long msr, u64 mask)
5520 {
5521 u64 val_old, val_new, val_tmp;
5522
5523 /*
5524 * Disable the check for real HW, so we don't
5525 * mess with potentially enabled registers:
5526 */
5527 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
5528 return true;
5529
5530 /*
5531 * Read the current value, change it and read it back to see if it
5532 * matches, this is needed to detect certain hardware emulators
5533 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
5534 */
5535 if (rdmsrl_safe(msr, &val_old))
5536 return false;
5537
5538 /*
5539 * Only change the bits which can be updated by wrmsrl.
5540 */
5541 val_tmp = val_old ^ mask;
5542
5543 if (is_lbr_from(msr))
5544 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
5545
5546 if (wrmsrl_safe(msr, val_tmp) ||
5547 rdmsrl_safe(msr, &val_new))
5548 return false;
5549
5550 /*
5551 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5552 * should equal rdmsrl()'s even with the quirk.
5553 */
5554 if (val_new != val_tmp)
5555 return false;
5556
5557 if (is_lbr_from(msr))
5558 val_old = lbr_from_signext_quirk_wr(val_old);
5559
5560 /* Here it's sure that the MSR can be safely accessed.
5561 * Restore the old value and return.
5562 */
5563 wrmsrl(msr, val_old);
5564
5565 return true;
5566 }
5567
intel_sandybridge_quirk(void)5568 static __init void intel_sandybridge_quirk(void)
5569 {
5570 x86_pmu.check_microcode = intel_snb_check_microcode;
5571 cpus_read_lock();
5572 intel_snb_check_microcode();
5573 cpus_read_unlock();
5574 }
5575
5576 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5577 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5578 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5579 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5580 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5581 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5582 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5583 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5584 };
5585
intel_arch_events_quirk(void)5586 static __init void intel_arch_events_quirk(void)
5587 {
5588 int bit;
5589
5590 /* disable event that reported as not present by cpuid */
5591 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5592 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5593 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5594 intel_arch_events_map[bit].name);
5595 }
5596 }
5597
intel_nehalem_quirk(void)5598 static __init void intel_nehalem_quirk(void)
5599 {
5600 union cpuid10_ebx ebx;
5601
5602 ebx.full = x86_pmu.events_maskl;
5603 if (ebx.split.no_branch_misses_retired) {
5604 /*
5605 * Erratum AAJ80 detected, we work it around by using
5606 * the BR_MISP_EXEC.ANY event. This will over-count
5607 * branch-misses, but it's still much better than the
5608 * architectural event which is often completely bogus:
5609 */
5610 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5611 ebx.split.no_branch_misses_retired = 0;
5612 x86_pmu.events_maskl = ebx.full;
5613 pr_info("CPU erratum AAJ80 worked around\n");
5614 }
5615 }
5616
5617 /*
5618 * enable software workaround for errata:
5619 * SNB: BJ122
5620 * IVB: BV98
5621 * HSW: HSD29
5622 *
5623 * Only needed when HT is enabled. However detecting
5624 * if HT is enabled is difficult (model specific). So instead,
5625 * we enable the workaround in the early boot, and verify if
5626 * it is needed in a later initcall phase once we have valid
5627 * topology information to check if HT is actually enabled
5628 */
intel_ht_bug(void)5629 static __init void intel_ht_bug(void)
5630 {
5631 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5632
5633 x86_pmu.start_scheduling = intel_start_scheduling;
5634 x86_pmu.commit_scheduling = intel_commit_scheduling;
5635 x86_pmu.stop_scheduling = intel_stop_scheduling;
5636 }
5637
5638 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
5639 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5640
5641 /* Haswell special events */
5642 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
5643 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
5644 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
5645 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
5646 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
5647 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
5648 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
5649 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
5650 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
5651 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
5652 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5653 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5654
5655 static struct attribute *hsw_events_attrs[] = {
5656 EVENT_PTR(td_slots_issued),
5657 EVENT_PTR(td_slots_retired),
5658 EVENT_PTR(td_fetch_bubbles),
5659 EVENT_PTR(td_total_slots),
5660 EVENT_PTR(td_total_slots_scale),
5661 EVENT_PTR(td_recovery_bubbles),
5662 EVENT_PTR(td_recovery_bubbles_scale),
5663 NULL
5664 };
5665
5666 static struct attribute *hsw_mem_events_attrs[] = {
5667 EVENT_PTR(mem_ld_hsw),
5668 EVENT_PTR(mem_st_hsw),
5669 NULL,
5670 };
5671
5672 static struct attribute *hsw_tsx_events_attrs[] = {
5673 EVENT_PTR(tx_start),
5674 EVENT_PTR(tx_commit),
5675 EVENT_PTR(tx_abort),
5676 EVENT_PTR(tx_capacity),
5677 EVENT_PTR(tx_conflict),
5678 EVENT_PTR(el_start),
5679 EVENT_PTR(el_commit),
5680 EVENT_PTR(el_abort),
5681 EVENT_PTR(el_capacity),
5682 EVENT_PTR(el_conflict),
5683 EVENT_PTR(cycles_t),
5684 EVENT_PTR(cycles_ct),
5685 NULL
5686 };
5687
5688 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5689 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5690 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5691 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5692
5693 static struct attribute *icl_events_attrs[] = {
5694 EVENT_PTR(mem_ld_hsw),
5695 EVENT_PTR(mem_st_hsw),
5696 NULL,
5697 };
5698
5699 static struct attribute *icl_td_events_attrs[] = {
5700 EVENT_PTR(slots),
5701 EVENT_PTR(td_retiring),
5702 EVENT_PTR(td_bad_spec),
5703 EVENT_PTR(td_fe_bound),
5704 EVENT_PTR(td_be_bound),
5705 NULL,
5706 };
5707
5708 static struct attribute *icl_tsx_events_attrs[] = {
5709 EVENT_PTR(tx_start),
5710 EVENT_PTR(tx_abort),
5711 EVENT_PTR(tx_commit),
5712 EVENT_PTR(tx_capacity_read),
5713 EVENT_PTR(tx_capacity_write),
5714 EVENT_PTR(tx_conflict),
5715 EVENT_PTR(el_start),
5716 EVENT_PTR(el_abort),
5717 EVENT_PTR(el_commit),
5718 EVENT_PTR(el_capacity_read),
5719 EVENT_PTR(el_capacity_write),
5720 EVENT_PTR(el_conflict),
5721 EVENT_PTR(cycles_t),
5722 EVENT_PTR(cycles_ct),
5723 NULL,
5724 };
5725
5726
5727 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5728 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5729
5730 static struct attribute *glc_events_attrs[] = {
5731 EVENT_PTR(mem_ld_hsw),
5732 EVENT_PTR(mem_st_spr),
5733 EVENT_PTR(mem_ld_aux),
5734 NULL,
5735 };
5736
5737 static struct attribute *glc_td_events_attrs[] = {
5738 EVENT_PTR(slots),
5739 EVENT_PTR(td_retiring),
5740 EVENT_PTR(td_bad_spec),
5741 EVENT_PTR(td_fe_bound),
5742 EVENT_PTR(td_be_bound),
5743 EVENT_PTR(td_heavy_ops),
5744 EVENT_PTR(td_br_mispredict),
5745 EVENT_PTR(td_fetch_lat),
5746 EVENT_PTR(td_mem_bound),
5747 NULL,
5748 };
5749
5750 static struct attribute *glc_tsx_events_attrs[] = {
5751 EVENT_PTR(tx_start),
5752 EVENT_PTR(tx_abort),
5753 EVENT_PTR(tx_commit),
5754 EVENT_PTR(tx_capacity_read),
5755 EVENT_PTR(tx_capacity_write),
5756 EVENT_PTR(tx_conflict),
5757 EVENT_PTR(cycles_t),
5758 EVENT_PTR(cycles_ct),
5759 NULL,
5760 };
5761
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)5762 static ssize_t freeze_on_smi_show(struct device *cdev,
5763 struct device_attribute *attr,
5764 char *buf)
5765 {
5766 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5767 }
5768
5769 static DEFINE_MUTEX(freeze_on_smi_mutex);
5770
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5771 static ssize_t freeze_on_smi_store(struct device *cdev,
5772 struct device_attribute *attr,
5773 const char *buf, size_t count)
5774 {
5775 unsigned long val;
5776 ssize_t ret;
5777
5778 ret = kstrtoul(buf, 0, &val);
5779 if (ret)
5780 return ret;
5781
5782 if (val > 1)
5783 return -EINVAL;
5784
5785 mutex_lock(&freeze_on_smi_mutex);
5786
5787 if (x86_pmu.attr_freeze_on_smi == val)
5788 goto done;
5789
5790 x86_pmu.attr_freeze_on_smi = val;
5791
5792 cpus_read_lock();
5793 on_each_cpu(flip_smm_bit, &val, 1);
5794 cpus_read_unlock();
5795 done:
5796 mutex_unlock(&freeze_on_smi_mutex);
5797
5798 return count;
5799 }
5800
update_tfa_sched(void * ignored)5801 static void update_tfa_sched(void *ignored)
5802 {
5803 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5804
5805 /*
5806 * check if PMC3 is used
5807 * and if so force schedule out for all event types all contexts
5808 */
5809 if (test_bit(3, cpuc->active_mask))
5810 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5811 }
5812
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)5813 static ssize_t show_sysctl_tfa(struct device *cdev,
5814 struct device_attribute *attr,
5815 char *buf)
5816 {
5817 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5818 }
5819
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5820 static ssize_t set_sysctl_tfa(struct device *cdev,
5821 struct device_attribute *attr,
5822 const char *buf, size_t count)
5823 {
5824 bool val;
5825 ssize_t ret;
5826
5827 ret = kstrtobool(buf, &val);
5828 if (ret)
5829 return ret;
5830
5831 /* no change */
5832 if (val == allow_tsx_force_abort)
5833 return count;
5834
5835 allow_tsx_force_abort = val;
5836
5837 cpus_read_lock();
5838 on_each_cpu(update_tfa_sched, NULL, 1);
5839 cpus_read_unlock();
5840
5841 return count;
5842 }
5843
5844
5845 static DEVICE_ATTR_RW(freeze_on_smi);
5846
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)5847 static ssize_t branches_show(struct device *cdev,
5848 struct device_attribute *attr,
5849 char *buf)
5850 {
5851 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5852 }
5853
5854 static DEVICE_ATTR_RO(branches);
5855
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)5856 static ssize_t branch_counter_nr_show(struct device *cdev,
5857 struct device_attribute *attr,
5858 char *buf)
5859 {
5860 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
5861 }
5862
5863 static DEVICE_ATTR_RO(branch_counter_nr);
5864
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)5865 static ssize_t branch_counter_width_show(struct device *cdev,
5866 struct device_attribute *attr,
5867 char *buf)
5868 {
5869 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
5870 }
5871
5872 static DEVICE_ATTR_RO(branch_counter_width);
5873
5874 static struct attribute *lbr_attrs[] = {
5875 &dev_attr_branches.attr,
5876 &dev_attr_branch_counter_nr.attr,
5877 &dev_attr_branch_counter_width.attr,
5878 NULL
5879 };
5880
5881 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)5882 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5883 {
5884 /* branches */
5885 if (i == 0)
5886 return x86_pmu.lbr_nr ? attr->mode : 0;
5887
5888 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
5889 }
5890
5891 static char pmu_name_str[30];
5892
5893 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
5894
5895 static struct attribute *intel_pmu_caps_attrs[] = {
5896 &dev_attr_pmu_name.attr.attr,
5897 NULL
5898 };
5899
5900 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5901 show_sysctl_tfa,
5902 set_sysctl_tfa);
5903
5904 static struct attribute *intel_pmu_attrs[] = {
5905 &dev_attr_freeze_on_smi.attr,
5906 &dev_attr_allow_tsx_force_abort.attr,
5907 NULL,
5908 };
5909
5910 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)5911 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5912 {
5913 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5914 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5915
5916 return attr->mode;
5917 }
5918
5919 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)5920 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5921 {
5922 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5923 }
5924
5925 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)5926 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5927 {
5928 return x86_pmu.pebs ? attr->mode : 0;
5929 }
5930
5931 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)5932 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5933 {
5934 if (attr == &event_attr_mem_ld_aux.attr.attr)
5935 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
5936
5937 return pebs_is_visible(kobj, attr, i);
5938 }
5939
5940 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)5941 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5942 {
5943 return x86_pmu.version >= 2 ? attr->mode : 0;
5944 }
5945
5946 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)5947 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5948 {
5949 /*
5950 * Hide the perf metrics topdown events
5951 * if the feature is not enumerated.
5952 */
5953 if (x86_pmu.num_topdown_events)
5954 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
5955
5956 return attr->mode;
5957 }
5958
5959 static struct attribute_group group_events_td = {
5960 .name = "events",
5961 .is_visible = td_is_visible,
5962 };
5963
5964 static struct attribute_group group_events_mem = {
5965 .name = "events",
5966 .is_visible = mem_is_visible,
5967 };
5968
5969 static struct attribute_group group_events_tsx = {
5970 .name = "events",
5971 .is_visible = tsx_is_visible,
5972 };
5973
5974 static struct attribute_group group_caps_gen = {
5975 .name = "caps",
5976 .attrs = intel_pmu_caps_attrs,
5977 };
5978
5979 static struct attribute_group group_caps_lbr = {
5980 .name = "caps",
5981 .attrs = lbr_attrs,
5982 .is_visible = lbr_is_visible,
5983 };
5984
5985 static struct attribute_group group_format_extra = {
5986 .name = "format",
5987 .is_visible = exra_is_visible,
5988 };
5989
5990 static struct attribute_group group_format_extra_skl = {
5991 .name = "format",
5992 .is_visible = exra_is_visible,
5993 };
5994
5995 static struct attribute_group group_format_evtsel_ext = {
5996 .name = "format",
5997 .attrs = format_evtsel_ext_attrs,
5998 .is_visible = evtsel_ext_is_visible,
5999 };
6000
6001 static struct attribute_group group_default = {
6002 .attrs = intel_pmu_attrs,
6003 .is_visible = default_is_visible,
6004 };
6005
6006 static const struct attribute_group *attr_update[] = {
6007 &group_events_td,
6008 &group_events_mem,
6009 &group_events_tsx,
6010 &group_caps_gen,
6011 &group_caps_lbr,
6012 &group_format_extra,
6013 &group_format_extra_skl,
6014 &group_format_evtsel_ext,
6015 &group_default,
6016 NULL,
6017 };
6018
6019 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
6020 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
6021 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
6022 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
6023 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
6024 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
6025 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
6026 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
6027 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
6028
6029 static struct attribute *adl_hybrid_events_attrs[] = {
6030 EVENT_PTR(slots_adl),
6031 EVENT_PTR(td_retiring_adl),
6032 EVENT_PTR(td_bad_spec_adl),
6033 EVENT_PTR(td_fe_bound_adl),
6034 EVENT_PTR(td_be_bound_adl),
6035 EVENT_PTR(td_heavy_ops_adl),
6036 EVENT_PTR(td_br_mis_adl),
6037 EVENT_PTR(td_fetch_lat_adl),
6038 EVENT_PTR(td_mem_bound_adl),
6039 NULL,
6040 };
6041
6042 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
6043 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
6044 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
6045
6046 static struct attribute *lnl_hybrid_events_attrs[] = {
6047 EVENT_PTR(slots_adl),
6048 EVENT_PTR(td_retiring_lnl),
6049 EVENT_PTR(td_bad_spec_adl),
6050 EVENT_PTR(td_fe_bound_lnl),
6051 EVENT_PTR(td_be_bound_lnl),
6052 EVENT_PTR(td_heavy_ops_adl),
6053 EVENT_PTR(td_br_mis_adl),
6054 EVENT_PTR(td_fetch_lat_adl),
6055 EVENT_PTR(td_mem_bound_adl),
6056 NULL
6057 };
6058
6059 /* Must be in IDX order */
6060 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
6061 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
6062 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
6063
6064 static struct attribute *adl_hybrid_mem_attrs[] = {
6065 EVENT_PTR(mem_ld_adl),
6066 EVENT_PTR(mem_st_adl),
6067 EVENT_PTR(mem_ld_aux_adl),
6068 NULL,
6069 };
6070
6071 static struct attribute *mtl_hybrid_mem_attrs[] = {
6072 EVENT_PTR(mem_ld_adl),
6073 EVENT_PTR(mem_st_adl),
6074 NULL
6075 };
6076
6077 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
6078 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
6079 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
6080 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
6081 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
6082 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
6083 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
6084 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
6085
6086 static struct attribute *adl_hybrid_tsx_attrs[] = {
6087 EVENT_PTR(tx_start_adl),
6088 EVENT_PTR(tx_abort_adl),
6089 EVENT_PTR(tx_commit_adl),
6090 EVENT_PTR(tx_capacity_read_adl),
6091 EVENT_PTR(tx_capacity_write_adl),
6092 EVENT_PTR(tx_conflict_adl),
6093 EVENT_PTR(cycles_t_adl),
6094 EVENT_PTR(cycles_ct_adl),
6095 NULL,
6096 };
6097
6098 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
6099 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6100 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
6101 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small);
6102 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
6103
6104 #define ADL_HYBRID_RTM_FORMAT_ATTR \
6105 FORMAT_HYBRID_PTR(in_tx), \
6106 FORMAT_HYBRID_PTR(in_tx_cp)
6107
6108 #define ADL_HYBRID_FORMAT_ATTR \
6109 FORMAT_HYBRID_PTR(offcore_rsp), \
6110 FORMAT_HYBRID_PTR(ldlat), \
6111 FORMAT_HYBRID_PTR(frontend)
6112
6113 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
6114 ADL_HYBRID_RTM_FORMAT_ATTR,
6115 ADL_HYBRID_FORMAT_ATTR,
6116 NULL
6117 };
6118
6119 static struct attribute *adl_hybrid_extra_attr[] = {
6120 ADL_HYBRID_FORMAT_ATTR,
6121 NULL
6122 };
6123
6124 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small);
6125
6126 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
6127 ADL_HYBRID_RTM_FORMAT_ATTR,
6128 ADL_HYBRID_FORMAT_ATTR,
6129 FORMAT_HYBRID_PTR(snoop_rsp),
6130 NULL
6131 };
6132
6133 static struct attribute *mtl_hybrid_extra_attr[] = {
6134 ADL_HYBRID_FORMAT_ATTR,
6135 FORMAT_HYBRID_PTR(snoop_rsp),
6136 NULL
6137 };
6138
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)6139 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
6140 {
6141 struct device *dev = kobj_to_dev(kobj);
6142 struct x86_hybrid_pmu *pmu =
6143 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6144 struct perf_pmu_events_hybrid_attr *pmu_attr =
6145 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
6146
6147 return pmu->pmu_type & pmu_attr->pmu_type;
6148 }
6149
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)6150 static umode_t hybrid_events_is_visible(struct kobject *kobj,
6151 struct attribute *attr, int i)
6152 {
6153 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
6154 }
6155
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)6156 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
6157 {
6158 int cpu = cpumask_first(&pmu->supported_cpus);
6159
6160 return (cpu >= nr_cpu_ids) ? -1 : cpu;
6161 }
6162
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6163 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
6164 struct attribute *attr, int i)
6165 {
6166 struct device *dev = kobj_to_dev(kobj);
6167 struct x86_hybrid_pmu *pmu =
6168 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6169 int cpu = hybrid_find_supported_cpu(pmu);
6170
6171 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
6172 }
6173
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)6174 static umode_t hybrid_format_is_visible(struct kobject *kobj,
6175 struct attribute *attr, int i)
6176 {
6177 struct device *dev = kobj_to_dev(kobj);
6178 struct x86_hybrid_pmu *pmu =
6179 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6180 struct perf_pmu_format_hybrid_attr *pmu_attr =
6181 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
6182 int cpu = hybrid_find_supported_cpu(pmu);
6183
6184 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
6185 }
6186
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6187 static umode_t hybrid_td_is_visible(struct kobject *kobj,
6188 struct attribute *attr, int i)
6189 {
6190 struct device *dev = kobj_to_dev(kobj);
6191 struct x86_hybrid_pmu *pmu =
6192 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6193
6194 if (!is_attr_for_this_pmu(kobj, attr))
6195 return 0;
6196
6197
6198 /* Only the big core supports perf metrics */
6199 if (pmu->pmu_type == hybrid_big)
6200 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
6201
6202 return attr->mode;
6203 }
6204
6205 static struct attribute_group hybrid_group_events_td = {
6206 .name = "events",
6207 .is_visible = hybrid_td_is_visible,
6208 };
6209
6210 static struct attribute_group hybrid_group_events_mem = {
6211 .name = "events",
6212 .is_visible = hybrid_events_is_visible,
6213 };
6214
6215 static struct attribute_group hybrid_group_events_tsx = {
6216 .name = "events",
6217 .is_visible = hybrid_tsx_is_visible,
6218 };
6219
6220 static struct attribute_group hybrid_group_format_extra = {
6221 .name = "format",
6222 .is_visible = hybrid_format_is_visible,
6223 };
6224
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)6225 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
6226 struct device_attribute *attr,
6227 char *buf)
6228 {
6229 struct x86_hybrid_pmu *pmu =
6230 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6231
6232 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
6233 }
6234
6235 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
6236 static struct attribute *intel_hybrid_cpus_attrs[] = {
6237 &dev_attr_cpus.attr,
6238 NULL,
6239 };
6240
6241 static struct attribute_group hybrid_group_cpus = {
6242 .attrs = intel_hybrid_cpus_attrs,
6243 };
6244
6245 static const struct attribute_group *hybrid_attr_update[] = {
6246 &hybrid_group_events_td,
6247 &hybrid_group_events_mem,
6248 &hybrid_group_events_tsx,
6249 &group_caps_gen,
6250 &group_caps_lbr,
6251 &hybrid_group_format_extra,
6252 &group_format_evtsel_ext,
6253 &group_default,
6254 &hybrid_group_cpus,
6255 NULL,
6256 };
6257
6258 static struct attribute *empty_attrs;
6259
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)6260 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
6261 u64 cntr_mask,
6262 u64 fixed_cntr_mask,
6263 u64 intel_ctrl)
6264 {
6265 struct event_constraint *c;
6266
6267 if (!event_constraints)
6268 return;
6269
6270 /*
6271 * event on fixed counter2 (REF_CYCLES) only works on this
6272 * counter, so do not extend mask to generic counters
6273 */
6274 for_each_event_constraint(c, event_constraints) {
6275 /*
6276 * Don't extend the topdown slots and metrics
6277 * events to the generic counters.
6278 */
6279 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
6280 /*
6281 * Disable topdown slots and metrics events,
6282 * if slots event is not in CPUID.
6283 */
6284 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
6285 c->idxmsk64 = 0;
6286 c->weight = hweight64(c->idxmsk64);
6287 continue;
6288 }
6289
6290 if (c->cmask == FIXED_EVENT_FLAGS) {
6291 /* Disabled fixed counters which are not in CPUID */
6292 c->idxmsk64 &= intel_ctrl;
6293
6294 /*
6295 * Don't extend the pseudo-encoding to the
6296 * generic counters
6297 */
6298 if (!use_fixed_pseudo_encoding(c->code))
6299 c->idxmsk64 |= cntr_mask;
6300 }
6301 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
6302 c->weight = hweight64(c->idxmsk64);
6303 }
6304 }
6305
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)6306 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
6307 {
6308 struct extra_reg *er;
6309
6310 /*
6311 * Access extra MSR may cause #GP under certain circumstances.
6312 * E.g. KVM doesn't support offcore event
6313 * Check all extra_regs here.
6314 */
6315 if (!extra_regs)
6316 return;
6317
6318 for (er = extra_regs; er->msr; er++) {
6319 er->extra_msr_access = check_msr(er->msr, 0x11UL);
6320 /* Disable LBR select mapping */
6321 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
6322 x86_pmu.lbr_sel_map = NULL;
6323 }
6324 }
6325
intel_pmu_v6_addr_offset(int index,bool eventsel)6326 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
6327 {
6328 return MSR_IA32_PMC_V6_STEP * index;
6329 }
6330
6331 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
6332 { hybrid_small, "cpu_atom" },
6333 { hybrid_big, "cpu_core" },
6334 };
6335
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)6336 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
6337 {
6338 unsigned long pmus_mask = pmus;
6339 struct x86_hybrid_pmu *pmu;
6340 int idx = 0, bit;
6341
6342 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
6343 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus,
6344 sizeof(struct x86_hybrid_pmu),
6345 GFP_KERNEL);
6346 if (!x86_pmu.hybrid_pmu)
6347 return -ENOMEM;
6348
6349 static_branch_enable(&perf_is_hybrid);
6350 x86_pmu.filter = intel_pmu_filter;
6351
6352 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
6353 pmu = &x86_pmu.hybrid_pmu[idx++];
6354 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
6355 pmu->name = intel_hybrid_pmu_type_map[bit].name;
6356
6357 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
6358 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
6359 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6360 pmu->config_mask = X86_RAW_EVENT_MASK;
6361 pmu->unconstrained = (struct event_constraint)
6362 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6363 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6364
6365 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6366 if (pmu->pmu_type & hybrid_small) {
6367 pmu->intel_cap.perf_metrics = 0;
6368 pmu->mid_ack = true;
6369 } else if (pmu->pmu_type & hybrid_big) {
6370 pmu->intel_cap.perf_metrics = 1;
6371 pmu->late_ack = true;
6372 }
6373 }
6374
6375 return 0;
6376 }
6377
intel_pmu_ref_cycles_ext(void)6378 static __always_inline void intel_pmu_ref_cycles_ext(void)
6379 {
6380 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
6381 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
6382 }
6383
intel_pmu_init_glc(struct pmu * pmu)6384 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
6385 {
6386 x86_pmu.late_ack = true;
6387 x86_pmu.limit_period = glc_limit_period;
6388 x86_pmu.pebs_aliases = NULL;
6389 x86_pmu.pebs_prec_dist = true;
6390 x86_pmu.pebs_block = true;
6391 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6392 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6393 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6394 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6395 x86_pmu.lbr_pt_coexist = true;
6396 x86_pmu.num_topdown_events = 8;
6397 static_call_update(intel_pmu_update_topdown_event,
6398 &icl_update_topdown_event);
6399 static_call_update(intel_pmu_set_topdown_event_period,
6400 &icl_set_topdown_event_period);
6401
6402 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6403 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6404 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
6405 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
6406
6407 intel_pmu_ref_cycles_ext();
6408 }
6409
intel_pmu_init_grt(struct pmu * pmu)6410 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
6411 {
6412 x86_pmu.mid_ack = true;
6413 x86_pmu.limit_period = glc_limit_period;
6414 x86_pmu.pebs_aliases = NULL;
6415 x86_pmu.pebs_prec_dist = true;
6416 x86_pmu.pebs_block = true;
6417 x86_pmu.lbr_pt_coexist = true;
6418 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6419 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6420
6421 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6422 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6423 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6424 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
6425 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
6426 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
6427
6428 intel_pmu_ref_cycles_ext();
6429 }
6430
intel_pmu_init_lnc(struct pmu * pmu)6431 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
6432 {
6433 intel_pmu_init_glc(pmu);
6434 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
6435 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
6436 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
6437 }
6438
intel_pmu_init_skt(struct pmu * pmu)6439 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
6440 {
6441 intel_pmu_init_grt(pmu);
6442 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
6443 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
6444 }
6445
intel_pmu_init(void)6446 __init int intel_pmu_init(void)
6447 {
6448 struct attribute **extra_skl_attr = &empty_attrs;
6449 struct attribute **extra_attr = &empty_attrs;
6450 struct attribute **td_attr = &empty_attrs;
6451 struct attribute **mem_attr = &empty_attrs;
6452 struct attribute **tsx_attr = &empty_attrs;
6453 union cpuid10_edx edx;
6454 union cpuid10_eax eax;
6455 union cpuid10_ebx ebx;
6456 unsigned int fixed_mask;
6457 bool pmem = false;
6458 int version, i;
6459 char *name;
6460 struct x86_hybrid_pmu *pmu;
6461
6462 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
6463 switch (boot_cpu_data.x86) {
6464 case 0x6:
6465 return p6_pmu_init();
6466 case 0xb:
6467 return knc_pmu_init();
6468 case 0xf:
6469 return p4_pmu_init();
6470 }
6471 return -ENODEV;
6472 }
6473
6474 /*
6475 * Check whether the Architectural PerfMon supports
6476 * Branch Misses Retired hw_event or not.
6477 */
6478 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
6479 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
6480 return -ENODEV;
6481
6482 version = eax.split.version_id;
6483 if (version < 2)
6484 x86_pmu = core_pmu;
6485 else
6486 x86_pmu = intel_pmu;
6487
6488 x86_pmu.version = version;
6489 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
6490 x86_pmu.cntval_bits = eax.split.bit_width;
6491 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
6492
6493 x86_pmu.events_maskl = ebx.full;
6494 x86_pmu.events_mask_len = eax.split.mask_length;
6495
6496 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
6497 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
6498
6499 /*
6500 * Quirk: v2 perfmon does not report fixed-purpose events, so
6501 * assume at least 3 events, when not running in a hypervisor:
6502 */
6503 if (version > 1 && version < 5) {
6504 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
6505
6506 x86_pmu.fixed_cntr_mask64 =
6507 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
6508 } else if (version >= 5)
6509 x86_pmu.fixed_cntr_mask64 = fixed_mask;
6510
6511 if (boot_cpu_has(X86_FEATURE_PDCM)) {
6512 u64 capabilities;
6513
6514 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
6515 x86_pmu.intel_cap.capabilities = capabilities;
6516 }
6517
6518 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
6519 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
6520 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
6521 }
6522
6523 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
6524 intel_pmu_arch_lbr_init();
6525
6526 intel_ds_init();
6527
6528 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
6529
6530 if (version >= 5) {
6531 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
6532 if (x86_pmu.intel_cap.anythread_deprecated)
6533 pr_cont(" AnyThread deprecated, ");
6534 }
6535
6536 /*
6537 * Install the hw-cache-events table:
6538 */
6539 switch (boot_cpu_data.x86_vfm) {
6540 case INTEL_CORE_YONAH:
6541 pr_cont("Core events, ");
6542 name = "core";
6543 break;
6544
6545 case INTEL_CORE2_MEROM:
6546 x86_add_quirk(intel_clovertown_quirk);
6547 fallthrough;
6548
6549 case INTEL_CORE2_MEROM_L:
6550 case INTEL_CORE2_PENRYN:
6551 case INTEL_CORE2_DUNNINGTON:
6552 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
6553 sizeof(hw_cache_event_ids));
6554
6555 intel_pmu_lbr_init_core();
6556
6557 x86_pmu.event_constraints = intel_core2_event_constraints;
6558 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
6559 pr_cont("Core2 events, ");
6560 name = "core2";
6561 break;
6562
6563 case INTEL_NEHALEM:
6564 case INTEL_NEHALEM_EP:
6565 case INTEL_NEHALEM_EX:
6566 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
6567 sizeof(hw_cache_event_ids));
6568 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6569 sizeof(hw_cache_extra_regs));
6570
6571 intel_pmu_lbr_init_nhm();
6572
6573 x86_pmu.event_constraints = intel_nehalem_event_constraints;
6574 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
6575 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6576 x86_pmu.extra_regs = intel_nehalem_extra_regs;
6577 x86_pmu.limit_period = nhm_limit_period;
6578
6579 mem_attr = nhm_mem_events_attrs;
6580
6581 /* UOPS_ISSUED.STALLED_CYCLES */
6582 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6583 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6584 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6585 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6586 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6587
6588 intel_pmu_pebs_data_source_nhm();
6589 x86_add_quirk(intel_nehalem_quirk);
6590 x86_pmu.pebs_no_tlb = 1;
6591 extra_attr = nhm_format_attr;
6592
6593 pr_cont("Nehalem events, ");
6594 name = "nehalem";
6595 break;
6596
6597 case INTEL_ATOM_BONNELL:
6598 case INTEL_ATOM_BONNELL_MID:
6599 case INTEL_ATOM_SALTWELL:
6600 case INTEL_ATOM_SALTWELL_MID:
6601 case INTEL_ATOM_SALTWELL_TABLET:
6602 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
6603 sizeof(hw_cache_event_ids));
6604
6605 intel_pmu_lbr_init_atom();
6606
6607 x86_pmu.event_constraints = intel_gen_event_constraints;
6608 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
6609 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
6610 pr_cont("Atom events, ");
6611 name = "bonnell";
6612 break;
6613
6614 case INTEL_ATOM_SILVERMONT:
6615 case INTEL_ATOM_SILVERMONT_D:
6616 case INTEL_ATOM_SILVERMONT_MID:
6617 case INTEL_ATOM_AIRMONT:
6618 case INTEL_ATOM_AIRMONT_MID:
6619 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
6620 sizeof(hw_cache_event_ids));
6621 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
6622 sizeof(hw_cache_extra_regs));
6623
6624 intel_pmu_lbr_init_slm();
6625
6626 x86_pmu.event_constraints = intel_slm_event_constraints;
6627 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6628 x86_pmu.extra_regs = intel_slm_extra_regs;
6629 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6630 td_attr = slm_events_attrs;
6631 extra_attr = slm_format_attr;
6632 pr_cont("Silvermont events, ");
6633 name = "silvermont";
6634 break;
6635
6636 case INTEL_ATOM_GOLDMONT:
6637 case INTEL_ATOM_GOLDMONT_D:
6638 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
6639 sizeof(hw_cache_event_ids));
6640 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
6641 sizeof(hw_cache_extra_regs));
6642
6643 intel_pmu_lbr_init_skl();
6644
6645 x86_pmu.event_constraints = intel_slm_event_constraints;
6646 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
6647 x86_pmu.extra_regs = intel_glm_extra_regs;
6648 /*
6649 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6650 * for precise cycles.
6651 * :pp is identical to :ppp
6652 */
6653 x86_pmu.pebs_aliases = NULL;
6654 x86_pmu.pebs_prec_dist = true;
6655 x86_pmu.lbr_pt_coexist = true;
6656 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6657 td_attr = glm_events_attrs;
6658 extra_attr = slm_format_attr;
6659 pr_cont("Goldmont events, ");
6660 name = "goldmont";
6661 break;
6662
6663 case INTEL_ATOM_GOLDMONT_PLUS:
6664 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6665 sizeof(hw_cache_event_ids));
6666 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
6667 sizeof(hw_cache_extra_regs));
6668
6669 intel_pmu_lbr_init_skl();
6670
6671 x86_pmu.event_constraints = intel_slm_event_constraints;
6672 x86_pmu.extra_regs = intel_glm_extra_regs;
6673 /*
6674 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6675 * for precise cycles.
6676 */
6677 x86_pmu.pebs_aliases = NULL;
6678 x86_pmu.pebs_prec_dist = true;
6679 x86_pmu.lbr_pt_coexist = true;
6680 x86_pmu.pebs_capable = ~0ULL;
6681 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6682 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6683 x86_pmu.get_event_constraints = glp_get_event_constraints;
6684 td_attr = glm_events_attrs;
6685 /* Goldmont Plus has 4-wide pipeline */
6686 event_attr_td_total_slots_scale_glm.event_str = "4";
6687 extra_attr = slm_format_attr;
6688 pr_cont("Goldmont plus events, ");
6689 name = "goldmont_plus";
6690 break;
6691
6692 case INTEL_ATOM_TREMONT_D:
6693 case INTEL_ATOM_TREMONT:
6694 case INTEL_ATOM_TREMONT_L:
6695 x86_pmu.late_ack = true;
6696 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6697 sizeof(hw_cache_event_ids));
6698 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6699 sizeof(hw_cache_extra_regs));
6700 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6701
6702 intel_pmu_lbr_init_skl();
6703
6704 x86_pmu.event_constraints = intel_slm_event_constraints;
6705 x86_pmu.extra_regs = intel_tnt_extra_regs;
6706 /*
6707 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6708 * for precise cycles.
6709 */
6710 x86_pmu.pebs_aliases = NULL;
6711 x86_pmu.pebs_prec_dist = true;
6712 x86_pmu.lbr_pt_coexist = true;
6713 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6714 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6715 td_attr = tnt_events_attrs;
6716 extra_attr = slm_format_attr;
6717 pr_cont("Tremont events, ");
6718 name = "Tremont";
6719 break;
6720
6721 case INTEL_ATOM_GRACEMONT:
6722 intel_pmu_init_grt(NULL);
6723 intel_pmu_pebs_data_source_grt();
6724 x86_pmu.pebs_latency_data = grt_latency_data;
6725 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6726 td_attr = tnt_events_attrs;
6727 mem_attr = grt_mem_attrs;
6728 extra_attr = nhm_format_attr;
6729 pr_cont("Gracemont events, ");
6730 name = "gracemont";
6731 break;
6732
6733 case INTEL_ATOM_CRESTMONT:
6734 case INTEL_ATOM_CRESTMONT_X:
6735 intel_pmu_init_grt(NULL);
6736 x86_pmu.extra_regs = intel_cmt_extra_regs;
6737 intel_pmu_pebs_data_source_cmt();
6738 x86_pmu.pebs_latency_data = cmt_latency_data;
6739 x86_pmu.get_event_constraints = cmt_get_event_constraints;
6740 td_attr = cmt_events_attrs;
6741 mem_attr = grt_mem_attrs;
6742 extra_attr = cmt_format_attr;
6743 pr_cont("Crestmont events, ");
6744 name = "crestmont";
6745 break;
6746
6747 case INTEL_WESTMERE:
6748 case INTEL_WESTMERE_EP:
6749 case INTEL_WESTMERE_EX:
6750 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6751 sizeof(hw_cache_event_ids));
6752 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6753 sizeof(hw_cache_extra_regs));
6754
6755 intel_pmu_lbr_init_nhm();
6756
6757 x86_pmu.event_constraints = intel_westmere_event_constraints;
6758 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6759 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6760 x86_pmu.extra_regs = intel_westmere_extra_regs;
6761 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6762
6763 mem_attr = nhm_mem_events_attrs;
6764
6765 /* UOPS_ISSUED.STALLED_CYCLES */
6766 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6767 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6768 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6769 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6770 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6771
6772 intel_pmu_pebs_data_source_nhm();
6773 extra_attr = nhm_format_attr;
6774 pr_cont("Westmere events, ");
6775 name = "westmere";
6776 break;
6777
6778 case INTEL_SANDYBRIDGE:
6779 case INTEL_SANDYBRIDGE_X:
6780 x86_add_quirk(intel_sandybridge_quirk);
6781 x86_add_quirk(intel_ht_bug);
6782 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6783 sizeof(hw_cache_event_ids));
6784 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6785 sizeof(hw_cache_extra_regs));
6786
6787 intel_pmu_lbr_init_snb();
6788
6789 x86_pmu.event_constraints = intel_snb_event_constraints;
6790 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6791 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6792 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
6793 x86_pmu.extra_regs = intel_snbep_extra_regs;
6794 else
6795 x86_pmu.extra_regs = intel_snb_extra_regs;
6796
6797
6798 /* all extra regs are per-cpu when HT is on */
6799 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6800 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6801
6802 td_attr = snb_events_attrs;
6803 mem_attr = snb_mem_events_attrs;
6804
6805 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6806 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6807 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6808 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6809 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6810 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6811
6812 extra_attr = nhm_format_attr;
6813
6814 pr_cont("SandyBridge events, ");
6815 name = "sandybridge";
6816 break;
6817
6818 case INTEL_IVYBRIDGE:
6819 case INTEL_IVYBRIDGE_X:
6820 x86_add_quirk(intel_ht_bug);
6821 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6822 sizeof(hw_cache_event_ids));
6823 /* dTLB-load-misses on IVB is different than SNB */
6824 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6825
6826 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6827 sizeof(hw_cache_extra_regs));
6828
6829 intel_pmu_lbr_init_snb();
6830
6831 x86_pmu.event_constraints = intel_ivb_event_constraints;
6832 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6833 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6834 x86_pmu.pebs_prec_dist = true;
6835 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
6836 x86_pmu.extra_regs = intel_snbep_extra_regs;
6837 else
6838 x86_pmu.extra_regs = intel_snb_extra_regs;
6839 /* all extra regs are per-cpu when HT is on */
6840 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6841 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6842
6843 td_attr = snb_events_attrs;
6844 mem_attr = snb_mem_events_attrs;
6845
6846 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6847 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6848 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6849
6850 extra_attr = nhm_format_attr;
6851
6852 pr_cont("IvyBridge events, ");
6853 name = "ivybridge";
6854 break;
6855
6856
6857 case INTEL_HASWELL:
6858 case INTEL_HASWELL_X:
6859 case INTEL_HASWELL_L:
6860 case INTEL_HASWELL_G:
6861 x86_add_quirk(intel_ht_bug);
6862 x86_add_quirk(intel_pebs_isolation_quirk);
6863 x86_pmu.late_ack = true;
6864 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6865 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6866
6867 intel_pmu_lbr_init_hsw();
6868
6869 x86_pmu.event_constraints = intel_hsw_event_constraints;
6870 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6871 x86_pmu.extra_regs = intel_snbep_extra_regs;
6872 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6873 x86_pmu.pebs_prec_dist = true;
6874 /* all extra regs are per-cpu when HT is on */
6875 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6876 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6877
6878 x86_pmu.hw_config = hsw_hw_config;
6879 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6880 x86_pmu.limit_period = hsw_limit_period;
6881 x86_pmu.lbr_double_abort = true;
6882 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6883 hsw_format_attr : nhm_format_attr;
6884 td_attr = hsw_events_attrs;
6885 mem_attr = hsw_mem_events_attrs;
6886 tsx_attr = hsw_tsx_events_attrs;
6887 pr_cont("Haswell events, ");
6888 name = "haswell";
6889 break;
6890
6891 case INTEL_BROADWELL:
6892 case INTEL_BROADWELL_D:
6893 case INTEL_BROADWELL_G:
6894 case INTEL_BROADWELL_X:
6895 x86_add_quirk(intel_pebs_isolation_quirk);
6896 x86_pmu.late_ack = true;
6897 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6898 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6899
6900 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6901 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6902 BDW_L3_MISS|HSW_SNOOP_DRAM;
6903 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6904 HSW_SNOOP_DRAM;
6905 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6906 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6907 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6908 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6909
6910 intel_pmu_lbr_init_hsw();
6911
6912 x86_pmu.event_constraints = intel_bdw_event_constraints;
6913 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
6914 x86_pmu.extra_regs = intel_snbep_extra_regs;
6915 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6916 x86_pmu.pebs_prec_dist = true;
6917 /* all extra regs are per-cpu when HT is on */
6918 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6919 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6920
6921 x86_pmu.hw_config = hsw_hw_config;
6922 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6923 x86_pmu.limit_period = bdw_limit_period;
6924 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6925 hsw_format_attr : nhm_format_attr;
6926 td_attr = hsw_events_attrs;
6927 mem_attr = hsw_mem_events_attrs;
6928 tsx_attr = hsw_tsx_events_attrs;
6929 pr_cont("Broadwell events, ");
6930 name = "broadwell";
6931 break;
6932
6933 case INTEL_XEON_PHI_KNL:
6934 case INTEL_XEON_PHI_KNM:
6935 memcpy(hw_cache_event_ids,
6936 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6937 memcpy(hw_cache_extra_regs,
6938 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6939 intel_pmu_lbr_init_knl();
6940
6941 x86_pmu.event_constraints = intel_slm_event_constraints;
6942 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6943 x86_pmu.extra_regs = intel_knl_extra_regs;
6944
6945 /* all extra regs are per-cpu when HT is on */
6946 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6947 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6948 extra_attr = slm_format_attr;
6949 pr_cont("Knights Landing/Mill events, ");
6950 name = "knights-landing";
6951 break;
6952
6953 case INTEL_SKYLAKE_X:
6954 pmem = true;
6955 fallthrough;
6956 case INTEL_SKYLAKE_L:
6957 case INTEL_SKYLAKE:
6958 case INTEL_KABYLAKE_L:
6959 case INTEL_KABYLAKE:
6960 case INTEL_COMETLAKE_L:
6961 case INTEL_COMETLAKE:
6962 x86_add_quirk(intel_pebs_isolation_quirk);
6963 x86_pmu.late_ack = true;
6964 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6965 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6966 intel_pmu_lbr_init_skl();
6967
6968 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6969 event_attr_td_recovery_bubbles.event_str_noht =
6970 "event=0xd,umask=0x1,cmask=1";
6971 event_attr_td_recovery_bubbles.event_str_ht =
6972 "event=0xd,umask=0x1,cmask=1,any=1";
6973
6974 x86_pmu.event_constraints = intel_skl_event_constraints;
6975 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6976 x86_pmu.extra_regs = intel_skl_extra_regs;
6977 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6978 x86_pmu.pebs_prec_dist = true;
6979 /* all extra regs are per-cpu when HT is on */
6980 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6981 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6982
6983 x86_pmu.hw_config = hsw_hw_config;
6984 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6985 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6986 hsw_format_attr : nhm_format_attr;
6987 extra_skl_attr = skl_format_attr;
6988 td_attr = hsw_events_attrs;
6989 mem_attr = hsw_mem_events_attrs;
6990 tsx_attr = hsw_tsx_events_attrs;
6991 intel_pmu_pebs_data_source_skl(pmem);
6992
6993 /*
6994 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
6995 * TSX force abort hooks are not required on these systems. Only deploy
6996 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
6997 */
6998 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
6999 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
7000 x86_pmu.flags |= PMU_FL_TFA;
7001 x86_pmu.get_event_constraints = tfa_get_event_constraints;
7002 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
7003 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
7004 }
7005
7006 pr_cont("Skylake events, ");
7007 name = "skylake";
7008 break;
7009
7010 case INTEL_ICELAKE_X:
7011 case INTEL_ICELAKE_D:
7012 x86_pmu.pebs_ept = 1;
7013 pmem = true;
7014 fallthrough;
7015 case INTEL_ICELAKE_L:
7016 case INTEL_ICELAKE:
7017 case INTEL_TIGERLAKE_L:
7018 case INTEL_TIGERLAKE:
7019 case INTEL_ROCKETLAKE:
7020 x86_pmu.late_ack = true;
7021 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7022 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7023 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7024 intel_pmu_lbr_init_skl();
7025
7026 x86_pmu.event_constraints = intel_icl_event_constraints;
7027 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
7028 x86_pmu.extra_regs = intel_icl_extra_regs;
7029 x86_pmu.pebs_aliases = NULL;
7030 x86_pmu.pebs_prec_dist = true;
7031 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7032 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7033
7034 x86_pmu.hw_config = hsw_hw_config;
7035 x86_pmu.get_event_constraints = icl_get_event_constraints;
7036 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7037 hsw_format_attr : nhm_format_attr;
7038 extra_skl_attr = skl_format_attr;
7039 mem_attr = icl_events_attrs;
7040 td_attr = icl_td_events_attrs;
7041 tsx_attr = icl_tsx_events_attrs;
7042 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7043 x86_pmu.lbr_pt_coexist = true;
7044 intel_pmu_pebs_data_source_skl(pmem);
7045 x86_pmu.num_topdown_events = 4;
7046 static_call_update(intel_pmu_update_topdown_event,
7047 &icl_update_topdown_event);
7048 static_call_update(intel_pmu_set_topdown_event_period,
7049 &icl_set_topdown_event_period);
7050 pr_cont("Icelake events, ");
7051 name = "icelake";
7052 break;
7053
7054 case INTEL_SAPPHIRERAPIDS_X:
7055 case INTEL_EMERALDRAPIDS_X:
7056 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7057 x86_pmu.extra_regs = intel_glc_extra_regs;
7058 pr_cont("Sapphire Rapids events, ");
7059 name = "sapphire_rapids";
7060 goto glc_common;
7061
7062 case INTEL_GRANITERAPIDS_X:
7063 case INTEL_GRANITERAPIDS_D:
7064 x86_pmu.extra_regs = intel_rwc_extra_regs;
7065 pr_cont("Granite Rapids events, ");
7066 name = "granite_rapids";
7067
7068 glc_common:
7069 intel_pmu_init_glc(NULL);
7070 x86_pmu.pebs_ept = 1;
7071 x86_pmu.hw_config = hsw_hw_config;
7072 x86_pmu.get_event_constraints = glc_get_event_constraints;
7073 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7074 hsw_format_attr : nhm_format_attr;
7075 extra_skl_attr = skl_format_attr;
7076 mem_attr = glc_events_attrs;
7077 td_attr = glc_td_events_attrs;
7078 tsx_attr = glc_tsx_events_attrs;
7079 intel_pmu_pebs_data_source_skl(true);
7080 break;
7081
7082 case INTEL_ALDERLAKE:
7083 case INTEL_ALDERLAKE_L:
7084 case INTEL_RAPTORLAKE:
7085 case INTEL_RAPTORLAKE_P:
7086 case INTEL_RAPTORLAKE_S:
7087 /*
7088 * Alder Lake has 2 types of CPU, core and atom.
7089 *
7090 * Initialize the common PerfMon capabilities here.
7091 */
7092 intel_pmu_init_hybrid(hybrid_big_small);
7093
7094 x86_pmu.pebs_latency_data = grt_latency_data;
7095 x86_pmu.get_event_constraints = adl_get_event_constraints;
7096 x86_pmu.hw_config = adl_hw_config;
7097 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
7098
7099 td_attr = adl_hybrid_events_attrs;
7100 mem_attr = adl_hybrid_mem_attrs;
7101 tsx_attr = adl_hybrid_tsx_attrs;
7102 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7103 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
7104
7105 /* Initialize big core specific PerfMon capabilities.*/
7106 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7107 intel_pmu_init_glc(&pmu->pmu);
7108 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
7109 pmu->cntr_mask64 <<= 2;
7110 pmu->cntr_mask64 |= 0x3;
7111 pmu->fixed_cntr_mask64 <<= 1;
7112 pmu->fixed_cntr_mask64 |= 0x1;
7113 } else {
7114 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7115 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7116 }
7117
7118 /*
7119 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
7120 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
7121 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
7122 * mistakenly add extra counters for P-cores. Correct the number of
7123 * counters here.
7124 */
7125 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
7126 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7127 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7128 }
7129
7130 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7131 pmu->unconstrained = (struct event_constraint)
7132 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7133 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7134
7135 pmu->extra_regs = intel_glc_extra_regs;
7136
7137 /* Initialize Atom core specific PerfMon capabilities.*/
7138 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7139 intel_pmu_init_grt(&pmu->pmu);
7140
7141 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7142 intel_pmu_pebs_data_source_adl();
7143 pr_cont("Alderlake Hybrid events, ");
7144 name = "alderlake_hybrid";
7145 break;
7146
7147 case INTEL_METEORLAKE:
7148 case INTEL_METEORLAKE_L:
7149 case INTEL_ARROWLAKE_U:
7150 intel_pmu_init_hybrid(hybrid_big_small);
7151
7152 x86_pmu.pebs_latency_data = cmt_latency_data;
7153 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7154 x86_pmu.hw_config = adl_hw_config;
7155
7156 td_attr = adl_hybrid_events_attrs;
7157 mem_attr = mtl_hybrid_mem_attrs;
7158 tsx_attr = adl_hybrid_tsx_attrs;
7159 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7160 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7161
7162 /* Initialize big core specific PerfMon capabilities.*/
7163 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7164 intel_pmu_init_glc(&pmu->pmu);
7165 pmu->extra_regs = intel_rwc_extra_regs;
7166
7167 /* Initialize Atom core specific PerfMon capabilities.*/
7168 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7169 intel_pmu_init_grt(&pmu->pmu);
7170 pmu->extra_regs = intel_cmt_extra_regs;
7171
7172 intel_pmu_pebs_data_source_mtl();
7173 pr_cont("Meteorlake Hybrid events, ");
7174 name = "meteorlake_hybrid";
7175 break;
7176
7177 case INTEL_LUNARLAKE_M:
7178 case INTEL_ARROWLAKE:
7179 intel_pmu_init_hybrid(hybrid_big_small);
7180
7181 x86_pmu.pebs_latency_data = lnl_latency_data;
7182 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7183 x86_pmu.hw_config = adl_hw_config;
7184
7185 td_attr = lnl_hybrid_events_attrs;
7186 mem_attr = mtl_hybrid_mem_attrs;
7187 tsx_attr = adl_hybrid_tsx_attrs;
7188 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7189 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7190
7191 /* Initialize big core specific PerfMon capabilities.*/
7192 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7193 intel_pmu_init_lnc(&pmu->pmu);
7194
7195 /* Initialize Atom core specific PerfMon capabilities.*/
7196 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7197 intel_pmu_init_skt(&pmu->pmu);
7198
7199 intel_pmu_pebs_data_source_lnl();
7200 pr_cont("Lunarlake Hybrid events, ");
7201 name = "lunarlake_hybrid";
7202 break;
7203
7204 default:
7205 switch (x86_pmu.version) {
7206 case 1:
7207 x86_pmu.event_constraints = intel_v1_event_constraints;
7208 pr_cont("generic architected perfmon v1, ");
7209 name = "generic_arch_v1";
7210 break;
7211 case 2:
7212 case 3:
7213 case 4:
7214 /*
7215 * default constraints for v2 and up
7216 */
7217 x86_pmu.event_constraints = intel_gen_event_constraints;
7218 pr_cont("generic architected perfmon, ");
7219 name = "generic_arch_v2+";
7220 break;
7221 default:
7222 /*
7223 * The default constraints for v5 and up can support up to
7224 * 16 fixed counters. For the fixed counters 4 and later,
7225 * the pseudo-encoding is applied.
7226 * The constraints may be cut according to the CPUID enumeration
7227 * by inserting the EVENT_CONSTRAINT_END.
7228 */
7229 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
7230 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
7231 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
7232 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
7233 pr_cont("generic architected perfmon, ");
7234 name = "generic_arch_v5+";
7235 break;
7236 }
7237 }
7238
7239 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
7240
7241 if (!is_hybrid()) {
7242 group_events_td.attrs = td_attr;
7243 group_events_mem.attrs = mem_attr;
7244 group_events_tsx.attrs = tsx_attr;
7245 group_format_extra.attrs = extra_attr;
7246 group_format_extra_skl.attrs = extra_skl_attr;
7247
7248 x86_pmu.attr_update = attr_update;
7249 } else {
7250 hybrid_group_events_td.attrs = td_attr;
7251 hybrid_group_events_mem.attrs = mem_attr;
7252 hybrid_group_events_tsx.attrs = tsx_attr;
7253 hybrid_group_format_extra.attrs = extra_attr;
7254
7255 x86_pmu.attr_update = hybrid_attr_update;
7256 }
7257
7258 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
7259 &x86_pmu.fixed_cntr_mask64,
7260 &x86_pmu.intel_ctrl);
7261
7262 /* AnyThread may be deprecated on arch perfmon v5 or later */
7263 if (x86_pmu.intel_cap.anythread_deprecated)
7264 x86_pmu.format_attrs = intel_arch_formats_attr;
7265
7266 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
7267 x86_pmu.cntr_mask64,
7268 x86_pmu.fixed_cntr_mask64,
7269 x86_pmu.intel_ctrl);
7270 /*
7271 * Access LBR MSR may cause #GP under certain circumstances.
7272 * Check all LBR MSR here.
7273 * Disable LBR access if any LBR MSRs can not be accessed.
7274 */
7275 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
7276 x86_pmu.lbr_nr = 0;
7277 for (i = 0; i < x86_pmu.lbr_nr; i++) {
7278 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
7279 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
7280 x86_pmu.lbr_nr = 0;
7281 }
7282
7283 if (x86_pmu.lbr_nr) {
7284 intel_pmu_lbr_init();
7285
7286 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
7287
7288 /* only support branch_stack snapshot for perfmon >= v2 */
7289 if (x86_pmu.disable_all == intel_pmu_disable_all) {
7290 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
7291 static_call_update(perf_snapshot_branch_stack,
7292 intel_pmu_snapshot_arch_branch_stack);
7293 } else {
7294 static_call_update(perf_snapshot_branch_stack,
7295 intel_pmu_snapshot_branch_stack);
7296 }
7297 }
7298 }
7299
7300 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
7301
7302 /* Support full width counters using alternative MSR range */
7303 if (x86_pmu.intel_cap.full_width_write) {
7304 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
7305 x86_pmu.perfctr = MSR_IA32_PMC0;
7306 pr_cont("full-width counters, ");
7307 }
7308
7309 /* Support V6+ MSR Aliasing */
7310 if (x86_pmu.version >= 6) {
7311 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
7312 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
7313 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
7314 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
7315 }
7316
7317 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
7318 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
7319
7320 if (x86_pmu.intel_cap.pebs_timing_info)
7321 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
7322
7323 intel_aux_output_init();
7324
7325 return 0;
7326 }
7327
7328 /*
7329 * HT bug: phase 2 init
7330 * Called once we have valid topology information to check
7331 * whether or not HT is enabled
7332 * If HT is off, then we disable the workaround
7333 */
fixup_ht_bug(void)7334 static __init int fixup_ht_bug(void)
7335 {
7336 int c;
7337 /*
7338 * problem not present on this CPU model, nothing to do
7339 */
7340 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
7341 return 0;
7342
7343 if (topology_max_smt_threads() > 1) {
7344 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
7345 return 0;
7346 }
7347
7348 cpus_read_lock();
7349
7350 hardlockup_detector_perf_stop();
7351
7352 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
7353
7354 x86_pmu.start_scheduling = NULL;
7355 x86_pmu.commit_scheduling = NULL;
7356 x86_pmu.stop_scheduling = NULL;
7357
7358 hardlockup_detector_perf_restart();
7359
7360 for_each_online_cpu(c)
7361 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
7362
7363 cpus_read_unlock();
7364 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
7365 return 0;
7366 }
7367 subsys_initcall(fixup_ht_bug)
7368