1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MWAIT_H
3 #define _ASM_X86_MWAIT_H
4
5 #include <linux/sched.h>
6 #include <linux/sched/idle.h>
7
8 #include <asm/cpufeature.h>
9 #include <asm/nospec-branch.h>
10
11 #define MWAIT_SUBSTATE_MASK 0xf
12 #define MWAIT_CSTATE_MASK 0xf
13 #define MWAIT_SUBSTATE_SIZE 4
14 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
15 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
16 #define MWAIT_C1_SUBSTATE_MASK 0xf0
17
18 #define CPUID_MWAIT_LEAF 5
19 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
20 #define CPUID5_ECX_INTERRUPT_BREAK 0x2
21
22 #define MWAIT_ECX_INTERRUPT_BREAK 0x1
23 #define MWAITX_ECX_TIMER_ENABLE BIT(1)
24 #define MWAITX_MAX_WAIT_CYCLES UINT_MAX
25 #define MWAITX_DISABLE_CSTATES 0xf0
26 #define TPAUSE_C01_STATE 1
27 #define TPAUSE_C02_STATE 0
28
__monitor(const void * eax,unsigned long ecx,unsigned long edx)29 static __always_inline void __monitor(const void *eax, unsigned long ecx,
30 unsigned long edx)
31 {
32 /* "monitor %eax, %ecx, %edx;" */
33 asm volatile(".byte 0x0f, 0x01, 0xc8;"
34 :: "a" (eax), "c" (ecx), "d"(edx));
35 }
36
__monitorx(const void * eax,unsigned long ecx,unsigned long edx)37 static __always_inline void __monitorx(const void *eax, unsigned long ecx,
38 unsigned long edx)
39 {
40 /* "monitorx %eax, %ecx, %edx;" */
41 asm volatile(".byte 0x0f, 0x01, 0xfa;"
42 :: "a" (eax), "c" (ecx), "d"(edx));
43 }
44
__mwait(unsigned long eax,unsigned long ecx)45 static __always_inline void __mwait(unsigned long eax, unsigned long ecx)
46 {
47 /* "mwait %eax, %ecx;" */
48 asm volatile(".byte 0x0f, 0x01, 0xc9;"
49 :: "a" (eax), "c" (ecx));
50 }
51
52 /*
53 * MWAITX allows for a timer expiration to get the core out a wait state in
54 * addition to the default MWAIT exit condition of a store appearing at a
55 * monitored virtual address.
56 *
57 * Registers:
58 *
59 * MWAITX ECX[1]: enable timer if set
60 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
61 * frequency is the same as the TSC frequency.
62 *
63 * Below is a comparison between MWAIT and MWAITX on AMD processors:
64 *
65 * MWAIT MWAITX
66 * opcode 0f 01 c9 | 0f 01 fb
67 * ECX[0] value of RFLAGS.IF seen by instruction
68 * ECX[1] unused/#GP if set | enable timer if set
69 * ECX[31:2] unused/#GP if set
70 * EAX unused (reserve for hint)
71 * EBX[31:0] unused | max wait time (P0 clocks)
72 *
73 * MONITOR MONITORX
74 * opcode 0f 01 c8 | 0f 01 fa
75 * EAX (logical) address to monitor
76 * ECX #GP if not zero
77 */
__mwaitx(unsigned long eax,unsigned long ebx,unsigned long ecx)78 static __always_inline void __mwaitx(unsigned long eax, unsigned long ebx,
79 unsigned long ecx)
80 {
81 /* No need for TSA buffer clearing on AMD */
82
83 /* "mwaitx %eax, %ebx, %ecx;" */
84 asm volatile(".byte 0x0f, 0x01, 0xfb;"
85 :: "a" (eax), "b" (ebx), "c" (ecx));
86 }
87
88 /*
89 * Re-enable interrupts right upon calling mwait in such a way that
90 * no interrupt can fire _before_ the execution of mwait, ie: no
91 * instruction must be placed between "sti" and "mwait".
92 *
93 * This is necessary because if an interrupt queues a timer before
94 * executing mwait, it would otherwise go unnoticed and the next tick
95 * would not be reprogrammed accordingly before mwait ever wakes up.
96 */
__sti_mwait(unsigned long eax,unsigned long ecx)97 static __always_inline void __sti_mwait(unsigned long eax, unsigned long ecx)
98 {
99
100 /* "mwait %eax, %ecx;" */
101 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
102 :: "a" (eax), "c" (ecx));
103 }
104
105 /*
106 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
107 * which can obviate IPI to trigger checking of need_resched.
108 * We execute MONITOR against need_resched and enter optimized wait state
109 * through MWAIT. Whenever someone changes need_resched, we would be woken
110 * up from MWAIT (without an IPI).
111 *
112 * New with Core Duo processors, MWAIT can take some hints based on CPU
113 * capability.
114 */
mwait_idle_with_hints(unsigned long eax,unsigned long ecx)115 static __always_inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
116 {
117 if (need_resched())
118 return;
119
120 x86_idle_clear_cpu_buffers();
121
122 if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
123 const void *addr = ¤t_thread_info()->flags;
124
125 alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, [addr] "a" (addr));
126 __monitor(addr, 0, 0);
127
128 if (need_resched())
129 goto out;
130
131 if (ecx & 1) {
132 __mwait(eax, ecx);
133 } else {
134 __sti_mwait(eax, ecx);
135 raw_local_irq_disable();
136 }
137 }
138
139 out:
140 current_clr_polling();
141 }
142
143 /*
144 * Caller can specify whether to enter C0.1 (low latency, less
145 * power saving) or C0.2 state (saves more power, but longer wakeup
146 * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR
147 * which can force requests for C0.2 to be downgraded to C0.1.
148 */
__tpause(u32 ecx,u32 edx,u32 eax)149 static inline void __tpause(u32 ecx, u32 edx, u32 eax)
150 {
151 /* "tpause %ecx, %edx, %eax;" */
152 #ifdef CONFIG_AS_TPAUSE
153 asm volatile("tpause %%ecx\n"
154 :
155 : "c"(ecx), "d"(edx), "a"(eax));
156 #else
157 asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n"
158 :
159 : "c"(ecx), "d"(edx), "a"(eax));
160 #endif
161 }
162
163 #endif /* _ASM_X86_MWAIT_H */
164