1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
5
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
9
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15 #include <asm/current.h>
16
17 /*
18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow
19 * issue in software.
20 *
21 * The tracking does not use a counter. It uses uses arithmetic shift
22 * right on call entry and logical shift left on return.
23 *
24 * The depth tracking variable is initialized to 0x8000.... when the call
25 * depth is zero. The arithmetic shift right sign extends the MSB and
26 * saturates after the 12th call. The shift count is 5 for both directions
27 * so the tracking covers 12 nested calls.
28 *
29 * Call
30 * 0: 0x8000000000000000 0x0000000000000000
31 * 1: 0xfc00000000000000 0xf000000000000000
32 * ...
33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00
34 * 12: 0xffffffffffffffff 0xffffffffffffffe0
35 *
36 * After a return buffer fill the depth is credited 12 calls before the
37 * next stuffing has to take place.
38 *
39 * There is a inaccuracy for situations like this:
40 *
41 * 10 calls
42 * 5 returns
43 * 3 calls
44 * 4 returns
45 * 3 calls
46 * ....
47 *
48 * The shift count might cause this to be off by one in either direction,
49 * but there is still a cushion vs. the RSB depth. The algorithm does not
50 * claim to be perfect and it can be speculated around by the CPU, but it
51 * is considered that it obfuscates the problem enough to make exploitation
52 * extremely difficult.
53 */
54 #define RET_DEPTH_SHIFT 5
55 #define RSB_RET_STUFF_LOOPS 16
56 #define RET_DEPTH_INIT 0x8000000000000000ULL
57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL
58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL
59
60 #ifdef CONFIG_CALL_THUNKS_DEBUG
61 # define CALL_THUNKS_DEBUG_INC_CALLS \
62 incq PER_CPU_VAR(__x86_call_count);
63 # define CALL_THUNKS_DEBUG_INC_RETS \
64 incq PER_CPU_VAR(__x86_ret_count);
65 # define CALL_THUNKS_DEBUG_INC_STUFFS \
66 incq PER_CPU_VAR(__x86_stuffs_count);
67 # define CALL_THUNKS_DEBUG_INC_CTXSW \
68 incq PER_CPU_VAR(__x86_ctxsw_count);
69 #else
70 # define CALL_THUNKS_DEBUG_INC_CALLS
71 # define CALL_THUNKS_DEBUG_INC_RETS
72 # define CALL_THUNKS_DEBUG_INC_STUFFS
73 # define CALL_THUNKS_DEBUG_INC_CTXSW
74 #endif
75
76 #if defined(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
77
78 #include <asm/asm-offsets.h>
79
80 #define CREDIT_CALL_DEPTH \
81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
82
83 #define RESET_CALL_DEPTH \
84 xor %eax, %eax; \
85 bts $63, %rax; \
86 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
87
88 #define RESET_CALL_DEPTH_FROM_CALL \
89 movb $0xfc, %al; \
90 shl $56, %rax; \
91 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
92 CALL_THUNKS_DEBUG_INC_CALLS
93
94 #define INCREMENT_CALL_DEPTH \
95 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
96 CALL_THUNKS_DEBUG_INC_CALLS
97
98 #else
99 #define CREDIT_CALL_DEPTH
100 #define RESET_CALL_DEPTH
101 #define RESET_CALL_DEPTH_FROM_CALL
102 #define INCREMENT_CALL_DEPTH
103 #endif
104
105 /*
106 * Fill the CPU return stack buffer.
107 *
108 * Each entry in the RSB, if used for a speculative 'ret', contains an
109 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
110 *
111 * This is required in various cases for retpoline and IBRS-based
112 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
113 * eliminate potentially bogus entries from the RSB, and sometimes
114 * purely to ensure that it doesn't get empty, which on some CPUs would
115 * allow predictions from other (unwanted!) sources to be used.
116 *
117 * We define a CPP macro such that it can be used from both .S files and
118 * inline assembly. It's possible to do a .macro and then include that
119 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
120 */
121
122 #define RETPOLINE_THUNK_SIZE 32
123 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
124
125 /*
126 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
127 */
128 #define __FILL_RETURN_SLOT \
129 ANNOTATE_INTRA_FUNCTION_CALL; \
130 call 772f; \
131 int3; \
132 772:
133
134 /*
135 * Stuff the entire RSB.
136 *
137 * Google experimented with loop-unrolling and this turned out to be
138 * the optimal version - two calls, each with their own speculation
139 * trap should their return address end up getting used, in a loop.
140 */
141 #ifdef CONFIG_X86_64
142 #define __FILL_RETURN_BUFFER(reg, nr) \
143 mov $(nr/2), reg; \
144 771: \
145 __FILL_RETURN_SLOT \
146 __FILL_RETURN_SLOT \
147 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
148 dec reg; \
149 jnz 771b; \
150 /* barrier for jnz misprediction */ \
151 lfence; \
152 CREDIT_CALL_DEPTH \
153 CALL_THUNKS_DEBUG_INC_CTXSW
154 #else
155 /*
156 * i386 doesn't unconditionally have LFENCE, as such it can't
157 * do a loop.
158 */
159 #define __FILL_RETURN_BUFFER(reg, nr) \
160 .rept nr; \
161 __FILL_RETURN_SLOT; \
162 .endr; \
163 add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
164 #endif
165
166 /*
167 * Stuff a single RSB slot.
168 *
169 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
170 * forced to retire before letting a RET instruction execute.
171 *
172 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
173 * before this point.
174 */
175 #define __FILL_ONE_RETURN \
176 __FILL_RETURN_SLOT \
177 add $(BITS_PER_LONG/8), %_ASM_SP; \
178 lfence;
179
180 #ifdef __ASSEMBLY__
181
182 /*
183 * This should be used immediately before an indirect jump/call. It tells
184 * objtool the subsequent indirect jump/call is vouched safe for retpoline
185 * builds.
186 */
187 .macro ANNOTATE_RETPOLINE_SAFE
188 .Lhere_\@:
189 .pushsection .discard.retpoline_safe
190 .long .Lhere_\@
191 .popsection
192 .endm
193
194 /*
195 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
196 * vs RETBleed validation.
197 */
198 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
199
200 /*
201 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
202 * eventually turn into its own annotation.
203 */
204 .macro VALIDATE_UNRET_END
205 #if defined(CONFIG_NOINSTR_VALIDATION) && \
206 (defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO))
207 ANNOTATE_RETPOLINE_SAFE
208 nop
209 #endif
210 .endm
211
212 /*
213 * Emits a conditional CS prefix that is compatible with
214 * -mindirect-branch-cs-prefix.
215 */
216 .macro __CS_PREFIX reg:req
217 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15
218 .ifc \reg,\rs
219 .byte 0x2e
220 .endif
221 .endr
222 .endm
223
224 /*
225 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
226 * indirect jmp/call which may be susceptible to the Spectre variant 2
227 * attack.
228 *
229 * NOTE: these do not take kCFI into account and are thus not comparable to C
230 * indirect calls, take care when using. The target of these should be an ENDBR
231 * instruction irrespective of kCFI.
232 */
233 .macro JMP_NOSPEC reg:req
234 #ifdef CONFIG_MITIGATION_RETPOLINE
235 __CS_PREFIX \reg
236 jmp __x86_indirect_thunk_\reg
237 #else
238 jmp *%\reg
239 int3
240 #endif
241 .endm
242
243 .macro CALL_NOSPEC reg:req
244 #ifdef CONFIG_MITIGATION_RETPOLINE
245 __CS_PREFIX \reg
246 call __x86_indirect_thunk_\reg
247 #else
248 call *%\reg
249 #endif
250 .endm
251
252 /*
253 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
254 * monstrosity above, manually.
255 */
256 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
257 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
258 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
259 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
260
261 .Lskip_rsb_\@:
262 .endm
263
264 /*
265 * The CALL to srso_alias_untrain_ret() must be patched in directly at
266 * the spot where untraining must be done, ie., srso_alias_untrain_ret()
267 * must be the target of a CALL instruction instead of indirectly
268 * jumping to a wrapper which then calls it. Therefore, this macro is
269 * called outside of __UNTRAIN_RET below, for the time being, before the
270 * kernel can support nested alternatives with arbitrary nesting.
271 */
272 .macro CALL_UNTRAIN_RET
273 #if defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO)
274 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \
275 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS
276 #endif
277 .endm
278
279 /*
280 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
281 * return thunk isn't mapped into the userspace tables (then again, AMD
282 * typically has NO_MELTDOWN).
283 *
284 * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
285 * entry_ibpb() will clobber AX, CX, DX.
286 *
287 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
288 * where we have a stack but before any RET instruction.
289 */
290 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns
291 #if defined(CONFIG_MITIGATION_RETHUNK) || defined(CONFIG_MITIGATION_IBPB_ENTRY)
292 VALIDATE_UNRET_END
293 CALL_UNTRAIN_RET
294 ALTERNATIVE_2 "", \
295 "call entry_ibpb", \ibpb_feature, \
296 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH
297 #endif
298 .endm
299
300 #define UNTRAIN_RET \
301 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH)
302
303 #define UNTRAIN_RET_VM \
304 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH)
305
306 #define UNTRAIN_RET_FROM_CALL \
307 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL)
308
309
310 .macro CALL_DEPTH_ACCOUNT
311 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
312 ALTERNATIVE "", \
313 __stringify(INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
314 #endif
315 .endm
316
317 /*
318 * Macro to execute VERW insns that mitigate transient data sampling
319 * attacks such as MDS or TSA. On affected systems a microcode update
320 * overloaded VERW insns to also clear the CPU buffers. VERW clobbers
321 * CFLAGS.ZF.
322 * Note: Only the memory operand variant of VERW clears the CPU buffers.
323 */
324 .macro __CLEAR_CPU_BUFFERS feature
325 #ifdef CONFIG_X86_64
326 ALTERNATIVE "", "verw x86_verw_sel(%rip)", \feature
327 #else
328 /*
329 * In 32bit mode, the memory operand must be a %cs reference. The data
330 * segments may not be usable (vm86 mode), and the stack segment may not
331 * be flat (ESPFIX32).
332 */
333 ALTERNATIVE "", "verw %cs:x86_verw_sel", \feature
334 #endif
335 .endm
336
337 #define CLEAR_CPU_BUFFERS \
338 __CLEAR_CPU_BUFFERS X86_FEATURE_CLEAR_CPU_BUF
339
340 #define VM_CLEAR_CPU_BUFFERS \
341 __CLEAR_CPU_BUFFERS X86_FEATURE_CLEAR_CPU_BUF_VM
342
343 #ifdef CONFIG_X86_64
344 .macro CLEAR_BRANCH_HISTORY
345 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP
346 .endm
347
348 .macro CLEAR_BRANCH_HISTORY_VMEXIT
349 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT
350 .endm
351 #else
352 #define CLEAR_BRANCH_HISTORY
353 #define CLEAR_BRANCH_HISTORY_VMEXIT
354 #endif
355
356 #else /* __ASSEMBLY__ */
357
358 #define ANNOTATE_RETPOLINE_SAFE \
359 "999:\n\t" \
360 ".pushsection .discard.retpoline_safe\n\t" \
361 ".long 999b\n\t" \
362 ".popsection\n\t"
363
364 #define ITS_THUNK_SIZE 64
365
366 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
367 typedef u8 its_thunk_t[ITS_THUNK_SIZE];
368 extern retpoline_thunk_t __x86_indirect_thunk_array[];
369 extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
370 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
371 extern its_thunk_t __x86_indirect_its_thunk_array[];
372
373 #ifdef CONFIG_MITIGATION_RETHUNK
374 extern void __x86_return_thunk(void);
375 #else
__x86_return_thunk(void)376 static inline void __x86_return_thunk(void) {}
377 #endif
378
379 #ifdef CONFIG_MITIGATION_UNRET_ENTRY
380 extern void retbleed_return_thunk(void);
381 #else
retbleed_return_thunk(void)382 static inline void retbleed_return_thunk(void) {}
383 #endif
384
385 extern void srso_alias_untrain_ret(void);
386
387 #ifdef CONFIG_MITIGATION_SRSO
388 extern void srso_return_thunk(void);
389 extern void srso_alias_return_thunk(void);
390 #else
srso_return_thunk(void)391 static inline void srso_return_thunk(void) {}
srso_alias_return_thunk(void)392 static inline void srso_alias_return_thunk(void) {}
393 #endif
394
395 #ifdef CONFIG_MITIGATION_ITS
396 extern void its_return_thunk(void);
397 #else
its_return_thunk(void)398 static inline void its_return_thunk(void) {}
399 #endif
400
401 extern void retbleed_return_thunk(void);
402 extern void srso_return_thunk(void);
403 extern void srso_alias_return_thunk(void);
404
405 extern void entry_untrain_ret(void);
406 extern void entry_ibpb(void);
407
408 #ifdef CONFIG_X86_64
409 extern void clear_bhb_loop(void);
410 #endif
411
412 extern void (*x86_return_thunk)(void);
413
414 extern void __warn_thunk(void);
415
416 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
417 extern void call_depth_return_thunk(void);
418
419 #define CALL_DEPTH_ACCOUNT \
420 ALTERNATIVE("", \
421 __stringify(INCREMENT_CALL_DEPTH), \
422 X86_FEATURE_CALL_DEPTH)
423
424 #ifdef CONFIG_CALL_THUNKS_DEBUG
425 DECLARE_PER_CPU(u64, __x86_call_count);
426 DECLARE_PER_CPU(u64, __x86_ret_count);
427 DECLARE_PER_CPU(u64, __x86_stuffs_count);
428 DECLARE_PER_CPU(u64, __x86_ctxsw_count);
429 #endif
430 #else /* !CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
431
call_depth_return_thunk(void)432 static inline void call_depth_return_thunk(void) {}
433 #define CALL_DEPTH_ACCOUNT ""
434
435 #endif /* CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
436
437 #ifdef CONFIG_MITIGATION_RETPOLINE
438
439 #define GEN(reg) \
440 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
441 #include <asm/GEN-for-each-reg.h>
442 #undef GEN
443
444 #define GEN(reg) \
445 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
446 #include <asm/GEN-for-each-reg.h>
447 #undef GEN
448
449 #define GEN(reg) \
450 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
451 #include <asm/GEN-for-each-reg.h>
452 #undef GEN
453
454 #ifdef CONFIG_X86_64
455
456 /*
457 * Emits a conditional CS prefix that is compatible with
458 * -mindirect-branch-cs-prefix.
459 */
460 #define __CS_PREFIX(reg) \
461 ".irp rs,r8,r9,r10,r11,r12,r13,r14,r15\n" \
462 ".ifc \\rs," reg "\n" \
463 ".byte 0x2e\n" \
464 ".endif\n" \
465 ".endr\n"
466
467 /*
468 * Inline asm uses the %V modifier which is only in newer GCC
469 * which is ensured when CONFIG_MITIGATION_RETPOLINE is defined.
470 */
471 #define CALL_NOSPEC __CS_PREFIX("%V[thunk_target]") \
472 "call __x86_indirect_thunk_%V[thunk_target]\n"
473
474 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
475
476 #else /* CONFIG_X86_32 */
477 /*
478 * For i386 we use the original ret-equivalent retpoline, because
479 * otherwise we'll run out of registers. We don't care about CET
480 * here, anyway.
481 */
482 # define CALL_NOSPEC \
483 ALTERNATIVE_2( \
484 ANNOTATE_RETPOLINE_SAFE \
485 "call *%[thunk_target]\n", \
486 " jmp 904f;\n" \
487 " .align 16\n" \
488 "901: call 903f;\n" \
489 "902: pause;\n" \
490 " lfence;\n" \
491 " jmp 902b;\n" \
492 " .align 16\n" \
493 "903: lea 4(%%esp), %%esp;\n" \
494 " pushl %[thunk_target];\n" \
495 " ret;\n" \
496 " .align 16\n" \
497 "904: call 901b;\n", \
498 X86_FEATURE_RETPOLINE, \
499 "lfence;\n" \
500 ANNOTATE_RETPOLINE_SAFE \
501 "call *%[thunk_target]\n", \
502 X86_FEATURE_RETPOLINE_LFENCE)
503
504 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
505 #endif
506 #else /* No retpoline for C / inline asm */
507 # define CALL_NOSPEC "call *%[thunk_target]\n"
508 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
509 #endif
510
511 /* The Spectre V2 mitigation variants */
512 enum spectre_v2_mitigation {
513 SPECTRE_V2_NONE,
514 SPECTRE_V2_RETPOLINE,
515 SPECTRE_V2_LFENCE,
516 SPECTRE_V2_EIBRS,
517 SPECTRE_V2_EIBRS_RETPOLINE,
518 SPECTRE_V2_EIBRS_LFENCE,
519 SPECTRE_V2_IBRS,
520 };
521
522 /* The indirect branch speculation control variants */
523 enum spectre_v2_user_mitigation {
524 SPECTRE_V2_USER_NONE,
525 SPECTRE_V2_USER_STRICT,
526 SPECTRE_V2_USER_STRICT_PREFERRED,
527 SPECTRE_V2_USER_PRCTL,
528 SPECTRE_V2_USER_SECCOMP,
529 };
530
531 /* The Speculative Store Bypass disable variants */
532 enum ssb_mitigation {
533 SPEC_STORE_BYPASS_NONE,
534 SPEC_STORE_BYPASS_DISABLE,
535 SPEC_STORE_BYPASS_PRCTL,
536 SPEC_STORE_BYPASS_SECCOMP,
537 };
538
539 static __always_inline
alternative_msr_write(unsigned int msr,u64 val,unsigned int feature)540 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
541 {
542 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
543 : : "c" (msr),
544 "a" ((u32)val),
545 "d" ((u32)(val >> 32)),
546 [feature] "i" (feature)
547 : "memory");
548 }
549
550 extern u64 x86_pred_cmd;
551
552 DECLARE_PER_CPU(bool, x86_ibpb_exit_to_user);
553
indirect_branch_prediction_barrier(void)554 static inline void indirect_branch_prediction_barrier(void)
555 {
556 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
557 }
558
559 /* The Intel SPEC CTRL MSR base value cache */
560 extern u64 x86_spec_ctrl_base;
561 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
562 extern void update_spec_ctrl_cond(u64 val);
563 extern u64 spec_ctrl_current(void);
564
565 /*
566 * With retpoline, we must use IBRS to restrict branch prediction
567 * before calling into firmware.
568 *
569 * (Implemented as CPP macros due to header hell.)
570 */
571 #define firmware_restrict_branch_speculation_start() \
572 do { \
573 preempt_disable(); \
574 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
575 spec_ctrl_current() | SPEC_CTRL_IBRS, \
576 X86_FEATURE_USE_IBRS_FW); \
577 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
578 X86_FEATURE_USE_IBPB_FW); \
579 } while (0)
580
581 #define firmware_restrict_branch_speculation_end() \
582 do { \
583 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
584 spec_ctrl_current(), \
585 X86_FEATURE_USE_IBRS_FW); \
586 preempt_enable(); \
587 } while (0)
588
589 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
590 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
591 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
592
593 DECLARE_STATIC_KEY_FALSE(cpu_buf_idle_clear);
594
595 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
596
597 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
598
599 extern u16 x86_verw_sel;
600
601 #include <asm/segment.h>
602
603 /**
604 * x86_clear_cpu_buffers - Buffer clearing support for different x86 CPU vulns
605 *
606 * This uses the otherwise unused and obsolete VERW instruction in
607 * combination with microcode which triggers a CPU buffer flush when the
608 * instruction is executed.
609 */
x86_clear_cpu_buffers(void)610 static __always_inline void x86_clear_cpu_buffers(void)
611 {
612 static const u16 ds = __KERNEL_DS;
613
614 /*
615 * Has to be the memory-operand variant because only that
616 * guarantees the CPU buffer flush functionality according to
617 * documentation. The register-operand variant does not.
618 * Works with any segment selector, but a valid writable
619 * data segment is the fastest variant.
620 *
621 * "cc" clobber is required because VERW modifies ZF.
622 */
623 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
624 }
625
626 /**
627 * x86_idle_clear_cpu_buffers - Buffer clearing support in idle for the MDS
628 * and TSA vulnerabilities.
629 *
630 * Clear CPU buffers if the corresponding static key is enabled
631 */
x86_idle_clear_cpu_buffers(void)632 static __always_inline void x86_idle_clear_cpu_buffers(void)
633 {
634 if (static_branch_likely(&cpu_buf_idle_clear))
635 x86_clear_cpu_buffers();
636 }
637
638 #endif /* __ASSEMBLY__ */
639
640 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
641