1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Common interrupt code for 32 and 64 bit
4 */
5 #include <linux/cpu.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/of.h>
9 #include <linux/seq_file.h>
10 #include <linux/smp.h>
11 #include <linux/ftrace.h>
12 #include <linux/delay.h>
13 #include <linux/export.h>
14 #include <linux/irq.h>
15
16 #include <asm/irq_stack.h>
17 #include <asm/apic.h>
18 #include <asm/io_apic.h>
19 #include <asm/irq.h>
20 #include <asm/mce.h>
21 #include <asm/hw_irq.h>
22 #include <asm/desc.h>
23 #include <asm/traps.h>
24 #include <asm/thermal.h>
25 #include <asm/posted_intr.h>
26 #include <asm/irq_remapping.h>
27
28 #if defined(CONFIG_X86_LOCAL_APIC) || defined(CONFIG_X86_THERMAL_VECTOR)
29 #define CREATE_TRACE_POINTS
30 #include <asm/trace/irq_vectors.h>
31 #endif
32
33 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
34 EXPORT_PER_CPU_SYMBOL(irq_stat);
35
36 atomic_t irq_err_count;
37
38 /*
39 * 'what should we do if we get a hw irq event on an illegal vector'.
40 * each architecture has to answer this themselves.
41 */
ack_bad_irq(unsigned int irq)42 void ack_bad_irq(unsigned int irq)
43 {
44 if (printk_ratelimit())
45 pr_err("unexpected IRQ trap at vector %02x\n", irq);
46
47 /*
48 * Currently unexpected vectors happen only on SMP and APIC.
49 * We _must_ ack these because every local APIC has only N
50 * irq slots per priority level, and a 'hanging, unacked' IRQ
51 * holds up an irq slot - in excessive cases (when multiple
52 * unexpected vectors occur) that might lock up the APIC
53 * completely.
54 * But only ack when the APIC is enabled -AK
55 */
56 apic_eoi();
57 }
58
59 #define irq_stats(x) (&per_cpu(irq_stat, x))
60 /*
61 * /proc/interrupts printing for arch specific interrupts
62 */
arch_show_interrupts(struct seq_file * p,int prec)63 int arch_show_interrupts(struct seq_file *p, int prec)
64 {
65 int j;
66
67 seq_printf(p, "%*s: ", prec, "NMI");
68 for_each_online_cpu(j)
69 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
70 seq_puts(p, " Non-maskable interrupts\n");
71 #ifdef CONFIG_X86_LOCAL_APIC
72 seq_printf(p, "%*s: ", prec, "LOC");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
75 seq_puts(p, " Local timer interrupts\n");
76
77 seq_printf(p, "%*s: ", prec, "SPU");
78 for_each_online_cpu(j)
79 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
80 seq_puts(p, " Spurious interrupts\n");
81 seq_printf(p, "%*s: ", prec, "PMI");
82 for_each_online_cpu(j)
83 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
84 seq_puts(p, " Performance monitoring interrupts\n");
85 seq_printf(p, "%*s: ", prec, "IWI");
86 for_each_online_cpu(j)
87 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
88 seq_puts(p, " IRQ work interrupts\n");
89 seq_printf(p, "%*s: ", prec, "RTR");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
92 seq_puts(p, " APIC ICR read retries\n");
93 if (x86_platform_ipi_callback) {
94 seq_printf(p, "%*s: ", prec, "PLT");
95 for_each_online_cpu(j)
96 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
97 seq_puts(p, " Platform interrupts\n");
98 }
99 #endif
100 #ifdef CONFIG_SMP
101 seq_printf(p, "%*s: ", prec, "RES");
102 for_each_online_cpu(j)
103 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
104 seq_puts(p, " Rescheduling interrupts\n");
105 seq_printf(p, "%*s: ", prec, "CAL");
106 for_each_online_cpu(j)
107 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
108 seq_puts(p, " Function call interrupts\n");
109 seq_printf(p, "%*s: ", prec, "TLB");
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
112 seq_puts(p, " TLB shootdowns\n");
113 #endif
114 #ifdef CONFIG_X86_THERMAL_VECTOR
115 seq_printf(p, "%*s: ", prec, "TRM");
116 for_each_online_cpu(j)
117 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
118 seq_puts(p, " Thermal event interrupts\n");
119 #endif
120 #ifdef CONFIG_X86_MCE_THRESHOLD
121 seq_printf(p, "%*s: ", prec, "THR");
122 for_each_online_cpu(j)
123 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
124 seq_puts(p, " Threshold APIC interrupts\n");
125 #endif
126 #ifdef CONFIG_X86_MCE_AMD
127 seq_printf(p, "%*s: ", prec, "DFR");
128 for_each_online_cpu(j)
129 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
130 seq_puts(p, " Deferred Error APIC interrupts\n");
131 #endif
132 #ifdef CONFIG_X86_MCE
133 seq_printf(p, "%*s: ", prec, "MCE");
134 for_each_online_cpu(j)
135 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
136 seq_puts(p, " Machine check exceptions\n");
137 seq_printf(p, "%*s: ", prec, "MCP");
138 for_each_online_cpu(j)
139 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
140 seq_puts(p, " Machine check polls\n");
141 #endif
142 #ifdef CONFIG_X86_HV_CALLBACK_VECTOR
143 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
144 seq_printf(p, "%*s: ", prec, "HYP");
145 for_each_online_cpu(j)
146 seq_printf(p, "%10u ",
147 irq_stats(j)->irq_hv_callback_count);
148 seq_puts(p, " Hypervisor callback interrupts\n");
149 }
150 #endif
151 #if IS_ENABLED(CONFIG_HYPERV)
152 if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
153 seq_printf(p, "%*s: ", prec, "HRE");
154 for_each_online_cpu(j)
155 seq_printf(p, "%10u ",
156 irq_stats(j)->irq_hv_reenlightenment_count);
157 seq_puts(p, " Hyper-V reenlightenment interrupts\n");
158 }
159 if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
160 seq_printf(p, "%*s: ", prec, "HVS");
161 for_each_online_cpu(j)
162 seq_printf(p, "%10u ",
163 irq_stats(j)->hyperv_stimer0_count);
164 seq_puts(p, " Hyper-V stimer0 interrupts\n");
165 }
166 #endif
167 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
168 #if defined(CONFIG_X86_IO_APIC)
169 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
170 #endif
171 #if IS_ENABLED(CONFIG_KVM)
172 seq_printf(p, "%*s: ", prec, "PIN");
173 for_each_online_cpu(j)
174 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
175 seq_puts(p, " Posted-interrupt notification event\n");
176
177 seq_printf(p, "%*s: ", prec, "NPI");
178 for_each_online_cpu(j)
179 seq_printf(p, "%10u ",
180 irq_stats(j)->kvm_posted_intr_nested_ipis);
181 seq_puts(p, " Nested posted-interrupt event\n");
182
183 seq_printf(p, "%*s: ", prec, "PIW");
184 for_each_online_cpu(j)
185 seq_printf(p, "%10u ",
186 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
187 seq_puts(p, " Posted-interrupt wakeup event\n");
188 #endif
189 #ifdef CONFIG_X86_POSTED_MSI
190 seq_printf(p, "%*s: ", prec, "PMN");
191 for_each_online_cpu(j)
192 seq_printf(p, "%10u ",
193 irq_stats(j)->posted_msi_notification_count);
194 seq_puts(p, " Posted MSI notification event\n");
195 #endif
196 return 0;
197 }
198
199 /*
200 * /proc/stat helpers
201 */
arch_irq_stat_cpu(unsigned int cpu)202 u64 arch_irq_stat_cpu(unsigned int cpu)
203 {
204 u64 sum = irq_stats(cpu)->__nmi_count;
205
206 #ifdef CONFIG_X86_LOCAL_APIC
207 sum += irq_stats(cpu)->apic_timer_irqs;
208 sum += irq_stats(cpu)->irq_spurious_count;
209 sum += irq_stats(cpu)->apic_perf_irqs;
210 sum += irq_stats(cpu)->apic_irq_work_irqs;
211 sum += irq_stats(cpu)->icr_read_retry_count;
212 if (x86_platform_ipi_callback)
213 sum += irq_stats(cpu)->x86_platform_ipis;
214 #endif
215 #ifdef CONFIG_SMP
216 sum += irq_stats(cpu)->irq_resched_count;
217 sum += irq_stats(cpu)->irq_call_count;
218 #endif
219 #ifdef CONFIG_X86_THERMAL_VECTOR
220 sum += irq_stats(cpu)->irq_thermal_count;
221 #endif
222 #ifdef CONFIG_X86_MCE_THRESHOLD
223 sum += irq_stats(cpu)->irq_threshold_count;
224 #endif
225 #ifdef CONFIG_X86_HV_CALLBACK_VECTOR
226 sum += irq_stats(cpu)->irq_hv_callback_count;
227 #endif
228 #if IS_ENABLED(CONFIG_HYPERV)
229 sum += irq_stats(cpu)->irq_hv_reenlightenment_count;
230 sum += irq_stats(cpu)->hyperv_stimer0_count;
231 #endif
232 #ifdef CONFIG_X86_MCE
233 sum += per_cpu(mce_exception_count, cpu);
234 sum += per_cpu(mce_poll_count, cpu);
235 #endif
236 return sum;
237 }
238
arch_irq_stat(void)239 u64 arch_irq_stat(void)
240 {
241 u64 sum = atomic_read(&irq_err_count);
242 return sum;
243 }
244
handle_irq(struct irq_desc * desc,struct pt_regs * regs)245 static __always_inline void handle_irq(struct irq_desc *desc,
246 struct pt_regs *regs)
247 {
248 if (IS_ENABLED(CONFIG_X86_64))
249 generic_handle_irq_desc(desc);
250 else
251 __handle_irq(desc, regs);
252 }
253
reevaluate_vector(int vector)254 static struct irq_desc *reevaluate_vector(int vector)
255 {
256 struct irq_desc *desc = __this_cpu_read(vector_irq[vector]);
257
258 if (!IS_ERR_OR_NULL(desc))
259 return desc;
260
261 if (desc == VECTOR_UNUSED)
262 pr_emerg_ratelimited("No irq handler for %d.%u\n", smp_processor_id(), vector);
263 else
264 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
265 return NULL;
266 }
267
call_irq_handler(int vector,struct pt_regs * regs)268 static __always_inline bool call_irq_handler(int vector, struct pt_regs *regs)
269 {
270 struct irq_desc *desc = __this_cpu_read(vector_irq[vector]);
271
272 if (likely(!IS_ERR_OR_NULL(desc))) {
273 handle_irq(desc, regs);
274 return true;
275 }
276
277 /*
278 * Reevaluate with vector_lock held to prevent a race against
279 * request_irq() setting up the vector:
280 *
281 * CPU0 CPU1
282 * interrupt is raised in APIC IRR
283 * but not handled
284 * free_irq()
285 * per_cpu(vector_irq, CPU1)[vector] = VECTOR_SHUTDOWN;
286 *
287 * request_irq() common_interrupt()
288 * d = this_cpu_read(vector_irq[vector]);
289 *
290 * per_cpu(vector_irq, CPU1)[vector] = desc;
291 *
292 * if (d == VECTOR_SHUTDOWN)
293 * this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
294 *
295 * This requires that the same vector on the same target CPU is
296 * handed out or that a spurious interrupt hits that CPU/vector.
297 */
298 lock_vector_lock();
299 desc = reevaluate_vector(vector);
300 unlock_vector_lock();
301
302 if (!desc)
303 return false;
304
305 handle_irq(desc, regs);
306 return true;
307 }
308
309 /*
310 * common_interrupt() handles all normal device IRQ's (the special SMP
311 * cross-CPU interrupts have their own entry points).
312 */
DEFINE_IDTENTRY_IRQ(common_interrupt)313 DEFINE_IDTENTRY_IRQ(common_interrupt)
314 {
315 struct pt_regs *old_regs = set_irq_regs(regs);
316
317 /* entry code tells RCU that we're not quiescent. Check it. */
318 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
319
320 if (unlikely(!call_irq_handler(vector, regs)))
321 apic_eoi();
322
323 set_irq_regs(old_regs);
324 }
325
326 #ifdef CONFIG_X86_LOCAL_APIC
327 /* Function pointer for generic interrupt vector handling */
328 void (*x86_platform_ipi_callback)(void) = NULL;
329 /*
330 * Handler for X86_PLATFORM_IPI_VECTOR.
331 */
DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)332 DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
333 {
334 struct pt_regs *old_regs = set_irq_regs(regs);
335
336 apic_eoi();
337 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
338 inc_irq_stat(x86_platform_ipis);
339 if (x86_platform_ipi_callback)
340 x86_platform_ipi_callback();
341 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
342 set_irq_regs(old_regs);
343 }
344 #endif
345
346 #if IS_ENABLED(CONFIG_KVM)
dummy_handler(void)347 static void dummy_handler(void) {}
348 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
349
kvm_set_posted_intr_wakeup_handler(void (* handler)(void))350 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
351 {
352 if (handler)
353 kvm_posted_intr_wakeup_handler = handler;
354 else {
355 kvm_posted_intr_wakeup_handler = dummy_handler;
356 synchronize_rcu();
357 }
358 }
359 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
360
361 /*
362 * Handler for POSTED_INTERRUPT_VECTOR.
363 */
DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)364 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
365 {
366 apic_eoi();
367 inc_irq_stat(kvm_posted_intr_ipis);
368 }
369
370 /*
371 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
372 */
DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)373 DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
374 {
375 apic_eoi();
376 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
377 kvm_posted_intr_wakeup_handler();
378 }
379
380 /*
381 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
382 */
DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)383 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
384 {
385 apic_eoi();
386 inc_irq_stat(kvm_posted_intr_nested_ipis);
387 }
388 #endif
389
390 #ifdef CONFIG_X86_POSTED_MSI
391
392 /* Posted Interrupt Descriptors for coalesced MSIs to be posted */
393 DEFINE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
394
intel_posted_msi_init(void)395 void intel_posted_msi_init(void)
396 {
397 u32 destination;
398 u32 apic_id;
399
400 this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR);
401
402 /*
403 * APIC destination ID is stored in bit 8:15 while in XAPIC mode.
404 * VT-d spec. CH 9.11
405 */
406 apic_id = this_cpu_read(x86_cpu_to_apicid);
407 destination = x2apic_enabled() ? apic_id : apic_id << 8;
408 this_cpu_write(posted_msi_pi_desc.ndst, destination);
409 }
410
411 /*
412 * De-multiplexing posted interrupts is on the performance path, the code
413 * below is written to optimize the cache performance based on the following
414 * considerations:
415 * 1.Posted interrupt descriptor (PID) fits in a cache line that is frequently
416 * accessed by both CPU and IOMMU.
417 * 2.During posted MSI processing, the CPU needs to do 64-bit read and xchg
418 * for checking and clearing posted interrupt request (PIR), a 256 bit field
419 * within the PID.
420 * 3.On the other side, the IOMMU does atomic swaps of the entire PID cache
421 * line when posting interrupts and setting control bits.
422 * 4.The CPU can access the cache line a magnitude faster than the IOMMU.
423 * 5.Each time the IOMMU does interrupt posting to the PIR will evict the PID
424 * cache line. The cache line states after each operation are as follows:
425 * CPU IOMMU PID Cache line state
426 * ---------------------------------------------------------------
427 *...read64 exclusive
428 *...lock xchg64 modified
429 *... post/atomic swap invalid
430 *...-------------------------------------------------------------
431 *
432 * To reduce L1 data cache miss, it is important to avoid contention with
433 * IOMMU's interrupt posting/atomic swap. Therefore, a copy of PIR is used
434 * to dispatch interrupt handlers.
435 *
436 * In addition, the code is trying to keep the cache line state consistent
437 * as much as possible. e.g. when making a copy and clearing the PIR
438 * (assuming non-zero PIR bits are present in the entire PIR), it does:
439 * read, read, read, read, xchg, xchg, xchg, xchg
440 * instead of:
441 * read, xchg, read, xchg, read, xchg, read, xchg
442 */
handle_pending_pir(u64 * pir,struct pt_regs * regs)443 static __always_inline bool handle_pending_pir(u64 *pir, struct pt_regs *regs)
444 {
445 int i, vec = FIRST_EXTERNAL_VECTOR;
446 unsigned long pir_copy[4];
447 bool handled = false;
448
449 for (i = 0; i < 4; i++)
450 pir_copy[i] = READ_ONCE(pir[i]);
451
452 for (i = 0; i < 4; i++) {
453 if (!pir_copy[i])
454 continue;
455
456 pir_copy[i] = arch_xchg(&pir[i], 0);
457 handled = true;
458 }
459
460 if (handled) {
461 for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
462 call_irq_handler(vec, regs);
463 }
464
465 return handled;
466 }
467
468 /*
469 * Performance data shows that 3 is good enough to harvest 90+% of the benefit
470 * on high IRQ rate workload.
471 */
472 #define MAX_POSTED_MSI_COALESCING_LOOP 3
473
474 /*
475 * For MSIs that are delivered as posted interrupts, the CPU notifications
476 * can be coalesced if the MSIs arrive in high frequency bursts.
477 */
DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)478 DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)
479 {
480 struct pt_regs *old_regs = set_irq_regs(regs);
481 struct pi_desc *pid;
482 int i = 0;
483
484 pid = this_cpu_ptr(&posted_msi_pi_desc);
485
486 inc_irq_stat(posted_msi_notification_count);
487 irq_enter();
488
489 /*
490 * Max coalescing count includes the extra round of handle_pending_pir
491 * after clearing the outstanding notification bit. Hence, at most
492 * MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here.
493 */
494 while (++i < MAX_POSTED_MSI_COALESCING_LOOP) {
495 if (!handle_pending_pir(pid->pir64, regs))
496 break;
497 }
498
499 /*
500 * Clear outstanding notification bit to allow new IRQ notifications,
501 * do this last to maximize the window of interrupt coalescing.
502 */
503 pi_clear_on(pid);
504
505 /*
506 * There could be a race of PI notification and the clearing of ON bit,
507 * process PIR bits one last time such that handling the new interrupts
508 * are not delayed until the next IRQ.
509 */
510 handle_pending_pir(pid->pir64, regs);
511
512 apic_eoi();
513 irq_exit();
514 set_irq_regs(old_regs);
515 }
516 #endif /* X86_POSTED_MSI */
517
518 #ifdef CONFIG_HOTPLUG_CPU
519 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
fixup_irqs(void)520 void fixup_irqs(void)
521 {
522 unsigned int vector;
523 struct irq_desc *desc;
524 struct irq_data *data;
525 struct irq_chip *chip;
526
527 irq_migrate_all_off_this_cpu();
528
529 /*
530 * We can remove mdelay() and then send spurious interrupts to
531 * new cpu targets for all the irqs that were handled previously by
532 * this cpu. While it works, I have seen spurious interrupt messages
533 * (nothing wrong but still...).
534 *
535 * So for now, retain mdelay(1) and check the IRR and then send those
536 * interrupts to new targets as this cpu is already offlined...
537 */
538 mdelay(1);
539
540 /*
541 * We can walk the vector array of this cpu without holding
542 * vector_lock because the cpu is already marked !online, so
543 * nothing else will touch it.
544 */
545 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
546 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
547 continue;
548
549 if (is_vector_pending(vector)) {
550 desc = __this_cpu_read(vector_irq[vector]);
551
552 raw_spin_lock(&desc->lock);
553 data = irq_desc_get_irq_data(desc);
554 chip = irq_data_get_irq_chip(data);
555 if (chip->irq_retrigger) {
556 chip->irq_retrigger(data);
557 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
558 }
559 raw_spin_unlock(&desc->lock);
560 }
561 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
562 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
563 }
564 }
565 #endif
566
567 #ifdef CONFIG_X86_THERMAL_VECTOR
smp_thermal_vector(void)568 static void smp_thermal_vector(void)
569 {
570 if (x86_thermal_enabled())
571 intel_thermal_interrupt();
572 else
573 pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
574 smp_processor_id());
575 }
576
DEFINE_IDTENTRY_SYSVEC(sysvec_thermal)577 DEFINE_IDTENTRY_SYSVEC(sysvec_thermal)
578 {
579 trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
580 inc_irq_stat(irq_thermal_count);
581 smp_thermal_vector();
582 trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
583 apic_eoi();
584 }
585 #endif
586