1 /*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9 /*
10 * Handle hardware traps and faults.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/kmsan.h>
19 #include <linux/spinlock.h>
20 #include <linux/kprobes.h>
21 #include <linux/uaccess.h>
22 #include <linux/kdebug.h>
23 #include <linux/kgdb.h>
24 #include <linux/kernel.h>
25 #include <linux/export.h>
26 #include <linux/ptrace.h>
27 #include <linux/uprobes.h>
28 #include <linux/string.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/kexec.h>
32 #include <linux/sched.h>
33 #include <linux/sched/task_stack.h>
34 #include <linux/timer.h>
35 #include <linux/init.h>
36 #include <linux/bug.h>
37 #include <linux/nmi.h>
38 #include <linux/mm.h>
39 #include <linux/smp.h>
40 #include <linux/cpu.h>
41 #include <linux/io.h>
42 #include <linux/hardirq.h>
43 #include <linux/atomic.h>
44 #include <linux/iommu.h>
45 #include <linux/ubsan.h>
46
47 #include <asm/stacktrace.h>
48 #include <asm/processor.h>
49 #include <asm/debugreg.h>
50 #include <asm/realmode.h>
51 #include <asm/text-patching.h>
52 #include <asm/ftrace.h>
53 #include <asm/traps.h>
54 #include <asm/desc.h>
55 #include <asm/fred.h>
56 #include <asm/fpu/api.h>
57 #include <asm/cpu.h>
58 #include <asm/cpu_entry_area.h>
59 #include <asm/mce.h>
60 #include <asm/fixmap.h>
61 #include <asm/mach_traps.h>
62 #include <asm/alternative.h>
63 #include <asm/fpu/xstate.h>
64 #include <asm/vm86.h>
65 #include <asm/umip.h>
66 #include <asm/insn.h>
67 #include <asm/insn-eval.h>
68 #include <asm/vdso.h>
69 #include <asm/tdx.h>
70 #include <asm/cfi.h>
71
72 #ifdef CONFIG_X86_64
73 #include <asm/x86_init.h>
74 #else
75 #include <asm/processor-flags.h>
76 #include <asm/setup.h>
77 #endif
78
79 #include <asm/proto.h>
80
81 DECLARE_BITMAP(system_vectors, NR_VECTORS);
82
is_valid_bugaddr(unsigned long addr)83 __always_inline int is_valid_bugaddr(unsigned long addr)
84 {
85 if (addr < TASK_SIZE_MAX)
86 return 0;
87
88 /*
89 * We got #UD, if the text isn't readable we'd have gotten
90 * a different exception.
91 */
92 return *(unsigned short *)addr == INSN_UD2;
93 }
94
95 /*
96 * Check for UD1 or UD2, accounting for Address Size Override Prefixes.
97 * If it's a UD1, further decode to determine its use:
98 *
99 * UBSan{0}: 67 0f b9 00 ud1 (%eax),%eax
100 * UBSan{10}: 67 0f b9 40 10 ud1 0x10(%eax),%eax
101 * static_call: 0f b9 cc ud1 %esp,%ecx
102 *
103 * Notably UBSAN uses EAX, static_call uses ECX.
104 */
decode_bug(unsigned long addr,s32 * imm,int * len)105 __always_inline int decode_bug(unsigned long addr, s32 *imm, int *len)
106 {
107 unsigned long start = addr;
108 u8 v;
109
110 if (addr < TASK_SIZE_MAX)
111 return BUG_NONE;
112
113 v = *(u8 *)(addr++);
114 if (v == INSN_ASOP)
115 v = *(u8 *)(addr++);
116 if (v != OPCODE_ESCAPE)
117 return BUG_NONE;
118
119 v = *(u8 *)(addr++);
120 if (v == SECOND_BYTE_OPCODE_UD2) {
121 *len = addr - start;
122 return BUG_UD2;
123 }
124
125 if (v != SECOND_BYTE_OPCODE_UD1)
126 return BUG_NONE;
127
128 *imm = 0;
129 v = *(u8 *)(addr++); /* ModRM */
130
131 if (X86_MODRM_MOD(v) != 3 && X86_MODRM_RM(v) == 4)
132 addr++; /* SIB */
133
134 /* Decode immediate, if present */
135 switch (X86_MODRM_MOD(v)) {
136 case 0: if (X86_MODRM_RM(v) == 5)
137 addr += 4; /* RIP + disp32 */
138 break;
139
140 case 1: *imm = *(s8 *)addr;
141 addr += 1;
142 break;
143
144 case 2: *imm = *(s32 *)addr;
145 addr += 4;
146 break;
147
148 case 3: break;
149 }
150
151 /* record instruction length */
152 *len = addr - start;
153
154 if (X86_MODRM_REG(v) == 0) /* EAX */
155 return BUG_UD1_UBSAN;
156
157 return BUG_UD1;
158 }
159
160
161 static nokprobe_inline int
do_trap_no_signal(struct task_struct * tsk,int trapnr,const char * str,struct pt_regs * regs,long error_code)162 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
163 struct pt_regs *regs, long error_code)
164 {
165 if (v8086_mode(regs)) {
166 /*
167 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
168 * On nmi (interrupt 2), do_trap should not be called.
169 */
170 if (trapnr < X86_TRAP_UD) {
171 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
172 error_code, trapnr))
173 return 0;
174 }
175 } else if (!user_mode(regs)) {
176 if (fixup_exception(regs, trapnr, error_code, 0))
177 return 0;
178
179 tsk->thread.error_code = error_code;
180 tsk->thread.trap_nr = trapnr;
181 die(str, regs, error_code);
182 } else {
183 if (fixup_vdso_exception(regs, trapnr, error_code, 0))
184 return 0;
185 }
186
187 /*
188 * We want error_code and trap_nr set for userspace faults and
189 * kernelspace faults which result in die(), but not
190 * kernelspace faults which are fixed up. die() gives the
191 * process no chance to handle the signal and notice the
192 * kernel fault information, so that won't result in polluting
193 * the information about previously queued, but not yet
194 * delivered, faults. See also exc_general_protection below.
195 */
196 tsk->thread.error_code = error_code;
197 tsk->thread.trap_nr = trapnr;
198
199 return -1;
200 }
201
show_signal(struct task_struct * tsk,int signr,const char * type,const char * desc,struct pt_regs * regs,long error_code)202 static void show_signal(struct task_struct *tsk, int signr,
203 const char *type, const char *desc,
204 struct pt_regs *regs, long error_code)
205 {
206 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
207 printk_ratelimit()) {
208 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
209 tsk->comm, task_pid_nr(tsk), type, desc,
210 regs->ip, regs->sp, error_code);
211 print_vma_addr(KERN_CONT " in ", regs->ip);
212 pr_cont("\n");
213 }
214 }
215
216 static void
do_trap(int trapnr,int signr,char * str,struct pt_regs * regs,long error_code,int sicode,void __user * addr)217 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
218 long error_code, int sicode, void __user *addr)
219 {
220 struct task_struct *tsk = current;
221
222 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
223 return;
224
225 show_signal(tsk, signr, "trap ", str, regs, error_code);
226
227 if (!sicode)
228 force_sig(signr);
229 else
230 force_sig_fault(signr, sicode, addr);
231 }
232 NOKPROBE_SYMBOL(do_trap);
233
do_error_trap(struct pt_regs * regs,long error_code,char * str,unsigned long trapnr,int signr,int sicode,void __user * addr)234 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
235 unsigned long trapnr, int signr, int sicode, void __user *addr)
236 {
237 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
238
239 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
240 NOTIFY_STOP) {
241 cond_local_irq_enable(regs);
242 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
243 cond_local_irq_disable(regs);
244 }
245 }
246
247 /*
248 * Posix requires to provide the address of the faulting instruction for
249 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
250 *
251 * This address is usually regs->ip, but when an uprobe moved the code out
252 * of line then regs->ip points to the XOL code which would confuse
253 * anything which analyzes the fault address vs. the unmodified binary. If
254 * a trap happened in XOL code then uprobe maps regs->ip back to the
255 * original instruction address.
256 */
error_get_trap_addr(struct pt_regs * regs)257 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
258 {
259 return (void __user *)uprobe_get_trap_addr(regs);
260 }
261
DEFINE_IDTENTRY(exc_divide_error)262 DEFINE_IDTENTRY(exc_divide_error)
263 {
264 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE,
265 FPE_INTDIV, error_get_trap_addr(regs));
266 }
267
DEFINE_IDTENTRY(exc_overflow)268 DEFINE_IDTENTRY(exc_overflow)
269 {
270 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
271 }
272
273 #ifdef CONFIG_X86_F00F_BUG
handle_invalid_op(struct pt_regs * regs)274 void handle_invalid_op(struct pt_regs *regs)
275 #else
276 static inline void handle_invalid_op(struct pt_regs *regs)
277 #endif
278 {
279 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
280 ILL_ILLOPN, error_get_trap_addr(regs));
281 }
282
handle_bug(struct pt_regs * regs)283 static noinstr bool handle_bug(struct pt_regs *regs)
284 {
285 bool handled = false;
286 int ud_type, ud_len;
287 s32 ud_imm;
288
289 ud_type = decode_bug(regs->ip, &ud_imm, &ud_len);
290 if (ud_type == BUG_NONE)
291 return handled;
292
293 /*
294 * All lies, just get the WARN/BUG out.
295 */
296 instrumentation_begin();
297 /*
298 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug()
299 * is a rare case that uses @regs without passing them to
300 * irqentry_enter().
301 */
302 kmsan_unpoison_entry_regs(regs);
303 /*
304 * Since we're emulating a CALL with exceptions, restore the interrupt
305 * state to what it was at the exception site.
306 */
307 if (regs->flags & X86_EFLAGS_IF)
308 raw_local_irq_enable();
309
310 switch (ud_type) {
311 case BUG_UD2:
312 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN ||
313 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) {
314 regs->ip += ud_len;
315 handled = true;
316 }
317 break;
318
319 case BUG_UD1_UBSAN:
320 if (IS_ENABLED(CONFIG_UBSAN_TRAP)) {
321 pr_crit("%s at %pS\n",
322 report_ubsan_failure(regs, ud_imm),
323 (void *)regs->ip);
324 }
325 break;
326
327 default:
328 break;
329 }
330
331 if (regs->flags & X86_EFLAGS_IF)
332 raw_local_irq_disable();
333 instrumentation_end();
334
335 return handled;
336 }
337
DEFINE_IDTENTRY_RAW(exc_invalid_op)338 DEFINE_IDTENTRY_RAW(exc_invalid_op)
339 {
340 irqentry_state_t state;
341
342 /*
343 * We use UD2 as a short encoding for 'CALL __WARN', as such
344 * handle it before exception entry to avoid recursive WARN
345 * in case exception entry is the one triggering WARNs.
346 */
347 if (!user_mode(regs) && handle_bug(regs))
348 return;
349
350 state = irqentry_enter(regs);
351 instrumentation_begin();
352 handle_invalid_op(regs);
353 instrumentation_end();
354 irqentry_exit(regs, state);
355 }
356
DEFINE_IDTENTRY(exc_coproc_segment_overrun)357 DEFINE_IDTENTRY(exc_coproc_segment_overrun)
358 {
359 do_error_trap(regs, 0, "coprocessor segment overrun",
360 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
361 }
362
DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)363 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
364 {
365 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
366 0, NULL);
367 }
368
DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)369 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
370 {
371 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
372 SIGBUS, 0, NULL);
373 }
374
DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)375 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
376 {
377 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
378 0, NULL);
379 }
380
DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)381 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
382 {
383 char *str = "alignment check";
384
385 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
386 return;
387
388 if (!user_mode(regs))
389 die("Split lock detected\n", regs, error_code);
390
391 local_irq_enable();
392
393 if (handle_user_split_lock(regs, error_code))
394 goto out;
395
396 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
397 error_code, BUS_ADRALN, NULL);
398
399 out:
400 local_irq_disable();
401 }
402
403 #ifdef CONFIG_VMAP_STACK
handle_stack_overflow(struct pt_regs * regs,unsigned long fault_address,struct stack_info * info)404 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs,
405 unsigned long fault_address,
406 struct stack_info *info)
407 {
408 const char *name = stack_type_name(info->type);
409
410 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n",
411 name, (void *)fault_address, info->begin, info->end);
412
413 die("stack guard page", regs, 0);
414
415 /* Be absolutely certain we don't return. */
416 panic("%s stack guard hit", name);
417 }
418 #endif
419
420 /*
421 * Prevent the compiler and/or objtool from marking the !CONFIG_X86_ESPFIX64
422 * version of exc_double_fault() as noreturn. Otherwise the noreturn mismatch
423 * between configs triggers objtool warnings.
424 *
425 * This is a temporary hack until we have compiler or plugin support for
426 * annotating noreturns.
427 */
428 #ifdef CONFIG_X86_ESPFIX64
429 #define always_true() true
430 #else
431 bool always_true(void);
always_true(void)432 bool __weak always_true(void) { return true; }
433 #endif
434
435 /*
436 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
437 *
438 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
439 * SDM's warnings about double faults being unrecoverable, returning works as
440 * expected. Presumably what the SDM actually means is that the CPU may get
441 * the register state wrong on entry, so returning could be a bad idea.
442 *
443 * Various CPU engineers have promised that double faults due to an IRET fault
444 * while the stack is read-only are, in fact, recoverable.
445 *
446 * On x86_32, this is entered through a task gate, and regs are synthesized
447 * from the TSS. Returning is, in principle, okay, but changes to regs will
448 * be lost. If, for some reason, we need to return to a context with modified
449 * regs, the shim code could be adjusted to synchronize the registers.
450 *
451 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
452 * to be read before doing anything else.
453 */
DEFINE_IDTENTRY_DF(exc_double_fault)454 DEFINE_IDTENTRY_DF(exc_double_fault)
455 {
456 static const char str[] = "double fault";
457 struct task_struct *tsk = current;
458
459 #ifdef CONFIG_VMAP_STACK
460 unsigned long address = read_cr2();
461 struct stack_info info;
462 #endif
463
464 #ifdef CONFIG_X86_ESPFIX64
465 extern unsigned char native_irq_return_iret[];
466
467 /*
468 * If IRET takes a non-IST fault on the espfix64 stack, then we
469 * end up promoting it to a doublefault. In that case, take
470 * advantage of the fact that we're not using the normal (TSS.sp0)
471 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
472 * and then modify our own IRET frame so that, when we return,
473 * we land directly at the #GP(0) vector with the stack already
474 * set up according to its expectations.
475 *
476 * The net result is that our #GP handler will think that we
477 * entered from usermode with the bad user context.
478 *
479 * No need for nmi_enter() here because we don't use RCU.
480 */
481 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
482 regs->cs == __KERNEL_CS &&
483 regs->ip == (unsigned long)native_irq_return_iret)
484 {
485 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
486 unsigned long *p = (unsigned long *)regs->sp;
487
488 /*
489 * regs->sp points to the failing IRET frame on the
490 * ESPFIX64 stack. Copy it to the entry stack. This fills
491 * in gpregs->ss through gpregs->ip.
492 *
493 */
494 gpregs->ip = p[0];
495 gpregs->cs = p[1];
496 gpregs->flags = p[2];
497 gpregs->sp = p[3];
498 gpregs->ss = p[4];
499 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
500
501 /*
502 * Adjust our frame so that we return straight to the #GP
503 * vector with the expected RSP value. This is safe because
504 * we won't enable interrupts or schedule before we invoke
505 * general_protection, so nothing will clobber the stack
506 * frame we just set up.
507 *
508 * We will enter general_protection with kernel GSBASE,
509 * which is what the stub expects, given that the faulting
510 * RIP will be the IRET instruction.
511 */
512 regs->ip = (unsigned long)asm_exc_general_protection;
513 regs->sp = (unsigned long)&gpregs->orig_ax;
514
515 return;
516 }
517 #endif
518
519 irqentry_nmi_enter(regs);
520 instrumentation_begin();
521 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
522
523 tsk->thread.error_code = error_code;
524 tsk->thread.trap_nr = X86_TRAP_DF;
525
526 #ifdef CONFIG_VMAP_STACK
527 /*
528 * If we overflow the stack into a guard page, the CPU will fail
529 * to deliver #PF and will send #DF instead. Similarly, if we
530 * take any non-IST exception while too close to the bottom of
531 * the stack, the processor will get a page fault while
532 * delivering the exception and will generate a double fault.
533 *
534 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
535 * Page-Fault Exception (#PF):
536 *
537 * Processors update CR2 whenever a page fault is detected. If a
538 * second page fault occurs while an earlier page fault is being
539 * delivered, the faulting linear address of the second fault will
540 * overwrite the contents of CR2 (replacing the previous
541 * address). These updates to CR2 occur even if the page fault
542 * results in a double fault or occurs during the delivery of a
543 * double fault.
544 *
545 * The logic below has a small possibility of incorrectly diagnosing
546 * some errors as stack overflows. For example, if the IDT or GDT
547 * gets corrupted such that #GP delivery fails due to a bad descriptor
548 * causing #GP and we hit this condition while CR2 coincidentally
549 * points to the stack guard page, we'll think we overflowed the
550 * stack. Given that we're going to panic one way or another
551 * if this happens, this isn't necessarily worth fixing.
552 *
553 * If necessary, we could improve the test by only diagnosing
554 * a stack overflow if the saved RSP points within 47 bytes of
555 * the bottom of the stack: if RSP == tsk_stack + 48 and we
556 * take an exception, the stack is already aligned and there
557 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
558 * possible error code, so a stack overflow would *not* double
559 * fault. With any less space left, exception delivery could
560 * fail, and, as a practical matter, we've overflowed the
561 * stack even if the actual trigger for the double fault was
562 * something else.
563 */
564 if (get_stack_guard_info((void *)address, &info))
565 handle_stack_overflow(regs, address, &info);
566 #endif
567
568 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
569 die("double fault", regs, error_code);
570 if (always_true())
571 panic("Machine halted.");
572 instrumentation_end();
573 }
574
DEFINE_IDTENTRY(exc_bounds)575 DEFINE_IDTENTRY(exc_bounds)
576 {
577 if (notify_die(DIE_TRAP, "bounds", regs, 0,
578 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
579 return;
580 cond_local_irq_enable(regs);
581
582 if (!user_mode(regs))
583 die("bounds", regs, 0);
584
585 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
586
587 cond_local_irq_disable(regs);
588 }
589
590 enum kernel_gp_hint {
591 GP_NO_HINT,
592 GP_NON_CANONICAL,
593 GP_CANONICAL
594 };
595
596 /*
597 * When an uncaught #GP occurs, try to determine the memory address accessed by
598 * the instruction and return that address to the caller. Also, try to figure
599 * out whether any part of the access to that address was non-canonical.
600 */
get_kernel_gp_address(struct pt_regs * regs,unsigned long * addr)601 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
602 unsigned long *addr)
603 {
604 u8 insn_buf[MAX_INSN_SIZE];
605 struct insn insn;
606 int ret;
607
608 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
609 MAX_INSN_SIZE))
610 return GP_NO_HINT;
611
612 ret = insn_decode_kernel(&insn, insn_buf);
613 if (ret < 0)
614 return GP_NO_HINT;
615
616 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
617 if (*addr == -1UL)
618 return GP_NO_HINT;
619
620 #ifdef CONFIG_X86_64
621 /*
622 * Check that:
623 * - the operand is not in the kernel half
624 * - the last byte of the operand is not in the user canonical half
625 */
626 if (*addr < ~__VIRTUAL_MASK &&
627 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
628 return GP_NON_CANONICAL;
629 #endif
630
631 return GP_CANONICAL;
632 }
633
634 #define GPFSTR "general protection fault"
635
fixup_iopl_exception(struct pt_regs * regs)636 static bool fixup_iopl_exception(struct pt_regs *regs)
637 {
638 struct thread_struct *t = ¤t->thread;
639 unsigned char byte;
640 unsigned long ip;
641
642 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3)
643 return false;
644
645 if (insn_get_effective_ip(regs, &ip))
646 return false;
647
648 if (get_user(byte, (const char __user *)ip))
649 return false;
650
651 if (byte != 0xfa && byte != 0xfb)
652 return false;
653
654 if (!t->iopl_warn && printk_ratelimit()) {
655 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx",
656 current->comm, task_pid_nr(current), ip);
657 print_vma_addr(KERN_CONT " in ", ip);
658 pr_cont("\n");
659 t->iopl_warn = 1;
660 }
661
662 regs->ip += 1;
663 return true;
664 }
665
666 /*
667 * The unprivileged ENQCMD instruction generates #GPs if the
668 * IA32_PASID MSR has not been populated. If possible, populate
669 * the MSR from a PASID previously allocated to the mm.
670 */
try_fixup_enqcmd_gp(void)671 static bool try_fixup_enqcmd_gp(void)
672 {
673 #ifdef CONFIG_ARCH_HAS_CPU_PASID
674 u32 pasid;
675
676 /*
677 * MSR_IA32_PASID is managed using XSAVE. Directly
678 * writing to the MSR is only possible when fpregs
679 * are valid and the fpstate is not. This is
680 * guaranteed when handling a userspace exception
681 * in *before* interrupts are re-enabled.
682 */
683 lockdep_assert_irqs_disabled();
684
685 /*
686 * Hardware without ENQCMD will not generate
687 * #GPs that can be fixed up here.
688 */
689 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
690 return false;
691
692 /*
693 * If the mm has not been allocated a
694 * PASID, the #GP can not be fixed up.
695 */
696 if (!mm_valid_pasid(current->mm))
697 return false;
698
699 pasid = mm_get_enqcmd_pasid(current->mm);
700
701 /*
702 * Did this thread already have its PASID activated?
703 * If so, the #GP must be from something else.
704 */
705 if (current->pasid_activated)
706 return false;
707
708 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);
709 current->pasid_activated = 1;
710
711 return true;
712 #else
713 return false;
714 #endif
715 }
716
gp_try_fixup_and_notify(struct pt_regs * regs,int trapnr,unsigned long error_code,const char * str,unsigned long address)717 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr,
718 unsigned long error_code, const char *str,
719 unsigned long address)
720 {
721 if (fixup_exception(regs, trapnr, error_code, address))
722 return true;
723
724 current->thread.error_code = error_code;
725 current->thread.trap_nr = trapnr;
726
727 /*
728 * To be potentially processing a kprobe fault and to trust the result
729 * from kprobe_running(), we have to be non-preemptible.
730 */
731 if (!preemptible() && kprobe_running() &&
732 kprobe_fault_handler(regs, trapnr))
733 return true;
734
735 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP;
736 }
737
gp_user_force_sig_segv(struct pt_regs * regs,int trapnr,unsigned long error_code,const char * str)738 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr,
739 unsigned long error_code, const char *str)
740 {
741 current->thread.error_code = error_code;
742 current->thread.trap_nr = trapnr;
743 show_signal(current, SIGSEGV, "", str, regs, error_code);
744 force_sig(SIGSEGV);
745 }
746
DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)747 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
748 {
749 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
750 enum kernel_gp_hint hint = GP_NO_HINT;
751 unsigned long gp_addr;
752
753 if (user_mode(regs) && try_fixup_enqcmd_gp())
754 return;
755
756 cond_local_irq_enable(regs);
757
758 if (static_cpu_has(X86_FEATURE_UMIP)) {
759 if (user_mode(regs) && fixup_umip_exception(regs))
760 goto exit;
761 }
762
763 if (v8086_mode(regs)) {
764 local_irq_enable();
765 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
766 local_irq_disable();
767 return;
768 }
769
770 if (user_mode(regs)) {
771 if (fixup_iopl_exception(regs))
772 goto exit;
773
774 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0))
775 goto exit;
776
777 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc);
778 goto exit;
779 }
780
781 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0))
782 goto exit;
783
784 if (error_code)
785 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
786 else
787 hint = get_kernel_gp_address(regs, &gp_addr);
788
789 if (hint != GP_NO_HINT)
790 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
791 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
792 : "maybe for address",
793 gp_addr);
794
795 /*
796 * KASAN is interested only in the non-canonical case, clear it
797 * otherwise.
798 */
799 if (hint != GP_NON_CANONICAL)
800 gp_addr = 0;
801
802 die_addr(desc, regs, error_code, gp_addr);
803
804 exit:
805 cond_local_irq_disable(regs);
806 }
807
do_int3(struct pt_regs * regs)808 static bool do_int3(struct pt_regs *regs)
809 {
810 int res;
811
812 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
813 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
814 SIGTRAP) == NOTIFY_STOP)
815 return true;
816 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
817
818 #ifdef CONFIG_KPROBES
819 if (kprobe_int3_handler(regs))
820 return true;
821 #endif
822 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
823
824 return res == NOTIFY_STOP;
825 }
826 NOKPROBE_SYMBOL(do_int3);
827
do_int3_user(struct pt_regs * regs)828 static void do_int3_user(struct pt_regs *regs)
829 {
830 if (do_int3(regs))
831 return;
832
833 cond_local_irq_enable(regs);
834 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
835 cond_local_irq_disable(regs);
836 }
837
DEFINE_IDTENTRY_RAW(exc_int3)838 DEFINE_IDTENTRY_RAW(exc_int3)
839 {
840 /*
841 * poke_int3_handler() is completely self contained code; it does (and
842 * must) *NOT* call out to anything, lest it hits upon yet another
843 * INT3.
844 */
845 if (poke_int3_handler(regs))
846 return;
847
848 /*
849 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
850 * and therefore can trigger INT3, hence poke_int3_handler() must
851 * be done before. If the entry came from kernel mode, then use
852 * nmi_enter() because the INT3 could have been hit in any context
853 * including NMI.
854 */
855 if (user_mode(regs)) {
856 irqentry_enter_from_user_mode(regs);
857 instrumentation_begin();
858 do_int3_user(regs);
859 instrumentation_end();
860 irqentry_exit_to_user_mode(regs);
861 } else {
862 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
863
864 instrumentation_begin();
865 if (!do_int3(regs))
866 die("int3", regs, 0);
867 instrumentation_end();
868 irqentry_nmi_exit(regs, irq_state);
869 }
870 }
871
872 #ifdef CONFIG_X86_64
873 /*
874 * Help handler running on a per-cpu (IST or entry trampoline) stack
875 * to switch to the normal thread stack if the interrupted code was in
876 * user mode. The actual stack switch is done in entry_64.S
877 */
sync_regs(struct pt_regs * eregs)878 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
879 {
880 struct pt_regs *regs = (struct pt_regs *)current_top_of_stack() - 1;
881 if (regs != eregs)
882 *regs = *eregs;
883 return regs;
884 }
885
886 #ifdef CONFIG_AMD_MEM_ENCRYPT
vc_switch_off_ist(struct pt_regs * regs)887 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs)
888 {
889 unsigned long sp, *stack;
890 struct stack_info info;
891 struct pt_regs *regs_ret;
892
893 /*
894 * In the SYSCALL entry path the RSP value comes from user-space - don't
895 * trust it and switch to the current kernel stack
896 */
897 if (ip_within_syscall_gap(regs)) {
898 sp = current_top_of_stack();
899 goto sync;
900 }
901
902 /*
903 * From here on the RSP value is trusted. Now check whether entry
904 * happened from a safe stack. Not safe are the entry or unknown stacks,
905 * use the fall-back stack instead in this case.
906 */
907 sp = regs->sp;
908 stack = (unsigned long *)sp;
909
910 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY ||
911 info.type > STACK_TYPE_EXCEPTION_LAST)
912 sp = __this_cpu_ist_top_va(VC2);
913
914 sync:
915 /*
916 * Found a safe stack - switch to it as if the entry didn't happen via
917 * IST stack. The code below only copies pt_regs, the real switch happens
918 * in assembly code.
919 */
920 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret);
921
922 regs_ret = (struct pt_regs *)sp;
923 *regs_ret = *regs;
924
925 return regs_ret;
926 }
927 #endif
928
fixup_bad_iret(struct pt_regs * bad_regs)929 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs)
930 {
931 struct pt_regs tmp, *new_stack;
932
933 /*
934 * This is called from entry_64.S early in handling a fault
935 * caused by a bad iret to user mode. To handle the fault
936 * correctly, we want to move our stack frame to where it would
937 * be had we entered directly on the entry stack (rather than
938 * just below the IRET frame) and we want to pretend that the
939 * exception came from the IRET target.
940 */
941 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
942
943 /* Copy the IRET target to the temporary storage. */
944 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8);
945
946 /* Copy the remainder of the stack from the current stack. */
947 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip));
948
949 /* Update the entry stack */
950 __memcpy(new_stack, &tmp, sizeof(tmp));
951
952 BUG_ON(!user_mode(new_stack));
953 return new_stack;
954 }
955 #endif
956
is_sysenter_singlestep(struct pt_regs * regs)957 static bool is_sysenter_singlestep(struct pt_regs *regs)
958 {
959 /*
960 * We don't try for precision here. If we're anywhere in the region of
961 * code that can be single-stepped in the SYSENTER entry path, then
962 * assume that this is a useless single-step trap due to SYSENTER
963 * being invoked with TF set. (We don't know in advance exactly
964 * which instructions will be hit because BTF could plausibly
965 * be set.)
966 */
967 #ifdef CONFIG_X86_32
968 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
969 (unsigned long)__end_SYSENTER_singlestep_region -
970 (unsigned long)__begin_SYSENTER_singlestep_region;
971 #elif defined(CONFIG_IA32_EMULATION)
972 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
973 (unsigned long)__end_entry_SYSENTER_compat -
974 (unsigned long)entry_SYSENTER_compat;
975 #else
976 return false;
977 #endif
978 }
979
debug_read_reset_dr6(void)980 static __always_inline unsigned long debug_read_reset_dr6(void)
981 {
982 unsigned long dr6;
983
984 get_debugreg(dr6, 6);
985 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */
986
987 /*
988 * The Intel SDM says:
989 *
990 * Certain debug exceptions may clear bits 0-3 of DR6.
991 *
992 * BLD induced #DB clears DR6.BLD and any other debug
993 * exception doesn't modify DR6.BLD.
994 *
995 * RTM induced #DB clears DR6.RTM and any other debug
996 * exception sets DR6.RTM.
997 *
998 * To avoid confusion in identifying debug exceptions,
999 * debug handlers should set DR6.BLD and DR6.RTM, and
1000 * clear other DR6 bits before returning.
1001 *
1002 * Keep it simple: write DR6 with its architectural reset
1003 * value 0xFFFF0FF0, defined as DR6_RESERVED, immediately.
1004 */
1005 set_debugreg(DR6_RESERVED, 6);
1006
1007 return dr6;
1008 }
1009
1010 /*
1011 * Our handling of the processor debug registers is non-trivial.
1012 * We do not clear them on entry and exit from the kernel. Therefore
1013 * it is possible to get a watchpoint trap here from inside the kernel.
1014 * However, the code in ./ptrace.c has ensured that the user can
1015 * only set watchpoints on userspace addresses. Therefore the in-kernel
1016 * watchpoint trap can only occur in code which is reading/writing
1017 * from user space. Such code must not hold kernel locks (since it
1018 * can equally take a page fault), therefore it is safe to call
1019 * force_sig_info even though that claims and releases locks.
1020 *
1021 * Code in ./signal.c ensures that the debug control register
1022 * is restored before we deliver any signal, and therefore that
1023 * user code runs with the correct debug control register even though
1024 * we clear it here.
1025 *
1026 * Being careful here means that we don't have to be as careful in a
1027 * lot of more complicated places (task switching can be a bit lazy
1028 * about restoring all the debug state, and ptrace doesn't have to
1029 * find every occurrence of the TF bit that could be saved away even
1030 * by user code)
1031 *
1032 * May run on IST stack.
1033 */
1034
notify_debug(struct pt_regs * regs,unsigned long * dr6)1035 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6)
1036 {
1037 /*
1038 * Notifiers will clear bits in @dr6 to indicate the event has been
1039 * consumed - hw_breakpoint_handler(), single_stop_cont().
1040 *
1041 * Notifiers will set bits in @virtual_dr6 to indicate the desire
1042 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler().
1043 */
1044 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP)
1045 return true;
1046
1047 return false;
1048 }
1049
exc_debug_kernel(struct pt_regs * regs,unsigned long dr6)1050 static noinstr void exc_debug_kernel(struct pt_regs *regs, unsigned long dr6)
1051 {
1052 /*
1053 * Disable breakpoints during exception handling; recursive exceptions
1054 * are exceedingly 'fun'.
1055 *
1056 * Since this function is NOKPROBE, and that also applies to
1057 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
1058 * HW_BREAKPOINT_W on our stack)
1059 *
1060 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
1061 * includes the entry stack is excluded for everything.
1062 *
1063 * For FRED, nested #DB should just work fine. But when a watchpoint or
1064 * breakpoint is set in the code path which is executed by #DB handler,
1065 * it results in an endless recursion and stack overflow. Thus we stay
1066 * with the IDT approach, i.e., save DR7 and disable #DB.
1067 */
1068 unsigned long dr7 = local_db_save();
1069 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
1070 instrumentation_begin();
1071
1072 /*
1073 * If something gets miswired and we end up here for a user mode
1074 * #DB, we will malfunction.
1075 */
1076 WARN_ON_ONCE(user_mode(regs));
1077
1078 if (test_thread_flag(TIF_BLOCKSTEP)) {
1079 /*
1080 * The SDM says "The processor clears the BTF flag when it
1081 * generates a debug exception." but PTRACE_BLOCKSTEP requested
1082 * it for userspace, but we just took a kernel #DB, so re-set
1083 * BTF.
1084 */
1085 unsigned long debugctl;
1086
1087 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1088 debugctl |= DEBUGCTLMSR_BTF;
1089 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1090 }
1091
1092 /*
1093 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
1094 * watchpoint at the same time then that will still be handled.
1095 */
1096 if (!cpu_feature_enabled(X86_FEATURE_FRED) &&
1097 (dr6 & DR_STEP) && is_sysenter_singlestep(regs))
1098 dr6 &= ~DR_STEP;
1099
1100 /*
1101 * The kernel doesn't use INT1
1102 */
1103 if (!dr6)
1104 goto out;
1105
1106 if (notify_debug(regs, &dr6))
1107 goto out;
1108
1109 /*
1110 * The kernel doesn't use TF single-step outside of:
1111 *
1112 * - Kprobes, consumed through kprobe_debug_handler()
1113 * - KGDB, consumed through notify_debug()
1114 *
1115 * So if we get here with DR_STEP set, something is wonky.
1116 *
1117 * A known way to trigger this is through QEMU's GDB stub,
1118 * which leaks #DB into the guest and causes IST recursion.
1119 */
1120 if (WARN_ON_ONCE(dr6 & DR_STEP))
1121 regs->flags &= ~X86_EFLAGS_TF;
1122 out:
1123 instrumentation_end();
1124 irqentry_nmi_exit(regs, irq_state);
1125
1126 local_db_restore(dr7);
1127 }
1128
exc_debug_user(struct pt_regs * regs,unsigned long dr6)1129 static noinstr void exc_debug_user(struct pt_regs *regs, unsigned long dr6)
1130 {
1131 bool icebp;
1132
1133 /*
1134 * If something gets miswired and we end up here for a kernel mode
1135 * #DB, we will malfunction.
1136 */
1137 WARN_ON_ONCE(!user_mode(regs));
1138
1139 /*
1140 * NB: We can't easily clear DR7 here because
1141 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access
1142 * user memory, etc. This means that a recursive #DB is possible. If
1143 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
1144 * Since we're not on the IST stack right now, everything will be
1145 * fine.
1146 */
1147
1148 irqentry_enter_from_user_mode(regs);
1149 instrumentation_begin();
1150
1151 /*
1152 * Start the virtual/ptrace DR6 value with just the DR_STEP mask
1153 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits.
1154 *
1155 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6)
1156 * even if it is not the result of PTRACE_SINGLESTEP.
1157 */
1158 current->thread.virtual_dr6 = (dr6 & DR_STEP);
1159
1160 /*
1161 * The SDM says "The processor clears the BTF flag when it
1162 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
1163 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
1164 */
1165 clear_thread_flag(TIF_BLOCKSTEP);
1166
1167 /*
1168 * If dr6 has no reason to give us about the origin of this trap,
1169 * then it's very likely the result of an icebp/int01 trap.
1170 * User wants a sigtrap for that.
1171 */
1172 icebp = !dr6;
1173
1174 if (notify_debug(regs, &dr6))
1175 goto out;
1176
1177 /* It's safe to allow irq's after DR6 has been saved */
1178 local_irq_enable();
1179
1180 if (v8086_mode(regs)) {
1181 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB);
1182 goto out_irq;
1183 }
1184
1185 /* #DB for bus lock can only be triggered from userspace. */
1186 if (dr6 & DR_BUS_LOCK)
1187 handle_bus_lock(regs);
1188
1189 /* Add the virtual_dr6 bits for signals. */
1190 dr6 |= current->thread.virtual_dr6;
1191 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp)
1192 send_sigtrap(regs, 0, get_si_code(dr6));
1193
1194 out_irq:
1195 local_irq_disable();
1196 out:
1197 instrumentation_end();
1198 irqentry_exit_to_user_mode(regs);
1199 }
1200
1201 #ifdef CONFIG_X86_64
1202 /* IST stack entry */
DEFINE_IDTENTRY_DEBUG(exc_debug)1203 DEFINE_IDTENTRY_DEBUG(exc_debug)
1204 {
1205 exc_debug_kernel(regs, debug_read_reset_dr6());
1206 }
1207
1208 /* User entry, runs on regular task stack */
DEFINE_IDTENTRY_DEBUG_USER(exc_debug)1209 DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
1210 {
1211 exc_debug_user(regs, debug_read_reset_dr6());
1212 }
1213
1214 #ifdef CONFIG_X86_FRED
1215 /*
1216 * When occurred on different ring level, i.e., from user or kernel
1217 * context, #DB needs to be handled on different stack: User #DB on
1218 * current task stack, while kernel #DB on a dedicated stack.
1219 *
1220 * This is exactly how FRED event delivery invokes an exception
1221 * handler: ring 3 event on level 0 stack, i.e., current task stack;
1222 * ring 0 event on the #DB dedicated stack specified in the
1223 * IA32_FRED_STKLVLS MSR. So unlike IDT, the FRED debug exception
1224 * entry stub doesn't do stack switch.
1225 */
DEFINE_FREDENTRY_DEBUG(exc_debug)1226 DEFINE_FREDENTRY_DEBUG(exc_debug)
1227 {
1228 /*
1229 * FRED #DB stores DR6 on the stack in the format which
1230 * debug_read_reset_dr6() returns for the IDT entry points.
1231 */
1232 unsigned long dr6 = fred_event_data(regs);
1233
1234 if (user_mode(regs))
1235 exc_debug_user(regs, dr6);
1236 else
1237 exc_debug_kernel(regs, dr6);
1238 }
1239 #endif /* CONFIG_X86_FRED */
1240
1241 #else
1242 /* 32 bit does not have separate entry points. */
DEFINE_IDTENTRY_RAW(exc_debug)1243 DEFINE_IDTENTRY_RAW(exc_debug)
1244 {
1245 unsigned long dr6 = debug_read_reset_dr6();
1246
1247 if (user_mode(regs))
1248 exc_debug_user(regs, dr6);
1249 else
1250 exc_debug_kernel(regs, dr6);
1251 }
1252 #endif
1253
1254 /*
1255 * Note that we play around with the 'TS' bit in an attempt to get
1256 * the correct behaviour even in the presence of the asynchronous
1257 * IRQ13 behaviour
1258 */
math_error(struct pt_regs * regs,int trapnr)1259 static void math_error(struct pt_regs *regs, int trapnr)
1260 {
1261 struct task_struct *task = current;
1262 struct fpu *fpu = &task->thread.fpu;
1263 int si_code;
1264 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
1265 "simd exception";
1266
1267 cond_local_irq_enable(regs);
1268
1269 if (!user_mode(regs)) {
1270 if (fixup_exception(regs, trapnr, 0, 0))
1271 goto exit;
1272
1273 task->thread.error_code = 0;
1274 task->thread.trap_nr = trapnr;
1275
1276 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
1277 SIGFPE) != NOTIFY_STOP)
1278 die(str, regs, 0);
1279 goto exit;
1280 }
1281
1282 /*
1283 * Synchronize the FPU register state to the memory register state
1284 * if necessary. This allows the exception handler to inspect it.
1285 */
1286 fpu_sync_fpstate(fpu);
1287
1288 task->thread.trap_nr = trapnr;
1289 task->thread.error_code = 0;
1290
1291 si_code = fpu__exception_code(fpu, trapnr);
1292 /* Retry when we get spurious exceptions: */
1293 if (!si_code)
1294 goto exit;
1295
1296 if (fixup_vdso_exception(regs, trapnr, 0, 0))
1297 goto exit;
1298
1299 force_sig_fault(SIGFPE, si_code,
1300 (void __user *)uprobe_get_trap_addr(regs));
1301 exit:
1302 cond_local_irq_disable(regs);
1303 }
1304
DEFINE_IDTENTRY(exc_coprocessor_error)1305 DEFINE_IDTENTRY(exc_coprocessor_error)
1306 {
1307 math_error(regs, X86_TRAP_MF);
1308 }
1309
DEFINE_IDTENTRY(exc_simd_coprocessor_error)1310 DEFINE_IDTENTRY(exc_simd_coprocessor_error)
1311 {
1312 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
1313 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
1314 if (!static_cpu_has(X86_FEATURE_XMM)) {
1315 __exc_general_protection(regs, 0);
1316 return;
1317 }
1318 }
1319 math_error(regs, X86_TRAP_XF);
1320 }
1321
DEFINE_IDTENTRY(exc_spurious_interrupt_bug)1322 DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1323 {
1324 /*
1325 * This addresses a Pentium Pro Erratum:
1326 *
1327 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1328 * Virtual Wire mode implemented through the local APIC, an
1329 * interrupt vector of 0Fh (Intel reserved encoding) may be
1330 * generated by the local APIC (Int 15). This vector may be
1331 * generated upon receipt of a spurious interrupt (an interrupt
1332 * which is removed before the system receives the INTA sequence)
1333 * instead of the programmed 8259 spurious interrupt vector.
1334 *
1335 * IMPLICATION: The spurious interrupt vector programmed in the
1336 * 8259 is normally handled by an operating system's spurious
1337 * interrupt handler. However, a vector of 0Fh is unknown to some
1338 * operating systems, which would crash if this erratum occurred.
1339 *
1340 * In theory this could be limited to 32bit, but the handler is not
1341 * hurting and who knows which other CPUs suffer from this.
1342 */
1343 }
1344
handle_xfd_event(struct pt_regs * regs)1345 static bool handle_xfd_event(struct pt_regs *regs)
1346 {
1347 u64 xfd_err;
1348 int err;
1349
1350 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD))
1351 return false;
1352
1353 rdmsrl(MSR_IA32_XFD_ERR, xfd_err);
1354 if (!xfd_err)
1355 return false;
1356
1357 wrmsrl(MSR_IA32_XFD_ERR, 0);
1358
1359 /* Die if that happens in kernel space */
1360 if (WARN_ON(!user_mode(regs)))
1361 return false;
1362
1363 local_irq_enable();
1364
1365 err = xfd_enable_feature(xfd_err);
1366
1367 switch (err) {
1368 case -EPERM:
1369 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs));
1370 break;
1371 case -EFAULT:
1372 force_sig(SIGSEGV);
1373 break;
1374 }
1375
1376 local_irq_disable();
1377 return true;
1378 }
1379
DEFINE_IDTENTRY(exc_device_not_available)1380 DEFINE_IDTENTRY(exc_device_not_available)
1381 {
1382 unsigned long cr0 = read_cr0();
1383
1384 if (handle_xfd_event(regs))
1385 return;
1386
1387 #ifdef CONFIG_MATH_EMULATION
1388 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1389 struct math_emu_info info = { };
1390
1391 cond_local_irq_enable(regs);
1392
1393 info.regs = regs;
1394 math_emulate(&info);
1395
1396 cond_local_irq_disable(regs);
1397 return;
1398 }
1399 #endif
1400
1401 /* This should not happen. */
1402 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1403 /* Try to fix it up and carry on. */
1404 write_cr0(cr0 & ~X86_CR0_TS);
1405 } else {
1406 /*
1407 * Something terrible happened, and we're better off trying
1408 * to kill the task than getting stuck in a never-ending
1409 * loop of #NM faults.
1410 */
1411 die("unexpected #NM exception", regs, 0);
1412 }
1413 }
1414
1415 #ifdef CONFIG_INTEL_TDX_GUEST
1416
1417 #define VE_FAULT_STR "VE fault"
1418
ve_raise_fault(struct pt_regs * regs,long error_code,unsigned long address)1419 static void ve_raise_fault(struct pt_regs *regs, long error_code,
1420 unsigned long address)
1421 {
1422 if (user_mode(regs)) {
1423 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR);
1424 return;
1425 }
1426
1427 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code,
1428 VE_FAULT_STR, address)) {
1429 return;
1430 }
1431
1432 die_addr(VE_FAULT_STR, regs, error_code, address);
1433 }
1434
1435 /*
1436 * Virtualization Exceptions (#VE) are delivered to TDX guests due to
1437 * specific guest actions which may happen in either user space or the
1438 * kernel:
1439 *
1440 * * Specific instructions (WBINVD, for example)
1441 * * Specific MSR accesses
1442 * * Specific CPUID leaf accesses
1443 * * Access to specific guest physical addresses
1444 *
1445 * In the settings that Linux will run in, virtualization exceptions are
1446 * never generated on accesses to normal, TD-private memory that has been
1447 * accepted (by BIOS or with tdx_enc_status_changed()).
1448 *
1449 * Syscall entry code has a critical window where the kernel stack is not
1450 * yet set up. Any exception in this window leads to hard to debug issues
1451 * and can be exploited for privilege escalation. Exceptions in the NMI
1452 * entry code also cause issues. Returning from the exception handler with
1453 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack.
1454 *
1455 * For these reasons, the kernel avoids #VEs during the syscall gap and
1456 * the NMI entry code. Entry code paths do not access TD-shared memory,
1457 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves
1458 * that might generate #VE. VMM can remove memory from TD at any point,
1459 * but access to unaccepted (or missing) private memory leads to VM
1460 * termination, not to #VE.
1461 *
1462 * Similarly to page faults and breakpoints, #VEs are allowed in NMI
1463 * handlers once the kernel is ready to deal with nested NMIs.
1464 *
1465 * During #VE delivery, all interrupts, including NMIs, are blocked until
1466 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads
1467 * the VE info.
1468 *
1469 * If a guest kernel action which would normally cause a #VE occurs in
1470 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault
1471 * exception) is delivered to the guest which will result in an oops.
1472 *
1473 * The entry code has been audited carefully for following these expectations.
1474 * Changes in the entry code have to be audited for correctness vs. this
1475 * aspect. Similarly to #PF, #VE in these places will expose kernel to
1476 * privilege escalation or may lead to random crashes.
1477 */
DEFINE_IDTENTRY(exc_virtualization_exception)1478 DEFINE_IDTENTRY(exc_virtualization_exception)
1479 {
1480 struct ve_info ve;
1481
1482 /*
1483 * NMIs/Machine-checks/Interrupts will be in a disabled state
1484 * till TDGETVEINFO TDCALL is executed. This ensures that VE
1485 * info cannot be overwritten by a nested #VE.
1486 */
1487 tdx_get_ve_info(&ve);
1488
1489 cond_local_irq_enable(regs);
1490
1491 /*
1492 * If tdx_handle_virt_exception() could not process
1493 * it successfully, treat it as #GP(0) and handle it.
1494 */
1495 if (!tdx_handle_virt_exception(regs, &ve))
1496 ve_raise_fault(regs, 0, ve.gla);
1497
1498 cond_local_irq_disable(regs);
1499 }
1500
1501 #endif
1502
1503 #ifdef CONFIG_X86_32
DEFINE_IDTENTRY_SW(iret_error)1504 DEFINE_IDTENTRY_SW(iret_error)
1505 {
1506 local_irq_enable();
1507 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1508 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1509 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1510 ILL_BADSTK, (void __user *)NULL);
1511 }
1512 local_irq_disable();
1513 }
1514 #endif
1515
trap_init(void)1516 void __init trap_init(void)
1517 {
1518 /* Init cpu_entry_area before IST entries are set up */
1519 setup_cpu_entry_areas();
1520
1521 /* Init GHCB memory pages when running as an SEV-ES guest */
1522 sev_es_init_vc_handling();
1523
1524 /* Initialize TSS before setting up traps so ISTs work */
1525 cpu_init_exception_handling(true);
1526
1527 /* Setup traps as cpu_init() might #GP */
1528 if (!cpu_feature_enabled(X86_FEATURE_FRED))
1529 idt_setup_traps();
1530
1531 cpu_init();
1532 }
1533