1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020-2025 Intel Corporation
4 */
5
6 #include <linux/firmware.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/pm_runtime.h>
10
11 #include <drm/drm_accel.h>
12 #include <drm/drm_file.h>
13 #include <drm/drm_gem.h>
14 #include <drm/drm_ioctl.h>
15 #include <drm/drm_prime.h>
16
17 #include "ivpu_coredump.h"
18 #include "ivpu_debugfs.h"
19 #include "ivpu_drv.h"
20 #include "ivpu_fw.h"
21 #include "ivpu_fw_log.h"
22 #include "ivpu_gem.h"
23 #include "ivpu_hw.h"
24 #include "ivpu_ipc.h"
25 #include "ivpu_job.h"
26 #include "ivpu_jsm_msg.h"
27 #include "ivpu_mmu.h"
28 #include "ivpu_mmu_context.h"
29 #include "ivpu_ms.h"
30 #include "ivpu_pm.h"
31 #include "ivpu_sysfs.h"
32 #include "vpu_boot_api.h"
33
34 #ifndef DRIVER_VERSION_STR
35 #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
36 __stringify(DRM_IVPU_DRIVER_MINOR) "."
37 #endif
38
39 int ivpu_dbg_mask;
40 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
41 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
42
43 int ivpu_test_mode;
44 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
45 MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
46
47 u8 ivpu_pll_min_ratio;
48 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
49 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set NPU frequency");
50
51 u8 ivpu_pll_max_ratio = U8_MAX;
52 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
53 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
54
55 int ivpu_sched_mode = IVPU_SCHED_MODE_AUTO;
56 module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
57 MODULE_PARM_DESC(sched_mode, "Scheduler mode: -1 - Use default scheduler, 0 - Use OS scheduler, 1 - Use HW scheduler");
58
59 bool ivpu_disable_mmu_cont_pages;
60 module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
61 MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
62
63 bool ivpu_force_snoop;
64 module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);
65 MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");
66
ivpu_file_priv_get(struct ivpu_file_priv * file_priv)67 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
68 {
69 struct ivpu_device *vdev = file_priv->vdev;
70
71 kref_get(&file_priv->ref);
72
73 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
74 file_priv->ctx.id, kref_read(&file_priv->ref));
75
76 return file_priv;
77 }
78
file_priv_unbind(struct ivpu_device * vdev,struct ivpu_file_priv * file_priv)79 static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv)
80 {
81 mutex_lock(&file_priv->lock);
82 if (file_priv->bound) {
83 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
84
85 ivpu_cmdq_release_all_locked(file_priv);
86 ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
87 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
88 file_priv->bound = false;
89 drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id));
90 }
91 mutex_unlock(&file_priv->lock);
92 }
93
file_priv_release(struct kref * ref)94 static void file_priv_release(struct kref *ref)
95 {
96 struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
97 struct ivpu_device *vdev = file_priv->vdev;
98
99 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n",
100 file_priv->ctx.id, (bool)file_priv->bound);
101
102 pm_runtime_get_sync(vdev->drm.dev);
103 mutex_lock(&vdev->context_list_lock);
104 file_priv_unbind(vdev, file_priv);
105 drm_WARN_ON(&vdev->drm, !xa_empty(&file_priv->cmdq_xa));
106 xa_destroy(&file_priv->cmdq_xa);
107 mutex_unlock(&vdev->context_list_lock);
108 pm_runtime_put_autosuspend(vdev->drm.dev);
109
110 mutex_destroy(&file_priv->ms_lock);
111 mutex_destroy(&file_priv->lock);
112 kfree(file_priv);
113 }
114
ivpu_file_priv_put(struct ivpu_file_priv ** link)115 void ivpu_file_priv_put(struct ivpu_file_priv **link)
116 {
117 struct ivpu_file_priv *file_priv = *link;
118 struct ivpu_device *vdev = file_priv->vdev;
119
120 drm_WARN_ON(&vdev->drm, !file_priv);
121
122 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
123 file_priv->ctx.id, kref_read(&file_priv->ref));
124
125 *link = NULL;
126 kref_put(&file_priv->ref, file_priv_release);
127 }
128
ivpu_get_capabilities(struct ivpu_device * vdev,struct drm_ivpu_param * args)129 static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param *args)
130 {
131 switch (args->index) {
132 case DRM_IVPU_CAP_METRIC_STREAMER:
133 args->value = 1;
134 break;
135 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
136 args->value = 1;
137 break;
138 default:
139 return -EINVAL;
140 }
141
142 return 0;
143 }
144
ivpu_get_param_ioctl(struct drm_device * dev,void * data,struct drm_file * file)145 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
146 {
147 struct ivpu_file_priv *file_priv = file->driver_priv;
148 struct ivpu_device *vdev = file_priv->vdev;
149 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
150 struct drm_ivpu_param *args = data;
151 int ret = 0;
152 int idx;
153
154 if (!drm_dev_enter(dev, &idx))
155 return -ENODEV;
156
157 switch (args->param) {
158 case DRM_IVPU_PARAM_DEVICE_ID:
159 args->value = pdev->device;
160 break;
161 case DRM_IVPU_PARAM_DEVICE_REVISION:
162 args->value = pdev->revision;
163 break;
164 case DRM_IVPU_PARAM_PLATFORM_TYPE:
165 args->value = vdev->platform;
166 break;
167 case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
168 args->value = ivpu_hw_dpu_max_freq_get(vdev);
169 break;
170 case DRM_IVPU_PARAM_NUM_CONTEXTS:
171 args->value = ivpu_get_context_count(vdev);
172 break;
173 case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
174 args->value = vdev->hw->ranges.user.start;
175 break;
176 case DRM_IVPU_PARAM_CONTEXT_ID:
177 args->value = file_priv->ctx.id;
178 break;
179 case DRM_IVPU_PARAM_FW_API_VERSION:
180 if (args->index < VPU_FW_API_VER_NUM) {
181 struct vpu_firmware_header *fw_hdr;
182
183 fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
184 args->value = fw_hdr->api_version[args->index];
185 } else {
186 ret = -EINVAL;
187 }
188 break;
189 case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
190 ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
191 break;
192 case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
193 args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
194 break;
195 case DRM_IVPU_PARAM_TILE_CONFIG:
196 args->value = vdev->hw->tile_fuse;
197 break;
198 case DRM_IVPU_PARAM_SKU:
199 args->value = vdev->hw->sku;
200 break;
201 case DRM_IVPU_PARAM_CAPABILITIES:
202 ret = ivpu_get_capabilities(vdev, args);
203 break;
204 default:
205 ret = -EINVAL;
206 break;
207 }
208
209 drm_dev_exit(idx);
210 return ret;
211 }
212
ivpu_set_param_ioctl(struct drm_device * dev,void * data,struct drm_file * file)213 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
214 {
215 struct drm_ivpu_param *args = data;
216 int ret = 0;
217
218 switch (args->param) {
219 default:
220 ret = -EINVAL;
221 }
222
223 return ret;
224 }
225
ivpu_open(struct drm_device * dev,struct drm_file * file)226 static int ivpu_open(struct drm_device *dev, struct drm_file *file)
227 {
228 struct ivpu_device *vdev = to_ivpu_device(dev);
229 struct ivpu_file_priv *file_priv;
230 u32 ctx_id;
231 int idx, ret;
232
233 if (!drm_dev_enter(dev, &idx))
234 return -ENODEV;
235
236 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
237 if (!file_priv) {
238 ret = -ENOMEM;
239 goto err_dev_exit;
240 }
241
242 INIT_LIST_HEAD(&file_priv->ms_instance_list);
243
244 file_priv->vdev = vdev;
245 file_priv->bound = true;
246 kref_init(&file_priv->ref);
247 mutex_init(&file_priv->lock);
248 mutex_init(&file_priv->ms_lock);
249
250 mutex_lock(&vdev->context_list_lock);
251
252 ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, file_priv,
253 vdev->context_xa_limit, GFP_KERNEL);
254 if (ret) {
255 ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
256 goto err_unlock;
257 }
258
259 ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id);
260 if (ret)
261 goto err_xa_erase;
262
263 file_priv->job_limit.min = FIELD_PREP(IVPU_JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1));
264 file_priv->job_limit.max = file_priv->job_limit.min | IVPU_JOB_ID_JOB_MASK;
265
266 xa_init_flags(&file_priv->cmdq_xa, XA_FLAGS_ALLOC1);
267 file_priv->cmdq_limit.min = IVPU_CMDQ_MIN_ID;
268 file_priv->cmdq_limit.max = IVPU_CMDQ_MAX_ID;
269
270 mutex_unlock(&vdev->context_list_lock);
271 drm_dev_exit(idx);
272
273 file->driver_priv = file_priv;
274
275 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
276 ctx_id, current->comm, task_pid_nr(current));
277
278 return 0;
279
280 err_xa_erase:
281 xa_erase_irq(&vdev->context_xa, ctx_id);
282 err_unlock:
283 mutex_unlock(&vdev->context_list_lock);
284 mutex_destroy(&file_priv->ms_lock);
285 mutex_destroy(&file_priv->lock);
286 kfree(file_priv);
287 err_dev_exit:
288 drm_dev_exit(idx);
289 return ret;
290 }
291
ivpu_postclose(struct drm_device * dev,struct drm_file * file)292 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
293 {
294 struct ivpu_file_priv *file_priv = file->driver_priv;
295 struct ivpu_device *vdev = to_ivpu_device(dev);
296
297 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
298 file_priv->ctx.id, current->comm, task_pid_nr(current));
299
300 ivpu_ms_cleanup(file_priv);
301 ivpu_file_priv_put(&file_priv);
302 }
303
304 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
305 DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
306 DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
307 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
308 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
309 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
310 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
311 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_START, ivpu_ms_start_ioctl, 0),
312 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_DATA, ivpu_ms_get_data_ioctl, 0),
313 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_STOP, ivpu_ms_stop_ioctl, 0),
314 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_INFO, ivpu_ms_get_info_ioctl, 0),
315 };
316
ivpu_wait_for_ready(struct ivpu_device * vdev)317 static int ivpu_wait_for_ready(struct ivpu_device *vdev)
318 {
319 struct ivpu_ipc_consumer cons;
320 struct ivpu_ipc_hdr ipc_hdr;
321 unsigned long timeout;
322 int ret;
323
324 if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST)
325 return 0;
326
327 ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG, NULL);
328
329 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
330 while (1) {
331 ivpu_ipc_irq_handler(vdev);
332 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
333 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
334 break;
335
336 cond_resched();
337 }
338
339 ivpu_ipc_consumer_del(vdev, &cons);
340
341 if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
342 ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n",
343 ipc_hdr.data_addr);
344 return -EIO;
345 }
346
347 if (!ret)
348 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n");
349
350 return ret;
351 }
352
ivpu_hw_sched_init(struct ivpu_device * vdev)353 static int ivpu_hw_sched_init(struct ivpu_device *vdev)
354 {
355 int ret = 0;
356
357 if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
358 ret = ivpu_jsm_hws_setup_priority_bands(vdev);
359 if (ret) {
360 ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
361 return ret;
362 }
363 }
364
365 return ret;
366 }
367
368 /**
369 * ivpu_boot() - Start VPU firmware
370 * @vdev: VPU device
371 *
372 * This function is paired with ivpu_shutdown() but it doesn't power up the
373 * VPU because power up has to be called very early in ivpu_probe().
374 */
ivpu_boot(struct ivpu_device * vdev)375 int ivpu_boot(struct ivpu_device *vdev)
376 {
377 int ret;
378
379 /* Update boot params located at first 4KB of FW memory */
380 ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem));
381
382 ret = ivpu_hw_boot_fw(vdev);
383 if (ret) {
384 ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
385 return ret;
386 }
387
388 ret = ivpu_wait_for_ready(vdev);
389 if (ret) {
390 ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
391 ivpu_hw_diagnose_failure(vdev);
392 ivpu_mmu_evtq_dump(vdev);
393 ivpu_dev_coredump(vdev);
394 return ret;
395 }
396
397 ivpu_hw_irq_clear(vdev);
398 enable_irq(vdev->irq);
399 ivpu_hw_irq_enable(vdev);
400 ivpu_ipc_enable(vdev);
401
402 if (ivpu_fw_is_cold_boot(vdev)) {
403 ret = ivpu_pm_dct_init(vdev);
404 if (ret)
405 return ret;
406
407 return ivpu_hw_sched_init(vdev);
408 }
409
410 return 0;
411 }
412
ivpu_prepare_for_reset(struct ivpu_device * vdev)413 void ivpu_prepare_for_reset(struct ivpu_device *vdev)
414 {
415 ivpu_hw_irq_disable(vdev);
416 disable_irq(vdev->irq);
417 ivpu_ipc_disable(vdev);
418 ivpu_mmu_disable(vdev);
419 }
420
ivpu_shutdown(struct ivpu_device * vdev)421 int ivpu_shutdown(struct ivpu_device *vdev)
422 {
423 int ret;
424
425 /* Save PCI state before powering down as it sometimes gets corrupted if NPU hangs */
426 pci_save_state(to_pci_dev(vdev->drm.dev));
427
428 ret = ivpu_hw_power_down(vdev);
429 if (ret)
430 ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
431
432 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
433
434 return ret;
435 }
436
437 static const struct file_operations ivpu_fops = {
438 .owner = THIS_MODULE,
439 DRM_ACCEL_FOPS,
440 };
441
442 static const struct drm_driver driver = {
443 .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
444
445 .open = ivpu_open,
446 .postclose = ivpu_postclose,
447
448 .gem_create_object = ivpu_gem_create_object,
449 .gem_prime_import_sg_table = drm_gem_shmem_prime_import_sg_table,
450
451 .ioctls = ivpu_drm_ioctls,
452 .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
453 .fops = &ivpu_fops,
454
455 .name = DRIVER_NAME,
456 .desc = DRIVER_DESC,
457 .date = DRIVER_DATE,
458 .major = DRM_IVPU_DRIVER_MAJOR,
459 .minor = DRM_IVPU_DRIVER_MINOR,
460 };
461
ivpu_irq_thread_handler(int irq,void * arg)462 static irqreturn_t ivpu_irq_thread_handler(int irq, void *arg)
463 {
464 struct ivpu_device *vdev = arg;
465 u8 irq_src;
466
467 if (kfifo_is_empty(&vdev->hw->irq.fifo))
468 return IRQ_NONE;
469
470 while (kfifo_get(&vdev->hw->irq.fifo, &irq_src)) {
471 switch (irq_src) {
472 case IVPU_HW_IRQ_SRC_IPC:
473 ivpu_ipc_irq_thread_handler(vdev);
474 break;
475 case IVPU_HW_IRQ_SRC_DCT:
476 ivpu_pm_dct_irq_thread_handler(vdev);
477 break;
478 default:
479 ivpu_err_ratelimited(vdev, "Unknown IRQ source: %u\n", irq_src);
480 break;
481 }
482 }
483
484 return IRQ_HANDLED;
485 }
486
ivpu_irq_init(struct ivpu_device * vdev)487 static int ivpu_irq_init(struct ivpu_device *vdev)
488 {
489 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
490 int ret;
491
492 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
493 if (ret < 0) {
494 ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
495 return ret;
496 }
497
498 ivpu_irq_handlers_init(vdev);
499
500 vdev->irq = pci_irq_vector(pdev, 0);
501
502 ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, ivpu_hw_irq_handler,
503 ivpu_irq_thread_handler, IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
504 if (ret)
505 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
506
507 return ret;
508 }
509
ivpu_pci_init(struct ivpu_device * vdev)510 static int ivpu_pci_init(struct ivpu_device *vdev)
511 {
512 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
513 struct resource *bar0 = &pdev->resource[0];
514 struct resource *bar4 = &pdev->resource[4];
515 int ret;
516
517 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
518 vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
519 if (IS_ERR(vdev->regv)) {
520 ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
521 return PTR_ERR(vdev->regv);
522 }
523
524 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
525 vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
526 if (IS_ERR(vdev->regb)) {
527 ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
528 return PTR_ERR(vdev->regb);
529 }
530
531 ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
532 if (ret) {
533 ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
534 return ret;
535 }
536 dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
537
538 /* Clear any pending errors */
539 pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
540
541 /* NPU does not require 10m D3hot delay */
542 pdev->d3hot_delay = 0;
543
544 ret = pcim_enable_device(pdev);
545 if (ret) {
546 ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
547 return ret;
548 }
549
550 pci_set_master(pdev);
551
552 return 0;
553 }
554
ivpu_dev_init(struct ivpu_device * vdev)555 static int ivpu_dev_init(struct ivpu_device *vdev)
556 {
557 int ret;
558
559 vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
560 if (!vdev->hw)
561 return -ENOMEM;
562
563 vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
564 if (!vdev->mmu)
565 return -ENOMEM;
566
567 vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
568 if (!vdev->fw)
569 return -ENOMEM;
570
571 vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
572 if (!vdev->ipc)
573 return -ENOMEM;
574
575 vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
576 if (!vdev->pm)
577 return -ENOMEM;
578
579 if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX)
580 vdev->hw->dma_bits = 48;
581 else
582 vdev->hw->dma_bits = 38;
583
584 vdev->platform = IVPU_PLATFORM_INVALID;
585 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
586 vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
587 atomic64_set(&vdev->unique_id_counter, 0);
588 xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
589 xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
590 xa_init_flags(&vdev->db_xa, XA_FLAGS_ALLOC1);
591 INIT_LIST_HEAD(&vdev->bo_list);
592
593 vdev->db_limit.min = IVPU_MIN_DB;
594 vdev->db_limit.max = IVPU_MAX_DB;
595
596 INIT_WORK(&vdev->context_abort_work, ivpu_context_abort_thread_handler);
597
598 ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
599 if (ret)
600 goto err_xa_destroy;
601
602 ret = drmm_mutex_init(&vdev->drm, &vdev->submitted_jobs_lock);
603 if (ret)
604 goto err_xa_destroy;
605
606 ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock);
607 if (ret)
608 goto err_xa_destroy;
609
610 ret = ivpu_pci_init(vdev);
611 if (ret)
612 goto err_xa_destroy;
613
614 ret = ivpu_irq_init(vdev);
615 if (ret)
616 goto err_xa_destroy;
617
618 /* Init basic HW info based on buttress registers which are accessible before power up */
619 ret = ivpu_hw_init(vdev);
620 if (ret)
621 goto err_xa_destroy;
622
623 /* Power up early so the rest of init code can access VPU registers */
624 ret = ivpu_hw_power_up(vdev);
625 if (ret)
626 goto err_shutdown;
627
628 ret = ivpu_mmu_global_context_init(vdev);
629 if (ret)
630 goto err_shutdown;
631
632 ret = ivpu_mmu_init(vdev);
633 if (ret)
634 goto err_mmu_gctx_fini;
635
636 ret = ivpu_mmu_reserved_context_init(vdev);
637 if (ret)
638 goto err_mmu_gctx_fini;
639
640 ret = ivpu_fw_init(vdev);
641 if (ret)
642 goto err_mmu_rctx_fini;
643
644 ret = ivpu_ipc_init(vdev);
645 if (ret)
646 goto err_fw_fini;
647
648 ivpu_pm_init(vdev);
649
650 ret = ivpu_boot(vdev);
651 if (ret)
652 goto err_ipc_fini;
653
654 ivpu_job_done_consumer_init(vdev);
655 ivpu_pm_enable(vdev);
656
657 return 0;
658
659 err_ipc_fini:
660 ivpu_ipc_fini(vdev);
661 err_fw_fini:
662 ivpu_fw_fini(vdev);
663 err_mmu_rctx_fini:
664 ivpu_mmu_reserved_context_fini(vdev);
665 err_mmu_gctx_fini:
666 ivpu_mmu_global_context_fini(vdev);
667 err_shutdown:
668 ivpu_shutdown(vdev);
669 err_xa_destroy:
670 xa_destroy(&vdev->db_xa);
671 xa_destroy(&vdev->submitted_jobs_xa);
672 xa_destroy(&vdev->context_xa);
673 return ret;
674 }
675
ivpu_bo_unbind_all_user_contexts(struct ivpu_device * vdev)676 static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
677 {
678 struct ivpu_file_priv *file_priv;
679 unsigned long ctx_id;
680
681 mutex_lock(&vdev->context_list_lock);
682
683 xa_for_each(&vdev->context_xa, ctx_id, file_priv)
684 file_priv_unbind(vdev, file_priv);
685
686 mutex_unlock(&vdev->context_list_lock);
687 }
688
ivpu_dev_fini(struct ivpu_device * vdev)689 static void ivpu_dev_fini(struct ivpu_device *vdev)
690 {
691 ivpu_jobs_abort_all(vdev);
692 ivpu_pm_disable_recovery(vdev);
693 ivpu_pm_disable(vdev);
694 ivpu_prepare_for_reset(vdev);
695 ivpu_shutdown(vdev);
696
697 ivpu_ms_cleanup_all(vdev);
698 ivpu_job_done_consumer_fini(vdev);
699 ivpu_bo_unbind_all_user_contexts(vdev);
700
701 ivpu_ipc_fini(vdev);
702 ivpu_fw_fini(vdev);
703 ivpu_mmu_reserved_context_fini(vdev);
704 ivpu_mmu_global_context_fini(vdev);
705
706 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->db_xa));
707 xa_destroy(&vdev->db_xa);
708 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
709 xa_destroy(&vdev->submitted_jobs_xa);
710 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
711 xa_destroy(&vdev->context_xa);
712 }
713
714 static struct pci_device_id ivpu_pci_ids[] = {
715 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
716 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
717 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
718 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
719 { }
720 };
721 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
722
ivpu_probe(struct pci_dev * pdev,const struct pci_device_id * id)723 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
724 {
725 struct ivpu_device *vdev;
726 int ret;
727
728 vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
729 if (IS_ERR(vdev))
730 return PTR_ERR(vdev);
731
732 pci_set_drvdata(pdev, vdev);
733
734 ret = ivpu_dev_init(vdev);
735 if (ret)
736 return ret;
737
738 ivpu_debugfs_init(vdev);
739 ivpu_sysfs_init(vdev);
740
741 ret = drm_dev_register(&vdev->drm, 0);
742 if (ret) {
743 dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
744 ivpu_dev_fini(vdev);
745 }
746
747 return ret;
748 }
749
ivpu_remove(struct pci_dev * pdev)750 static void ivpu_remove(struct pci_dev *pdev)
751 {
752 struct ivpu_device *vdev = pci_get_drvdata(pdev);
753
754 drm_dev_unplug(&vdev->drm);
755 ivpu_dev_fini(vdev);
756 }
757
758 static const struct dev_pm_ops ivpu_drv_pci_pm = {
759 SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
760 SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
761 };
762
763 static const struct pci_error_handlers ivpu_drv_pci_err = {
764 .reset_prepare = ivpu_pm_reset_prepare_cb,
765 .reset_done = ivpu_pm_reset_done_cb,
766 };
767
768 static struct pci_driver ivpu_pci_driver = {
769 .name = KBUILD_MODNAME,
770 .id_table = ivpu_pci_ids,
771 .probe = ivpu_probe,
772 .remove = ivpu_remove,
773 .driver = {
774 .pm = &ivpu_drv_pci_pm,
775 },
776 .err_handler = &ivpu_drv_pci_err,
777 };
778
779 module_pci_driver(ivpu_pci_driver);
780
781 MODULE_AUTHOR("Intel Corporation");
782 MODULE_DESCRIPTION(DRIVER_DESC);
783 MODULE_LICENSE("GPL and additional rights");
784 MODULE_VERSION(DRIVER_VERSION_STR);
785