1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6 #include <linux/genalloc.h>
7 #include <linux/highmem.h>
8 #include <linux/pm_runtime.h>
9 #include <linux/wait.h>
10
11 #include "ivpu_drv.h"
12 #include "ivpu_gem.h"
13 #include "ivpu_hw.h"
14 #include "ivpu_hw_reg_io.h"
15 #include "ivpu_ipc.h"
16 #include "ivpu_jsm_msg.h"
17 #include "ivpu_pm.h"
18
19 #define IPC_MAX_RX_MSG 128
20
21 struct ivpu_ipc_tx_buf {
22 struct ivpu_ipc_hdr ipc;
23 struct vpu_jsm_msg jsm;
24 };
25
ivpu_ipc_msg_dump(struct ivpu_device * vdev,char * c,struct ivpu_ipc_hdr * ipc_hdr,u32 vpu_addr)26 static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c,
27 struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr)
28 {
29 ivpu_dbg(vdev, IPC,
30 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)",
31 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel,
32 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status);
33 }
34
ivpu_jsm_msg_dump(struct ivpu_device * vdev,char * c,struct vpu_jsm_msg * jsm_msg,u32 vpu_addr)35 static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c,
36 struct vpu_jsm_msg *jsm_msg, u32 vpu_addr)
37 {
38 u32 *payload = (u32 *)&jsm_msg->payload;
39
40 ivpu_dbg(vdev, JSM,
41 "%s: vpu:0x%08x (type:%s, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n",
42 c, vpu_addr, ivpu_jsm_msg_type_to_str(jsm_msg->type),
43 jsm_msg->status, jsm_msg->request_id, jsm_msg->result,
44 payload[0], payload[1], payload[2], payload[3], payload[4]);
45 }
46
47 static void
ivpu_ipc_rx_mark_free(struct ivpu_device * vdev,struct ivpu_ipc_hdr * ipc_hdr,struct vpu_jsm_msg * jsm_msg)48 ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr,
49 struct vpu_jsm_msg *jsm_msg)
50 {
51 ipc_hdr->status = IVPU_IPC_HDR_FREE;
52 if (jsm_msg)
53 jsm_msg->status = VPU_JSM_MSG_FREE;
54 wmb(); /* Flush WC buffers for message statuses */
55 }
56
ivpu_ipc_mem_fini(struct ivpu_device * vdev)57 static void ivpu_ipc_mem_fini(struct ivpu_device *vdev)
58 {
59 struct ivpu_ipc_info *ipc = vdev->ipc;
60
61 ivpu_bo_free(ipc->mem_rx);
62 ivpu_bo_free(ipc->mem_tx);
63 }
64
65 static int
ivpu_ipc_tx_prepare(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,struct vpu_jsm_msg * req)66 ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
67 struct vpu_jsm_msg *req)
68 {
69 struct ivpu_ipc_info *ipc = vdev->ipc;
70 struct ivpu_ipc_tx_buf *tx_buf;
71 u32 tx_buf_vpu_addr;
72 u32 jsm_vpu_addr;
73
74 tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf));
75 if (!tx_buf_vpu_addr) {
76 ivpu_err_ratelimited(vdev, "Failed to reserve IPC buffer, size %ld\n",
77 sizeof(*tx_buf));
78 return -ENOMEM;
79 }
80
81 tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr);
82 if (drm_WARN_ON(&vdev->drm, !tx_buf)) {
83 gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf));
84 return -EIO;
85 }
86
87 jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm);
88
89 if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE)
90 ivpu_warn_ratelimited(vdev, "IPC message vpu:0x%x not released by firmware\n",
91 tx_buf_vpu_addr);
92
93 if (tx_buf->jsm.status != VPU_JSM_MSG_FREE)
94 ivpu_warn_ratelimited(vdev, "JSM message vpu:0x%x not released by firmware\n",
95 jsm_vpu_addr);
96
97 memset(tx_buf, 0, sizeof(*tx_buf));
98 tx_buf->ipc.data_addr = jsm_vpu_addr;
99 /* TODO: Set data_size to actual JSM message size, not union of all messages */
100 tx_buf->ipc.data_size = sizeof(*req);
101 tx_buf->ipc.channel = cons->channel;
102 tx_buf->ipc.src_node = 0;
103 tx_buf->ipc.dst_node = 1;
104 tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED;
105 tx_buf->jsm.type = req->type;
106 tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED;
107 tx_buf->jsm.payload = req->payload;
108
109 req->request_id = atomic_inc_return(&ipc->request_id);
110 tx_buf->jsm.request_id = req->request_id;
111 cons->request_id = req->request_id;
112 wmb(); /* Flush WC buffers for IPC, JSM msgs */
113
114 cons->tx_vpu_addr = tx_buf_vpu_addr;
115
116 ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr);
117 ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr);
118
119 return 0;
120 }
121
ivpu_ipc_tx_release(struct ivpu_device * vdev,u32 vpu_addr)122 static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr)
123 {
124 struct ivpu_ipc_info *ipc = vdev->ipc;
125
126 if (vpu_addr)
127 gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf));
128 }
129
ivpu_ipc_tx(struct ivpu_device * vdev,u32 vpu_addr)130 static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr)
131 {
132 ivpu_hw_ipc_tx_set(vdev, vpu_addr);
133 }
134
135 static void
ivpu_ipc_rx_msg_add(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,struct ivpu_ipc_hdr * ipc_hdr,struct vpu_jsm_msg * jsm_msg)136 ivpu_ipc_rx_msg_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
137 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg)
138 {
139 struct ivpu_ipc_info *ipc = vdev->ipc;
140 struct ivpu_ipc_rx_msg *rx_msg;
141
142 lockdep_assert_held(&ipc->cons_lock);
143 lockdep_assert_irqs_disabled();
144
145 rx_msg = kzalloc(sizeof(*rx_msg), GFP_ATOMIC);
146 if (!rx_msg) {
147 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
148 return;
149 }
150
151 atomic_inc(&ipc->rx_msg_count);
152
153 rx_msg->ipc_hdr = ipc_hdr;
154 rx_msg->jsm_msg = jsm_msg;
155 rx_msg->callback = cons->rx_callback;
156
157 if (rx_msg->callback) {
158 list_add_tail(&rx_msg->link, &ipc->cb_msg_list);
159 } else {
160 spin_lock(&cons->rx_lock);
161 list_add_tail(&rx_msg->link, &cons->rx_msg_list);
162 spin_unlock(&cons->rx_lock);
163 wake_up(&cons->rx_msg_wq);
164 }
165 }
166
167 static void
ivpu_ipc_rx_msg_del(struct ivpu_device * vdev,struct ivpu_ipc_rx_msg * rx_msg)168 ivpu_ipc_rx_msg_del(struct ivpu_device *vdev, struct ivpu_ipc_rx_msg *rx_msg)
169 {
170 list_del(&rx_msg->link);
171 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);
172 atomic_dec(&vdev->ipc->rx_msg_count);
173 kfree(rx_msg);
174 }
175
ivpu_ipc_consumer_add(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,u32 channel,ivpu_ipc_rx_callback_t rx_callback)176 void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
177 u32 channel, ivpu_ipc_rx_callback_t rx_callback)
178 {
179 struct ivpu_ipc_info *ipc = vdev->ipc;
180
181 INIT_LIST_HEAD(&cons->link);
182 cons->channel = channel;
183 cons->tx_vpu_addr = 0;
184 cons->request_id = 0;
185 cons->aborted = false;
186 cons->rx_callback = rx_callback;
187 spin_lock_init(&cons->rx_lock);
188 INIT_LIST_HEAD(&cons->rx_msg_list);
189 init_waitqueue_head(&cons->rx_msg_wq);
190
191 spin_lock_irq(&ipc->cons_lock);
192 list_add_tail(&cons->link, &ipc->cons_list);
193 spin_unlock_irq(&ipc->cons_lock);
194 }
195
ivpu_ipc_consumer_del(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons)196 void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons)
197 {
198 struct ivpu_ipc_info *ipc = vdev->ipc;
199 struct ivpu_ipc_rx_msg *rx_msg, *r;
200
201 spin_lock_irq(&ipc->cons_lock);
202 list_del(&cons->link);
203 spin_unlock_irq(&ipc->cons_lock);
204
205 spin_lock_irq(&cons->rx_lock);
206 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link)
207 ivpu_ipc_rx_msg_del(vdev, rx_msg);
208 spin_unlock_irq(&cons->rx_lock);
209
210 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr);
211 }
212
ivpu_ipc_send(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,struct vpu_jsm_msg * req)213 int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req)
214 {
215 struct ivpu_ipc_info *ipc = vdev->ipc;
216 int ret;
217
218 mutex_lock(&ipc->lock);
219
220 if (!ipc->on) {
221 ret = -EAGAIN;
222 goto unlock;
223 }
224
225 ret = ivpu_ipc_tx_prepare(vdev, cons, req);
226 if (ret)
227 goto unlock;
228
229 ivpu_ipc_tx(vdev, cons->tx_vpu_addr);
230
231 unlock:
232 mutex_unlock(&ipc->lock);
233 return ret;
234 }
235
ivpu_ipc_rx_need_wakeup(struct ivpu_ipc_consumer * cons)236 static bool ivpu_ipc_rx_need_wakeup(struct ivpu_ipc_consumer *cons)
237 {
238 bool ret;
239
240 spin_lock_irq(&cons->rx_lock);
241 ret = !list_empty(&cons->rx_msg_list) || cons->aborted;
242 spin_unlock_irq(&cons->rx_lock);
243
244 return ret;
245 }
246
ivpu_ipc_receive(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,struct ivpu_ipc_hdr * ipc_buf,struct vpu_jsm_msg * jsm_msg,unsigned long timeout_ms)247 int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
248 struct ivpu_ipc_hdr *ipc_buf,
249 struct vpu_jsm_msg *jsm_msg, unsigned long timeout_ms)
250 {
251 struct ivpu_ipc_rx_msg *rx_msg;
252 int wait_ret, ret = 0;
253
254 if (drm_WARN_ONCE(&vdev->drm, cons->rx_callback, "Consumer works only in async mode\n"))
255 return -EINVAL;
256
257 wait_ret = wait_event_timeout(cons->rx_msg_wq,
258 ivpu_ipc_rx_need_wakeup(cons),
259 msecs_to_jiffies(timeout_ms));
260
261 if (wait_ret == 0)
262 return -ETIMEDOUT;
263
264 spin_lock_irq(&cons->rx_lock);
265 if (cons->aborted) {
266 spin_unlock_irq(&cons->rx_lock);
267 return -ECANCELED;
268 }
269 rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link);
270 if (!rx_msg) {
271 spin_unlock_irq(&cons->rx_lock);
272 return -EAGAIN;
273 }
274
275 if (ipc_buf)
276 memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf));
277 if (rx_msg->jsm_msg) {
278 u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*jsm_msg));
279
280 if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) {
281 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result);
282 ret = -EBADMSG;
283 }
284
285 if (jsm_msg)
286 memcpy(jsm_msg, rx_msg->jsm_msg, size);
287 }
288
289 ivpu_ipc_rx_msg_del(vdev, rx_msg);
290 spin_unlock_irq(&cons->rx_lock);
291 return ret;
292 }
293
294 int
ivpu_ipc_send_receive_internal(struct ivpu_device * vdev,struct vpu_jsm_msg * req,enum vpu_ipc_msg_type expected_resp_type,struct vpu_jsm_msg * resp,u32 channel,unsigned long timeout_ms)295 ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
296 enum vpu_ipc_msg_type expected_resp_type,
297 struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms)
298 {
299 struct ivpu_ipc_consumer cons;
300 int ret;
301
302 drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev) &&
303 pm_runtime_enabled(vdev->drm.dev));
304
305 ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
306
307 ret = ivpu_ipc_send(vdev, &cons, req);
308 if (ret) {
309 ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret);
310 goto consumer_del;
311 }
312
313 ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms);
314 if (ret) {
315 ivpu_warn_ratelimited(vdev, "IPC receive failed: type %s, ret %d\n",
316 ivpu_jsm_msg_type_to_str(req->type), ret);
317 goto consumer_del;
318 }
319
320 if (resp->type != expected_resp_type) {
321 ivpu_warn_ratelimited(vdev, "Invalid JSM response type: 0x%x\n", resp->type);
322 ret = -EBADE;
323 }
324
325 consumer_del:
326 ivpu_ipc_consumer_del(vdev, &cons);
327 return ret;
328 }
329
ivpu_ipc_send_receive(struct ivpu_device * vdev,struct vpu_jsm_msg * req,enum vpu_ipc_msg_type expected_resp,struct vpu_jsm_msg * resp,u32 channel,unsigned long timeout_ms)330 int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
331 enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp,
332 u32 channel, unsigned long timeout_ms)
333 {
334 struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB };
335 struct vpu_jsm_msg hb_resp;
336 int ret, hb_ret;
337
338 ret = ivpu_rpm_get(vdev);
339 if (ret < 0)
340 return ret;
341
342 ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp, resp, channel, timeout_ms);
343 if (ret != -ETIMEDOUT)
344 goto rpm_put;
345
346 hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE,
347 &hb_resp, VPU_IPC_CHAN_ASYNC_CMD,
348 vdev->timeout.jsm);
349 if (hb_ret == -ETIMEDOUT)
350 ivpu_pm_trigger_recovery(vdev, "IPC timeout");
351
352 rpm_put:
353 ivpu_rpm_put(vdev);
354 return ret;
355 }
356
ivpu_ipc_send_and_wait(struct ivpu_device * vdev,struct vpu_jsm_msg * req,u32 channel,unsigned long timeout_ms)357 int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req,
358 u32 channel, unsigned long timeout_ms)
359 {
360 struct ivpu_ipc_consumer cons;
361 int ret;
362
363 ret = ivpu_rpm_get(vdev);
364 if (ret < 0)
365 return ret;
366
367 ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
368
369 ret = ivpu_ipc_send(vdev, &cons, req);
370 if (ret) {
371 ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret);
372 goto consumer_del;
373 }
374
375 msleep(timeout_ms);
376
377 consumer_del:
378 ivpu_ipc_consumer_del(vdev, &cons);
379 ivpu_rpm_put(vdev);
380 return ret;
381 }
382
383 static bool
ivpu_ipc_match_consumer(struct ivpu_device * vdev,struct ivpu_ipc_consumer * cons,struct ivpu_ipc_hdr * ipc_hdr,struct vpu_jsm_msg * jsm_msg)384 ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons,
385 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg)
386 {
387 if (cons->channel != ipc_hdr->channel)
388 return false;
389
390 if (!jsm_msg || jsm_msg->request_id == cons->request_id)
391 return true;
392
393 return false;
394 }
395
ivpu_ipc_irq_handler(struct ivpu_device * vdev)396 void ivpu_ipc_irq_handler(struct ivpu_device *vdev)
397 {
398 struct ivpu_ipc_info *ipc = vdev->ipc;
399 struct ivpu_ipc_consumer *cons;
400 struct ivpu_ipc_hdr *ipc_hdr;
401 struct vpu_jsm_msg *jsm_msg;
402 unsigned long flags;
403 bool dispatched;
404 u32 vpu_addr;
405
406 /*
407 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt.
408 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated.
409 */
410 while (ivpu_hw_ipc_rx_count_get(vdev)) {
411 vpu_addr = ivpu_hw_ipc_rx_addr_get(vdev);
412 if (vpu_addr == REG_IO_ERROR) {
413 ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n");
414 return;
415 }
416
417 ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr);
418 if (!ipc_hdr) {
419 ivpu_warn_ratelimited(vdev, "IPC msg 0x%x out of range\n", vpu_addr);
420 continue;
421 }
422 ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr);
423
424 jsm_msg = NULL;
425 if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) {
426 jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr);
427 if (!jsm_msg) {
428 ivpu_warn_ratelimited(vdev, "JSM msg 0x%x out of range\n",
429 ipc_hdr->data_addr);
430 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL);
431 continue;
432 }
433 ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr);
434 }
435
436 if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) {
437 ivpu_warn_ratelimited(vdev, "IPC RX msg dropped, msg count %d\n",
438 IPC_MAX_RX_MSG);
439 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
440 continue;
441 }
442
443 dispatched = false;
444 spin_lock_irqsave(&ipc->cons_lock, flags);
445 list_for_each_entry(cons, &ipc->cons_list, link) {
446 if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) {
447 ivpu_ipc_rx_msg_add(vdev, cons, ipc_hdr, jsm_msg);
448 dispatched = true;
449 break;
450 }
451 }
452 spin_unlock_irqrestore(&ipc->cons_lock, flags);
453
454 if (!dispatched) {
455 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr);
456 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg);
457 }
458 }
459
460 if (!list_empty(&ipc->cb_msg_list))
461 if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_IPC))
462 ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");
463 }
464
ivpu_ipc_irq_thread_handler(struct ivpu_device * vdev)465 void ivpu_ipc_irq_thread_handler(struct ivpu_device *vdev)
466 {
467 struct ivpu_ipc_info *ipc = vdev->ipc;
468 struct ivpu_ipc_rx_msg *rx_msg, *r;
469 struct list_head cb_msg_list;
470
471 INIT_LIST_HEAD(&cb_msg_list);
472
473 spin_lock_irq(&ipc->cons_lock);
474 list_splice_tail_init(&ipc->cb_msg_list, &cb_msg_list);
475 spin_unlock_irq(&ipc->cons_lock);
476
477 list_for_each_entry_safe(rx_msg, r, &cb_msg_list, link) {
478 rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg);
479 ivpu_ipc_rx_msg_del(vdev, rx_msg);
480 }
481 }
482
ivpu_ipc_init(struct ivpu_device * vdev)483 int ivpu_ipc_init(struct ivpu_device *vdev)
484 {
485 struct ivpu_ipc_info *ipc = vdev->ipc;
486 int ret;
487
488 ipc->mem_tx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
489 if (!ipc->mem_tx) {
490 ivpu_err(vdev, "Failed to allocate mem_tx\n");
491 return -ENOMEM;
492 }
493
494 ipc->mem_rx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
495 if (!ipc->mem_rx) {
496 ivpu_err(vdev, "Failed to allocate mem_rx\n");
497 ret = -ENOMEM;
498 goto err_free_tx;
499 }
500
501 ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT),
502 -1, "TX_IPC_JSM");
503 if (IS_ERR(ipc->mm_tx)) {
504 ret = PTR_ERR(ipc->mm_tx);
505 ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx);
506 goto err_free_rx;
507 }
508
509 ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ivpu_bo_size(ipc->mem_tx), -1);
510 if (ret) {
511 ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret);
512 goto err_free_rx;
513 }
514
515 spin_lock_init(&ipc->cons_lock);
516 INIT_LIST_HEAD(&ipc->cons_list);
517 INIT_LIST_HEAD(&ipc->cb_msg_list);
518 ret = drmm_mutex_init(&vdev->drm, &ipc->lock);
519 if (ret) {
520 ivpu_err(vdev, "Failed to initialize ipc->lock, ret %d\n", ret);
521 goto err_free_rx;
522 }
523 ivpu_ipc_reset(vdev);
524 return 0;
525
526 err_free_rx:
527 ivpu_bo_free(ipc->mem_rx);
528 err_free_tx:
529 ivpu_bo_free(ipc->mem_tx);
530 return ret;
531 }
532
ivpu_ipc_fini(struct ivpu_device * vdev)533 void ivpu_ipc_fini(struct ivpu_device *vdev)
534 {
535 struct ivpu_ipc_info *ipc = vdev->ipc;
536
537 drm_WARN_ON(&vdev->drm, ipc->on);
538 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cons_list));
539 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list));
540 drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0);
541
542 ivpu_ipc_mem_fini(vdev);
543 }
544
ivpu_ipc_enable(struct ivpu_device * vdev)545 void ivpu_ipc_enable(struct ivpu_device *vdev)
546 {
547 struct ivpu_ipc_info *ipc = vdev->ipc;
548
549 mutex_lock(&ipc->lock);
550 ipc->on = true;
551 mutex_unlock(&ipc->lock);
552 }
553
ivpu_ipc_disable(struct ivpu_device * vdev)554 void ivpu_ipc_disable(struct ivpu_device *vdev)
555 {
556 struct ivpu_ipc_info *ipc = vdev->ipc;
557 struct ivpu_ipc_consumer *cons, *c;
558 struct ivpu_ipc_rx_msg *rx_msg, *r;
559
560 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list));
561
562 mutex_lock(&ipc->lock);
563 ipc->on = false;
564 mutex_unlock(&ipc->lock);
565
566 spin_lock_irq(&ipc->cons_lock);
567 list_for_each_entry_safe(cons, c, &ipc->cons_list, link) {
568 spin_lock(&cons->rx_lock);
569 if (!cons->rx_callback)
570 cons->aborted = true;
571 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link)
572 ivpu_ipc_rx_msg_del(vdev, rx_msg);
573 spin_unlock(&cons->rx_lock);
574 wake_up(&cons->rx_msg_wq);
575 }
576 spin_unlock_irq(&ipc->cons_lock);
577
578 drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0);
579 }
580
ivpu_ipc_reset(struct ivpu_device * vdev)581 void ivpu_ipc_reset(struct ivpu_device *vdev)
582 {
583 struct ivpu_ipc_info *ipc = vdev->ipc;
584
585 mutex_lock(&ipc->lock);
586 drm_WARN_ON(&vdev->drm, ipc->on);
587
588 memset(ivpu_bo_vaddr(ipc->mem_tx), 0, ivpu_bo_size(ipc->mem_tx));
589 memset(ivpu_bo_vaddr(ipc->mem_rx), 0, ivpu_bo_size(ipc->mem_rx));
590 wmb(); /* Flush WC buffers for TX and RX rings */
591
592 mutex_unlock(&ipc->lock);
593 }
594