1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 *
4 * Bluetooth support for Intel PCIe devices
5 *
6 * Copyright (C) 2024 Intel Corporation
7 */
8
9 /* Control and Status Register(BTINTEL_PCIE_CSR) */
10 #define BTINTEL_PCIE_CSR_BASE (0x000)
11 #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024)
12 #define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028)
13 #define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C)
14 #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108)
15 #define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114)
16 #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118)
17 #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C)
18 #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C)
19 #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460)
20
21 /* BTINTEL_PCIE_CSR Function Control Register */
22 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0))
23 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6))
24 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7))
25 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20))
26 #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31))
27
28 /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */
29 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0))
30 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1))
31 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2))
32 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10))
33 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11))
34 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16))
35 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23))
36 #define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24))
37
38 /* Registers for MSI-X */
39 #define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000)
40 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800)
41 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804)
42 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808)
43 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C)
44 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810)
45 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814)
46 #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880)
47 #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause))
48
49 /* Causes for the FH register interrupts */
50 enum msix_fh_int_causes {
51 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */
52 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */
53 };
54
55 /* Causes for the HW register interrupts */
56 enum msix_hw_int_causes {
57 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */
58 };
59
60 /* PCIe device states
61 * Host-Device interface is active
62 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
63 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
64 */
65 enum {
66 BTINTEL_PCIE_STATE_D0 = 0,
67 BTINTEL_PCIE_STATE_D3_HOT = 2,
68 BTINTEL_PCIE_STATE_D3_COLD = 3,
69 };
70 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
71
72 /* Minimum and Maximum number of MSI-X Vector
73 * Intel Bluetooth PCIe support only 1 vector
74 */
75 #define BTINTEL_PCIE_MSIX_VEC_MAX 1
76 #define BTINTEL_PCIE_MSIX_VEC_MIN 1
77
78 /* Default poll time for MAC access during init */
79 #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000
80
81 /* Default interrupt timeout in msec */
82 #define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000
83
84 /* The number of descriptors in TX queues */
85 #define BTINTEL_PCIE_TX_DESCS_COUNT 32
86
87 /* The number of descriptors in RX queues */
88 #define BTINTEL_PCIE_RX_DESCS_COUNT 64
89
90 /* Number of Queue for TX and RX
91 * It indicates the index of the IA(Index Array)
92 */
93 enum {
94 BTINTEL_PCIE_TXQ_NUM = 0,
95 BTINTEL_PCIE_RXQ_NUM = 1,
96 BTINTEL_PCIE_NUM_QUEUES = 2,
97 };
98
99 /* The size of DMA buffer for TX and RX in bytes */
100 #define BTINTEL_PCIE_BUFFER_SIZE 4096
101
102 /* DMA allocation alignment */
103 #define BTINTEL_PCIE_DMA_POOL_ALIGNMENT 256
104
105 #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500
106
107 /* Doorbell vector for TFD */
108 #define BTINTEL_PCIE_TX_DB_VEC 0
109
110 /* Doorbell vector for FRBD */
111 #define BTINTEL_PCIE_RX_DB_VEC 513
112
113 /* RBD buffer size mapping */
114 #define BTINTEL_PCIE_RBD_SIZE_4K 0x04
115
116 /*
117 * Struct for Context Information (v2)
118 *
119 * All members are write-only for host and read-only for device.
120 *
121 * @version: Version of context information
122 * @size: Size of context information
123 * @config: Config with which host wants peripheral to execute
124 * Subset of capability register published by device
125 * @addr_tr_hia: Address of TR Head Index Array
126 * @addr_tr_tia: Address of TR Tail Index Array
127 * @addr_cr_hia: Address of CR Head Index Array
128 * @addr_cr_tia: Address of CR Tail Index Array
129 * @num_tr_ia: Number of entries in TR Index Arrays
130 * @num_cr_ia: Number of entries in CR Index Arrays
131 * @rbd_siz: RBD Size { 0x4=4K }
132 * @addr_tfdq: Address of TFD Queue(tx)
133 * @addr_urbdq0: Address of URBD Queue(tx)
134 * @num_tfdq: Number of TFD in TFD Queue(tx)
135 * @num_urbdq0: Number of URBD in URBD Queue(tx)
136 * @tfdq_db_vec: Queue number of TFD
137 * @urbdq0_db_vec: Queue number of URBD
138 * @addr_frbdq: Address of FRBD Queue(rx)
139 * @addr_urbdq1: Address of URBD Queue(rx)
140 * @num_frbdq: Number of FRBD in FRBD Queue(rx)
141 * @frbdq_db_vec: Queue number of FRBD
142 * @num_urbdq1: Number of URBD in URBD Queue(rx)
143 * @urbdq_db_vec: Queue number of URBDQ1
144 * @tr_msi_vec: Transfer Ring MSI-X Vector
145 * @cr_msi_vec: Completion Ring MSI-X Vector
146 * @dbgc_addr: DBGC first fragment address
147 * @dbgc_size: DBGC buffer size
148 * @early_enable: Enarly debug enable
149 * @dbg_output_mode: Debug output mode
150 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) }
151 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI }
152 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1)
153 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK }
154 * @dbg_preset: Debug preset
155 * @ext_addr: Address of context information extension
156 * @ext_size: Size of context information part
157 *
158 * Total 38 DWords
159 */
160 struct ctx_info {
161 u16 version;
162 u16 size;
163 u32 config;
164 u32 reserved_dw02;
165 u32 reserved_dw03;
166 u64 addr_tr_hia;
167 u64 addr_tr_tia;
168 u64 addr_cr_hia;
169 u64 addr_cr_tia;
170 u16 num_tr_ia;
171 u16 num_cr_ia;
172 u32 rbd_size:4,
173 reserved_dw13:28;
174 u64 addr_tfdq;
175 u64 addr_urbdq0;
176 u16 num_tfdq;
177 u16 num_urbdq0;
178 u16 tfdq_db_vec;
179 u16 urbdq0_db_vec;
180 u64 addr_frbdq;
181 u64 addr_urbdq1;
182 u16 num_frbdq;
183 u16 frbdq_db_vec;
184 u16 num_urbdq1;
185 u16 urbdq_db_vec;
186 u16 tr_msi_vec;
187 u16 cr_msi_vec;
188 u32 reserved_dw27;
189 u64 dbgc_addr;
190 u32 dbgc_size;
191 u32 early_enable:1,
192 reserved_dw31:3,
193 dbg_output_mode:4,
194 dbg_preset:8,
195 reserved2_dw31:16;
196 u64 ext_addr;
197 u32 ext_size;
198 u32 test_param;
199 u32 reserved_dw36;
200 u32 reserved_dw37;
201 } __packed;
202
203 /* Transfer Descriptor for TX
204 * @type: Not in use. Set to 0x0
205 * @size: Size of data in the buffer
206 * @addr: DMA Address of buffer
207 */
208 struct tfd {
209 u8 type;
210 u16 size;
211 u8 reserved;
212 u64 addr;
213 u32 reserved1;
214 } __packed;
215
216 /* URB Descriptor for TX
217 * @tfd_index: Index of TFD in TFDQ + 1
218 * @num_txq: Queue index of TFD Queue
219 * @cmpl_count: Completion count. Always 0x01
220 * @immediate_cmpl: Immediate completion flag: Always 0x01
221 */
222 struct urbd0 {
223 u32 tfd_index:16,
224 num_txq:8,
225 cmpl_count:4,
226 reserved:3,
227 immediate_cmpl:1;
228 } __packed;
229
230 /* FRB Descriptor for RX
231 * @tag: RX buffer tag (index of RX buffer queue)
232 * @addr: Address of buffer
233 */
234 struct frbd {
235 u32 tag:16,
236 reserved:16;
237 u32 reserved2;
238 u64 addr;
239 } __packed;
240
241 /* URB Descriptor for RX
242 * @frbd_tag: Tag from FRBD
243 * @status: Status
244 */
245 struct urbd1 {
246 u32 frbd_tag:16,
247 status:1,
248 reserved:14,
249 fixed:1;
250 } __packed;
251
252 /* RFH header in RX packet
253 * @packet_len: Length of the data in the buffer
254 * @rxq: RX Queue number
255 * @cmd_id: Command ID. Not in Use
256 */
257 struct rfh_hdr {
258 u64 packet_len:16,
259 rxq:6,
260 reserved:10,
261 cmd_id:16,
262 reserved1:16;
263 } __packed;
264
265 /* Internal data buffer
266 * @data: pointer to the data buffer
267 * @p_addr: physical address of data buffer
268 */
269 struct data_buf {
270 u8 *data;
271 dma_addr_t data_p_addr;
272 };
273
274 /* Index Array */
275 struct ia {
276 dma_addr_t tr_hia_p_addr;
277 u16 *tr_hia;
278 dma_addr_t tr_tia_p_addr;
279 u16 *tr_tia;
280 dma_addr_t cr_hia_p_addr;
281 u16 *cr_hia;
282 dma_addr_t cr_tia_p_addr;
283 u16 *cr_tia;
284 };
285
286 /* Structure for TX Queue
287 * @count: Number of descriptors
288 * @tfds: Array of TFD
289 * @urbd0s: Array of URBD0
290 * @buf: Array of data_buf structure
291 */
292 struct txq {
293 u16 count;
294
295 dma_addr_t tfds_p_addr;
296 struct tfd *tfds;
297
298 dma_addr_t urbd0s_p_addr;
299 struct urbd0 *urbd0s;
300
301 dma_addr_t buf_p_addr;
302 void *buf_v_addr;
303 struct data_buf *bufs;
304 };
305
306 /* Structure for RX Queue
307 * @count: Number of descriptors
308 * @frbds: Array of FRBD
309 * @urbd1s: Array of URBD1
310 * @buf: Array of data_buf structure
311 */
312 struct rxq {
313 u16 count;
314
315 dma_addr_t frbds_p_addr;
316 struct frbd *frbds;
317
318 dma_addr_t urbd1s_p_addr;
319 struct urbd1 *urbd1s;
320
321 dma_addr_t buf_p_addr;
322 void *buf_v_addr;
323 struct data_buf *bufs;
324 };
325
326 /* struct btintel_pcie_data
327 * @pdev: pci device
328 * @hdev: hdev device
329 * @flags: driver state
330 * @irq_lock: spinlock for MSI-X
331 * @hci_rx_lock: spinlock for HCI RX flow
332 * @base_addr: pci base address (from BAR)
333 * @msix_entries: array of MSI-X entries
334 * @msix_enabled: true if MSI-X is enabled;
335 * @alloc_vecs: number of interrupt vectors allocated
336 * @def_irq: default irq for all causes
337 * @fh_init_mask: initial unmasked rxq causes
338 * @hw_init_mask: initial unmaksed hw causes
339 * @boot_stage_cache: cached value of boot stage register
340 * @img_resp_cache: cached value of image response register
341 * @cnvi: CNVi register value
342 * @cnvr: CNVr register value
343 * @gp0_received: condition for gp0 interrupt
344 * @gp0_wait_q: wait_q for gp0 interrupt
345 * @tx_wait_done: condition for tx interrupt
346 * @tx_wait_q: wait_q for tx interrupt
347 * @workqueue: workqueue for RX work
348 * @rx_skb_q: SKB queue for RX packet
349 * @rx_work: RX work struct to process the RX packet in @rx_skb_q
350 * @dma_pool: DMA pool for descriptors, index array and ci
351 * @dma_p_addr: DMA address for pool
352 * @dma_v_addr: address of pool
353 * @ci_p_addr: DMA address for CI struct
354 * @ci: CI struct
355 * @ia: Index Array struct
356 * @txq: TX Queue struct
357 * @rxq: RX Queue struct
358 * @alive_intr_ctxt: Alive interrupt context
359 */
360 struct btintel_pcie_data {
361 struct pci_dev *pdev;
362 struct hci_dev *hdev;
363
364 unsigned long flags;
365 /* lock used in MSI-X interrupt */
366 spinlock_t irq_lock;
367 /* lock to serialize rx events */
368 spinlock_t hci_rx_lock;
369
370 void __iomem *base_addr;
371
372 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX];
373 bool msix_enabled;
374 u32 alloc_vecs;
375 u32 def_irq;
376
377 u32 fh_init_mask;
378 u32 hw_init_mask;
379
380 u32 boot_stage_cache;
381 u32 img_resp_cache;
382
383 u32 cnvi;
384 u32 cnvr;
385
386 bool gp0_received;
387 wait_queue_head_t gp0_wait_q;
388
389 bool tx_wait_done;
390 wait_queue_head_t tx_wait_q;
391
392 struct workqueue_struct *workqueue;
393 struct sk_buff_head rx_skb_q;
394 struct work_struct rx_work;
395
396 struct dma_pool *dma_pool;
397 dma_addr_t dma_p_addr;
398 void *dma_v_addr;
399
400 dma_addr_t ci_p_addr;
401 struct ctx_info *ci;
402 struct ia ia;
403 struct txq txq;
404 struct rxq rxq;
405 u32 alive_intr_ctxt;
406 };
407
btintel_pcie_rd_reg32(struct btintel_pcie_data * data,u32 offset)408 static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data,
409 u32 offset)
410 {
411 return ioread32(data->base_addr + offset);
412 }
413
btintel_pcie_wr_reg8(struct btintel_pcie_data * data,u32 offset,u8 val)414 static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data,
415 u32 offset, u8 val)
416 {
417 iowrite8(val, data->base_addr + offset);
418 }
419
btintel_pcie_wr_reg32(struct btintel_pcie_data * data,u32 offset,u32 val)420 static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data,
421 u32 offset, u32 val)
422 {
423 iowrite32(val, data->base_addr + offset);
424 }
425
btintel_pcie_set_reg_bits(struct btintel_pcie_data * data,u32 offset,u32 bits)426 static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data,
427 u32 offset, u32 bits)
428 {
429 u32 r;
430
431 r = ioread32(data->base_addr + offset);
432 r |= bits;
433 iowrite32(r, data->base_addr + offset);
434 }
435
btintel_pcie_clr_reg_bits(struct btintel_pcie_data * data,u32 offset,u32 bits)436 static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data,
437 u32 offset, u32 bits)
438 {
439 u32 r;
440
441 r = ioread32(data->base_addr + offset);
442 r &= ~bits;
443 iowrite32(r, data->base_addr + offset);
444 }
445