1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2H(P) Clock Pulse Generator
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 *
7 * Based on rzg2l-cpg.c
8 *
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2013 Ideas On Board SPRL
11 * Copyright (C) 2015 Renesas Electronics Corp.
12 */
13
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/iopoll.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_clock.h>
25 #include <linux/pm_domain.h>
26 #include <linux/reset-controller.h>
27
28 #include <dt-bindings/clock/renesas-cpg-mssr.h>
29
30 #include "rzv2h-cpg.h"
31
32 #ifdef DEBUG
33 #define WARN_DEBUG(x) WARN_ON(x)
34 #else
35 #define WARN_DEBUG(x) do { } while (0)
36 #endif
37
38 #define GET_CLK_ON_OFFSET(x) (0x600 + ((x) * 4))
39 #define GET_CLK_MON_OFFSET(x) (0x800 + ((x) * 4))
40 #define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
41 #define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
42
43 #define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
44 #define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
45 #define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
46 #define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
47
48 #define DDIV_DIVCTL_WEN(shift) BIT((shift) + 16)
49
50 #define GET_MOD_CLK_ID(base, index, bit) \
51 ((base) + ((((index) * (16))) + (bit)))
52
53 #define CPG_CLKSTATUS0 (0x700)
54
55 /**
56 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
57 *
58 * @dev: CPG device
59 * @base: CPG register block base address
60 * @rmw_lock: protects register accesses
61 * @clks: Array containing all Core and Module Clocks
62 * @num_core_clks: Number of Core Clocks in clks[]
63 * @num_mod_clks: Number of Module Clocks in clks[]
64 * @resets: Array of resets
65 * @num_resets: Number of Module Resets in info->resets[]
66 * @last_dt_core_clk: ID of the last Core Clock exported to DT
67 * @rcdev: Reset controller entity
68 */
69 struct rzv2h_cpg_priv {
70 struct device *dev;
71 void __iomem *base;
72 spinlock_t rmw_lock;
73
74 struct clk **clks;
75 unsigned int num_core_clks;
76 unsigned int num_mod_clks;
77 struct rzv2h_reset *resets;
78 unsigned int num_resets;
79 unsigned int last_dt_core_clk;
80
81 struct reset_controller_dev rcdev;
82 };
83
84 #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev)
85
86 struct pll_clk {
87 struct rzv2h_cpg_priv *priv;
88 void __iomem *base;
89 struct clk_hw hw;
90 unsigned int conf;
91 unsigned int type;
92 };
93
94 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
95
96 /**
97 * struct mod_clock - Module clock
98 *
99 * @priv: CPG private data
100 * @hw: handle between common and hardware-specific interfaces
101 * @on_index: register offset
102 * @on_bit: ON/MON bit
103 * @mon_index: monitor register offset
104 * @mon_bit: montor bit
105 */
106 struct mod_clock {
107 struct rzv2h_cpg_priv *priv;
108 struct clk_hw hw;
109 u8 on_index;
110 u8 on_bit;
111 s8 mon_index;
112 u8 mon_bit;
113 };
114
115 #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
116
117 /**
118 * struct ddiv_clk - DDIV clock
119 *
120 * @priv: CPG private data
121 * @div: divider clk
122 * @mon: monitor bit in CPG_CLKSTATUS0 register
123 */
124 struct ddiv_clk {
125 struct rzv2h_cpg_priv *priv;
126 struct clk_divider div;
127 u8 mon;
128 };
129
130 #define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
131
rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)132 static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
133 unsigned long parent_rate)
134 {
135 struct pll_clk *pll_clk = to_pll(hw);
136 struct rzv2h_cpg_priv *priv = pll_clk->priv;
137 unsigned int clk1, clk2;
138 u64 rate;
139
140 if (!PLL_CLK_ACCESS(pll_clk->conf))
141 return 0;
142
143 clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));
144 clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));
145
146 rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
147 16 + SDIV(clk2));
148
149 return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
150 }
151
152 static const struct clk_ops rzv2h_cpg_pll_ops = {
153 .recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
154 };
155
156 static struct clk * __init
rzv2h_cpg_pll_clk_register(const struct cpg_core_clk * core,struct rzv2h_cpg_priv * priv,const struct clk_ops * ops)157 rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
158 struct rzv2h_cpg_priv *priv,
159 const struct clk_ops *ops)
160 {
161 void __iomem *base = priv->base;
162 struct device *dev = priv->dev;
163 struct clk_init_data init;
164 const struct clk *parent;
165 const char *parent_name;
166 struct pll_clk *pll_clk;
167 int ret;
168
169 parent = priv->clks[core->parent];
170 if (IS_ERR(parent))
171 return ERR_CAST(parent);
172
173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
174 if (!pll_clk)
175 return ERR_PTR(-ENOMEM);
176
177 parent_name = __clk_get_name(parent);
178 init.name = core->name;
179 init.ops = ops;
180 init.flags = 0;
181 init.parent_names = &parent_name;
182 init.num_parents = 1;
183
184 pll_clk->hw.init = &init;
185 pll_clk->conf = core->cfg.conf;
186 pll_clk->base = base;
187 pll_clk->priv = priv;
188 pll_clk->type = core->type;
189
190 ret = devm_clk_hw_register(dev, &pll_clk->hw);
191 if (ret)
192 return ERR_PTR(ret);
193
194 return pll_clk->hw.clk;
195 }
196
rzv2h_ddiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)197 static unsigned long rzv2h_ddiv_recalc_rate(struct clk_hw *hw,
198 unsigned long parent_rate)
199 {
200 struct clk_divider *divider = to_clk_divider(hw);
201 unsigned int val;
202
203 val = readl(divider->reg) >> divider->shift;
204 val &= clk_div_mask(divider->width);
205
206 return divider_recalc_rate(hw, parent_rate, val, divider->table,
207 divider->flags, divider->width);
208 }
209
rzv2h_ddiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)210 static long rzv2h_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long *prate)
212 {
213 struct clk_divider *divider = to_clk_divider(hw);
214
215 return divider_round_rate(hw, rate, prate, divider->table,
216 divider->width, divider->flags);
217 }
218
rzv2h_ddiv_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)219 static int rzv2h_ddiv_determine_rate(struct clk_hw *hw,
220 struct clk_rate_request *req)
221 {
222 struct clk_divider *divider = to_clk_divider(hw);
223
224 return divider_determine_rate(hw, req, divider->table, divider->width,
225 divider->flags);
226 }
227
rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem * base,u8 mon)228 static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon)
229 {
230 u32 bitmask = BIT(mon);
231 u32 val;
232
233 return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
234 }
235
rzv2h_ddiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)236 static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
237 unsigned long parent_rate)
238 {
239 struct clk_divider *divider = to_clk_divider(hw);
240 struct ddiv_clk *ddiv = to_ddiv_clock(divider);
241 struct rzv2h_cpg_priv *priv = ddiv->priv;
242 unsigned long flags = 0;
243 int value;
244 u32 val;
245 int ret;
246
247 value = divider_get_val(rate, parent_rate, divider->table,
248 divider->width, divider->flags);
249 if (value < 0)
250 return value;
251
252 spin_lock_irqsave(divider->lock, flags);
253
254 ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
255 if (ret)
256 goto ddiv_timeout;
257
258 val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);
259 val &= ~(clk_div_mask(divider->width) << divider->shift);
260 val |= (u32)value << divider->shift;
261 writel(val, divider->reg);
262
263 ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
264 if (ret)
265 goto ddiv_timeout;
266
267 spin_unlock_irqrestore(divider->lock, flags);
268
269 return 0;
270
271 ddiv_timeout:
272 spin_unlock_irqrestore(divider->lock, flags);
273 return ret;
274 }
275
276 static const struct clk_ops rzv2h_ddiv_clk_divider_ops = {
277 .recalc_rate = rzv2h_ddiv_recalc_rate,
278 .round_rate = rzv2h_ddiv_round_rate,
279 .determine_rate = rzv2h_ddiv_determine_rate,
280 .set_rate = rzv2h_ddiv_set_rate,
281 };
282
283 static struct clk * __init
rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk * core,struct rzv2h_cpg_priv * priv)284 rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
285 struct rzv2h_cpg_priv *priv)
286 {
287 struct ddiv cfg_ddiv = core->cfg.ddiv;
288 struct clk_init_data init = {};
289 struct device *dev = priv->dev;
290 u8 shift = cfg_ddiv.shift;
291 u8 width = cfg_ddiv.width;
292 const struct clk *parent;
293 const char *parent_name;
294 struct clk_divider *div;
295 struct ddiv_clk *ddiv;
296 int ret;
297
298 parent = priv->clks[core->parent];
299 if (IS_ERR(parent))
300 return ERR_CAST(parent);
301
302 parent_name = __clk_get_name(parent);
303
304 if ((shift + width) > 16)
305 return ERR_PTR(-EINVAL);
306
307 ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL);
308 if (!ddiv)
309 return ERR_PTR(-ENOMEM);
310
311 init.name = core->name;
312 init.ops = &rzv2h_ddiv_clk_divider_ops;
313 init.parent_names = &parent_name;
314 init.num_parents = 1;
315 init.flags = CLK_SET_RATE_PARENT;
316
317 ddiv->priv = priv;
318 ddiv->mon = cfg_ddiv.monbit;
319 div = &ddiv->div;
320 div->reg = priv->base + cfg_ddiv.offset;
321 div->shift = shift;
322 div->width = width;
323 div->flags = core->flag;
324 div->lock = &priv->rmw_lock;
325 div->hw.init = &init;
326 div->table = core->dtable;
327
328 ret = devm_clk_hw_register(dev, &div->hw);
329 if (ret)
330 return ERR_PTR(ret);
331
332 return div->hw.clk;
333 }
334
335 static struct clk
rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args * clkspec,void * data)336 *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
337 void *data)
338 {
339 unsigned int clkidx = clkspec->args[1];
340 struct rzv2h_cpg_priv *priv = data;
341 struct device *dev = priv->dev;
342 const char *type;
343 struct clk *clk;
344
345 switch (clkspec->args[0]) {
346 case CPG_CORE:
347 type = "core";
348 if (clkidx > priv->last_dt_core_clk) {
349 dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
350 return ERR_PTR(-EINVAL);
351 }
352 clk = priv->clks[clkidx];
353 break;
354
355 case CPG_MOD:
356 type = "module";
357 if (clkidx >= priv->num_mod_clks) {
358 dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
359 return ERR_PTR(-EINVAL);
360 }
361 clk = priv->clks[priv->num_core_clks + clkidx];
362 break;
363
364 default:
365 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
366 return ERR_PTR(-EINVAL);
367 }
368
369 if (IS_ERR(clk))
370 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
371 PTR_ERR(clk));
372 else
373 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
374 clkspec->args[0], clkspec->args[1], clk,
375 clk_get_rate(clk));
376 return clk;
377 }
378
379 static void __init
rzv2h_cpg_register_core_clk(const struct cpg_core_clk * core,struct rzv2h_cpg_priv * priv)380 rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
381 struct rzv2h_cpg_priv *priv)
382 {
383 struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
384 unsigned int id = core->id, div = core->div;
385 struct device *dev = priv->dev;
386 const char *parent_name;
387 struct clk_hw *clk_hw;
388
389 WARN_DEBUG(id >= priv->num_core_clks);
390 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
391
392 switch (core->type) {
393 case CLK_TYPE_IN:
394 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
395 break;
396 case CLK_TYPE_FF:
397 WARN_DEBUG(core->parent >= priv->num_core_clks);
398 parent = priv->clks[core->parent];
399 if (IS_ERR(parent)) {
400 clk = parent;
401 goto fail;
402 }
403
404 parent_name = __clk_get_name(parent);
405 clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,
406 parent_name, CLK_SET_RATE_PARENT,
407 core->mult, div);
408 if (IS_ERR(clk_hw))
409 clk = ERR_CAST(clk_hw);
410 else
411 clk = clk_hw->clk;
412 break;
413 case CLK_TYPE_PLL:
414 clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
415 break;
416 case CLK_TYPE_DDIV:
417 clk = rzv2h_cpg_ddiv_clk_register(core, priv);
418 break;
419 default:
420 goto fail;
421 }
422
423 if (IS_ERR_OR_NULL(clk))
424 goto fail;
425
426 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
427 priv->clks[id] = clk;
428 return;
429
430 fail:
431 dev_err(dev, "Failed to register core clock %s: %ld\n",
432 core->name, PTR_ERR(clk));
433 }
434
rzv2h_mod_clock_endisable(struct clk_hw * hw,bool enable)435 static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
436 {
437 struct mod_clock *clock = to_mod_clock(hw);
438 unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
439 struct rzv2h_cpg_priv *priv = clock->priv;
440 u32 bitmask = BIT(clock->on_bit);
441 struct device *dev = priv->dev;
442 u32 value;
443 int error;
444
445 dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
446 enable ? "ON" : "OFF");
447
448 value = bitmask << 16;
449 if (enable)
450 value |= bitmask;
451
452 writel(value, priv->base + reg);
453
454 if (!enable || clock->mon_index < 0)
455 return 0;
456
457 reg = GET_CLK_MON_OFFSET(clock->mon_index);
458 bitmask = BIT(clock->mon_bit);
459 error = readl_poll_timeout_atomic(priv->base + reg, value,
460 value & bitmask, 0, 10);
461 if (error)
462 dev_err(dev, "Failed to enable CLK_ON %p\n",
463 priv->base + reg);
464
465 return error;
466 }
467
rzv2h_mod_clock_enable(struct clk_hw * hw)468 static int rzv2h_mod_clock_enable(struct clk_hw *hw)
469 {
470 return rzv2h_mod_clock_endisable(hw, true);
471 }
472
rzv2h_mod_clock_disable(struct clk_hw * hw)473 static void rzv2h_mod_clock_disable(struct clk_hw *hw)
474 {
475 rzv2h_mod_clock_endisable(hw, false);
476 }
477
rzv2h_mod_clock_is_enabled(struct clk_hw * hw)478 static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
479 {
480 struct mod_clock *clock = to_mod_clock(hw);
481 struct rzv2h_cpg_priv *priv = clock->priv;
482 u32 bitmask;
483 u32 offset;
484
485 if (clock->mon_index >= 0) {
486 offset = GET_CLK_MON_OFFSET(clock->mon_index);
487 bitmask = BIT(clock->mon_bit);
488 } else {
489 offset = GET_CLK_ON_OFFSET(clock->on_index);
490 bitmask = BIT(clock->on_bit);
491 }
492
493 return readl(priv->base + offset) & bitmask;
494 }
495
496 static const struct clk_ops rzv2h_mod_clock_ops = {
497 .enable = rzv2h_mod_clock_enable,
498 .disable = rzv2h_mod_clock_disable,
499 .is_enabled = rzv2h_mod_clock_is_enabled,
500 };
501
502 static void __init
rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk * mod,struct rzv2h_cpg_priv * priv)503 rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
504 struct rzv2h_cpg_priv *priv)
505 {
506 struct mod_clock *clock = NULL;
507 struct device *dev = priv->dev;
508 struct clk_init_data init;
509 struct clk *parent, *clk;
510 const char *parent_name;
511 unsigned int id;
512 int ret;
513
514 id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);
515 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
516 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
517 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
518
519 parent = priv->clks[mod->parent];
520 if (IS_ERR(parent)) {
521 clk = parent;
522 goto fail;
523 }
524
525 clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
526 if (!clock) {
527 clk = ERR_PTR(-ENOMEM);
528 goto fail;
529 }
530
531 init.name = mod->name;
532 init.ops = &rzv2h_mod_clock_ops;
533 init.flags = CLK_SET_RATE_PARENT;
534 if (mod->critical)
535 init.flags |= CLK_IS_CRITICAL;
536
537 parent_name = __clk_get_name(parent);
538 init.parent_names = &parent_name;
539 init.num_parents = 1;
540
541 clock->on_index = mod->on_index;
542 clock->on_bit = mod->on_bit;
543 clock->mon_index = mod->mon_index;
544 clock->mon_bit = mod->mon_bit;
545 clock->priv = priv;
546 clock->hw.init = &init;
547
548 ret = devm_clk_hw_register(dev, &clock->hw);
549 if (ret) {
550 clk = ERR_PTR(ret);
551 goto fail;
552 }
553
554 priv->clks[id] = clock->hw.clk;
555
556 return;
557
558 fail:
559 dev_err(dev, "Failed to register module clock %s: %ld\n",
560 mod->name, PTR_ERR(clk));
561 }
562
rzv2h_cpg_assert(struct reset_controller_dev * rcdev,unsigned long id)563 static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
564 unsigned long id)
565 {
566 struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
567 unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
568 u32 mask = BIT(priv->resets[id].reset_bit);
569 u8 monbit = priv->resets[id].mon_bit;
570 u32 value = mask << 16;
571
572 dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
573
574 writel(value, priv->base + reg);
575
576 reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
577 mask = BIT(monbit);
578
579 return readl_poll_timeout_atomic(priv->base + reg, value,
580 value & mask, 10, 200);
581 }
582
rzv2h_cpg_deassert(struct reset_controller_dev * rcdev,unsigned long id)583 static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
584 unsigned long id)
585 {
586 struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
587 unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
588 u32 mask = BIT(priv->resets[id].reset_bit);
589 u8 monbit = priv->resets[id].mon_bit;
590 u32 value = (mask << 16) | mask;
591
592 dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
593
594 writel(value, priv->base + reg);
595
596 reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
597 mask = BIT(monbit);
598
599 return readl_poll_timeout_atomic(priv->base + reg, value,
600 !(value & mask), 10, 200);
601 }
602
rzv2h_cpg_reset(struct reset_controller_dev * rcdev,unsigned long id)603 static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
604 unsigned long id)
605 {
606 int ret;
607
608 ret = rzv2h_cpg_assert(rcdev, id);
609 if (ret)
610 return ret;
611
612 return rzv2h_cpg_deassert(rcdev, id);
613 }
614
rzv2h_cpg_status(struct reset_controller_dev * rcdev,unsigned long id)615 static int rzv2h_cpg_status(struct reset_controller_dev *rcdev,
616 unsigned long id)
617 {
618 struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
619 unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
620 u8 monbit = priv->resets[id].mon_bit;
621
622 return !!(readl(priv->base + reg) & BIT(monbit));
623 }
624
625 static const struct reset_control_ops rzv2h_cpg_reset_ops = {
626 .reset = rzv2h_cpg_reset,
627 .assert = rzv2h_cpg_assert,
628 .deassert = rzv2h_cpg_deassert,
629 .status = rzv2h_cpg_status,
630 };
631
rzv2h_cpg_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)632 static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev,
633 const struct of_phandle_args *reset_spec)
634 {
635 struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
636 unsigned int id = reset_spec->args[0];
637 u8 rst_index = id / 16;
638 u8 rst_bit = id % 16;
639 unsigned int i;
640
641 for (i = 0; i < rcdev->nr_resets; i++) {
642 if (rst_index == priv->resets[i].reset_index &&
643 rst_bit == priv->resets[i].reset_bit)
644 return i;
645 }
646
647 return -EINVAL;
648 }
649
rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv * priv)650 static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv)
651 {
652 priv->rcdev.ops = &rzv2h_cpg_reset_ops;
653 priv->rcdev.of_node = priv->dev->of_node;
654 priv->rcdev.dev = priv->dev;
655 priv->rcdev.of_reset_n_cells = 1;
656 priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;
657 priv->rcdev.nr_resets = priv->num_resets;
658
659 return devm_reset_controller_register(priv->dev, &priv->rcdev);
660 }
661
662 /**
663 * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
664 * @priv: pointer to CPG private data structure
665 * @genpd: generic PM domain
666 */
667 struct rzv2h_cpg_pd {
668 struct rzv2h_cpg_priv *priv;
669 struct generic_pm_domain genpd;
670 };
671
rzv2h_cpg_attach_dev(struct generic_pm_domain * domain,struct device * dev)672 static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
673 {
674 struct device_node *np = dev->of_node;
675 struct of_phandle_args clkspec;
676 bool once = true;
677 struct clk *clk;
678 int error;
679 int i = 0;
680
681 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
682 &clkspec)) {
683 if (once) {
684 once = false;
685 error = pm_clk_create(dev);
686 if (error) {
687 of_node_put(clkspec.np);
688 goto err;
689 }
690 }
691 clk = of_clk_get_from_provider(&clkspec);
692 of_node_put(clkspec.np);
693 if (IS_ERR(clk)) {
694 error = PTR_ERR(clk);
695 goto fail_destroy;
696 }
697
698 error = pm_clk_add_clk(dev, clk);
699 if (error) {
700 dev_err(dev, "pm_clk_add_clk failed %d\n",
701 error);
702 goto fail_put;
703 }
704 i++;
705 }
706
707 return 0;
708
709 fail_put:
710 clk_put(clk);
711
712 fail_destroy:
713 pm_clk_destroy(dev);
714 err:
715 return error;
716 }
717
rzv2h_cpg_detach_dev(struct generic_pm_domain * unused,struct device * dev)718 static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
719 {
720 if (!pm_clk_no_clocks(dev))
721 pm_clk_destroy(dev);
722 }
723
rzv2h_cpg_genpd_remove_simple(void * data)724 static void rzv2h_cpg_genpd_remove_simple(void *data)
725 {
726 pm_genpd_remove(data);
727 }
728
rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv * priv)729 static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv)
730 {
731 struct device *dev = priv->dev;
732 struct device_node *np = dev->of_node;
733 struct rzv2h_cpg_pd *pd;
734 int ret;
735
736 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
737 if (!pd)
738 return -ENOMEM;
739
740 pd->genpd.name = np->name;
741 pd->priv = priv;
742 pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
743 pd->genpd.attach_dev = rzv2h_cpg_attach_dev;
744 pd->genpd.detach_dev = rzv2h_cpg_detach_dev;
745 ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);
746 if (ret)
747 return ret;
748
749 ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);
750 if (ret)
751 return ret;
752
753 return of_genpd_add_provider_simple(np, &pd->genpd);
754 }
755
rzv2h_cpg_del_clk_provider(void * data)756 static void rzv2h_cpg_del_clk_provider(void *data)
757 {
758 of_clk_del_provider(data);
759 }
760
rzv2h_cpg_probe(struct platform_device * pdev)761 static int __init rzv2h_cpg_probe(struct platform_device *pdev)
762 {
763 struct device *dev = &pdev->dev;
764 struct device_node *np = dev->of_node;
765 const struct rzv2h_cpg_info *info;
766 struct rzv2h_cpg_priv *priv;
767 unsigned int nclks, i;
768 struct clk **clks;
769 int error;
770
771 info = of_device_get_match_data(dev);
772
773 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
774 if (!priv)
775 return -ENOMEM;
776
777 spin_lock_init(&priv->rmw_lock);
778
779 priv->dev = dev;
780
781 priv->base = devm_platform_ioremap_resource(pdev, 0);
782 if (IS_ERR(priv->base))
783 return PTR_ERR(priv->base);
784
785 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
786 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
787 if (!clks)
788 return -ENOMEM;
789
790 priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
791 info->num_resets, GFP_KERNEL);
792 if (!priv->resets)
793 return -ENOMEM;
794
795 dev_set_drvdata(dev, priv);
796 priv->clks = clks;
797 priv->num_core_clks = info->num_total_core_clks;
798 priv->num_mod_clks = info->num_hw_mod_clks;
799 priv->last_dt_core_clk = info->last_dt_core_clk;
800 priv->num_resets = info->num_resets;
801
802 for (i = 0; i < nclks; i++)
803 clks[i] = ERR_PTR(-ENOENT);
804
805 for (i = 0; i < info->num_core_clks; i++)
806 rzv2h_cpg_register_core_clk(&info->core_clks[i], priv);
807
808 for (i = 0; i < info->num_mod_clks; i++)
809 rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);
810
811 error = of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv);
812 if (error)
813 return error;
814
815 error = devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np);
816 if (error)
817 return error;
818
819 error = rzv2h_cpg_add_pm_domains(priv);
820 if (error)
821 return error;
822
823 error = rzv2h_cpg_reset_controller_register(priv);
824 if (error)
825 return error;
826
827 return 0;
828 }
829
830 static const struct of_device_id rzv2h_cpg_match[] = {
831 #ifdef CONFIG_CLK_R9A09G057
832 {
833 .compatible = "renesas,r9a09g057-cpg",
834 .data = &r9a09g057_cpg_info,
835 },
836 #endif
837 { /* sentinel */ }
838 };
839
840 static struct platform_driver rzv2h_cpg_driver = {
841 .driver = {
842 .name = "rzv2h-cpg",
843 .of_match_table = rzv2h_cpg_match,
844 },
845 };
846
rzv2h_cpg_init(void)847 static int __init rzv2h_cpg_init(void)
848 {
849 return platform_driver_probe(&rzv2h_cpg_driver, rzv2h_cpg_probe);
850 }
851
852 subsys_initcall(rzv2h_cpg_init);
853
854 MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");
855