1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
4 * Author: Sunyeal Hong <sunyeal.hong@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto v920 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynosautov920.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
21 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
22
23 /* ---- CMU_TOP ------------------------------------------------------------ */
24
25 /* Register Offset definitions for CMU_TOP (0x11000000) */
26 #define PLL_LOCKTIME_PLL_MMC 0x0004
27 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
28 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
29 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
30 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
31 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
32 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
33 #define PLL_CON0_PLL_MMC 0x0140
34 #define PLL_CON3_PLL_MMC 0x014c
35 #define PLL_CON0_PLL_SHARED0 0x0180
36 #define PLL_CON3_PLL_SHARED0 0x018c
37 #define PLL_CON0_PLL_SHARED1 0x01c0
38 #define PLL_CON3_PLL_SHARED1 0x01cc
39 #define PLL_CON0_PLL_SHARED2 0x0200
40 #define PLL_CON3_PLL_SHARED2 0x020c
41 #define PLL_CON0_PLL_SHARED3 0x0240
42 #define PLL_CON3_PLL_SHARED3 0x024c
43 #define PLL_CON0_PLL_SHARED4 0x0280
44 #define PLL_CON3_PLL_SHARED4 0x028c
45 #define PLL_CON0_PLL_SHARED5 0x02c0
46 #define PLL_CON3_PLL_SHARED5 0x02cc
47
48 /* MUX */
49 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
50 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
51 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
52 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
55 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
57 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
58 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
59 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
65 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
66 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
67 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
68 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
69 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
70 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
71 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
72 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
73 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
74 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
75 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
76 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
77 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
78 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
79 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
80 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
88 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
89 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
90 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
91 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
92 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
93 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
94 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
95 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
96 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
97 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
98 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
99 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
103 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
104 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
105 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
106 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
107 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
108 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
109 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
110 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
111
112 /* DIV */
113 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
114 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
115 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
116 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
117 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
118 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
119 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
120 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
121 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
122 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
123 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
124 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
125 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
126 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
127 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
128 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
129 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
130 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
131 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
132 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
133 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
134 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
135 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
136 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
137 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
138 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
139 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
140 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
141 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
142 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
143 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
144 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
145 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
146 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
147 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
148 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
149 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
150 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
151 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
152 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
153 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
154 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
155 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
156 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
157 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
158 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
159 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
160 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
161 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
162 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
163 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
164 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
165 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
166 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
167 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
168 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
169 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
170 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
171 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
172 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
173 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
174
175 static const unsigned long top_clk_regs[] __initconst = {
176 PLL_LOCKTIME_PLL_MMC,
177 PLL_LOCKTIME_PLL_SHARED0,
178 PLL_LOCKTIME_PLL_SHARED1,
179 PLL_LOCKTIME_PLL_SHARED2,
180 PLL_LOCKTIME_PLL_SHARED3,
181 PLL_LOCKTIME_PLL_SHARED4,
182 PLL_LOCKTIME_PLL_SHARED5,
183 PLL_CON0_PLL_MMC,
184 PLL_CON3_PLL_MMC,
185 PLL_CON0_PLL_SHARED0,
186 PLL_CON3_PLL_SHARED0,
187 PLL_CON0_PLL_SHARED1,
188 PLL_CON3_PLL_SHARED1,
189 PLL_CON0_PLL_SHARED2,
190 PLL_CON3_PLL_SHARED2,
191 PLL_CON0_PLL_SHARED3,
192 PLL_CON3_PLL_SHARED3,
193 PLL_CON0_PLL_SHARED4,
194 PLL_CON3_PLL_SHARED4,
195 PLL_CON0_PLL_SHARED5,
196 PLL_CON3_PLL_SHARED5,
197 CLK_CON_MUX_MUX_CLKCMU_ACC_NOC,
198 CLK_CON_MUX_MUX_CLKCMU_APM_NOC,
199 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
200 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
201 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0,
202 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1,
203 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2,
204 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3,
205 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
206 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
207 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
208 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
209 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
210 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
211 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
212 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
213 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
214 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
215 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC,
216 CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC,
217 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
218 CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC,
219 CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC,
220 CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC,
221 CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC,
222 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
223 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
224 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
225 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
226 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
227 CLK_CON_MUX_MUX_CLKCMU_ACC_ORB,
228 CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA,
229 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
230 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
231 CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
232 CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
233 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
234 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
235 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
236 CLK_CON_MUX_MUX_CLKCMU_ISP_NOC,
237 CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG,
238 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
239 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
240 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
241 CLK_CON_MUX_MUX_CLKCMU_MFD_NOC,
242 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
243 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
244 CLK_CON_MUX_MUX_CLKCMU_MISC_NOC,
245 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
246 CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC,
247 CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC,
248 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
249 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
250 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
251 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
252 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
253 CLK_CON_MUX_MUX_CLKCMU_SNW_NOC,
254 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
255 CLK_CON_MUX_MUX_CLKCMU_TAA_NOC,
256 CLK_CON_MUX_MUX_CLK_CMU_NOCP,
257 CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT,
258 CLK_CON_MUX_MUX_CMU_CMUREF,
259 CLK_CON_DIV_CLKCMU_ACC_NOC,
260 CLK_CON_DIV_CLKCMU_APM_NOC,
261 CLK_CON_DIV_CLKCMU_AUD_CPU,
262 CLK_CON_DIV_CLKCMU_AUD_NOC,
263 CLK_CON_DIV_CLKCMU_CIS_MCLK0,
264 CLK_CON_DIV_CLKCMU_CIS_MCLK1,
265 CLK_CON_DIV_CLKCMU_CIS_MCLK2,
266 CLK_CON_DIV_CLKCMU_CIS_MCLK3,
267 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
268 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
269 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
270 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
271 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
272 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER,
273 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
274 CLK_CON_DIV_CLKCMU_DNC_NOC,
275 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
276 CLK_CON_DIV_CLKCMU_DPTX_DPOSC,
277 CLK_CON_DIV_CLKCMU_DPTX_NOC,
278 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
279 CLK_CON_DIV_CLKCMU_DPUB_NOC,
280 CLK_CON_DIV_CLKCMU_DPUF0_NOC,
281 CLK_CON_DIV_CLKCMU_DPUF1_NOC,
282 CLK_CON_DIV_CLKCMU_DPUF2_NOC,
283 CLK_CON_DIV_CLKCMU_DSP_NOC,
284 CLK_CON_DIV_CLKCMU_G3D_NOCP,
285 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
286 CLK_CON_DIV_CLKCMU_GNPU_NOC,
287 CLK_CON_DIV_CLKCMU_HSI0_NOC,
288 CLK_CON_DIV_CLKCMU_ACC_ORB,
289 CLK_CON_DIV_CLKCMU_GNPU_XMAA,
290 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
291 CLK_CON_DIV_CLKCMU_HSI1_NOC,
292 CLK_CON_DIV_CLKCMU_HSI1_USBDRD,
293 CLK_CON_DIV_CLKCMU_HSI2_ETHERNET,
294 CLK_CON_DIV_CLKCMU_HSI2_NOC,
295 CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS,
296 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
297 CLK_CON_DIV_CLKCMU_ISP_NOC,
298 CLK_CON_DIV_CLKCMU_M2M_JPEG,
299 CLK_CON_DIV_CLKCMU_M2M_NOC,
300 CLK_CON_DIV_CLKCMU_MFC_MFC,
301 CLK_CON_DIV_CLKCMU_MFC_WFD,
302 CLK_CON_DIV_CLKCMU_MFD_NOC,
303 CLK_CON_DIV_CLKCMU_MIF_NOCP,
304 CLK_CON_DIV_CLKCMU_MISC_NOC,
305 CLK_CON_DIV_CLKCMU_NOCL0_NOC,
306 CLK_CON_DIV_CLKCMU_NOCL1_NOC,
307 CLK_CON_DIV_CLKCMU_NOCL2_NOC,
308 CLK_CON_DIV_CLKCMU_PERIC0_IP,
309 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
310 CLK_CON_DIV_CLKCMU_PERIC1_IP,
311 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
312 CLK_CON_DIV_CLKCMU_SDMA_NOC,
313 CLK_CON_DIV_CLKCMU_SNW_NOC,
314 CLK_CON_DIV_CLKCMU_SSP_NOC,
315 CLK_CON_DIV_CLKCMU_TAA_NOC,
316 CLK_CON_DIV_CLK_ADD_CH_CLK,
317 CLK_CON_DIV_CLK_CMU_PLLCLKOUT,
318 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
319 CLK_CON_DIV_DIV_CLK_CMU_NOCP,
320 };
321
322 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
323 /* CMU_TOP_PURECLKCOMP */
324 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
325 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
326 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
327 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
328 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
329 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
330 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
331 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
332 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
333 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
334 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
335 PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL),
336 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
337 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
338 };
339
340 /* List of parent clocks for Muxes in CMU_TOP */
341 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
342 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
343 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
344 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
345 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
346 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" };
347 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
348
349 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
350 "dout_shared2_div4", "dout_shared4_div4" };
351
352 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
353
354 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
355 "dout_shared4_div2", "dout_shared1_div3",
356 "dout_shared2_div3", "dout_shared5_div1",
357 "dout_shared3_div1", "oscclk" };
358
359 PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3",
360 "dout_shared1_div2", "dout_shared1_div3",
361 "dout_shared2_div3", "fout_shared5_pll",
362 "fout_shared3_pll", "oscclk" };
363
364 PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4",
365 "dout_shared2_div4", "dout_shared4_div4" };
366
367 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
368 "dout_shared2_div2", "dout_shared0_div3",
369 "dout_shared4_div2", "dout_shared1_div3",
370 "dout_shared2_div3", "dout_shared4_div3" };
371
372 PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2",
373 "dout_shared1_div2", "dout_shared2_div3" };
374
375 PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
376 "dout_shared2_div2", "dout_shared4_div2" };
377
378 PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
379 "dout_shared0_div2", "dout_shared1_div2",
380 "dout_shared2_div2", "dout_shared4_div2",
381 "dout_shared2_div3", "fout_shared3_pll" };
382
383 PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3",
384 "dout_shared4_div2", "dout_shared0_div4" };
385
386 PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
387 "dout_shared2_div2", "dout_shared4_div2" };
388
389 PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
390 "dout_shared0_div2", "dout_shared1_div2",
391 "dout_shared2_div2", "dout_shared4_div2",
392 "dout_shared2_div3", "fout_shared3_pll" };
393
394 PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
395 "dout_shared2_div2", "dout_shared4_div2" };
396
397 PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
398 "dout_shared0_div2", "dout_shared1_div2",
399 "dout_shared2_div2", "dout_shared4_div2",
400 "dout_shared2_div3", "fout_shared3_pll" };
401
402 PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
403 "dout_shared0_div3", "dout_shared4_div2",
404 "dout_shared1_div3", "dout_shared2_div3",
405 "dout_shared1_div4", "fout_shared3_pll" };
406
407 PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
408 "dout_shared1_div4", "dout_shared2_div4" };
409
410 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
411 "dout_shared2_div4", "dout_shared4_div4" };
412
413 PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" };
414
415 PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
416 "dout_shared2_div3", "dout_shared1_div4",
417 "dout_shared2_div4", "dout_shared4_div4",
418 "fout_shared3_pll" };
419
420 PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" };
421
422 PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
423 "dout_shared2_div3", "dout_shared1_div4",
424 "dout_shared2_div4", "dout_shared4_div4",
425 "fout_shared3_pll" };
426
427 PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
428 "dout_shared2_div2", "dout_shared0_div3",
429 "dout_shared4_div2", "dout_shared1_div3",
430 "fout_shared5_pll", "fout_shared3_pll" };
431
432 PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
433 "dout_shared2_div2", "dout_shared4_div2" };
434
435 PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
436 "dout_shared2_div4", "dout_shared4_div4" };
437
438 PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
439 "dout_shared2_div2", "dout_shared0_div3",
440 "dout_shared4_div2", "dout_shared2_div3",
441 "fout_shared5_pll", "fout_shared3_pll" };
442
443 PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
444 "dout_shared1_div4", "dout_shared2_div4" };
445
446 PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
447 "dout_shared2_div4", "dout_shared4_div4" };
448
449 PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3",
450 "dout_shared2_div4", "dout_shared4_div4" };
451
452 PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2",
453 "dout_shared4_div2", "fout_mmc_pll" };
454
455 PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
456 "dout_shared1_div4", "dout_shared2_div4" };
457
458 PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3",
459 "dout_shared1_div4", "dout_shared2_div2" };
460
461 PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3",
462 "dout_shared2_div4", "dout_shared4_div4" };
463
464 PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2",
465 "dout_shared0_div3", "dout_shared1_div3" };
466
467 PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
468 "dout_shared4_div2", "dout_shared1_div3",
469 "dout_shared2_div3", "fout_shared5_pll",
470 "fout_shared3_pll", "oscclk" };
471
472 PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2",
473 "dout_shared2_div3", "dout_shared1_div4" };
474
475 PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2",
476 "dout_shared2_div3", "dout_shared1_div4" };
477
478 PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2",
479 "dout_shared2_div3", "dout_shared1_div4" };
480
481 PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2",
482 "dout_shared2_div3", "dout_shared1_div4" };
483
484 PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
485 "dout_shared4_div2", "dout_shared1_div3",
486 "dout_shared2_div3", "fout_shared5_pll",
487 "fout_shared3_pll", "oscclk" };
488
489 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
490 "fout_shared2_pll", "fout_shared4_pll",
491 "dout_shared0_div2", "dout_shared1_div2",
492 "dout_shared2_div2", "fout_shared5_pll" };
493
494 PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
495 "dout_shared2_div4", "dout_shared4_div4" };
496
497 PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
498 "dout_shared1_div4", "dout_shared2_div4" };
499
500 PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
501 "dout_shared2_div2", "dout_shared0_div3",
502 "dout_shared4_div2", "dout_shared1_div3",
503 "dout_shared2_div3", "fout_shared3_pll" };
504
505 PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
506 "dout_shared4_div2", "dout_shared1_div3",
507 "dout_shared2_div3", "fout_shared5_pll",
508 "fout_shared3_pll", "oscclk" };
509
510 PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
511 "dout_shared4_div2", "dout_shared1_div3",
512 "dout_shared2_div3", "fout_shared5_pll",
513 "fout_shared3_pll", "oscclk" };
514
515 PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
516
517 PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
518
519 PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
520
521 PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
522
523 PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
524 "dout_shared0_div3", "dout_shared4_div2",
525 "dout_shared1_div3", "dout_shared2_div3",
526 "dout_shared1_div4", "fout_shared3_pll" };
527
528 PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
529 "dout_shared4_div2", "dout_shared1_div3",
530 "dout_shared2_div3", "fout_shared5_pll",
531 "fout_shared3_pll", "oscclk" };
532
533 PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
534 "dout_shared2_div2", "dout_shared4_div4" };
535
536 PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
537 "dout_shared4_div2", "dout_shared1_div3",
538 "dout_shared2_div3", "fout_shared5_pll",
539 "fout_shared3_pll", "oscclk" };
540
541 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
542 /* CMU_TOP_PURECLKCOMP */
543 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
544 PLL_CON0_PLL_SHARED0, 4, 1),
545 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
546 PLL_CON0_PLL_SHARED1, 4, 1),
547 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
548 PLL_CON0_PLL_SHARED2, 4, 1),
549 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
550 PLL_CON0_PLL_SHARED3, 4, 1),
551 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
552 PLL_CON0_PLL_SHARED4, 4, 1),
553 MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p,
554 PLL_CON0_PLL_SHARED5, 4, 1),
555 MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
556 PLL_CON0_PLL_MMC, 4, 1),
557
558 /* BOOST */
559 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
560 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
561 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
562 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
563
564 /* ACC */
565 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc",
566 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
567 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb",
568 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
569
570 /* APM */
571 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc",
572 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
573
574 /* AUD */
575 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu",
576 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
577 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc",
578 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
579
580 /* CPUCL0 */
581 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
582 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
583 0, 2),
584 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
585 mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
586 0, 3),
587 MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg",
588 mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
589 0, 2),
590
591 /* CPUCL1 */
592 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
593 mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
594 0, 2),
595 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
596 mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
597 0, 3),
598
599 /* CPUCL2 */
600 MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch",
601 mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
602 0, 2),
603 MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster",
604 mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
605 0, 3),
606
607 /* DNC */
608 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc",
609 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
610
611 /* DPTX */
612 MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc",
613 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
614 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
615 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
616 MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc",
617 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
618
619 /* DPUB */
620 MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc",
621 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
622 MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim",
623 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
624
625 /* DPUF */
626 MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc",
627 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
628 MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc",
629 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
630 MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc",
631 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
632
633 /* DSP */
634 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc",
635 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
636
637 /* G3D */
638 MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch",
639 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
640 MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp",
641 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
642
643 /* GNPU */
644 MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc",
645 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
646
647 /* HSI0 */
648 MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc",
649 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
650
651 /* HSI1 */
652 MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc",
653 mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
654 0, 2),
655 MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd",
656 mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
657 0, 2),
658 MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card",
659 mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
660 0, 2),
661
662 /* HSI2 */
663 MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc",
664 mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
665 0, 2),
666 MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs",
667 mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
668 0, 2),
669 MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd",
670 mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
671 0, 2),
672 MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet",
673 mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
674 0, 2),
675
676 /* ISP */
677 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc",
678 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
679
680 /* M2M */
681 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc",
682 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
683 MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg",
684 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
685
686 /* MFC */
687 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
688 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
689 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
690 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
691
692 /* MFD */
693 MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc",
694 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
695
696 /* MIF */
697 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
698 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
699 MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp",
700 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
701
702 /* MISC */
703 MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc",
704 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
705
706 /* NOCL0 */
707 MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc",
708 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
709
710 /* NOCL1 */
711 MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc",
712 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
713
714 /* NOCL2 */
715 MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc",
716 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
717
718 /* PERIC0 */
719 MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc",
720 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
721 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
722 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
723
724 /* PERIC1 */
725 MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc",
726 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
727 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
728 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
729
730 /* SDMA */
731 MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc",
732 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
733
734 /* SNW */
735 MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc",
736 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
737
738 /* SSP */
739 MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc",
740 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
741
742 /* TAA */
743 MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc",
744 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
745 };
746
747 static const struct samsung_div_clock top_div_clks[] __initconst = {
748 /* CMU_TOP_PURECLKCOMP */
749
750 /* BOOST */
751 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
752 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
753
754 /* ACC */
755 DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc",
756 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
757 DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb",
758 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
759
760 /* APM */
761 DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc",
762 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
763
764 /* AUD */
765 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu",
766 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
767 DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc",
768 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
769
770 /* CPUCL0 */
771 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
772 "mout_clkcmu_cpucl0_switch",
773 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
774 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
775 "mout_clkcmu_cpucl0_cluster",
776 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
777 DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg",
778 "mout_clkcmu_cpucl0_dbg",
779 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
780
781 /* CPUCL1 */
782 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
783 "mout_clkcmu_cpucl1_switch",
784 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
785 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
786 "mout_clkcmu_cpucl1_cluster",
787 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
788
789 /* CPUCL2 */
790 DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch",
791 "mout_clkcmu_cpucl2_switch",
792 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
793 DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster",
794 "mout_clkcmu_cpucl2_cluster",
795 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
796
797 /* DNC */
798 DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc",
799 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
800
801 /* DPTX */
802 DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc",
803 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
804 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
805 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
806 DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc",
807 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
808
809 /* DPUB */
810 DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc",
811 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
812 DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim",
813 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
814
815 /* DPUF */
816 DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc",
817 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
818 DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc",
819 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
820 DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc",
821 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
822
823 /* DSP */
824 DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc",
825 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
826
827 /* G3D */
828 DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch",
829 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
830 DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp",
831 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
832
833 /* GNPU */
834 DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc",
835 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
836
837 /* HSI0 */
838 DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc",
839 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
840
841 /* HSI1 */
842 DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc",
843 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
844 DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd",
845 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
846 DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card",
847 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
848
849 /* HSI2 */
850 DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc",
851 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
852 DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs",
853 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
854 DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd",
855 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
856 DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet",
857 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
858
859 /* ISP */
860 DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc",
861 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
862
863 /* M2M */
864 DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc",
865 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
866 DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg",
867 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
868
869 /* MFC */
870 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc",
871 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
872 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd",
873 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
874
875 /* MFD */
876 DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc",
877 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
878
879 /* MIF */
880 DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp",
881 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
882
883 /* MISC */
884 DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc",
885 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
886
887 /* NOCL0 */
888 DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc",
889 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
890
891 /* NOCL1 */
892 DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc",
893 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
894
895 /* NOCL2 */
896 DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc",
897 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
898
899 /* PERIC0 */
900 DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc",
901 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
902 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
903 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
904
905 /* PERIC1 */
906 DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc",
907 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
908 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
909 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
910
911 /* SDMA */
912 DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc",
913 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
914
915 /* SNW */
916 DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc",
917 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
918
919 /* SSP */
920 DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc",
921 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
922
923 /* TAA */
924 DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc",
925 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
926 };
927
928 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
929 FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
930 "mout_shared0_pll", 1, 1, 0),
931 FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
932 "mout_shared0_pll", 1, 2, 0),
933 FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
934 "mout_shared0_pll", 1, 3, 0),
935 FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
936 "mout_shared0_pll", 1, 4, 0),
937 FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
938 "mout_shared1_pll", 1, 1, 0),
939 FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
940 "mout_shared1_pll", 1, 2, 0),
941 FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
942 "mout_shared1_pll", 1, 3, 0),
943 FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
944 "mout_shared1_pll", 1, 4, 0),
945 FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
946 "mout_shared2_pll", 1, 1, 0),
947 FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
948 "mout_shared2_pll", 1, 2, 0),
949 FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
950 "mout_shared2_pll", 1, 3, 0),
951 FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
952 "mout_shared2_pll", 1, 4, 0),
953 FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
954 "mout_shared3_pll", 1, 1, 0),
955 FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
956 "mout_shared3_pll", 1, 2, 0),
957 FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
958 "mout_shared3_pll", 1, 3, 0),
959 FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
960 "mout_shared3_pll", 1, 4, 0),
961 FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
962 "mout_shared4_pll", 1, 1, 0),
963 FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
964 "mout_shared4_pll", 1, 2, 0),
965 FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
966 "mout_shared4_pll", 1, 3, 0),
967 FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
968 "mout_shared4_pll", 1, 4, 0),
969 FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1",
970 "mout_shared5_pll", 1, 1, 0),
971 FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2",
972 "mout_shared5_pll", 1, 2, 0),
973 FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3",
974 "mout_shared5_pll", 1, 3, 0),
975 FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
976 "mout_shared5_pll", 1, 4, 0),
977 };
978
979 static const struct samsung_cmu_info top_cmu_info __initconst = {
980 .pll_clks = top_pll_clks,
981 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
982 .mux_clks = top_mux_clks,
983 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
984 .div_clks = top_div_clks,
985 .nr_div_clks = ARRAY_SIZE(top_div_clks),
986 .fixed_factor_clks = top_fixed_factor_clks,
987 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
988 .nr_clk_ids = CLKS_NR_TOP,
989 .clk_regs = top_clk_regs,
990 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
991 };
992
exynosautov920_cmu_top_init(struct device_node * np)993 static void __init exynosautov920_cmu_top_init(struct device_node *np)
994 {
995 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
996 }
997
998 /* Register CMU_TOP early, as it's a dependency for other early domains */
999 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1000 exynosautov920_cmu_top_init);
1001
1002 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1003
1004 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1005 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1006 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1007 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1008 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1009 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1010 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1011 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1012 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1013 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1014 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1015 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1016 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1017 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1018 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1019 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1020 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1021 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1022 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1023 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1024 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1025 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1026 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1027 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1028 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1029
1030 static const unsigned long peric0_clk_regs[] __initconst = {
1031 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1032 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
1033 CLK_CON_MUX_MUX_CLK_PERIC0_I3C,
1034 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1035 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1036 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1037 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1038 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1039 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1040 CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI,
1041 CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI,
1042 CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI,
1043 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1044 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
1045 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1046 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1047 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1048 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1049 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1050 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1051 CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1052 CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1053 CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1054 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1055 };
1056
1057 /* List of parent clocks for Muxes in CMU_PERIC0 */
1058 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1059 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" };
1060 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1061
1062 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1063 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1064 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1065 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user",
1066 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1),
1067 /* USI00 ~ USI08 */
1068 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1069 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1070 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1071 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1072 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1073 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1074 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1075 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1076 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1077 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1078 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1079 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1080 MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi",
1081 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1082 MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi",
1083 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1084 MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi",
1085 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1086 /* USI_I2C */
1087 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1088 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1089 /* USI_I3C */
1090 MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c",
1091 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1092 };
1093
1094 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1095 /* USI00 ~ USI08 */
1096 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1097 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1098 0, 4),
1099 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1100 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1101 0, 4),
1102 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1103 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1104 0, 4),
1105 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1106 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1107 0, 4),
1108 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1109 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1110 0, 4),
1111 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1112 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1113 0, 4),
1114 DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi",
1115 "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1116 0, 4),
1117 DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi",
1118 "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1119 0, 4),
1120 DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi",
1121 "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1122 0, 4),
1123 /* USI_I2C */
1124 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1125 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1126 /* USI_I3C */
1127 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c",
1128 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1129 };
1130
1131 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1132 .mux_clks = peric0_mux_clks,
1133 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1134 .div_clks = peric0_div_clks,
1135 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1136 .nr_clk_ids = CLKS_NR_PERIC0,
1137 .clk_regs = peric0_clk_regs,
1138 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1139 .clk_name = "noc",
1140 };
1141
exynosautov920_cmu_probe(struct platform_device * pdev)1142 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1143 {
1144 const struct samsung_cmu_info *info;
1145 struct device *dev = &pdev->dev;
1146
1147 info = of_device_get_match_data(dev);
1148 exynos_arm64_register_cmu(dev, dev->of_node, info);
1149
1150 return 0;
1151 }
1152
1153 static const struct of_device_id exynosautov920_cmu_of_match[] = {
1154 {
1155 .compatible = "samsung,exynosautov920-cmu-peric0",
1156 .data = &peric0_cmu_info,
1157 },
1158 { }
1159 };
1160
1161 static struct platform_driver exynosautov920_cmu_driver __refdata = {
1162 .driver = {
1163 .name = "exynosautov920-cmu",
1164 .of_match_table = exynosautov920_cmu_of_match,
1165 .suppress_bind_attrs = true,
1166 },
1167 .probe = exynosautov920_cmu_probe,
1168 };
1169
exynosautov920_cmu_init(void)1170 static int __init exynosautov920_cmu_init(void)
1171 {
1172 return platform_driver_register(&exynosautov920_cmu_driver);
1173 }
1174 core_initcall(exynosautov920_cmu_init);
1175