1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Copyright (c) 2013 Linaro Ltd.
5 *
6 * This file contains the utility functions to register the pll clocks.
7 */
8
9 #include <linux/errno.h>
10 #include <linux/hrtimer.h>
11 #include <linux/iopoll.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/timekeeping.h>
15 #include <linux/clk-provider.h>
16 #include <linux/io.h>
17 #include "clk.h"
18 #include "clk-pll.h"
19
20 #define PLL_TIMEOUT_US 20000U
21 #define PLL_TIMEOUT_LOOPS 1000000U
22
23 struct samsung_clk_pll {
24 struct clk_hw hw;
25 void __iomem *lock_reg;
26 void __iomem *con_reg;
27 /* PLL enable control bit offset in @con_reg register */
28 unsigned short enable_offs;
29 /* PLL lock status bit offset in @con_reg register */
30 unsigned short lock_offs;
31 enum samsung_pll_type type;
32 unsigned int rate_count;
33 const struct samsung_pll_rate_table *rate_table;
34 };
35
36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
37
samsung_get_pll_settings(struct samsung_clk_pll * pll,unsigned long rate)38 static const struct samsung_pll_rate_table *samsung_get_pll_settings(
39 struct samsung_clk_pll *pll, unsigned long rate)
40 {
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
42 int i;
43
44 for (i = 0; i < pll->rate_count; i++) {
45 if (rate == rate_table[i].rate)
46 return &rate_table[i];
47 }
48
49 return NULL;
50 }
51
samsung_pll_round_rate(struct clk_hw * hw,unsigned long drate,unsigned long * prate)52 static long samsung_pll_round_rate(struct clk_hw *hw,
53 unsigned long drate, unsigned long *prate)
54 {
55 struct samsung_clk_pll *pll = to_clk_pll(hw);
56 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
57 int i;
58
59 /* Assumming rate_table is in descending order */
60 for (i = 0; i < pll->rate_count; i++) {
61 if (drate >= rate_table[i].rate)
62 return rate_table[i].rate;
63 }
64
65 /* return minimum supported value */
66 return rate_table[i - 1].rate;
67 }
68
69 static bool pll_early_timeout = true;
70
samsung_pll_disable_early_timeout(void)71 static int __init samsung_pll_disable_early_timeout(void)
72 {
73 pll_early_timeout = false;
74 return 0;
75 }
76 arch_initcall(samsung_pll_disable_early_timeout);
77
78 /* Wait until the PLL is locked */
samsung_pll_lock_wait(struct samsung_clk_pll * pll,unsigned int reg_mask)79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
80 unsigned int reg_mask)
81 {
82 int i, ret;
83 u32 val;
84
85 /*
86 * This function might be called when the timekeeping API can't be used
87 * to detect timeouts. One situation is when the clocksource is not yet
88 * initialized, another when the timekeeping is suspended. udelay() also
89 * cannot be used when the clocksource is not running on arm64, since
90 * the current timer is used as cycle counter. So a simple busy loop
91 * is used here in that special cases. The limit of iterations has been
92 * derived from experimental measurements of various PLLs on multiple
93 * Exynos SoC variants. Single register read time was usually in range
94 * 0.4...1.5 us, never less than 0.4 us.
95 */
96 if (pll_early_timeout || timekeeping_suspended) {
97 i = PLL_TIMEOUT_LOOPS;
98 while (i-- > 0) {
99 if (readl_relaxed(pll->con_reg) & reg_mask)
100 return 0;
101
102 cpu_relax();
103 }
104 ret = -ETIMEDOUT;
105 } else {
106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
107 val & reg_mask, 0, PLL_TIMEOUT_US);
108 }
109
110 if (ret < 0)
111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
112
113 return ret;
114 }
115
samsung_pll3xxx_enable(struct clk_hw * hw)116 static int samsung_pll3xxx_enable(struct clk_hw *hw)
117 {
118 struct samsung_clk_pll *pll = to_clk_pll(hw);
119 u32 tmp;
120
121 tmp = readl_relaxed(pll->con_reg);
122 tmp |= BIT(pll->enable_offs);
123 writel_relaxed(tmp, pll->con_reg);
124
125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
126 }
127
samsung_pll3xxx_disable(struct clk_hw * hw)128 static void samsung_pll3xxx_disable(struct clk_hw *hw)
129 {
130 struct samsung_clk_pll *pll = to_clk_pll(hw);
131 u32 tmp;
132
133 tmp = readl_relaxed(pll->con_reg);
134 tmp &= ~BIT(pll->enable_offs);
135 writel_relaxed(tmp, pll->con_reg);
136 }
137
138 /*
139 * PLL2126 Clock Type
140 */
141
142 #define PLL2126_MDIV_MASK (0xff)
143 #define PLL2126_PDIV_MASK (0x3f)
144 #define PLL2126_SDIV_MASK (0x3)
145 #define PLL2126_MDIV_SHIFT (16)
146 #define PLL2126_PDIV_SHIFT (8)
147 #define PLL2126_SDIV_SHIFT (0)
148
samsung_pll2126_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
150 unsigned long parent_rate)
151 {
152 struct samsung_clk_pll *pll = to_clk_pll(hw);
153 u32 pll_con, mdiv, pdiv, sdiv;
154 u64 fvco = parent_rate;
155
156 pll_con = readl_relaxed(pll->con_reg);
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
159 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
160
161 fvco *= (mdiv + 8);
162 do_div(fvco, (pdiv + 2) << sdiv);
163
164 return (unsigned long)fvco;
165 }
166
167 static const struct clk_ops samsung_pll2126_clk_ops = {
168 .recalc_rate = samsung_pll2126_recalc_rate,
169 };
170
171 /*
172 * PLL3000 Clock Type
173 */
174
175 #define PLL3000_MDIV_MASK (0xff)
176 #define PLL3000_PDIV_MASK (0x3)
177 #define PLL3000_SDIV_MASK (0x3)
178 #define PLL3000_MDIV_SHIFT (16)
179 #define PLL3000_PDIV_SHIFT (8)
180 #define PLL3000_SDIV_SHIFT (0)
181
samsung_pll3000_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
183 unsigned long parent_rate)
184 {
185 struct samsung_clk_pll *pll = to_clk_pll(hw);
186 u32 pll_con, mdiv, pdiv, sdiv;
187 u64 fvco = parent_rate;
188
189 pll_con = readl_relaxed(pll->con_reg);
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
192 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
193
194 fvco *= (2 * (mdiv + 8));
195 do_div(fvco, pdiv << sdiv);
196
197 return (unsigned long)fvco;
198 }
199
200 static const struct clk_ops samsung_pll3000_clk_ops = {
201 .recalc_rate = samsung_pll3000_recalc_rate,
202 };
203
204 /*
205 * PLL35xx Clock Type
206 */
207 /* Maximum lock time can be 270 * PDIV cycles */
208 #define PLL35XX_LOCK_FACTOR (270)
209 #define PLL142XX_LOCK_FACTOR (150)
210
211 #define PLL35XX_MDIV_MASK (0x3FF)
212 #define PLL35XX_PDIV_MASK (0x3F)
213 #define PLL35XX_SDIV_MASK (0x7)
214 #define PLL35XX_MDIV_SHIFT (16)
215 #define PLL35XX_PDIV_SHIFT (8)
216 #define PLL35XX_SDIV_SHIFT (0)
217 #define PLL35XX_LOCK_STAT_SHIFT (29)
218 #define PLL35XX_ENABLE_SHIFT (31)
219
samsung_pll35xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)220 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
221 unsigned long parent_rate)
222 {
223 struct samsung_clk_pll *pll = to_clk_pll(hw);
224 u32 mdiv, pdiv, sdiv, pll_con;
225 u64 fvco = parent_rate;
226
227 pll_con = readl_relaxed(pll->con_reg);
228 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
229 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
230 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
231
232 fvco *= mdiv;
233 do_div(fvco, (pdiv << sdiv));
234
235 return (unsigned long)fvco;
236 }
237
samsung_pll35xx_mp_change(const struct samsung_pll_rate_table * rate,u32 pll_con)238 static inline bool samsung_pll35xx_mp_change(
239 const struct samsung_pll_rate_table *rate, u32 pll_con)
240 {
241 u32 old_mdiv, old_pdiv;
242
243 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
244 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
245
246 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
247 }
248
samsung_pll35xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)249 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
250 unsigned long prate)
251 {
252 struct samsung_clk_pll *pll = to_clk_pll(hw);
253 const struct samsung_pll_rate_table *rate;
254 u32 tmp;
255
256 /* Get required rate settings from table */
257 rate = samsung_get_pll_settings(pll, drate);
258 if (!rate) {
259 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
260 drate, clk_hw_get_name(hw));
261 return -EINVAL;
262 }
263
264 tmp = readl_relaxed(pll->con_reg);
265
266 if (!(samsung_pll35xx_mp_change(rate, tmp))) {
267 /* If only s change, change just s value only*/
268 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
269 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
270 writel_relaxed(tmp, pll->con_reg);
271
272 return 0;
273 }
274
275 /* Set PLL lock time. */
276 if (pll->type == pll_142xx)
277 writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
278 pll->lock_reg);
279 else
280 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
281 pll->lock_reg);
282
283 /* Change PLL PMS values */
284 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
285 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
286 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
287 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
288 (rate->pdiv << PLL35XX_PDIV_SHIFT) |
289 (rate->sdiv << PLL35XX_SDIV_SHIFT);
290 writel_relaxed(tmp, pll->con_reg);
291
292 /* Wait for PLL lock if the PLL is enabled */
293 if (tmp & BIT(pll->enable_offs))
294 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
295
296 return 0;
297 }
298
299 static const struct clk_ops samsung_pll35xx_clk_ops = {
300 .recalc_rate = samsung_pll35xx_recalc_rate,
301 .round_rate = samsung_pll_round_rate,
302 .set_rate = samsung_pll35xx_set_rate,
303 .enable = samsung_pll3xxx_enable,
304 .disable = samsung_pll3xxx_disable,
305 };
306
307 static const struct clk_ops samsung_pll35xx_clk_min_ops = {
308 .recalc_rate = samsung_pll35xx_recalc_rate,
309 };
310
311 /*
312 * PLL36xx Clock Type
313 */
314 /* Maximum lock time can be 3000 * PDIV cycles */
315 #define PLL36XX_LOCK_FACTOR (3000)
316
317 #define PLL36XX_KDIV_MASK (0xFFFF)
318 #define PLL36XX_MDIV_MASK (0x1FF)
319 #define PLL36XX_PDIV_MASK (0x3F)
320 #define PLL36XX_SDIV_MASK (0x7)
321 #define PLL36XX_MDIV_SHIFT (16)
322 #define PLL36XX_PDIV_SHIFT (8)
323 #define PLL36XX_SDIV_SHIFT (0)
324 #define PLL36XX_KDIV_SHIFT (0)
325 #define PLL36XX_LOCK_STAT_SHIFT (29)
326 #define PLL36XX_ENABLE_SHIFT (31)
327
samsung_pll36xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)328 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
329 unsigned long parent_rate)
330 {
331 struct samsung_clk_pll *pll = to_clk_pll(hw);
332 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
333 s16 kdiv;
334 u64 fvco = parent_rate;
335
336 pll_con0 = readl_relaxed(pll->con_reg);
337 pll_con1 = readl_relaxed(pll->con_reg + 4);
338 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
339 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
340 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
341 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
342
343 fvco *= (mdiv << 16) + kdiv;
344 do_div(fvco, (pdiv << sdiv));
345 fvco >>= 16;
346
347 return (unsigned long)fvco;
348 }
349
samsung_pll36xx_mpk_change(const struct samsung_pll_rate_table * rate,u32 pll_con0,u32 pll_con1)350 static inline bool samsung_pll36xx_mpk_change(
351 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
352 {
353 u32 old_mdiv, old_pdiv, old_kdiv;
354
355 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
356 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
357 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
358
359 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
360 rate->kdiv != old_kdiv);
361 }
362
samsung_pll36xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long parent_rate)363 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
364 unsigned long parent_rate)
365 {
366 struct samsung_clk_pll *pll = to_clk_pll(hw);
367 u32 pll_con0, pll_con1;
368 const struct samsung_pll_rate_table *rate;
369
370 rate = samsung_get_pll_settings(pll, drate);
371 if (!rate) {
372 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
373 drate, clk_hw_get_name(hw));
374 return -EINVAL;
375 }
376
377 pll_con0 = readl_relaxed(pll->con_reg);
378 pll_con1 = readl_relaxed(pll->con_reg + 4);
379
380 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
381 /* If only s change, change just s value only*/
382 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
383 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
384 writel_relaxed(pll_con0, pll->con_reg);
385
386 return 0;
387 }
388
389 /* Set PLL lock time. */
390 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
391
392 /* Change PLL PMS values */
393 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
394 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
395 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
396 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
397 (rate->pdiv << PLL36XX_PDIV_SHIFT) |
398 (rate->sdiv << PLL36XX_SDIV_SHIFT);
399 writel_relaxed(pll_con0, pll->con_reg);
400
401 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
402 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
403 writel_relaxed(pll_con1, pll->con_reg + 4);
404
405 if (pll_con0 & BIT(pll->enable_offs))
406 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
407
408 return 0;
409 }
410
411 static const struct clk_ops samsung_pll36xx_clk_ops = {
412 .recalc_rate = samsung_pll36xx_recalc_rate,
413 .set_rate = samsung_pll36xx_set_rate,
414 .round_rate = samsung_pll_round_rate,
415 .enable = samsung_pll3xxx_enable,
416 .disable = samsung_pll3xxx_disable,
417 };
418
419 static const struct clk_ops samsung_pll36xx_clk_min_ops = {
420 .recalc_rate = samsung_pll36xx_recalc_rate,
421 };
422
423 /*
424 * PLL0822x Clock Type
425 */
426 /* Maximum lock time can be 150 * PDIV cycles */
427 #define PLL0822X_LOCK_FACTOR (150)
428
429 #define PLL0822X_MDIV_MASK (0x3FF)
430 #define PLL0822X_PDIV_MASK (0x3F)
431 #define PLL0822X_SDIV_MASK (0x7)
432 #define PLL0822X_MDIV_SHIFT (16)
433 #define PLL0822X_PDIV_SHIFT (8)
434 #define PLL0822X_SDIV_SHIFT (0)
435 #define PLL0822X_LOCK_STAT_SHIFT (29)
436 #define PLL0822X_ENABLE_SHIFT (31)
437
438 /* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
439 #define PLL1418X_MDIV_MASK (0x1FF)
440
samsung_pll0822x_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)441 static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
442 unsigned long parent_rate)
443 {
444 struct samsung_clk_pll *pll = to_clk_pll(hw);
445 u32 mdiv, pdiv, sdiv, pll_con3;
446 u64 fvco = parent_rate;
447
448 pll_con3 = readl_relaxed(pll->con_reg);
449 if (pll->type != pll_1418x)
450 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
451 else
452 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
453 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
454 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
455
456 fvco *= mdiv;
457 if (pll->type == pll_0516x)
458 fvco *= 2;
459
460 do_div(fvco, (pdiv << sdiv));
461
462 return (unsigned long)fvco;
463 }
464
samsung_pll0822x_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)465 static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
466 unsigned long prate)
467 {
468 const struct samsung_pll_rate_table *rate;
469 struct samsung_clk_pll *pll = to_clk_pll(hw);
470 u32 mdiv_mask, pll_con3;
471
472 if (pll->type != pll_1418x)
473 mdiv_mask = PLL0822X_MDIV_MASK;
474 else
475 mdiv_mask = PLL1418X_MDIV_MASK;
476
477 /* Get required rate settings from table */
478 rate = samsung_get_pll_settings(pll, drate);
479 if (!rate) {
480 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
481 drate, clk_hw_get_name(hw));
482 return -EINVAL;
483 }
484
485 /* Change PLL PMS values */
486 pll_con3 = readl_relaxed(pll->con_reg);
487 pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) |
488 (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
489 (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
490 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
491 (rate->pdiv << PLL0822X_PDIV_SHIFT) |
492 (rate->sdiv << PLL0822X_SDIV_SHIFT);
493
494 /* Set PLL lock time */
495 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
496 pll->lock_reg);
497
498 /* Write PMS values */
499 writel_relaxed(pll_con3, pll->con_reg);
500
501 /* Wait for PLL lock if the PLL is enabled */
502 if (pll_con3 & BIT(pll->enable_offs))
503 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
504
505 return 0;
506 }
507
508 static const struct clk_ops samsung_pll0822x_clk_ops = {
509 .recalc_rate = samsung_pll0822x_recalc_rate,
510 .round_rate = samsung_pll_round_rate,
511 .set_rate = samsung_pll0822x_set_rate,
512 .enable = samsung_pll3xxx_enable,
513 .disable = samsung_pll3xxx_disable,
514 };
515
516 static const struct clk_ops samsung_pll0822x_clk_min_ops = {
517 .recalc_rate = samsung_pll0822x_recalc_rate,
518 };
519
520 /*
521 * PLL0831x Clock Type
522 */
523 /* Maximum lock time can be 500 * PDIV cycles */
524 #define PLL0831X_LOCK_FACTOR (500)
525
526 #define PLL0831X_KDIV_MASK (0xFFFF)
527 #define PLL0831X_MDIV_MASK (0x1FF)
528 #define PLL0831X_PDIV_MASK (0x3F)
529 #define PLL0831X_SDIV_MASK (0x7)
530 #define PLL0831X_MDIV_SHIFT (16)
531 #define PLL0831X_PDIV_SHIFT (8)
532 #define PLL0831X_SDIV_SHIFT (0)
533 #define PLL0831X_KDIV_SHIFT (0)
534 #define PLL0831X_LOCK_STAT_SHIFT (29)
535 #define PLL0831X_ENABLE_SHIFT (31)
536
samsung_pll0831x_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)537 static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw,
538 unsigned long parent_rate)
539 {
540 struct samsung_clk_pll *pll = to_clk_pll(hw);
541 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
542 s16 kdiv;
543 u64 fvco = parent_rate;
544
545 pll_con3 = readl_relaxed(pll->con_reg);
546 pll_con5 = readl_relaxed(pll->con_reg + 8);
547 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
548 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
549 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
550 kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
551
552 fvco *= (mdiv << 16) + kdiv;
553 do_div(fvco, (pdiv << sdiv));
554 fvco >>= 16;
555
556 return (unsigned long)fvco;
557 }
558
samsung_pll0831x_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long parent_rate)559 static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
560 unsigned long parent_rate)
561 {
562 const struct samsung_pll_rate_table *rate;
563 struct samsung_clk_pll *pll = to_clk_pll(hw);
564 u32 pll_con3, pll_con5;
565
566 /* Get required rate settings from table */
567 rate = samsung_get_pll_settings(pll, drate);
568 if (!rate) {
569 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
570 drate, clk_hw_get_name(hw));
571 return -EINVAL;
572 }
573
574 pll_con3 = readl_relaxed(pll->con_reg);
575 pll_con5 = readl_relaxed(pll->con_reg + 8);
576
577 /* Change PLL PMSK values */
578 pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) |
579 (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) |
580 (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT));
581 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) |
582 (rate->pdiv << PLL0831X_PDIV_SHIFT) |
583 (rate->sdiv << PLL0831X_SDIV_SHIFT);
584 pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT);
585 /*
586 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int.
587 * Cast it to u16 to avoid leading 0xffff's in case of negative value.
588 */
589 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT);
590
591 /* Set PLL lock time */
592 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
593
594 /* Write PMSK values */
595 writel_relaxed(pll_con3, pll->con_reg);
596 writel_relaxed(pll_con5, pll->con_reg + 8);
597
598 /* Wait for PLL lock if the PLL is enabled */
599 if (pll_con3 & BIT(pll->enable_offs))
600 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
601
602 return 0;
603 }
604
605 static const struct clk_ops samsung_pll0831x_clk_ops = {
606 .recalc_rate = samsung_pll0831x_recalc_rate,
607 .set_rate = samsung_pll0831x_set_rate,
608 .round_rate = samsung_pll_round_rate,
609 .enable = samsung_pll3xxx_enable,
610 .disable = samsung_pll3xxx_disable,
611 };
612
613 static const struct clk_ops samsung_pll0831x_clk_min_ops = {
614 .recalc_rate = samsung_pll0831x_recalc_rate,
615 };
616
617 /*
618 * PLL45xx Clock Type
619 */
620 #define PLL4502_LOCK_FACTOR 400
621 #define PLL4508_LOCK_FACTOR 240
622
623 #define PLL45XX_MDIV_MASK (0x3FF)
624 #define PLL45XX_PDIV_MASK (0x3F)
625 #define PLL45XX_SDIV_MASK (0x7)
626 #define PLL45XX_AFC_MASK (0x1F)
627 #define PLL45XX_MDIV_SHIFT (16)
628 #define PLL45XX_PDIV_SHIFT (8)
629 #define PLL45XX_SDIV_SHIFT (0)
630 #define PLL45XX_AFC_SHIFT (0)
631
632 #define PLL45XX_ENABLE BIT(31)
633 #define PLL45XX_LOCKED BIT(29)
634
samsung_pll45xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)635 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
636 unsigned long parent_rate)
637 {
638 struct samsung_clk_pll *pll = to_clk_pll(hw);
639 u32 mdiv, pdiv, sdiv, pll_con;
640 u64 fvco = parent_rate;
641
642 pll_con = readl_relaxed(pll->con_reg);
643 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
644 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
645 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
646
647 if (pll->type == pll_4508)
648 sdiv = sdiv - 1;
649
650 fvco *= mdiv;
651 do_div(fvco, (pdiv << sdiv));
652
653 return (unsigned long)fvco;
654 }
655
samsung_pll45xx_mp_change(u32 pll_con0,u32 pll_con1,const struct samsung_pll_rate_table * rate)656 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
657 const struct samsung_pll_rate_table *rate)
658 {
659 u32 old_mdiv, old_pdiv, old_afc;
660
661 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
662 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
663 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
664
665 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
666 || old_afc != rate->afc);
667 }
668
samsung_pll45xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)669 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
670 unsigned long prate)
671 {
672 struct samsung_clk_pll *pll = to_clk_pll(hw);
673 const struct samsung_pll_rate_table *rate;
674 u32 con0, con1;
675
676 /* Get required rate settings from table */
677 rate = samsung_get_pll_settings(pll, drate);
678 if (!rate) {
679 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
680 drate, clk_hw_get_name(hw));
681 return -EINVAL;
682 }
683
684 con0 = readl_relaxed(pll->con_reg);
685 con1 = readl_relaxed(pll->con_reg + 0x4);
686
687 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
688 /* If only s change, change just s value only*/
689 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
690 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
691 writel_relaxed(con0, pll->con_reg);
692
693 return 0;
694 }
695
696 /* Set PLL PMS values. */
697 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
698 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
699 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
700 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
701 (rate->pdiv << PLL45XX_PDIV_SHIFT) |
702 (rate->sdiv << PLL45XX_SDIV_SHIFT);
703
704 /* Set PLL AFC value. */
705 con1 = readl_relaxed(pll->con_reg + 0x4);
706 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
707 con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
708
709 /* Set PLL lock time. */
710 switch (pll->type) {
711 case pll_4502:
712 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
713 break;
714 case pll_4508:
715 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
716 break;
717 default:
718 break;
719 }
720
721 /* Set new configuration. */
722 writel_relaxed(con1, pll->con_reg + 0x4);
723 writel_relaxed(con0, pll->con_reg);
724
725 /* Wait for PLL lock */
726 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
727 }
728
729 static const struct clk_ops samsung_pll45xx_clk_ops = {
730 .recalc_rate = samsung_pll45xx_recalc_rate,
731 .round_rate = samsung_pll_round_rate,
732 .set_rate = samsung_pll45xx_set_rate,
733 };
734
735 static const struct clk_ops samsung_pll45xx_clk_min_ops = {
736 .recalc_rate = samsung_pll45xx_recalc_rate,
737 };
738
739 /*
740 * PLL46xx Clock Type
741 */
742 #define PLL46XX_LOCK_FACTOR 3000
743
744 #define PLL46XX_VSEL_MASK (1)
745 #define PLL46XX_MDIV_MASK (0x1FF)
746 #define PLL1460X_MDIV_MASK (0x3FF)
747
748 #define PLL46XX_PDIV_MASK (0x3F)
749 #define PLL46XX_SDIV_MASK (0x7)
750 #define PLL46XX_VSEL_SHIFT (27)
751 #define PLL46XX_MDIV_SHIFT (16)
752 #define PLL46XX_PDIV_SHIFT (8)
753 #define PLL46XX_SDIV_SHIFT (0)
754
755 #define PLL46XX_KDIV_MASK (0xFFFF)
756 #define PLL4650C_KDIV_MASK (0xFFF)
757 #define PLL46XX_KDIV_SHIFT (0)
758 #define PLL46XX_MFR_MASK (0x3F)
759 #define PLL46XX_MRR_MASK (0x1F)
760 #define PLL46XX_KDIV_SHIFT (0)
761 #define PLL46XX_MFR_SHIFT (16)
762 #define PLL46XX_MRR_SHIFT (24)
763
764 #define PLL46XX_ENABLE BIT(31)
765 #define PLL46XX_LOCKED BIT(29)
766 #define PLL46XX_VSEL BIT(27)
767
samsung_pll46xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)768 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
769 unsigned long parent_rate)
770 {
771 struct samsung_clk_pll *pll = to_clk_pll(hw);
772 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
773 u64 fvco = parent_rate;
774
775 pll_con0 = readl_relaxed(pll->con_reg);
776 pll_con1 = readl_relaxed(pll->con_reg + 4);
777 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
778 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
779 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
780 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
781 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
782 pll_con1 & PLL46XX_KDIV_MASK;
783
784 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
785
786 fvco *= (mdiv << shift) + kdiv;
787 do_div(fvco, (pdiv << sdiv));
788 fvco >>= shift;
789
790 return (unsigned long)fvco;
791 }
792
samsung_pll46xx_mpk_change(u32 pll_con0,u32 pll_con1,const struct samsung_pll_rate_table * rate)793 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
794 const struct samsung_pll_rate_table *rate)
795 {
796 u32 old_mdiv, old_pdiv, old_kdiv;
797
798 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
799 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
800 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
801
802 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
803 || old_kdiv != rate->kdiv);
804 }
805
samsung_pll46xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)806 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
807 unsigned long prate)
808 {
809 struct samsung_clk_pll *pll = to_clk_pll(hw);
810 const struct samsung_pll_rate_table *rate;
811 u32 con0, con1, lock;
812
813 /* Get required rate settings from table */
814 rate = samsung_get_pll_settings(pll, drate);
815 if (!rate) {
816 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
817 drate, clk_hw_get_name(hw));
818 return -EINVAL;
819 }
820
821 con0 = readl_relaxed(pll->con_reg);
822 con1 = readl_relaxed(pll->con_reg + 0x4);
823
824 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
825 /* If only s change, change just s value only*/
826 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
827 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
828 writel_relaxed(con0, pll->con_reg);
829
830 return 0;
831 }
832
833 /* Set PLL lock time. */
834 lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
835 if (lock > 0xffff)
836 /* Maximum lock time bitfield is 16-bit. */
837 lock = 0xffff;
838
839 /* Set PLL PMS and VSEL values. */
840 if (pll->type == pll_1460x) {
841 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
842 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
843 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
844 } else {
845 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
846 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
847 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
848 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
849 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
850 }
851
852 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
853 (rate->pdiv << PLL46XX_PDIV_SHIFT) |
854 (rate->sdiv << PLL46XX_SDIV_SHIFT);
855
856 /* Set PLL K, MFR and MRR values. */
857 con1 = readl_relaxed(pll->con_reg + 0x4);
858 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
859 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
860 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
861 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
862 (rate->mfr << PLL46XX_MFR_SHIFT) |
863 (rate->mrr << PLL46XX_MRR_SHIFT);
864
865 /* Write configuration to PLL */
866 writel_relaxed(lock, pll->lock_reg);
867 writel_relaxed(con0, pll->con_reg);
868 writel_relaxed(con1, pll->con_reg + 0x4);
869
870 /* Wait for PLL lock */
871 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
872 }
873
874 static const struct clk_ops samsung_pll46xx_clk_ops = {
875 .recalc_rate = samsung_pll46xx_recalc_rate,
876 .round_rate = samsung_pll_round_rate,
877 .set_rate = samsung_pll46xx_set_rate,
878 };
879
880 static const struct clk_ops samsung_pll46xx_clk_min_ops = {
881 .recalc_rate = samsung_pll46xx_recalc_rate,
882 };
883
884 /*
885 * PLL6552 Clock Type
886 */
887
888 #define PLL6552_MDIV_MASK 0x3ff
889 #define PLL6552_PDIV_MASK 0x3f
890 #define PLL6552_SDIV_MASK 0x7
891 #define PLL6552_MDIV_SHIFT 16
892 #define PLL6552_MDIV_SHIFT_2416 14
893 #define PLL6552_PDIV_SHIFT 8
894 #define PLL6552_PDIV_SHIFT_2416 5
895 #define PLL6552_SDIV_SHIFT 0
896
samsung_pll6552_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)897 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
898 unsigned long parent_rate)
899 {
900 struct samsung_clk_pll *pll = to_clk_pll(hw);
901 u32 mdiv, pdiv, sdiv, pll_con;
902 u64 fvco = parent_rate;
903
904 pll_con = readl_relaxed(pll->con_reg);
905 if (pll->type == pll_6552_s3c2416) {
906 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
907 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
908 } else {
909 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
910 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
911 }
912 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
913
914 fvco *= mdiv;
915 do_div(fvco, (pdiv << sdiv));
916
917 return (unsigned long)fvco;
918 }
919
920 static const struct clk_ops samsung_pll6552_clk_ops = {
921 .recalc_rate = samsung_pll6552_recalc_rate,
922 };
923
924 /*
925 * PLL6553 Clock Type
926 */
927
928 #define PLL6553_MDIV_MASK 0xff
929 #define PLL6553_PDIV_MASK 0x3f
930 #define PLL6553_SDIV_MASK 0x7
931 #define PLL6553_KDIV_MASK 0xffff
932 #define PLL6553_MDIV_SHIFT 16
933 #define PLL6553_PDIV_SHIFT 8
934 #define PLL6553_SDIV_SHIFT 0
935 #define PLL6553_KDIV_SHIFT 0
936
samsung_pll6553_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)937 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
938 unsigned long parent_rate)
939 {
940 struct samsung_clk_pll *pll = to_clk_pll(hw);
941 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
942 u64 fvco = parent_rate;
943
944 pll_con0 = readl_relaxed(pll->con_reg);
945 pll_con1 = readl_relaxed(pll->con_reg + 0x4);
946 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
947 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
948 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
949 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
950
951 fvco *= (mdiv << 16) + kdiv;
952 do_div(fvco, (pdiv << sdiv));
953 fvco >>= 16;
954
955 return (unsigned long)fvco;
956 }
957
958 static const struct clk_ops samsung_pll6553_clk_ops = {
959 .recalc_rate = samsung_pll6553_recalc_rate,
960 };
961
962 /*
963 * PLL2550x Clock Type
964 */
965
966 #define PLL2550X_R_MASK (0x1)
967 #define PLL2550X_P_MASK (0x3F)
968 #define PLL2550X_M_MASK (0x3FF)
969 #define PLL2550X_S_MASK (0x7)
970 #define PLL2550X_R_SHIFT (20)
971 #define PLL2550X_P_SHIFT (14)
972 #define PLL2550X_M_SHIFT (4)
973 #define PLL2550X_S_SHIFT (0)
974
samsung_pll2550x_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)975 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
976 unsigned long parent_rate)
977 {
978 struct samsung_clk_pll *pll = to_clk_pll(hw);
979 u32 r, p, m, s, pll_stat;
980 u64 fvco = parent_rate;
981
982 pll_stat = readl_relaxed(pll->con_reg);
983 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
984 if (!r)
985 return 0;
986 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
987 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
988 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
989
990 fvco *= m;
991 do_div(fvco, (p << s));
992
993 return (unsigned long)fvco;
994 }
995
996 static const struct clk_ops samsung_pll2550x_clk_ops = {
997 .recalc_rate = samsung_pll2550x_recalc_rate,
998 };
999
1000 /*
1001 * PLL2550xx Clock Type
1002 */
1003
1004 /* Maximum lock time can be 270 * PDIV cycles */
1005 #define PLL2550XX_LOCK_FACTOR 270
1006
1007 #define PLL2550XX_M_MASK 0x3FF
1008 #define PLL2550XX_P_MASK 0x3F
1009 #define PLL2550XX_S_MASK 0x7
1010 #define PLL2550XX_LOCK_STAT_MASK 0x1
1011 #define PLL2550XX_M_SHIFT 9
1012 #define PLL2550XX_P_SHIFT 3
1013 #define PLL2550XX_S_SHIFT 0
1014 #define PLL2550XX_LOCK_STAT_SHIFT 21
1015
samsung_pll2550xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1016 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
1017 unsigned long parent_rate)
1018 {
1019 struct samsung_clk_pll *pll = to_clk_pll(hw);
1020 u32 mdiv, pdiv, sdiv, pll_con;
1021 u64 fvco = parent_rate;
1022
1023 pll_con = readl_relaxed(pll->con_reg);
1024 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
1025 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
1026 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
1027
1028 fvco *= mdiv;
1029 do_div(fvco, (pdiv << sdiv));
1030
1031 return (unsigned long)fvco;
1032 }
1033
samsung_pll2550xx_mp_change(u32 mdiv,u32 pdiv,u32 pll_con)1034 static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
1035 {
1036 u32 old_mdiv, old_pdiv;
1037
1038 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
1039 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
1040
1041 return mdiv != old_mdiv || pdiv != old_pdiv;
1042 }
1043
samsung_pll2550xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)1044 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
1045 unsigned long prate)
1046 {
1047 struct samsung_clk_pll *pll = to_clk_pll(hw);
1048 const struct samsung_pll_rate_table *rate;
1049 u32 tmp;
1050
1051 /* Get required rate settings from table */
1052 rate = samsung_get_pll_settings(pll, drate);
1053 if (!rate) {
1054 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1055 drate, clk_hw_get_name(hw));
1056 return -EINVAL;
1057 }
1058
1059 tmp = readl_relaxed(pll->con_reg);
1060
1061 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
1062 /* If only s change, change just s value only*/
1063 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
1064 tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
1065 writel_relaxed(tmp, pll->con_reg);
1066
1067 return 0;
1068 }
1069
1070 /* Set PLL lock time. */
1071 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1072
1073 /* Change PLL PMS values */
1074 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
1075 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
1076 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
1077 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
1078 (rate->pdiv << PLL2550XX_P_SHIFT) |
1079 (rate->sdiv << PLL2550XX_S_SHIFT);
1080 writel_relaxed(tmp, pll->con_reg);
1081
1082 /* Wait for PLL lock */
1083 return samsung_pll_lock_wait(pll,
1084 PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT);
1085 }
1086
1087 static const struct clk_ops samsung_pll2550xx_clk_ops = {
1088 .recalc_rate = samsung_pll2550xx_recalc_rate,
1089 .round_rate = samsung_pll_round_rate,
1090 .set_rate = samsung_pll2550xx_set_rate,
1091 };
1092
1093 static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
1094 .recalc_rate = samsung_pll2550xx_recalc_rate,
1095 };
1096
1097 /*
1098 * PLL2650x Clock Type
1099 */
1100
1101 /* Maximum lock time can be 3000 * PDIV cycles */
1102 #define PLL2650X_LOCK_FACTOR 3000
1103
1104 #define PLL2650X_M_MASK 0x1ff
1105 #define PLL2650X_P_MASK 0x3f
1106 #define PLL2650X_S_MASK 0x7
1107 #define PLL2650X_K_MASK 0xffff
1108 #define PLL2650X_LOCK_STAT_MASK 0x1
1109 #define PLL2650X_M_SHIFT 16
1110 #define PLL2650X_P_SHIFT 8
1111 #define PLL2650X_S_SHIFT 0
1112 #define PLL2650X_K_SHIFT 0
1113 #define PLL2650X_LOCK_STAT_SHIFT 29
1114 #define PLL2650X_PLL_ENABLE_SHIFT 31
1115
samsung_pll2650x_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1116 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
1117 unsigned long parent_rate)
1118 {
1119 struct samsung_clk_pll *pll = to_clk_pll(hw);
1120 u64 fout = parent_rate;
1121 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
1122 s16 kdiv;
1123
1124 pll_con0 = readl_relaxed(pll->con_reg);
1125 mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
1126 pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
1127 sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
1128
1129 pll_con1 = readl_relaxed(pll->con_reg + 4);
1130 kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK);
1131
1132 fout *= (mdiv << 16) + kdiv;
1133 do_div(fout, (pdiv << sdiv));
1134 fout >>= 16;
1135
1136 return (unsigned long)fout;
1137 }
1138
samsung_pll2650x_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)1139 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
1140 unsigned long prate)
1141 {
1142 struct samsung_clk_pll *pll = to_clk_pll(hw);
1143 const struct samsung_pll_rate_table *rate;
1144 u32 con0, con1;
1145
1146 /* Get required rate settings from table */
1147 rate = samsung_get_pll_settings(pll, drate);
1148 if (!rate) {
1149 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1150 drate, clk_hw_get_name(hw));
1151 return -EINVAL;
1152 }
1153
1154 con0 = readl_relaxed(pll->con_reg);
1155 con1 = readl_relaxed(pll->con_reg + 4);
1156
1157 /* Set PLL lock time. */
1158 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
1159
1160 /* Change PLL PMS values */
1161 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1162 (PLL2650X_P_MASK << PLL2650X_P_SHIFT) |
1163 (PLL2650X_S_MASK << PLL2650X_S_SHIFT));
1164 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1165 (rate->pdiv << PLL2650X_P_SHIFT) |
1166 (rate->sdiv << PLL2650X_S_SHIFT);
1167 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1168 writel_relaxed(con0, pll->con_reg);
1169
1170 con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
1171 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
1172 writel_relaxed(con1, pll->con_reg + 4);
1173
1174 /* Wait for PLL lock */
1175 return samsung_pll_lock_wait(pll,
1176 PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT);
1177 }
1178
1179 static const struct clk_ops samsung_pll2650x_clk_ops = {
1180 .recalc_rate = samsung_pll2650x_recalc_rate,
1181 .round_rate = samsung_pll_round_rate,
1182 .set_rate = samsung_pll2650x_set_rate,
1183 };
1184
1185 static const struct clk_ops samsung_pll2650x_clk_min_ops = {
1186 .recalc_rate = samsung_pll2650x_recalc_rate,
1187 };
1188
1189 /*
1190 * PLL2650XX Clock Type
1191 */
1192
1193 /* Maximum lock time can be 3000 * PDIV cycles */
1194 #define PLL2650XX_LOCK_FACTOR 3000
1195
1196 #define PLL2650XX_MDIV_SHIFT 9
1197 #define PLL2650XX_PDIV_SHIFT 3
1198 #define PLL2650XX_SDIV_SHIFT 0
1199 #define PLL2650XX_KDIV_SHIFT 0
1200 #define PLL2650XX_MDIV_MASK 0x1ff
1201 #define PLL2650XX_PDIV_MASK 0x3f
1202 #define PLL2650XX_SDIV_MASK 0x7
1203 #define PLL2650XX_KDIV_MASK 0xffff
1204 #define PLL2650XX_PLL_ENABLE_SHIFT 23
1205 #define PLL2650XX_PLL_LOCKTIME_SHIFT 21
1206 #define PLL2650XX_PLL_FOUTMASK_SHIFT 31
1207
samsung_pll2650xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1208 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
1209 unsigned long parent_rate)
1210 {
1211 struct samsung_clk_pll *pll = to_clk_pll(hw);
1212 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
1213 s16 kdiv;
1214 u64 fvco = parent_rate;
1215
1216 pll_con0 = readl_relaxed(pll->con_reg);
1217 pll_con2 = readl_relaxed(pll->con_reg + 8);
1218 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1219 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1220 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
1221 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
1222
1223 fvco *= (mdiv << 16) + kdiv;
1224 do_div(fvco, (pdiv << sdiv));
1225 fvco >>= 16;
1226
1227 return (unsigned long)fvco;
1228 }
1229
samsung_pll2650xx_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long parent_rate)1230 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
1231 unsigned long parent_rate)
1232 {
1233 struct samsung_clk_pll *pll = to_clk_pll(hw);
1234 u32 pll_con0, pll_con2;
1235 const struct samsung_pll_rate_table *rate;
1236
1237 rate = samsung_get_pll_settings(pll, drate);
1238 if (!rate) {
1239 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1240 drate, clk_hw_get_name(hw));
1241 return -EINVAL;
1242 }
1243
1244 pll_con0 = readl_relaxed(pll->con_reg);
1245 pll_con2 = readl_relaxed(pll->con_reg + 8);
1246
1247 /* Change PLL PMS values */
1248 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
1249 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
1250 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
1251 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
1252 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
1253 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
1254 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
1255 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
1256
1257 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
1258 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
1259 << PLL2650XX_KDIV_SHIFT;
1260
1261 /* Set PLL lock time. */
1262 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1263
1264 writel_relaxed(pll_con0, pll->con_reg);
1265 writel_relaxed(pll_con2, pll->con_reg + 8);
1266
1267 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
1268 }
1269
1270 static const struct clk_ops samsung_pll2650xx_clk_ops = {
1271 .recalc_rate = samsung_pll2650xx_recalc_rate,
1272 .set_rate = samsung_pll2650xx_set_rate,
1273 .round_rate = samsung_pll_round_rate,
1274 };
1275
1276 static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
1277 .recalc_rate = samsung_pll2650xx_recalc_rate,
1278 };
1279
1280 /*
1281 * PLL531X Clock Type
1282 */
1283 /* Maximum lock time can be 500 * PDIV cycles */
1284 #define PLL531X_LOCK_FACTOR (500)
1285 #define PLL531X_MDIV_MASK (0x3FF)
1286 #define PLL531X_PDIV_MASK (0x3F)
1287 #define PLL531X_SDIV_MASK (0x7)
1288 #define PLL531X_FDIV_MASK (0xFFFFFFFF)
1289 #define PLL531X_MDIV_SHIFT (16)
1290 #define PLL531X_PDIV_SHIFT (8)
1291 #define PLL531X_SDIV_SHIFT (0)
1292
samsung_pll531x_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1293 static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw,
1294 unsigned long parent_rate)
1295 {
1296 struct samsung_clk_pll *pll = to_clk_pll(hw);
1297 u32 pdiv, sdiv, fdiv, pll_con0, pll_con8;
1298 u64 mdiv, fout = parent_rate;
1299
1300 pll_con0 = readl_relaxed(pll->con_reg);
1301 pll_con8 = readl_relaxed(pll->con_reg + 20);
1302 mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK;
1303 pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK;
1304 sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK;
1305 fdiv = (pll_con8 & PLL531X_FDIV_MASK);
1306
1307 if (fdiv >> 31)
1308 mdiv--;
1309
1310 fout *= (mdiv << 24) + (fdiv >> 8);
1311 do_div(fout, (pdiv << sdiv));
1312 fout >>= 24;
1313
1314 return (unsigned long)fout;
1315 }
1316
1317 static const struct clk_ops samsung_pll531x_clk_ops = {
1318 .recalc_rate = samsung_pll531x_recalc_rate,
1319 };
1320
_samsung_clk_register_pll(struct samsung_clk_provider * ctx,const struct samsung_pll_clock * pll_clk)1321 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1322 const struct samsung_pll_clock *pll_clk)
1323 {
1324 struct samsung_clk_pll *pll;
1325 struct clk_init_data init;
1326 int ret, len;
1327
1328 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1329 if (!pll) {
1330 pr_err("%s: could not allocate pll clk %s\n",
1331 __func__, pll_clk->name);
1332 return;
1333 }
1334
1335 init.name = pll_clk->name;
1336 init.flags = pll_clk->flags;
1337 init.parent_names = &pll_clk->parent_name;
1338 init.num_parents = 1;
1339
1340 if (pll_clk->rate_table) {
1341 /* find count of rates in rate_table */
1342 for (len = 0; pll_clk->rate_table[len].rate != 0; )
1343 len++;
1344
1345 pll->rate_count = len;
1346 pll->rate_table = kmemdup_array(pll_clk->rate_table,
1347 pll->rate_count,
1348 sizeof(*pll->rate_table),
1349 GFP_KERNEL);
1350 WARN(!pll->rate_table,
1351 "%s: could not allocate rate table for %s\n",
1352 __func__, pll_clk->name);
1353 }
1354
1355 switch (pll_clk->type) {
1356 case pll_2126:
1357 init.ops = &samsung_pll2126_clk_ops;
1358 break;
1359 case pll_3000:
1360 init.ops = &samsung_pll3000_clk_ops;
1361 break;
1362 /* clk_ops for 35xx and 2550 are similar */
1363 case pll_35xx:
1364 case pll_2550:
1365 case pll_1450x:
1366 case pll_1451x:
1367 case pll_1452x:
1368 case pll_142xx:
1369 pll->enable_offs = PLL35XX_ENABLE_SHIFT;
1370 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
1371 if (!pll->rate_table)
1372 init.ops = &samsung_pll35xx_clk_min_ops;
1373 else
1374 init.ops = &samsung_pll35xx_clk_ops;
1375 break;
1376 case pll_1417x:
1377 case pll_1418x:
1378 case pll_0818x:
1379 case pll_0822x:
1380 case pll_0516x:
1381 case pll_0517x:
1382 case pll_0518x:
1383 pll->enable_offs = PLL0822X_ENABLE_SHIFT;
1384 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
1385 if (!pll->rate_table)
1386 init.ops = &samsung_pll0822x_clk_min_ops;
1387 else
1388 init.ops = &samsung_pll0822x_clk_ops;
1389 break;
1390 case pll_4500:
1391 init.ops = &samsung_pll45xx_clk_min_ops;
1392 break;
1393 case pll_4502:
1394 case pll_4508:
1395 if (!pll->rate_table)
1396 init.ops = &samsung_pll45xx_clk_min_ops;
1397 else
1398 init.ops = &samsung_pll45xx_clk_ops;
1399 break;
1400 /* clk_ops for 36xx and 2650 are similar */
1401 case pll_36xx:
1402 case pll_2650:
1403 pll->enable_offs = PLL36XX_ENABLE_SHIFT;
1404 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
1405 if (!pll->rate_table)
1406 init.ops = &samsung_pll36xx_clk_min_ops;
1407 else
1408 init.ops = &samsung_pll36xx_clk_ops;
1409 break;
1410 case pll_0831x:
1411 pll->enable_offs = PLL0831X_ENABLE_SHIFT;
1412 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
1413 if (!pll->rate_table)
1414 init.ops = &samsung_pll0831x_clk_min_ops;
1415 else
1416 init.ops = &samsung_pll0831x_clk_ops;
1417 break;
1418 case pll_6552:
1419 case pll_6552_s3c2416:
1420 init.ops = &samsung_pll6552_clk_ops;
1421 break;
1422 case pll_6553:
1423 init.ops = &samsung_pll6553_clk_ops;
1424 break;
1425 case pll_4600:
1426 case pll_4650:
1427 case pll_4650c:
1428 case pll_1460x:
1429 if (!pll->rate_table)
1430 init.ops = &samsung_pll46xx_clk_min_ops;
1431 else
1432 init.ops = &samsung_pll46xx_clk_ops;
1433 break;
1434 case pll_2550x:
1435 init.ops = &samsung_pll2550x_clk_ops;
1436 break;
1437 case pll_2550xx:
1438 if (!pll->rate_table)
1439 init.ops = &samsung_pll2550xx_clk_min_ops;
1440 else
1441 init.ops = &samsung_pll2550xx_clk_ops;
1442 break;
1443 case pll_2650x:
1444 if (!pll->rate_table)
1445 init.ops = &samsung_pll2650x_clk_min_ops;
1446 else
1447 init.ops = &samsung_pll2650x_clk_ops;
1448 break;
1449 case pll_2650xx:
1450 if (!pll->rate_table)
1451 init.ops = &samsung_pll2650xx_clk_min_ops;
1452 else
1453 init.ops = &samsung_pll2650xx_clk_ops;
1454 break;
1455 case pll_531x:
1456 init.ops = &samsung_pll531x_clk_ops;
1457 break;
1458 default:
1459 pr_warn("%s: Unknown pll type for pll clk %s\n",
1460 __func__, pll_clk->name);
1461 }
1462
1463 pll->hw.init = &init;
1464 pll->type = pll_clk->type;
1465 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
1466 pll->con_reg = ctx->reg_base + pll_clk->con_offset;
1467
1468 ret = clk_hw_register(ctx->dev, &pll->hw);
1469 if (ret) {
1470 pr_err("%s: failed to register pll clock %s : %d\n",
1471 __func__, pll_clk->name, ret);
1472 kfree(pll->rate_table);
1473 kfree(pll);
1474 return;
1475 }
1476
1477 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
1478 }
1479
samsung_clk_register_pll(struct samsung_clk_provider * ctx,const struct samsung_pll_clock * pll_list,unsigned int nr_pll)1480 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1481 const struct samsung_pll_clock *pll_list,
1482 unsigned int nr_pll)
1483 {
1484 int cnt;
1485
1486 for (cnt = 0; cnt < nr_pll; cnt++)
1487 _samsung_clk_register_pll(ctx, &pll_list[cnt]);
1488 }
1489