1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx ZynqMP SHA Driver.
4 * Copyright (c) 2022 Xilinx Inc.
5 */
6 #include <crypto/hash.h>
7 #include <crypto/internal/hash.h>
8 #include <crypto/sha3.h>
9 #include <linux/cacheflush.h>
10 #include <linux/cleanup.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/firmware/xlnx-zynqmp.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/platform_device.h>
20
21 #define ZYNQMP_DMA_BIT_MASK 32U
22 #define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U
23
24 enum zynqmp_sha_op {
25 ZYNQMP_SHA3_INIT = 1,
26 ZYNQMP_SHA3_UPDATE = 2,
27 ZYNQMP_SHA3_FINAL = 4,
28 };
29
30 struct zynqmp_sha_drv_ctx {
31 struct shash_alg sha3_384;
32 struct device *dev;
33 };
34
35 struct zynqmp_sha_tfm_ctx {
36 struct device *dev;
37 struct crypto_shash *fbk_tfm;
38 };
39
40 struct zynqmp_sha_desc_ctx {
41 struct shash_desc fbk_req;
42 };
43
44 static dma_addr_t update_dma_addr, final_dma_addr;
45 static char *ubuf, *fbuf;
46
47 static DEFINE_SPINLOCK(zynqmp_sha_lock);
48
zynqmp_sha_init_tfm(struct crypto_shash * hash)49 static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
50 {
51 const char *fallback_driver_name = crypto_shash_alg_name(hash);
52 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
53 struct shash_alg *alg = crypto_shash_alg(hash);
54 struct crypto_shash *fallback_tfm;
55 struct zynqmp_sha_drv_ctx *drv_ctx;
56
57 drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
58 tfm_ctx->dev = drv_ctx->dev;
59
60 /* Allocate a fallback and abort if it failed. */
61 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
62 CRYPTO_ALG_NEED_FALLBACK);
63 if (IS_ERR(fallback_tfm))
64 return PTR_ERR(fallback_tfm);
65
66 tfm_ctx->fbk_tfm = fallback_tfm;
67 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
68
69 return 0;
70 }
71
zynqmp_sha_exit_tfm(struct crypto_shash * hash)72 static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
73 {
74 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
75
76 if (tfm_ctx->fbk_tfm) {
77 crypto_free_shash(tfm_ctx->fbk_tfm);
78 tfm_ctx->fbk_tfm = NULL;
79 }
80
81 memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
82 }
83
zynqmp_sha_init(struct shash_desc * desc)84 static int zynqmp_sha_init(struct shash_desc *desc)
85 {
86 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
87 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
88
89 dctx->fbk_req.tfm = tctx->fbk_tfm;
90 return crypto_shash_init(&dctx->fbk_req);
91 }
92
zynqmp_sha_update(struct shash_desc * desc,const u8 * data,unsigned int length)93 static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
94 {
95 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
96
97 return crypto_shash_update(&dctx->fbk_req, data, length);
98 }
99
zynqmp_sha_final(struct shash_desc * desc,u8 * out)100 static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
101 {
102 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
103
104 return crypto_shash_final(&dctx->fbk_req, out);
105 }
106
zynqmp_sha_finup(struct shash_desc * desc,const u8 * data,unsigned int length,u8 * out)107 static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
108 {
109 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
110
111 return crypto_shash_finup(&dctx->fbk_req, data, length, out);
112 }
113
zynqmp_sha_import(struct shash_desc * desc,const void * in)114 static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
115 {
116 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
117 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
118
119 dctx->fbk_req.tfm = tctx->fbk_tfm;
120 return crypto_shash_import(&dctx->fbk_req, in);
121 }
122
zynqmp_sha_export(struct shash_desc * desc,void * out)123 static int zynqmp_sha_export(struct shash_desc *desc, void *out)
124 {
125 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
126
127 return crypto_shash_export(&dctx->fbk_req, out);
128 }
129
__zynqmp_sha_digest(struct shash_desc * desc,const u8 * data,unsigned int len,u8 * out)130 static int __zynqmp_sha_digest(struct shash_desc *desc, const u8 *data,
131 unsigned int len, u8 *out)
132 {
133 unsigned int remaining_len = len;
134 int update_size;
135 int ret;
136
137 ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
138 if (ret)
139 return ret;
140
141 while (remaining_len != 0) {
142 memzero_explicit(ubuf, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
143 if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
144 update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
145 remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
146 } else {
147 update_size = remaining_len;
148 remaining_len = 0;
149 }
150 memcpy(ubuf, data, update_size);
151 flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
152 ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
153 if (ret)
154 return ret;
155
156 data += update_size;
157 }
158
159 ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
160 memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
161 memzero_explicit(fbuf, SHA3_384_DIGEST_SIZE);
162
163 return ret;
164 }
165
zynqmp_sha_digest(struct shash_desc * desc,const u8 * data,unsigned int len,u8 * out)166 static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
167 {
168 scoped_guard(spinlock_bh, &zynqmp_sha_lock)
169 return __zynqmp_sha_digest(desc, data, len, out);
170 }
171
172 static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
173 .sha3_384 = {
174 .init = zynqmp_sha_init,
175 .update = zynqmp_sha_update,
176 .final = zynqmp_sha_final,
177 .finup = zynqmp_sha_finup,
178 .digest = zynqmp_sha_digest,
179 .export = zynqmp_sha_export,
180 .import = zynqmp_sha_import,
181 .init_tfm = zynqmp_sha_init_tfm,
182 .exit_tfm = zynqmp_sha_exit_tfm,
183 .descsize = sizeof(struct zynqmp_sha_desc_ctx),
184 .statesize = sizeof(struct sha3_state),
185 .digestsize = SHA3_384_DIGEST_SIZE,
186 .base = {
187 .cra_name = "sha3-384",
188 .cra_driver_name = "zynqmp-sha3-384",
189 .cra_priority = 300,
190 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
191 CRYPTO_ALG_ALLOCATES_MEMORY |
192 CRYPTO_ALG_NEED_FALLBACK,
193 .cra_blocksize = SHA3_384_BLOCK_SIZE,
194 .cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
195 .cra_module = THIS_MODULE,
196 }
197 }
198 };
199
zynqmp_sha_probe(struct platform_device * pdev)200 static int zynqmp_sha_probe(struct platform_device *pdev)
201 {
202 struct device *dev = &pdev->dev;
203 int err;
204 u32 v;
205
206 /* Verify the hardware is present */
207 err = zynqmp_pm_get_api_version(&v);
208 if (err)
209 return err;
210
211
212 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
213 if (err < 0) {
214 dev_err(dev, "No usable DMA configuration\n");
215 return err;
216 }
217
218 err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
219 if (err < 0) {
220 dev_err(dev, "Failed to register shash alg.\n");
221 return err;
222 }
223
224 sha3_drv_ctx.dev = dev;
225 platform_set_drvdata(pdev, &sha3_drv_ctx);
226
227 ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
228 if (!ubuf) {
229 err = -ENOMEM;
230 goto err_shash;
231 }
232
233 fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
234 if (!fbuf) {
235 err = -ENOMEM;
236 goto err_mem;
237 }
238
239 return 0;
240
241 err_mem:
242 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
243
244 err_shash:
245 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
246
247 return err;
248 }
249
zynqmp_sha_remove(struct platform_device * pdev)250 static void zynqmp_sha_remove(struct platform_device *pdev)
251 {
252 sha3_drv_ctx.dev = platform_get_drvdata(pdev);
253
254 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
255 dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
256 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
257 }
258
259 static struct platform_driver zynqmp_sha_driver = {
260 .probe = zynqmp_sha_probe,
261 .remove_new = zynqmp_sha_remove,
262 .driver = {
263 .name = "zynqmp-sha3-384",
264 },
265 };
266
267 module_platform_driver(zynqmp_sha_driver);
268 MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support.");
269 MODULE_LICENSE("GPL v2");
270 MODULE_AUTHOR("Harsha <harsha.harsha@xilinx.com>");
271