1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12 #include <dt-bindings/dma/fsl-edma.h>
13 #include <linux/bitfield.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/clk.h>
17 #include <linux/of.h>
18 #include <linux/of_dma.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_domain.h>
22 #include <linux/property.h>
23
24 #include "fsl-edma-common.h"
25
fsl_edma_synchronize(struct dma_chan * chan)26 static void fsl_edma_synchronize(struct dma_chan *chan)
27 {
28 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
29
30 vchan_synchronize(&fsl_chan->vchan);
31 }
32
fsl_edma_tx_handler(int irq,void * dev_id)33 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
34 {
35 struct fsl_edma_engine *fsl_edma = dev_id;
36 unsigned int intr, ch;
37 struct edma_regs *regs = &fsl_edma->regs;
38
39 intr = edma_readl(fsl_edma, regs->intl);
40 if (!intr)
41 return IRQ_NONE;
42
43 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
44 if (intr & (0x1 << ch)) {
45 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
46 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
47 }
48 }
49 return IRQ_HANDLED;
50 }
51
fsl_edma3_tx_handler(int irq,void * dev_id)52 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
53 {
54 struct fsl_edma_chan *fsl_chan = dev_id;
55 unsigned int intr;
56
57 intr = edma_readl_chreg(fsl_chan, ch_int);
58 if (!intr)
59 return IRQ_NONE;
60
61 edma_writel_chreg(fsl_chan, 1, ch_int);
62
63 fsl_edma_tx_chan_handler(fsl_chan);
64
65 return IRQ_HANDLED;
66 }
67
fsl_edma2_tx_handler(int irq,void * devi_id)68 static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id)
69 {
70 struct fsl_edma_chan *fsl_chan = devi_id;
71
72 return fsl_edma_tx_handler(irq, fsl_chan->edma);
73 }
74
fsl_edma_err_handler(int irq,void * dev_id)75 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
76 {
77 struct fsl_edma_engine *fsl_edma = dev_id;
78 unsigned int err, ch;
79 struct edma_regs *regs = &fsl_edma->regs;
80
81 err = edma_readl(fsl_edma, regs->errl);
82 if (!err)
83 return IRQ_NONE;
84
85 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
86 if (err & (0x1 << ch)) {
87 fsl_edma_disable_request(&fsl_edma->chans[ch]);
88 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
89 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
90 }
91 }
92 return IRQ_HANDLED;
93 }
94
fsl_edma_irq_handler(int irq,void * dev_id)95 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
96 {
97 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
98 return IRQ_HANDLED;
99
100 return fsl_edma_err_handler(irq, dev_id);
101 }
102
fsl_edma_srcid_in_use(struct fsl_edma_engine * fsl_edma,u32 srcid)103 static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid)
104 {
105 struct fsl_edma_chan *fsl_chan;
106 int i;
107
108 for (i = 0; i < fsl_edma->n_chans; i++) {
109 fsl_chan = &fsl_edma->chans[i];
110
111 if (fsl_chan->srcid && srcid == fsl_chan->srcid) {
112 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!");
113 return true;
114 }
115 }
116 return false;
117 }
118
fsl_edma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)119 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
120 struct of_dma *ofdma)
121 {
122 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
123 struct dma_chan *chan, *_chan;
124 struct fsl_edma_chan *fsl_chan;
125 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
126 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
127
128 if (dma_spec->args_count != 2)
129 return NULL;
130
131 guard(mutex)(&fsl_edma->fsl_edma_mutex);
132
133 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
134 if (chan->client_count)
135 continue;
136
137 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1]))
138 return NULL;
139
140 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
141 chan = dma_get_slave_channel(chan);
142 if (chan) {
143 chan->device->privatecnt++;
144 fsl_chan = to_fsl_edma_chan(chan);
145 fsl_chan->srcid = dma_spec->args[1];
146
147 if (!fsl_chan->srcid) {
148 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n",
149 fsl_chan->srcid);
150 return NULL;
151 }
152
153 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid,
154 true);
155 return chan;
156 }
157 }
158 }
159 return NULL;
160 }
161
fsl_edma3_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)162 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
163 struct of_dma *ofdma)
164 {
165 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
166 struct dma_chan *chan, *_chan;
167 struct fsl_edma_chan *fsl_chan;
168 bool b_chmux;
169 int i;
170
171 if (dma_spec->args_count != 3)
172 return NULL;
173
174 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
175
176 guard(mutex)(&fsl_edma->fsl_edma_mutex);
177 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
178 device_node) {
179
180 if (chan->client_count)
181 continue;
182
183 fsl_chan = to_fsl_edma_chan(chan);
184 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0]))
185 return NULL;
186 i = fsl_chan - fsl_edma->chans;
187
188 fsl_chan->priority = dma_spec->args[1];
189 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
190 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
191 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
192
193 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
194 continue;
195
196 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
197 continue;
198
199 if (!b_chmux && i == dma_spec->args[0]) {
200 chan = dma_get_slave_channel(chan);
201 chan->device->privatecnt++;
202 return chan;
203 } else if (b_chmux && !fsl_chan->srcid) {
204 /* if controller support channel mux, choose a free channel */
205 chan = dma_get_slave_channel(chan);
206 chan->device->privatecnt++;
207 fsl_chan->srcid = dma_spec->args[0];
208 return chan;
209 }
210 }
211 return NULL;
212 }
213
214 static int
fsl_edma_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)215 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
216 {
217 int ret;
218
219 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
220
221 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
222 if (fsl_edma->txirq < 0)
223 return fsl_edma->txirq;
224
225 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
226 if (fsl_edma->errirq < 0)
227 return fsl_edma->errirq;
228
229 if (fsl_edma->txirq == fsl_edma->errirq) {
230 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
231 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
232 if (ret) {
233 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
234 return ret;
235 }
236 } else {
237 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
238 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
239 if (ret) {
240 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
241 return ret;
242 }
243
244 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
245 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
246 if (ret) {
247 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
248 return ret;
249 }
250 }
251
252 return 0;
253 }
254
fsl_edma3_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)255 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
256 {
257 int i;
258
259 for (i = 0; i < fsl_edma->n_chans; i++) {
260
261 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
262
263 if (fsl_edma->chan_masked & BIT(i))
264 continue;
265
266 /* request channel irq */
267 fsl_chan->txirq = platform_get_irq(pdev, i);
268 if (fsl_chan->txirq < 0)
269 return -EINVAL;
270
271 fsl_chan->irq_handler = fsl_edma3_tx_handler;
272 }
273
274 return 0;
275 }
276
277 static int
fsl_edma2_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)278 fsl_edma2_irq_init(struct platform_device *pdev,
279 struct fsl_edma_engine *fsl_edma)
280 {
281 int i, ret, irq;
282 int count;
283
284 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
285
286 count = platform_irq_count(pdev);
287 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
288 if (count <= 2) {
289 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
290 return -EINVAL;
291 }
292 /*
293 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
294 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
295 * For now, just simply request irq without IRQF_SHARED flag, since 16
296 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
297 */
298 for (i = 0; i < count; i++) {
299 irq = platform_get_irq(pdev, i);
300 ret = 0;
301 if (irq < 0)
302 return -ENXIO;
303
304 /* The last IRQ is for eDMA err */
305 if (i == count - 1) {
306 fsl_edma->errirq = irq;
307 ret = devm_request_irq(&pdev->dev, irq,
308 fsl_edma_err_handler,
309 0, "eDMA2-ERR", fsl_edma);
310 } else {
311 fsl_edma->chans[i].txirq = irq;
312 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler;
313 }
314
315 if (ret)
316 return ret;
317 }
318
319 return 0;
320 }
321
fsl_edma_irq_exit(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)322 static void fsl_edma_irq_exit(
323 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
324 {
325 if (fsl_edma->txirq == fsl_edma->errirq) {
326 if (fsl_edma->txirq >= 0)
327 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
328 } else {
329 if (fsl_edma->txirq >= 0)
330 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
331 if (fsl_edma->errirq >= 0)
332 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
333 }
334 }
335
fsl_disable_clocks(struct fsl_edma_engine * fsl_edma,int nr_clocks)336 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
337 {
338 int i;
339
340 for (i = 0; i < nr_clocks; i++)
341 clk_disable_unprepare(fsl_edma->muxclk[i]);
342 }
343
344 static struct fsl_edma_drvdata vf610_data = {
345 .dmamuxs = DMAMUX_NR,
346 .flags = FSL_EDMA_DRV_WRAP_IO,
347 .chreg_off = EDMA_TCD,
348 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
349 .setup_irq = fsl_edma_irq_init,
350 };
351
352 static struct fsl_edma_drvdata ls1028a_data = {
353 .dmamuxs = DMAMUX_NR,
354 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
355 .chreg_off = EDMA_TCD,
356 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
357 .setup_irq = fsl_edma_irq_init,
358 };
359
360 static struct fsl_edma_drvdata imx7ulp_data = {
361 .dmamuxs = 1,
362 .chreg_off = EDMA_TCD,
363 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
364 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
365 .setup_irq = fsl_edma2_irq_init,
366 };
367
368 static struct fsl_edma_drvdata imx8qm_data = {
369 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE,
370 .chreg_space_sz = 0x10000,
371 .chreg_off = 0x10000,
372 .setup_irq = fsl_edma3_irq_init,
373 };
374
375 static struct fsl_edma_drvdata imx8ulp_data = {
376 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
377 FSL_EDMA_DRV_EDMA3,
378 .chreg_space_sz = 0x10000,
379 .chreg_off = 0x10000,
380 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
381 .mux_skip = 0x10000,
382 .setup_irq = fsl_edma3_irq_init,
383 };
384
385 static struct fsl_edma_drvdata imx93_data3 = {
386 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
387 .chreg_space_sz = 0x10000,
388 .chreg_off = 0x10000,
389 .setup_irq = fsl_edma3_irq_init,
390 };
391
392 static struct fsl_edma_drvdata imx93_data4 = {
393 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
394 .chreg_space_sz = 0x8000,
395 .chreg_off = 0x10000,
396 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
397 .mux_skip = 0x8000,
398 .setup_irq = fsl_edma3_irq_init,
399 };
400
401 static struct fsl_edma_drvdata imx95_data5 = {
402 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 |
403 FSL_EDMA_DRV_TCD64,
404 .chreg_space_sz = 0x8000,
405 .chreg_off = 0x10000,
406 .mux_off = 0x200,
407 .mux_skip = sizeof(u32),
408 .setup_irq = fsl_edma3_irq_init,
409 };
410
411 static const struct of_device_id fsl_edma_dt_ids[] = {
412 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
413 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
414 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
415 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
416 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
417 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
418 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
419 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
420 { /* sentinel */ }
421 };
422 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
423
fsl_edma3_detach_pd(struct fsl_edma_engine * fsl_edma)424 static void fsl_edma3_detach_pd(struct fsl_edma_engine *fsl_edma)
425 {
426 struct fsl_edma_chan *fsl_chan;
427 int i;
428
429 for (i = 0; i < fsl_edma->n_chans; i++) {
430 if (fsl_edma->chan_masked & BIT(i))
431 continue;
432 fsl_chan = &fsl_edma->chans[i];
433 if (fsl_chan->pd_dev_link)
434 device_link_del(fsl_chan->pd_dev_link);
435 if (fsl_chan->pd_dev) {
436 dev_pm_domain_detach(fsl_chan->pd_dev, false);
437 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev);
438 pm_runtime_set_suspended(fsl_chan->pd_dev);
439 }
440 }
441 }
442
devm_fsl_edma3_detach_pd(void * data)443 static void devm_fsl_edma3_detach_pd(void *data)
444 {
445 fsl_edma3_detach_pd(data);
446 }
447
fsl_edma3_attach_pd(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)448 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
449 {
450 struct fsl_edma_chan *fsl_chan;
451 struct device *pd_chan;
452 struct device *dev;
453 int i;
454
455 dev = &pdev->dev;
456
457 for (i = 0; i < fsl_edma->n_chans; i++) {
458 if (fsl_edma->chan_masked & BIT(i))
459 continue;
460
461 fsl_chan = &fsl_edma->chans[i];
462
463 pd_chan = dev_pm_domain_attach_by_id(dev, i);
464 if (IS_ERR_OR_NULL(pd_chan)) {
465 dev_err(dev, "Failed attach pd %d\n", i);
466 goto detach;
467 }
468
469 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
470 DL_FLAG_PM_RUNTIME |
471 DL_FLAG_RPM_ACTIVE);
472 if (!fsl_chan->pd_dev_link) {
473 dev_err(dev, "Failed to add device_link to %d\n", i);
474 dev_pm_domain_detach(pd_chan, false);
475 goto detach;
476 }
477
478 fsl_chan->pd_dev = pd_chan;
479
480 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
481 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
482 pm_runtime_set_active(fsl_chan->pd_dev);
483 }
484
485 return 0;
486
487 detach:
488 fsl_edma3_detach_pd(fsl_edma);
489 return -EINVAL;
490 }
491
fsl_edma_probe(struct platform_device * pdev)492 static int fsl_edma_probe(struct platform_device *pdev)
493 {
494 struct device_node *np = pdev->dev.of_node;
495 struct fsl_edma_engine *fsl_edma;
496 const struct fsl_edma_drvdata *drvdata = NULL;
497 u32 chan_mask[2] = {0, 0};
498 char clk_name[36];
499 struct edma_regs *regs;
500 int chans;
501 int ret, i;
502
503 drvdata = device_get_match_data(&pdev->dev);
504 if (!drvdata) {
505 dev_err(&pdev->dev, "unable to find driver data\n");
506 return -EINVAL;
507 }
508
509 ret = of_property_read_u32(np, "dma-channels", &chans);
510 if (ret) {
511 dev_err(&pdev->dev, "Can't get dma-channels.\n");
512 return ret;
513 }
514
515 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
516 GFP_KERNEL);
517 if (!fsl_edma)
518 return -ENOMEM;
519
520 fsl_edma->errirq = -EINVAL;
521 fsl_edma->txirq = -EINVAL;
522 fsl_edma->drvdata = drvdata;
523 fsl_edma->n_chans = chans;
524 mutex_init(&fsl_edma->fsl_edma_mutex);
525
526 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
527 if (IS_ERR(fsl_edma->membase))
528 return PTR_ERR(fsl_edma->membase);
529
530 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
531 fsl_edma_setup_regs(fsl_edma);
532 regs = &fsl_edma->regs;
533 }
534
535 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
536 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
537 if (IS_ERR(fsl_edma->dmaclk)) {
538 dev_err(&pdev->dev, "Missing DMA block clock.\n");
539 return PTR_ERR(fsl_edma->dmaclk);
540 }
541 }
542
543 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
544
545 if (ret > 0) {
546 fsl_edma->chan_masked = chan_mask[1];
547 fsl_edma->chan_masked <<= 32;
548 fsl_edma->chan_masked |= chan_mask[0];
549 }
550
551 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
552 char clkname[32];
553
554 /* eDMAv3 mux register move to TCD area if ch_mux exist */
555 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
556 break;
557
558 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
559 1 + i);
560 if (IS_ERR(fsl_edma->muxbase[i])) {
561 /* on error: disable all previously enabled clks */
562 fsl_disable_clocks(fsl_edma, i);
563 return PTR_ERR(fsl_edma->muxbase[i]);
564 }
565
566 sprintf(clkname, "dmamux%d", i);
567 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
568 if (IS_ERR(fsl_edma->muxclk[i])) {
569 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
570 /* on error: disable all previously enabled clks */
571 return PTR_ERR(fsl_edma->muxclk[i]);
572 }
573 }
574
575 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
576
577 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
578 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
579 if (ret)
580 return ret;
581 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma);
582 if (ret)
583 return ret;
584 }
585
586 if (drvdata->flags & FSL_EDMA_DRV_TCD64)
587 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
588
589 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
590 for (i = 0; i < fsl_edma->n_chans; i++) {
591 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
592 int len;
593
594 if (fsl_edma->chan_masked & BIT(i))
595 continue;
596
597 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
598 dev_name(&pdev->dev), i);
599
600 fsl_chan->edma = fsl_edma;
601 fsl_chan->pm_state = RUNNING;
602 fsl_chan->srcid = 0;
603 fsl_chan->dma_dir = DMA_NONE;
604 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
605
606 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
607 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
608 fsl_chan->tcd = fsl_edma->membase
609 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
610 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
611
612 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
613 snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
614 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
615 (const char *)clk_name);
616
617 if (IS_ERR(fsl_chan->clk))
618 return PTR_ERR(fsl_chan->clk);
619 }
620 fsl_chan->pdev = pdev;
621 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
622
623 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);
624 fsl_edma_chan_mux(fsl_chan, 0, false);
625 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
626 clk_disable_unprepare(fsl_chan->clk);
627 }
628
629 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
630 if (ret)
631 return ret;
632
633 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
634 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
635 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
636 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
637
638 fsl_edma->dma_dev.dev = &pdev->dev;
639 fsl_edma->dma_dev.device_alloc_chan_resources
640 = fsl_edma_alloc_chan_resources;
641 fsl_edma->dma_dev.device_free_chan_resources
642 = fsl_edma_free_chan_resources;
643 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
644 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
645 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
646 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
647 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
648 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
649 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
650 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
651 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
652 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
653
654 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
655 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
656
657 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
658 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
659 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
660 }
661
662 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
663 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
664 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
665
666 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
667 DMAENGINE_ALIGN_64_BYTES :
668 DMAENGINE_ALIGN_32_BYTES;
669
670 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
671 dma_set_max_seg_size(fsl_edma->dma_dev.dev,
672 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
673
674 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
675
676 platform_set_drvdata(pdev, fsl_edma);
677
678 ret = dma_async_device_register(&fsl_edma->dma_dev);
679 if (ret) {
680 dev_err(&pdev->dev,
681 "Can't register Freescale eDMA engine. (%d)\n", ret);
682 return ret;
683 }
684
685 ret = of_dma_controller_register(np,
686 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
687 fsl_edma);
688 if (ret) {
689 dev_err(&pdev->dev,
690 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
691 dma_async_device_unregister(&fsl_edma->dma_dev);
692 return ret;
693 }
694
695 /* enable round robin arbitration */
696 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
697 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
698
699 return 0;
700 }
701
fsl_edma_remove(struct platform_device * pdev)702 static void fsl_edma_remove(struct platform_device *pdev)
703 {
704 struct device_node *np = pdev->dev.of_node;
705 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
706
707 fsl_edma_irq_exit(pdev, fsl_edma);
708 of_dma_controller_free(np);
709 dma_async_device_unregister(&fsl_edma->dma_dev);
710 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
711 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
712 }
713
fsl_edma_suspend_late(struct device * dev)714 static int fsl_edma_suspend_late(struct device *dev)
715 {
716 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
717 struct fsl_edma_chan *fsl_chan;
718 unsigned long flags;
719 int i;
720
721 for (i = 0; i < fsl_edma->n_chans; i++) {
722 fsl_chan = &fsl_edma->chans[i];
723 if (fsl_edma->chan_masked & BIT(i))
724 continue;
725 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
726 /* Make sure chan is idle or will force disable. */
727 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
728 dev_warn(dev, "WARN: There is non-idle channel.");
729 fsl_edma_disable_request(fsl_chan);
730 fsl_edma_chan_mux(fsl_chan, 0, false);
731 }
732
733 fsl_chan->pm_state = SUSPENDED;
734 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
735 }
736
737 return 0;
738 }
739
fsl_edma_resume_early(struct device * dev)740 static int fsl_edma_resume_early(struct device *dev)
741 {
742 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
743 struct fsl_edma_chan *fsl_chan;
744 struct edma_regs *regs = &fsl_edma->regs;
745 int i;
746
747 for (i = 0; i < fsl_edma->n_chans; i++) {
748 fsl_chan = &fsl_edma->chans[i];
749 if (fsl_edma->chan_masked & BIT(i))
750 continue;
751 fsl_chan->pm_state = RUNNING;
752 edma_write_tcdreg(fsl_chan, 0, csr);
753 if (fsl_chan->srcid != 0)
754 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true);
755 }
756
757 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
758 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
759
760 return 0;
761 }
762
763 /*
764 * eDMA provides the service to others, so it should be suspend late
765 * and resume early. When eDMA suspend, all of the clients should stop
766 * the DMA data transmission and let the channel idle.
767 */
768 static const struct dev_pm_ops fsl_edma_pm_ops = {
769 .suspend_late = fsl_edma_suspend_late,
770 .resume_early = fsl_edma_resume_early,
771 };
772
773 static struct platform_driver fsl_edma_driver = {
774 .driver = {
775 .name = "fsl-edma",
776 .of_match_table = fsl_edma_dt_ids,
777 .pm = &fsl_edma_pm_ops,
778 },
779 .probe = fsl_edma_probe,
780 .remove_new = fsl_edma_remove,
781 };
782
fsl_edma_init(void)783 static int __init fsl_edma_init(void)
784 {
785 return platform_driver_register(&fsl_edma_driver);
786 }
787 subsys_initcall(fsl_edma_init);
788
fsl_edma_exit(void)789 static void __exit fsl_edma_exit(void)
790 {
791 platform_driver_unregister(&fsl_edma_driver);
792 }
793 module_exit(fsl_edma_exit);
794
795 MODULE_ALIAS("platform:fsl-edma");
796 MODULE_DESCRIPTION("Freescale eDMA engine driver");
797 MODULE_LICENSE("GPL v2");
798