1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/slab.h>
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/workqueue.h>
12 #include <linux/fs.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/device.h>
15 #include <linux/idr.h>
16 #include <linux/iommu.h>
17 #include <uapi/linux/idxd.h>
18 #include <linux/dmaengine.h>
19 #include "../dmaengine.h"
20 #include "registers.h"
21 #include "idxd.h"
22 #include "perfmon.h"
23
24 MODULE_VERSION(IDXD_DRIVER_VERSION);
25 MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common driver");
26 MODULE_LICENSE("GPL v2");
27 MODULE_AUTHOR("Intel Corporation");
28 MODULE_IMPORT_NS(IDXD);
29
30 static bool sva = true;
31 module_param(sva, bool, 0644);
32 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
33
34 bool tc_override;
35 module_param(tc_override, bool, 0644);
36 MODULE_PARM_DESC(tc_override, "Override traffic class defaults");
37
38 #define DRV_NAME "idxd"
39
40 bool support_enqcmd;
41 DEFINE_IDA(idxd_ida);
42
43 static struct idxd_driver_data idxd_driver_data[] = {
44 [IDXD_TYPE_DSA] = {
45 .name_prefix = "dsa",
46 .type = IDXD_TYPE_DSA,
47 .compl_size = sizeof(struct dsa_completion_record),
48 .align = 32,
49 .dev_type = &dsa_device_type,
50 .evl_cr_off = offsetof(struct dsa_evl_entry, cr),
51 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
52 .cr_status_off = offsetof(struct dsa_completion_record, status),
53 .cr_result_off = offsetof(struct dsa_completion_record, result),
54 },
55 [IDXD_TYPE_IAX] = {
56 .name_prefix = "iax",
57 .type = IDXD_TYPE_IAX,
58 .compl_size = sizeof(struct iax_completion_record),
59 .align = 64,
60 .dev_type = &iax_device_type,
61 .evl_cr_off = offsetof(struct iax_evl_entry, cr),
62 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
63 .cr_status_off = offsetof(struct iax_completion_record, status),
64 .cr_result_off = offsetof(struct iax_completion_record, error_code),
65 .load_device_defaults = idxd_load_iaa_device_defaults,
66 },
67 };
68
69 static struct pci_device_id idxd_pci_tbl[] = {
70 /* DSA ver 1.0 platforms */
71 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
72 /* DSA on GNR-D platforms */
73 { PCI_DEVICE_DATA(INTEL, DSA_GNRD, &idxd_driver_data[IDXD_TYPE_DSA]) },
74 /* DSA on DMR platforms */
75 { PCI_DEVICE_DATA(INTEL, DSA_DMR, &idxd_driver_data[IDXD_TYPE_DSA]) },
76
77 /* IAX ver 1.0 platforms */
78 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
79 /* IAA on DMR platforms */
80 { PCI_DEVICE_DATA(INTEL, IAA_DMR, &idxd_driver_data[IDXD_TYPE_IAX]) },
81 { 0, }
82 };
83 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
84
idxd_setup_interrupts(struct idxd_device * idxd)85 static int idxd_setup_interrupts(struct idxd_device *idxd)
86 {
87 struct pci_dev *pdev = idxd->pdev;
88 struct device *dev = &pdev->dev;
89 struct idxd_irq_entry *ie;
90 int i, msixcnt;
91 int rc = 0;
92
93 msixcnt = pci_msix_vec_count(pdev);
94 if (msixcnt < 0) {
95 dev_err(dev, "Not MSI-X interrupt capable.\n");
96 return -ENOSPC;
97 }
98 idxd->irq_cnt = msixcnt;
99
100 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
101 if (rc != msixcnt) {
102 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
103 return -ENOSPC;
104 }
105 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
106
107
108 ie = idxd_get_ie(idxd, 0);
109 ie->vector = pci_irq_vector(pdev, 0);
110 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie);
111 if (rc < 0) {
112 dev_err(dev, "Failed to allocate misc interrupt.\n");
113 goto err_misc_irq;
114 }
115 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
116
117 for (i = 0; i < idxd->max_wqs; i++) {
118 int msix_idx = i + 1;
119
120 ie = idxd_get_ie(idxd, msix_idx);
121 ie->id = msix_idx;
122 ie->int_handle = INVALID_INT_HANDLE;
123 ie->pasid = IOMMU_PASID_INVALID;
124
125 spin_lock_init(&ie->list_lock);
126 init_llist_head(&ie->pending_llist);
127 INIT_LIST_HEAD(&ie->work_list);
128 }
129
130 idxd_unmask_error_interrupts(idxd);
131 return 0;
132
133 err_misc_irq:
134 idxd_mask_error_interrupts(idxd);
135 pci_free_irq_vectors(pdev);
136 dev_err(dev, "No usable interrupts\n");
137 return rc;
138 }
139
idxd_cleanup_interrupts(struct idxd_device * idxd)140 static void idxd_cleanup_interrupts(struct idxd_device *idxd)
141 {
142 struct pci_dev *pdev = idxd->pdev;
143 struct idxd_irq_entry *ie;
144 int msixcnt;
145
146 msixcnt = pci_msix_vec_count(pdev);
147 if (msixcnt <= 0)
148 return;
149
150 ie = idxd_get_ie(idxd, 0);
151 idxd_mask_error_interrupts(idxd);
152 free_irq(ie->vector, ie);
153 pci_free_irq_vectors(pdev);
154 }
155
idxd_clean_wqs(struct idxd_device * idxd)156 static void idxd_clean_wqs(struct idxd_device *idxd)
157 {
158 struct idxd_wq *wq;
159 struct device *conf_dev;
160 int i;
161
162 for (i = 0; i < idxd->max_wqs; i++) {
163 wq = idxd->wqs[i];
164 if (idxd->hw.wq_cap.op_config)
165 bitmap_free(wq->opcap_bmap);
166 kfree(wq->wqcfg);
167 conf_dev = wq_confdev(wq);
168 put_device(conf_dev);
169 kfree(wq);
170 }
171 bitmap_free(idxd->wq_enable_map);
172 kfree(idxd->wqs);
173 }
174
idxd_setup_wqs(struct idxd_device * idxd)175 static int idxd_setup_wqs(struct idxd_device *idxd)
176 {
177 struct device *dev = &idxd->pdev->dev;
178 struct idxd_wq *wq;
179 struct device *conf_dev;
180 int i, rc;
181
182 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
183 GFP_KERNEL, dev_to_node(dev));
184 if (!idxd->wqs)
185 return -ENOMEM;
186
187 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev));
188 if (!idxd->wq_enable_map) {
189 rc = -ENOMEM;
190 goto err_free_wqs;
191 }
192
193 for (i = 0; i < idxd->max_wqs; i++) {
194 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
195 if (!wq) {
196 rc = -ENOMEM;
197 goto err_unwind;
198 }
199
200 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ);
201 conf_dev = wq_confdev(wq);
202 wq->id = i;
203 wq->idxd = idxd;
204 device_initialize(conf_dev);
205 conf_dev->parent = idxd_confdev(idxd);
206 conf_dev->bus = &dsa_bus_type;
207 conf_dev->type = &idxd_wq_device_type;
208 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id);
209 if (rc < 0) {
210 put_device(conf_dev);
211 kfree(wq);
212 goto err_unwind;
213 }
214
215 mutex_init(&wq->wq_lock);
216 init_waitqueue_head(&wq->err_queue);
217 init_completion(&wq->wq_dead);
218 init_completion(&wq->wq_resurrect);
219 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
220 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
221 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
222 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
223 if (!wq->wqcfg) {
224 put_device(conf_dev);
225 kfree(wq);
226 rc = -ENOMEM;
227 goto err_unwind;
228 }
229
230 if (idxd->hw.wq_cap.op_config) {
231 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL);
232 if (!wq->opcap_bmap) {
233 kfree(wq->wqcfg);
234 put_device(conf_dev);
235 kfree(wq);
236 rc = -ENOMEM;
237 goto err_unwind;
238 }
239 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
240 }
241 mutex_init(&wq->uc_lock);
242 xa_init(&wq->upasid_xa);
243 idxd->wqs[i] = wq;
244 }
245
246 return 0;
247
248 err_unwind:
249 while (--i >= 0) {
250 wq = idxd->wqs[i];
251 if (idxd->hw.wq_cap.op_config)
252 bitmap_free(wq->opcap_bmap);
253 kfree(wq->wqcfg);
254 conf_dev = wq_confdev(wq);
255 put_device(conf_dev);
256 kfree(wq);
257 }
258 bitmap_free(idxd->wq_enable_map);
259
260 err_free_wqs:
261 kfree(idxd->wqs);
262
263 return rc;
264 }
265
idxd_clean_engines(struct idxd_device * idxd)266 static void idxd_clean_engines(struct idxd_device *idxd)
267 {
268 struct idxd_engine *engine;
269 struct device *conf_dev;
270 int i;
271
272 for (i = 0; i < idxd->max_engines; i++) {
273 engine = idxd->engines[i];
274 conf_dev = engine_confdev(engine);
275 put_device(conf_dev);
276 kfree(engine);
277 }
278 kfree(idxd->engines);
279 }
280
idxd_setup_engines(struct idxd_device * idxd)281 static int idxd_setup_engines(struct idxd_device *idxd)
282 {
283 struct idxd_engine *engine;
284 struct device *dev = &idxd->pdev->dev;
285 struct device *conf_dev;
286 int i, rc;
287
288 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
289 GFP_KERNEL, dev_to_node(dev));
290 if (!idxd->engines)
291 return -ENOMEM;
292
293 for (i = 0; i < idxd->max_engines; i++) {
294 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
295 if (!engine) {
296 rc = -ENOMEM;
297 goto err;
298 }
299
300 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE);
301 conf_dev = engine_confdev(engine);
302 engine->id = i;
303 engine->idxd = idxd;
304 device_initialize(conf_dev);
305 conf_dev->parent = idxd_confdev(idxd);
306 conf_dev->bus = &dsa_bus_type;
307 conf_dev->type = &idxd_engine_device_type;
308 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id);
309 if (rc < 0) {
310 put_device(conf_dev);
311 kfree(engine);
312 goto err;
313 }
314
315 idxd->engines[i] = engine;
316 }
317
318 return 0;
319
320 err:
321 while (--i >= 0) {
322 engine = idxd->engines[i];
323 conf_dev = engine_confdev(engine);
324 put_device(conf_dev);
325 kfree(engine);
326 }
327 kfree(idxd->engines);
328
329 return rc;
330 }
331
idxd_clean_groups(struct idxd_device * idxd)332 static void idxd_clean_groups(struct idxd_device *idxd)
333 {
334 struct idxd_group *group;
335 int i;
336
337 for (i = 0; i < idxd->max_groups; i++) {
338 group = idxd->groups[i];
339 put_device(group_confdev(group));
340 kfree(group);
341 }
342 kfree(idxd->groups);
343 }
344
idxd_setup_groups(struct idxd_device * idxd)345 static int idxd_setup_groups(struct idxd_device *idxd)
346 {
347 struct device *dev = &idxd->pdev->dev;
348 struct device *conf_dev;
349 struct idxd_group *group;
350 int i, rc;
351
352 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
353 GFP_KERNEL, dev_to_node(dev));
354 if (!idxd->groups)
355 return -ENOMEM;
356
357 for (i = 0; i < idxd->max_groups; i++) {
358 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
359 if (!group) {
360 rc = -ENOMEM;
361 goto err;
362 }
363
364 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP);
365 conf_dev = group_confdev(group);
366 group->id = i;
367 group->idxd = idxd;
368 device_initialize(conf_dev);
369 conf_dev->parent = idxd_confdev(idxd);
370 conf_dev->bus = &dsa_bus_type;
371 conf_dev->type = &idxd_group_device_type;
372 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id);
373 if (rc < 0) {
374 put_device(conf_dev);
375 kfree(group);
376 goto err;
377 }
378
379 idxd->groups[i] = group;
380 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
381 group->tc_a = 1;
382 group->tc_b = 1;
383 } else {
384 group->tc_a = -1;
385 group->tc_b = -1;
386 }
387 /*
388 * The default value is the same as the value of
389 * total read buffers in GRPCAP.
390 */
391 group->rdbufs_allowed = idxd->max_rdbufs;
392 }
393
394 return 0;
395
396 err:
397 while (--i >= 0) {
398 group = idxd->groups[i];
399 put_device(group_confdev(group));
400 kfree(group);
401 }
402 kfree(idxd->groups);
403
404 return rc;
405 }
406
idxd_cleanup_internals(struct idxd_device * idxd)407 static void idxd_cleanup_internals(struct idxd_device *idxd)
408 {
409 idxd_clean_groups(idxd);
410 idxd_clean_engines(idxd);
411 idxd_clean_wqs(idxd);
412 destroy_workqueue(idxd->wq);
413 }
414
idxd_init_evl(struct idxd_device * idxd)415 static int idxd_init_evl(struct idxd_device *idxd)
416 {
417 struct device *dev = &idxd->pdev->dev;
418 unsigned int evl_cache_size;
419 struct idxd_evl *evl;
420 const char *idxd_name;
421
422 if (idxd->hw.gen_cap.evl_support == 0)
423 return 0;
424
425 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev));
426 if (!evl)
427 return -ENOMEM;
428
429 mutex_init(&evl->lock);
430 evl->size = IDXD_EVL_SIZE_MIN;
431
432 idxd_name = dev_name(idxd_confdev(idxd));
433 evl_cache_size = sizeof(struct idxd_evl_fault) + evl_ent_size(idxd);
434 /*
435 * Since completion record in evl_cache will be copied to user
436 * when handling completion record page fault, need to create
437 * the cache suitable for user copy.
438 */
439 idxd->evl_cache = kmem_cache_create_usercopy(idxd_name, evl_cache_size,
440 0, 0, 0, evl_cache_size,
441 NULL);
442 if (!idxd->evl_cache) {
443 kfree(evl);
444 return -ENOMEM;
445 }
446
447 idxd->evl = evl;
448 return 0;
449 }
450
idxd_setup_internals(struct idxd_device * idxd)451 static int idxd_setup_internals(struct idxd_device *idxd)
452 {
453 struct device *dev = &idxd->pdev->dev;
454 int rc;
455
456 init_waitqueue_head(&idxd->cmd_waitq);
457
458 rc = idxd_setup_wqs(idxd);
459 if (rc < 0)
460 goto err_wqs;
461
462 rc = idxd_setup_engines(idxd);
463 if (rc < 0)
464 goto err_engine;
465
466 rc = idxd_setup_groups(idxd);
467 if (rc < 0)
468 goto err_group;
469
470 idxd->wq = create_workqueue(dev_name(dev));
471 if (!idxd->wq) {
472 rc = -ENOMEM;
473 goto err_wkq_create;
474 }
475
476 rc = idxd_init_evl(idxd);
477 if (rc < 0)
478 goto err_evl;
479
480 return 0;
481
482 err_evl:
483 destroy_workqueue(idxd->wq);
484 err_wkq_create:
485 idxd_clean_groups(idxd);
486 err_group:
487 idxd_clean_engines(idxd);
488 err_engine:
489 idxd_clean_wqs(idxd);
490 err_wqs:
491 return rc;
492 }
493
idxd_read_table_offsets(struct idxd_device * idxd)494 static void idxd_read_table_offsets(struct idxd_device *idxd)
495 {
496 union offsets_reg offsets;
497 struct device *dev = &idxd->pdev->dev;
498
499 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
500 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
501 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
502 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
503 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
504 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
505 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
506 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
507 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
508 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
509 }
510
multi_u64_to_bmap(unsigned long * bmap,u64 * val,int count)511 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
512 {
513 int i, j, nr;
514
515 for (i = 0, nr = 0; i < count; i++) {
516 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
517 if (val[i] & BIT(j))
518 set_bit(nr, bmap);
519 nr++;
520 }
521 }
522 }
523
idxd_read_caps(struct idxd_device * idxd)524 static void idxd_read_caps(struct idxd_device *idxd)
525 {
526 struct device *dev = &idxd->pdev->dev;
527 int i;
528
529 /* reading generic capabilities */
530 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
531 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
532
533 if (idxd->hw.gen_cap.cmd_cap) {
534 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
535 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
536 }
537
538 /* reading command capabilities */
539 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))
540 idxd->request_int_handles = true;
541
542 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
543 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
544 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
545 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
546 if (idxd->hw.gen_cap.config_en)
547 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
548
549 /* reading group capabilities */
550 idxd->hw.group_cap.bits =
551 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
552 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
553 idxd->max_groups = idxd->hw.group_cap.num_groups;
554 dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
555 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs;
556 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs);
557 idxd->nr_rdbufs = idxd->max_rdbufs;
558
559 /* read engine capabilities */
560 idxd->hw.engine_cap.bits =
561 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
562 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
563 idxd->max_engines = idxd->hw.engine_cap.num_engines;
564 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
565
566 /* read workqueue capabilities */
567 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
568 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
569 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
570 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
571 idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
572 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
573 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
574 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
575
576 /* reading operation capabilities */
577 for (i = 0; i < 4; i++) {
578 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
579 IDXD_OPCAP_OFFSET + i * sizeof(u64));
580 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
581 }
582 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4);
583
584 /* read iaa cap */
585 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2)
586 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
587 }
588
idxd_free(struct idxd_device * idxd)589 static void idxd_free(struct idxd_device *idxd)
590 {
591 if (!idxd)
592 return;
593
594 put_device(idxd_confdev(idxd));
595 bitmap_free(idxd->opcap_bmap);
596 ida_free(&idxd_ida, idxd->id);
597 kfree(idxd);
598 }
599
idxd_alloc(struct pci_dev * pdev,struct idxd_driver_data * data)600 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
601 {
602 struct device *dev = &pdev->dev;
603 struct device *conf_dev;
604 struct idxd_device *idxd;
605 int rc;
606
607 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
608 if (!idxd)
609 return NULL;
610
611 conf_dev = idxd_confdev(idxd);
612 idxd->pdev = pdev;
613 idxd->data = data;
614 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type);
615 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
616 if (idxd->id < 0)
617 goto err_ida;
618
619 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
620 if (!idxd->opcap_bmap)
621 goto err_opcap;
622
623 device_initialize(conf_dev);
624 conf_dev->parent = dev;
625 conf_dev->bus = &dsa_bus_type;
626 conf_dev->type = idxd->data->dev_type;
627 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
628 if (rc < 0)
629 goto err_name;
630
631 spin_lock_init(&idxd->dev_lock);
632 spin_lock_init(&idxd->cmd_lock);
633
634 return idxd;
635
636 err_name:
637 put_device(conf_dev);
638 bitmap_free(idxd->opcap_bmap);
639 err_opcap:
640 ida_free(&idxd_ida, idxd->id);
641 err_ida:
642 kfree(idxd);
643
644 return NULL;
645 }
646
idxd_enable_system_pasid(struct idxd_device * idxd)647 static int idxd_enable_system_pasid(struct idxd_device *idxd)
648 {
649 struct pci_dev *pdev = idxd->pdev;
650 struct device *dev = &pdev->dev;
651 struct iommu_domain *domain;
652 ioasid_t pasid;
653 int ret;
654
655 /*
656 * Attach a global PASID to the DMA domain so that we can use ENQCMDS
657 * to submit work on buffers mapped by DMA API.
658 */
659 domain = iommu_get_domain_for_dev(dev);
660 if (!domain)
661 return -EPERM;
662
663 pasid = iommu_alloc_global_pasid(dev);
664 if (pasid == IOMMU_PASID_INVALID)
665 return -ENOSPC;
666
667 /*
668 * DMA domain is owned by the driver, it should support all valid
669 * types such as DMA-FQ, identity, etc.
670 */
671 ret = iommu_attach_device_pasid(domain, dev, pasid, NULL);
672 if (ret) {
673 dev_err(dev, "failed to attach device pasid %d, domain type %d",
674 pasid, domain->type);
675 iommu_free_global_pasid(pasid);
676 return ret;
677 }
678
679 /* Since we set user privilege for kernel DMA, enable completion IRQ */
680 idxd_set_user_intr(idxd, 1);
681 idxd->pasid = pasid;
682
683 return ret;
684 }
685
idxd_disable_system_pasid(struct idxd_device * idxd)686 static void idxd_disable_system_pasid(struct idxd_device *idxd)
687 {
688 struct pci_dev *pdev = idxd->pdev;
689 struct device *dev = &pdev->dev;
690 struct iommu_domain *domain;
691
692 domain = iommu_get_domain_for_dev(dev);
693 if (!domain)
694 return;
695
696 iommu_detach_device_pasid(domain, dev, idxd->pasid);
697 iommu_free_global_pasid(idxd->pasid);
698
699 idxd_set_user_intr(idxd, 0);
700 idxd->sva = NULL;
701 idxd->pasid = IOMMU_PASID_INVALID;
702 }
703
idxd_enable_sva(struct pci_dev * pdev)704 static int idxd_enable_sva(struct pci_dev *pdev)
705 {
706 int ret;
707
708 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
709 if (ret)
710 return ret;
711
712 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
713 if (ret)
714 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
715
716 return ret;
717 }
718
idxd_disable_sva(struct pci_dev * pdev)719 static void idxd_disable_sva(struct pci_dev *pdev)
720 {
721 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
722 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
723 }
724
idxd_probe(struct idxd_device * idxd)725 static int idxd_probe(struct idxd_device *idxd)
726 {
727 struct pci_dev *pdev = idxd->pdev;
728 struct device *dev = &pdev->dev;
729 int rc;
730
731 dev_dbg(dev, "%s entered and resetting device\n", __func__);
732 rc = idxd_device_init_reset(idxd);
733 if (rc < 0)
734 return rc;
735
736 dev_dbg(dev, "IDXD reset complete\n");
737
738 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
739 if (idxd_enable_sva(pdev)) {
740 dev_warn(dev, "Unable to turn on user SVA feature.\n");
741 } else {
742 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
743
744 rc = idxd_enable_system_pasid(idxd);
745 if (rc)
746 dev_warn(dev, "No in-kernel DMA with PASID. %d\n", rc);
747 else
748 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
749 }
750 } else if (!sva) {
751 dev_warn(dev, "User forced SVA off via module param.\n");
752 }
753
754 idxd_read_caps(idxd);
755 idxd_read_table_offsets(idxd);
756
757 rc = idxd_setup_internals(idxd);
758 if (rc)
759 goto err;
760
761 /* If the configs are readonly, then load them from device */
762 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
763 dev_dbg(dev, "Loading RO device config\n");
764 rc = idxd_device_load_config(idxd);
765 if (rc < 0)
766 goto err_config;
767 }
768
769 rc = idxd_setup_interrupts(idxd);
770 if (rc)
771 goto err_config;
772
773 idxd->major = idxd_cdev_get_major(idxd);
774
775 rc = perfmon_pmu_init(idxd);
776 if (rc < 0)
777 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
778
779 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
780 return 0;
781
782 err_config:
783 idxd_cleanup_internals(idxd);
784 err:
785 if (device_pasid_enabled(idxd))
786 idxd_disable_system_pasid(idxd);
787 if (device_user_pasid_enabled(idxd))
788 idxd_disable_sva(pdev);
789 return rc;
790 }
791
idxd_cleanup(struct idxd_device * idxd)792 static void idxd_cleanup(struct idxd_device *idxd)
793 {
794 perfmon_pmu_remove(idxd);
795 idxd_cleanup_interrupts(idxd);
796 idxd_cleanup_internals(idxd);
797 if (device_pasid_enabled(idxd))
798 idxd_disable_system_pasid(idxd);
799 if (device_user_pasid_enabled(idxd))
800 idxd_disable_sva(idxd->pdev);
801 }
802
idxd_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)803 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
804 {
805 struct device *dev = &pdev->dev;
806 struct idxd_device *idxd;
807 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
808 int rc;
809
810 rc = pci_enable_device(pdev);
811 if (rc)
812 return rc;
813
814 dev_dbg(dev, "Alloc IDXD context\n");
815 idxd = idxd_alloc(pdev, data);
816 if (!idxd) {
817 rc = -ENOMEM;
818 goto err_idxd_alloc;
819 }
820
821 dev_dbg(dev, "Mapping BARs\n");
822 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
823 if (!idxd->reg_base) {
824 rc = -ENOMEM;
825 goto err_iomap;
826 }
827
828 dev_dbg(dev, "Set DMA masks\n");
829 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
830 if (rc)
831 goto err;
832
833 dev_dbg(dev, "Set PCI master\n");
834 pci_set_master(pdev);
835 pci_set_drvdata(pdev, idxd);
836
837 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
838 rc = idxd_probe(idxd);
839 if (rc) {
840 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
841 goto err;
842 }
843
844 if (data->load_device_defaults) {
845 rc = data->load_device_defaults(idxd);
846 if (rc)
847 dev_warn(dev, "IDXD loading device defaults failed\n");
848 }
849
850 rc = idxd_register_devices(idxd);
851 if (rc) {
852 dev_err(dev, "IDXD sysfs setup failed\n");
853 goto err_dev_register;
854 }
855
856 rc = idxd_device_init_debugfs(idxd);
857 if (rc)
858 dev_warn(dev, "IDXD debugfs failed to setup\n");
859
860 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
861 idxd->hw.version);
862
863 idxd->user_submission_safe = data->user_submission_safe;
864
865 return 0;
866
867 err_dev_register:
868 idxd_cleanup(idxd);
869 err:
870 pci_iounmap(pdev, idxd->reg_base);
871 err_iomap:
872 idxd_free(idxd);
873 err_idxd_alloc:
874 pci_disable_device(pdev);
875 return rc;
876 }
877
idxd_wqs_quiesce(struct idxd_device * idxd)878 void idxd_wqs_quiesce(struct idxd_device *idxd)
879 {
880 struct idxd_wq *wq;
881 int i;
882
883 for (i = 0; i < idxd->max_wqs; i++) {
884 wq = idxd->wqs[i];
885 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
886 idxd_wq_quiesce(wq);
887 }
888 }
889
idxd_shutdown(struct pci_dev * pdev)890 static void idxd_shutdown(struct pci_dev *pdev)
891 {
892 struct idxd_device *idxd = pci_get_drvdata(pdev);
893 struct idxd_irq_entry *irq_entry;
894 int rc;
895
896 rc = idxd_device_disable(idxd);
897 if (rc)
898 dev_err(&pdev->dev, "Disabling device failed\n");
899
900 irq_entry = &idxd->ie;
901 synchronize_irq(irq_entry->vector);
902 idxd_mask_error_interrupts(idxd);
903 flush_workqueue(idxd->wq);
904 }
905
idxd_remove(struct pci_dev * pdev)906 static void idxd_remove(struct pci_dev *pdev)
907 {
908 struct idxd_device *idxd = pci_get_drvdata(pdev);
909
910 idxd_unregister_devices(idxd);
911 /*
912 * When ->release() is called for the idxd->conf_dev, it frees all the memory related
913 * to the idxd context. The driver still needs those bits in order to do the rest of
914 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref
915 * on the device here to hold off the freeing while allowing the idxd sub-driver
916 * to unbind.
917 */
918 get_device(idxd_confdev(idxd));
919 device_unregister(idxd_confdev(idxd));
920 idxd_shutdown(pdev);
921 idxd_device_remove_debugfs(idxd);
922 perfmon_pmu_remove(idxd);
923 idxd_cleanup_interrupts(idxd);
924 if (device_pasid_enabled(idxd))
925 idxd_disable_system_pasid(idxd);
926 pci_iounmap(pdev, idxd->reg_base);
927 put_device(idxd_confdev(idxd));
928 pci_disable_device(pdev);
929 }
930
931 static struct pci_driver idxd_pci_driver = {
932 .name = DRV_NAME,
933 .id_table = idxd_pci_tbl,
934 .probe = idxd_pci_probe,
935 .remove = idxd_remove,
936 .shutdown = idxd_shutdown,
937 };
938
idxd_init_module(void)939 static int __init idxd_init_module(void)
940 {
941 int err;
942
943 /*
944 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
945 * enumerating the device. We can not utilize it.
946 */
947 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
948 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
949 return -ENODEV;
950 }
951
952 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
953 pr_warn("Platform does not have ENQCMD(S) support.\n");
954 else
955 support_enqcmd = true;
956
957 err = idxd_driver_register(&idxd_drv);
958 if (err < 0)
959 goto err_idxd_driver_register;
960
961 err = idxd_driver_register(&idxd_dmaengine_drv);
962 if (err < 0)
963 goto err_idxd_dmaengine_driver_register;
964
965 err = idxd_driver_register(&idxd_user_drv);
966 if (err < 0)
967 goto err_idxd_user_driver_register;
968
969 err = idxd_cdev_register();
970 if (err)
971 goto err_cdev_register;
972
973 err = idxd_init_debugfs();
974 if (err)
975 goto err_debugfs;
976
977 err = pci_register_driver(&idxd_pci_driver);
978 if (err)
979 goto err_pci_register;
980
981 return 0;
982
983 err_pci_register:
984 idxd_remove_debugfs();
985 err_debugfs:
986 idxd_cdev_remove();
987 err_cdev_register:
988 idxd_driver_unregister(&idxd_user_drv);
989 err_idxd_user_driver_register:
990 idxd_driver_unregister(&idxd_dmaengine_drv);
991 err_idxd_dmaengine_driver_register:
992 idxd_driver_unregister(&idxd_drv);
993 err_idxd_driver_register:
994 return err;
995 }
996 module_init(idxd_init_module);
997
idxd_exit_module(void)998 static void __exit idxd_exit_module(void)
999 {
1000 idxd_driver_unregister(&idxd_user_drv);
1001 idxd_driver_unregister(&idxd_dmaengine_drv);
1002 idxd_driver_unregister(&idxd_drv);
1003 pci_unregister_driver(&idxd_pci_driver);
1004 idxd_cdev_remove();
1005 idxd_remove_debugfs();
1006 }
1007 module_exit(idxd_exit_module);
1008