1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *
4 * Shared code by both skx_edac and i10nm_edac. Originally split out
5 * from the skx_edac driver.
6 *
7 * This file is linked into both skx_edac and i10nm_edac drivers. In
8 * order to avoid link errors, this file must be like a pure library
9 * without including symbols and defines which would otherwise conflict,
10 * when linked once into a module and into a built-in object, at the
11 * same time. For example, __this_module symbol references when that
12 * file is being linked into a built-in object.
13 *
14 * Copyright (c) 2018, Intel Corporation.
15 */
16
17 #include <linux/acpi.h>
18 #include <linux/dmi.h>
19 #include <linux/adxl.h>
20 #include <acpi/nfit.h>
21 #include <asm/mce.h>
22 #include "edac_module.h"
23 #include "skx_common.h"
24
25 static const char * const component_names[] = {
26 [INDEX_SOCKET] = "ProcessorSocketId",
27 [INDEX_MEMCTRL] = "MemoryControllerId",
28 [INDEX_CHANNEL] = "ChannelId",
29 [INDEX_DIMM] = "DimmSlotId",
30 [INDEX_CS] = "ChipSelect",
31 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId",
32 [INDEX_NM_CHANNEL] = "NmChannelId",
33 [INDEX_NM_DIMM] = "NmDimmSlotId",
34 [INDEX_NM_CS] = "NmChipSelect",
35 };
36
37 static int component_indices[ARRAY_SIZE(component_names)];
38 static int adxl_component_count;
39 static const char * const *adxl_component_names;
40 static u64 *adxl_values;
41 static char *adxl_msg;
42 static unsigned long adxl_nm_bitmap;
43
44 static char skx_msg[MSG_SIZE];
45 static skx_decode_f driver_decode;
46 static skx_show_retry_log_f skx_show_retry_rd_err_log;
47 static u64 skx_tolm, skx_tohm;
48 static LIST_HEAD(dev_edac_list);
49 static bool skx_mem_cfg_2lm;
50 static struct res_config *skx_res_cfg;
51
skx_adxl_get(void)52 int skx_adxl_get(void)
53 {
54 const char * const *names;
55 int i, j;
56
57 names = adxl_get_component_names();
58 if (!names) {
59 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
60 return -ENODEV;
61 }
62
63 for (i = 0; i < INDEX_MAX; i++) {
64 for (j = 0; names[j]; j++) {
65 if (!strcmp(component_names[i], names[j])) {
66 component_indices[i] = j;
67
68 if (i >= INDEX_NM_FIRST)
69 adxl_nm_bitmap |= 1 << i;
70
71 break;
72 }
73 }
74
75 if (!names[j] && i < INDEX_NM_FIRST)
76 goto err;
77 }
78
79 if (skx_mem_cfg_2lm) {
80 if (!adxl_nm_bitmap)
81 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n");
82 else
83 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap);
84 }
85
86 adxl_component_names = names;
87 while (*names++)
88 adxl_component_count++;
89
90 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
91 GFP_KERNEL);
92 if (!adxl_values) {
93 adxl_component_count = 0;
94 return -ENOMEM;
95 }
96
97 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
98 if (!adxl_msg) {
99 adxl_component_count = 0;
100 kfree(adxl_values);
101 return -ENOMEM;
102 }
103
104 return 0;
105 err:
106 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
107 component_names[i]);
108 for (j = 0; names[j]; j++)
109 skx_printk(KERN_CONT, "%s ", names[j]);
110 skx_printk(KERN_CONT, "\n");
111
112 return -ENODEV;
113 }
114 EXPORT_SYMBOL_GPL(skx_adxl_get);
115
skx_adxl_put(void)116 void skx_adxl_put(void)
117 {
118 adxl_component_count = 0;
119 kfree(adxl_values);
120 kfree(adxl_msg);
121 }
122 EXPORT_SYMBOL_GPL(skx_adxl_put);
123
skx_init_mc_mapping(struct skx_dev * d)124 static void skx_init_mc_mapping(struct skx_dev *d)
125 {
126 /*
127 * By default, the BIOS presents all memory controllers within each
128 * socket to the EDAC driver. The physical indices are the same as
129 * the logical indices of the memory controllers enumerated by the
130 * EDAC driver.
131 */
132 for (int i = 0; i < NUM_IMC; i++)
133 d->mc_mapping[i] = i;
134 }
135
skx_set_mc_mapping(struct skx_dev * d,u8 pmc,u8 lmc)136 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc)
137 {
138 edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n",
139 pmc, lmc);
140
141 d->mc_mapping[pmc] = lmc;
142 }
143 EXPORT_SYMBOL_GPL(skx_set_mc_mapping);
144
skx_get_mc_mapping(struct skx_dev * d,u8 pmc)145 static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc)
146 {
147 edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n",
148 pmc, d->mc_mapping[pmc]);
149
150 return d->mc_mapping[pmc];
151 }
152
skx_adxl_decode(struct decoded_addr * res,enum error_source err_src)153 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src)
154 {
155 struct skx_dev *d;
156 int i, len = 0;
157
158 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
159 res->addr < BIT_ULL(32))) {
160 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
161 return false;
162 }
163
164 if (adxl_decode(res->addr, adxl_values)) {
165 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
166 return false;
167 }
168
169 /*
170 * GNR with a Flat2LM memory configuration may mistakenly classify
171 * a near-memory error(DDR5) as a far-memory error(CXL), resulting
172 * in the incorrect selection of decoded ADXL components.
173 * To address this, prefetch the decoded far-memory controller ID
174 * and adjust the error source to near-memory if the far-memory
175 * controller ID is invalid.
176 */
177 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) {
178 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
179 if (res->imc == -1) {
180 err_src = ERR_SRC_2LM_NM;
181 edac_dbg(0, "Adjust the error source to near-memory.\n");
182 }
183 }
184
185 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
186 if (err_src == ERR_SRC_2LM_NM) {
187 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ?
188 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1;
189 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ?
190 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1;
191 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ?
192 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
193 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ?
194 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1;
195 } else {
196 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
197 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
198 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
199 res->cs = (int)adxl_values[component_indices[INDEX_CS]];
200 }
201
202 if (res->imc > NUM_IMC - 1 || res->imc < 0) {
203 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
204 return false;
205 }
206
207 list_for_each_entry(d, &dev_edac_list, list) {
208 if (d->imc[0].src_id == res->socket) {
209 res->dev = d;
210 break;
211 }
212 }
213
214 if (!res->dev) {
215 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
216 res->socket, res->imc);
217 return false;
218 }
219
220 res->imc = skx_get_mc_mapping(d, res->imc);
221
222 for (i = 0; i < adxl_component_count; i++) {
223 if (adxl_values[i] == ~0x0ull)
224 continue;
225
226 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
227 adxl_component_names[i], adxl_values[i]);
228 if (MSG_SIZE - len <= 0)
229 break;
230 }
231
232 res->decoded_by_adxl = true;
233
234 return true;
235 }
236
skx_set_mem_cfg(bool mem_cfg_2lm)237 void skx_set_mem_cfg(bool mem_cfg_2lm)
238 {
239 skx_mem_cfg_2lm = mem_cfg_2lm;
240 }
241 EXPORT_SYMBOL_GPL(skx_set_mem_cfg);
242
skx_set_res_cfg(struct res_config * cfg)243 void skx_set_res_cfg(struct res_config *cfg)
244 {
245 skx_res_cfg = cfg;
246 }
247 EXPORT_SYMBOL_GPL(skx_set_res_cfg);
248
skx_set_decode(skx_decode_f decode,skx_show_retry_log_f show_retry_log)249 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
250 {
251 driver_decode = decode;
252 skx_show_retry_rd_err_log = show_retry_log;
253 }
254 EXPORT_SYMBOL_GPL(skx_set_decode);
255
skx_get_src_id(struct skx_dev * d,int off,u8 * id)256 int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
257 {
258 u32 reg;
259
260 if (pci_read_config_dword(d->util_all, off, ®)) {
261 skx_printk(KERN_ERR, "Failed to read src id\n");
262 return -ENODEV;
263 }
264
265 *id = GET_BITFIELD(reg, 12, 14);
266 return 0;
267 }
268 EXPORT_SYMBOL_GPL(skx_get_src_id);
269
skx_get_node_id(struct skx_dev * d,u8 * id)270 int skx_get_node_id(struct skx_dev *d, u8 *id)
271 {
272 u32 reg;
273
274 if (pci_read_config_dword(d->util_all, 0xf4, ®)) {
275 skx_printk(KERN_ERR, "Failed to read node id\n");
276 return -ENODEV;
277 }
278
279 *id = GET_BITFIELD(reg, 0, 2);
280 return 0;
281 }
282 EXPORT_SYMBOL_GPL(skx_get_node_id);
283
get_width(u32 mtr)284 static int get_width(u32 mtr)
285 {
286 switch (GET_BITFIELD(mtr, 8, 9)) {
287 case 0:
288 return DEV_X4;
289 case 1:
290 return DEV_X8;
291 case 2:
292 return DEV_X16;
293 }
294 return DEV_UNKNOWN;
295 }
296
297 /*
298 * We use the per-socket device @cfg->did to count how many sockets are present,
299 * and to detemine which PCI buses are associated with each socket. Allocate
300 * and build the full list of all the skx_dev structures that we need here.
301 */
skx_get_all_bus_mappings(struct res_config * cfg,struct list_head ** list)302 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
303 {
304 struct pci_dev *pdev, *prev;
305 struct skx_dev *d;
306 u32 reg;
307 int ndev = 0;
308
309 prev = NULL;
310 for (;;) {
311 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
312 if (!pdev)
313 break;
314 ndev++;
315 d = kzalloc(sizeof(*d), GFP_KERNEL);
316 if (!d) {
317 pci_dev_put(pdev);
318 return -ENOMEM;
319 }
320
321 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) {
322 kfree(d);
323 pci_dev_put(pdev);
324 skx_printk(KERN_ERR, "Failed to read bus idx\n");
325 return -ENODEV;
326 }
327
328 d->bus[0] = GET_BITFIELD(reg, 0, 7);
329 d->bus[1] = GET_BITFIELD(reg, 8, 15);
330 if (cfg->type == SKX) {
331 d->seg = pci_domain_nr(pdev->bus);
332 d->bus[2] = GET_BITFIELD(reg, 16, 23);
333 d->bus[3] = GET_BITFIELD(reg, 24, 31);
334 } else {
335 d->seg = GET_BITFIELD(reg, 16, 23);
336 }
337
338 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
339 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
340 list_add_tail(&d->list, &dev_edac_list);
341 prev = pdev;
342
343 skx_init_mc_mapping(d);
344 }
345
346 if (list)
347 *list = &dev_edac_list;
348 return ndev;
349 }
350 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings);
351
skx_get_hi_lo(unsigned int did,int off[],u64 * tolm,u64 * tohm)352 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
353 {
354 struct pci_dev *pdev;
355 u32 reg;
356
357 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
358 if (!pdev) {
359 edac_dbg(2, "Can't get tolm/tohm\n");
360 return -ENODEV;
361 }
362
363 if (pci_read_config_dword(pdev, off[0], ®)) {
364 skx_printk(KERN_ERR, "Failed to read tolm\n");
365 goto fail;
366 }
367 skx_tolm = reg;
368
369 if (pci_read_config_dword(pdev, off[1], ®)) {
370 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
371 goto fail;
372 }
373 skx_tohm = reg;
374
375 if (pci_read_config_dword(pdev, off[2], ®)) {
376 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
377 goto fail;
378 }
379 skx_tohm |= (u64)reg << 32;
380
381 pci_dev_put(pdev);
382 *tolm = skx_tolm;
383 *tohm = skx_tohm;
384 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
385 return 0;
386 fail:
387 pci_dev_put(pdev);
388 return -ENODEV;
389 }
390 EXPORT_SYMBOL_GPL(skx_get_hi_lo);
391
skx_get_dimm_attr(u32 reg,int lobit,int hibit,int add,int minval,int maxval,const char * name)392 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
393 int minval, int maxval, const char *name)
394 {
395 u32 val = GET_BITFIELD(reg, lobit, hibit);
396
397 if (val < minval || val > maxval) {
398 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
399 return -EINVAL;
400 }
401 return val + add;
402 }
403
404 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
405 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
406 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
407
skx_get_dimm_info(u32 mtr,u32 mcmtr,u32 amap,struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,struct res_config * cfg)408 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
409 struct skx_imc *imc, int chan, int dimmno,
410 struct res_config *cfg)
411 {
412 int banks, ranks, rows, cols, npages;
413 enum mem_type mtype;
414 u64 size;
415
416 ranks = numrank(mtr);
417 rows = numrow(mtr);
418 cols = imc->hbm_mc ? 6 : numcol(mtr);
419
420 if (imc->hbm_mc) {
421 banks = 32;
422 mtype = MEM_HBM2;
423 } else if (cfg->support_ddr5) {
424 banks = 32;
425 mtype = MEM_DDR5;
426 } else {
427 banks = 16;
428 mtype = MEM_DDR4;
429 }
430
431 /*
432 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
433 */
434 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
435 npages = MiB_TO_PAGES(size);
436
437 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
438 imc->mc, chan, dimmno, size, npages,
439 banks, 1 << ranks, rows, cols);
440
441 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
442 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
443 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
444 imc->chan[chan].dimms[dimmno].rowbits = rows;
445 imc->chan[chan].dimms[dimmno].colbits = cols;
446
447 dimm->nr_pages = npages;
448 dimm->grain = 32;
449 dimm->dtype = get_width(mtr);
450 dimm->mtype = mtype;
451 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
452
453 if (imc->hbm_mc)
454 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
455 imc->src_id, imc->lmc, chan);
456 else
457 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
458 imc->src_id, imc->lmc, chan, dimmno);
459
460 return 1;
461 }
462 EXPORT_SYMBOL_GPL(skx_get_dimm_info);
463
skx_get_nvdimm_info(struct dimm_info * dimm,struct skx_imc * imc,int chan,int dimmno,const char * mod_str)464 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
465 int chan, int dimmno, const char *mod_str)
466 {
467 int smbios_handle;
468 u32 dev_handle;
469 u16 flags;
470 u64 size = 0;
471
472 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
473 imc->src_id, 0);
474
475 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
476 if (smbios_handle == -EOPNOTSUPP) {
477 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
478 goto unknown_size;
479 }
480
481 if (smbios_handle < 0) {
482 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
483 goto unknown_size;
484 }
485
486 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
487 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
488 goto unknown_size;
489 }
490
491 size = dmi_memdev_size(smbios_handle);
492 if (size == ~0ull)
493 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
494 dev_handle, smbios_handle);
495
496 unknown_size:
497 dimm->nr_pages = size >> PAGE_SHIFT;
498 dimm->grain = 32;
499 dimm->dtype = DEV_UNKNOWN;
500 dimm->mtype = MEM_NVDIMM;
501 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
502
503 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
504 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
505
506 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
507 imc->src_id, imc->lmc, chan, dimmno);
508
509 return (size == 0 || size == ~0ull) ? 0 : 1;
510 }
511 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info);
512
skx_register_mci(struct skx_imc * imc,struct pci_dev * pdev,const char * ctl_name,const char * mod_str,get_dimm_config_f get_dimm_config,struct res_config * cfg)513 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
514 const char *ctl_name, const char *mod_str,
515 get_dimm_config_f get_dimm_config,
516 struct res_config *cfg)
517 {
518 struct mem_ctl_info *mci;
519 struct edac_mc_layer layers[2];
520 struct skx_pvt *pvt;
521 int rc;
522
523 /* Allocate a new MC control structure */
524 layers[0].type = EDAC_MC_LAYER_CHANNEL;
525 layers[0].size = NUM_CHANNELS;
526 layers[0].is_virt_csrow = false;
527 layers[1].type = EDAC_MC_LAYER_SLOT;
528 layers[1].size = NUM_DIMMS;
529 layers[1].is_virt_csrow = true;
530 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
531 sizeof(struct skx_pvt));
532
533 if (unlikely(!mci))
534 return -ENOMEM;
535
536 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
537
538 /* Associate skx_dev and mci for future usage */
539 imc->mci = mci;
540 pvt = mci->pvt_info;
541 pvt->imc = imc;
542
543 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
544 imc->node_id, imc->lmc);
545 if (!mci->ctl_name) {
546 rc = -ENOMEM;
547 goto fail0;
548 }
549
550 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
551 if (cfg->support_ddr5)
552 mci->mtype_cap |= MEM_FLAG_DDR5;
553 mci->edac_ctl_cap = EDAC_FLAG_NONE;
554 mci->edac_cap = EDAC_FLAG_NONE;
555 mci->mod_name = mod_str;
556 mci->dev_name = pci_name(pdev);
557 mci->ctl_page_to_phys = NULL;
558
559 rc = get_dimm_config(mci, cfg);
560 if (rc < 0)
561 goto fail;
562
563 /* Record ptr to the generic device */
564 mci->pdev = &pdev->dev;
565
566 /* Add this new MC control structure to EDAC's list of MCs */
567 if (unlikely(edac_mc_add_mc(mci))) {
568 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
569 rc = -EINVAL;
570 goto fail;
571 }
572
573 return 0;
574
575 fail:
576 kfree(mci->ctl_name);
577 fail0:
578 edac_mc_free(mci);
579 imc->mci = NULL;
580 return rc;
581 }
582 EXPORT_SYMBOL_GPL(skx_register_mci);
583
skx_unregister_mci(struct skx_imc * imc)584 static void skx_unregister_mci(struct skx_imc *imc)
585 {
586 struct mem_ctl_info *mci = imc->mci;
587
588 if (!mci)
589 return;
590
591 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
592
593 /* Remove MC sysfs nodes */
594 edac_mc_del_mc(mci->pdev);
595
596 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
597 kfree(mci->ctl_name);
598 edac_mc_free(mci);
599 }
600
skx_mce_output_error(struct mem_ctl_info * mci,const struct mce * m,struct decoded_addr * res)601 static void skx_mce_output_error(struct mem_ctl_info *mci,
602 const struct mce *m,
603 struct decoded_addr *res)
604 {
605 enum hw_event_mc_err_type tp_event;
606 char *optype;
607 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
608 bool overflow = GET_BITFIELD(m->status, 62, 62);
609 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
610 bool scrub_err = false;
611 bool recoverable;
612 int len;
613 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
614 u32 mscod = GET_BITFIELD(m->status, 16, 31);
615 u32 errcode = GET_BITFIELD(m->status, 0, 15);
616 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
617
618 recoverable = GET_BITFIELD(m->status, 56, 56);
619
620 if (uncorrected_error) {
621 core_err_cnt = 1;
622 if (ripv) {
623 tp_event = HW_EVENT_ERR_UNCORRECTED;
624 } else {
625 tp_event = HW_EVENT_ERR_FATAL;
626 }
627 } else {
628 tp_event = HW_EVENT_ERR_CORRECTED;
629 }
630
631 switch (optypenum) {
632 case 0:
633 optype = "generic undef request error";
634 break;
635 case 1:
636 optype = "memory read error";
637 break;
638 case 2:
639 optype = "memory write error";
640 break;
641 case 3:
642 optype = "addr/cmd error";
643 break;
644 case 4:
645 optype = "memory scrubbing error";
646 scrub_err = true;
647 break;
648 default:
649 optype = "reserved";
650 break;
651 }
652
653 if (res->decoded_by_adxl) {
654 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
655 overflow ? " OVERFLOW" : "",
656 (uncorrected_error && recoverable) ? " recoverable" : "",
657 mscod, errcode, adxl_msg);
658 } else {
659 len = snprintf(skx_msg, MSG_SIZE,
660 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x",
661 overflow ? " OVERFLOW" : "",
662 (uncorrected_error && recoverable) ? " recoverable" : "",
663 mscod, errcode,
664 res->socket, res->imc, res->rank,
665 res->row, res->column, res->bank_address, res->bank_group);
666 }
667
668 if (skx_show_retry_rd_err_log)
669 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err);
670
671 edac_dbg(0, "%s\n", skx_msg);
672
673 /* Call the helper to output message */
674 edac_mc_handle_error(tp_event, mci, core_err_cnt,
675 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
676 res->channel, res->dimm, -1,
677 optype, skx_msg);
678 }
679
skx_error_source(const struct mce * m)680 static enum error_source skx_error_source(const struct mce *m)
681 {
682 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK;
683
684 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR)
685 return ERR_SRC_NOT_MEMORY;
686
687 if (!skx_mem_cfg_2lm)
688 return ERR_SRC_1LM;
689
690 if (errcode == MCACOD_EXT_MEM_ERR)
691 return ERR_SRC_2LM_NM;
692
693 return ERR_SRC_2LM_FM;
694 }
695
skx_mce_check_error(struct notifier_block * nb,unsigned long val,void * data)696 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
697 void *data)
698 {
699 struct mce *mce = (struct mce *)data;
700 enum error_source err_src;
701 struct decoded_addr res;
702 struct mem_ctl_info *mci;
703 char *type;
704
705 if (mce->kflags & MCE_HANDLED_CEC)
706 return NOTIFY_DONE;
707
708 err_src = skx_error_source(mce);
709
710 /* Ignore unless this is memory related with an address */
711 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV))
712 return NOTIFY_DONE;
713
714 memset(&res, 0, sizeof(res));
715 res.mce = mce;
716 res.addr = mce->addr & MCI_ADDR_PHYSADDR;
717 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) {
718 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank);
719 return NOTIFY_DONE;
720 }
721
722 /* Try driver decoder first */
723 if (!(driver_decode && driver_decode(&res))) {
724 /* Then try firmware decoder (ACPI DSM methods) */
725 if (!(adxl_component_count && skx_adxl_decode(&res, err_src)))
726 return NOTIFY_DONE;
727 }
728
729 mci = res.dev->imc[res.imc].mci;
730
731 if (!mci)
732 return NOTIFY_DONE;
733
734 if (mce->mcgstatus & MCG_STATUS_MCIP)
735 type = "Exception";
736 else
737 type = "Event";
738
739 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
740
741 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
742 "Bank %d: 0x%llx\n", mce->extcpu, type,
743 mce->mcgstatus, mce->bank, mce->status);
744 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
745 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
746 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
747
748 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
749 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
750 mce->time, mce->socketid, mce->apicid);
751
752 skx_mce_output_error(mci, mce, &res);
753
754 mce->kflags |= MCE_HANDLED_EDAC;
755 return NOTIFY_DONE;
756 }
757 EXPORT_SYMBOL_GPL(skx_mce_check_error);
758
skx_remove(void)759 void skx_remove(void)
760 {
761 int i, j;
762 struct skx_dev *d, *tmp;
763
764 edac_dbg(0, "\n");
765
766 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
767 list_del(&d->list);
768 for (i = 0; i < NUM_IMC; i++) {
769 if (d->imc[i].mci)
770 skx_unregister_mci(&d->imc[i]);
771
772 if (d->imc[i].mdev)
773 pci_dev_put(d->imc[i].mdev);
774
775 if (d->imc[i].mbase)
776 iounmap(d->imc[i].mbase);
777
778 for (j = 0; j < NUM_CHANNELS; j++) {
779 if (d->imc[i].chan[j].cdev)
780 pci_dev_put(d->imc[i].chan[j].cdev);
781 }
782 }
783 if (d->util_all)
784 pci_dev_put(d->util_all);
785 if (d->pcu_cr3)
786 pci_dev_put(d->pcu_cr3);
787 if (d->sad_all)
788 pci_dev_put(d->sad_all);
789 if (d->uracu)
790 pci_dev_put(d->uracu);
791
792 kfree(d);
793 }
794 }
795 EXPORT_SYMBOL_GPL(skx_remove);
796
797 #ifdef CONFIG_EDAC_DEBUG
798 /*
799 * Debug feature.
800 * Exercise the address decode logic by writing an address to
801 * /sys/kernel/debug/edac/{skx,i10nm}_test/addr.
802 */
803 static struct dentry *skx_test;
804
debugfs_u64_set(void * data,u64 val)805 static int debugfs_u64_set(void *data, u64 val)
806 {
807 struct mce m;
808
809 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
810
811 memset(&m, 0, sizeof(m));
812 /* ADDRV + MemRd + Unknown channel */
813 m.status = MCI_STATUS_ADDRV + 0x90;
814 /* One corrected error */
815 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
816 m.addr = val;
817 skx_mce_check_error(NULL, 0, &m);
818
819 return 0;
820 }
821 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
822
skx_setup_debug(const char * name)823 void skx_setup_debug(const char *name)
824 {
825 skx_test = edac_debugfs_create_dir(name);
826 if (!skx_test)
827 return;
828
829 if (!edac_debugfs_create_file("addr", 0200, skx_test,
830 NULL, &fops_u64_wo)) {
831 debugfs_remove(skx_test);
832 skx_test = NULL;
833 }
834 }
835 EXPORT_SYMBOL_GPL(skx_setup_debug);
836
skx_teardown_debug(void)837 void skx_teardown_debug(void)
838 {
839 debugfs_remove_recursive(skx_test);
840 }
841 EXPORT_SYMBOL_GPL(skx_teardown_debug);
842 #endif /*CONFIG_EDAC_DEBUG*/
843
844 MODULE_LICENSE("GPL v2");
845 MODULE_AUTHOR("Tony Luck");
846 MODULE_DESCRIPTION("MC Driver for Intel server processors");
847