1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <drm/drm_edid.h>
25 #include <drm/drm_fourcc.h>
26 #include <drm/drm_modeset_helper.h>
27 #include <drm/drm_modeset_helper_vtables.h>
28 #include <drm/drm_vblank.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_i2c.h"
33 #include "vid.h"
34 #include "atom.h"
35 #include "amdgpu_atombios.h"
36 #include "atombios_crtc.h"
37 #include "atombios_encoders.h"
38 #include "amdgpu_pll.h"
39 #include "amdgpu_connectors.h"
40 #include "amdgpu_display.h"
41 #include "dce_v11_0.h"
42
43 #include "dce/dce_11_0_d.h"
44 #include "dce/dce_11_0_sh_mask.h"
45 #include "dce/dce_11_0_enum.h"
46 #include "oss/oss_3_0_d.h"
47 #include "oss/oss_3_0_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50
51 #include "ivsrcid/ivsrcid_vislands30.h"
52
53 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
54 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57 static const u32 crtc_offsets[] =
58 {
59 CRTC0_REGISTER_OFFSET,
60 CRTC1_REGISTER_OFFSET,
61 CRTC2_REGISTER_OFFSET,
62 CRTC3_REGISTER_OFFSET,
63 CRTC4_REGISTER_OFFSET,
64 CRTC5_REGISTER_OFFSET,
65 CRTC6_REGISTER_OFFSET
66 };
67
68 static const u32 hpd_offsets[] =
69 {
70 HPD0_REGISTER_OFFSET,
71 HPD1_REGISTER_OFFSET,
72 HPD2_REGISTER_OFFSET,
73 HPD3_REGISTER_OFFSET,
74 HPD4_REGISTER_OFFSET,
75 HPD5_REGISTER_OFFSET
76 };
77
78 static const uint32_t dig_offsets[] = {
79 DIG0_REGISTER_OFFSET,
80 DIG1_REGISTER_OFFSET,
81 DIG2_REGISTER_OFFSET,
82 DIG3_REGISTER_OFFSET,
83 DIG4_REGISTER_OFFSET,
84 DIG5_REGISTER_OFFSET,
85 DIG6_REGISTER_OFFSET,
86 DIG7_REGISTER_OFFSET,
87 DIG8_REGISTER_OFFSET
88 };
89
90 static const struct {
91 uint32_t reg;
92 uint32_t vblank;
93 uint32_t vline;
94 uint32_t hpd;
95
96 } interrupt_status_offsets[] = { {
97 .reg = mmDISP_INTERRUPT_STATUS,
98 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 }, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 }, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 }, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 }, {
117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
119 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 }, {
122 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
123 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
124 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
126 } };
127
128 static const u32 cz_golden_settings_a11[] =
129 {
130 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
131 mmFBC_MISC, 0x1f311fff, 0x14300000,
132 };
133
134 static const u32 cz_mgcg_cgcg_init[] =
135 {
136 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
137 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
138 };
139
140 static const u32 stoney_golden_settings_a11[] =
141 {
142 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
143 mmFBC_MISC, 0x1f311fff, 0x14302000,
144 };
145
146 static const u32 polaris11_golden_settings_a11[] =
147 {
148 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
149 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
150 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
151 mmFBC_MISC, 0x9f313fff, 0x14302008,
152 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
153 };
154
155 static const u32 polaris10_golden_settings_a11[] =
156 {
157 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
158 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
159 mmFBC_MISC, 0x9f313fff, 0x14302008,
160 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
161 };
162
dce_v11_0_init_golden_registers(struct amdgpu_device * adev)163 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
164 {
165 switch (adev->asic_type) {
166 case CHIP_CARRIZO:
167 amdgpu_device_program_register_sequence(adev,
168 cz_mgcg_cgcg_init,
169 ARRAY_SIZE(cz_mgcg_cgcg_init));
170 amdgpu_device_program_register_sequence(adev,
171 cz_golden_settings_a11,
172 ARRAY_SIZE(cz_golden_settings_a11));
173 break;
174 case CHIP_STONEY:
175 amdgpu_device_program_register_sequence(adev,
176 stoney_golden_settings_a11,
177 ARRAY_SIZE(stoney_golden_settings_a11));
178 break;
179 case CHIP_POLARIS11:
180 case CHIP_POLARIS12:
181 amdgpu_device_program_register_sequence(adev,
182 polaris11_golden_settings_a11,
183 ARRAY_SIZE(polaris11_golden_settings_a11));
184 break;
185 case CHIP_POLARIS10:
186 case CHIP_VEGAM:
187 amdgpu_device_program_register_sequence(adev,
188 polaris10_golden_settings_a11,
189 ARRAY_SIZE(polaris10_golden_settings_a11));
190 break;
191 default:
192 break;
193 }
194 }
195
dce_v11_0_audio_endpt_rreg(struct amdgpu_device * adev,u32 block_offset,u32 reg)196 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
197 u32 block_offset, u32 reg)
198 {
199 unsigned long flags;
200 u32 r;
201
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
206
207 return r;
208 }
209
dce_v11_0_audio_endpt_wreg(struct amdgpu_device * adev,u32 block_offset,u32 reg,u32 v)210 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
211 u32 block_offset, u32 reg, u32 v)
212 {
213 unsigned long flags;
214
215 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
216 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
217 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
218 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
219 }
220
dce_v11_0_vblank_get_counter(struct amdgpu_device * adev,int crtc)221 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
222 {
223 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
224 return 0;
225 else
226 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
227 }
228
dce_v11_0_pageflip_interrupt_init(struct amdgpu_device * adev)229 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
230 {
231 unsigned i;
232
233 /* Enable pflip interrupts */
234 for (i = 0; i < adev->mode_info.num_crtc; i++)
235 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
236 }
237
dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device * adev)238 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
239 {
240 unsigned i;
241
242 /* Disable pflip interrupts */
243 for (i = 0; i < adev->mode_info.num_crtc; i++)
244 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
245 }
246
247 /**
248 * dce_v11_0_page_flip - pageflip callback.
249 *
250 * @adev: amdgpu_device pointer
251 * @crtc_id: crtc to cleanup pageflip on
252 * @crtc_base: new address of the crtc (GPU MC address)
253 * @async: asynchronous flip
254 *
255 * Triggers the actual pageflip by updating the primary
256 * surface base address.
257 */
dce_v11_0_page_flip(struct amdgpu_device * adev,int crtc_id,u64 crtc_base,bool async)258 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
259 int crtc_id, u64 crtc_base, bool async)
260 {
261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
262 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
263 u32 tmp;
264
265 /* flip immediate for async, default is vsync */
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
267 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
268 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
270 /* update pitch */
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
272 fb->pitches[0] / fb->format->cpp[0]);
273 /* update the scanout addresses */
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
275 upper_32_bits(crtc_base));
276 /* writing to the low address triggers the update */
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
278 lower_32_bits(crtc_base));
279 /* post the write */
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
281 }
282
dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device * adev,int crtc,u32 * vbl,u32 * position)283 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
284 u32 *vbl, u32 *position)
285 {
286 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
287 return -EINVAL;
288
289 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
290 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
291
292 return 0;
293 }
294
295 /**
296 * dce_v11_0_hpd_sense - hpd sense callback.
297 *
298 * @adev: amdgpu_device pointer
299 * @hpd: hpd (hotplug detect) pin
300 *
301 * Checks if a digital monitor is connected (evergreen+).
302 * Returns true if connected, false if not connected.
303 */
dce_v11_0_hpd_sense(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)304 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
305 enum amdgpu_hpd_id hpd)
306 {
307 bool connected = false;
308
309 if (hpd >= adev->mode_info.num_hpd)
310 return connected;
311
312 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
313 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
314 connected = true;
315
316 return connected;
317 }
318
319 /**
320 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
321 *
322 * @adev: amdgpu_device pointer
323 * @hpd: hpd (hotplug detect) pin
324 *
325 * Set the polarity of the hpd pin (evergreen+).
326 */
dce_v11_0_hpd_set_polarity(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)327 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
328 enum amdgpu_hpd_id hpd)
329 {
330 u32 tmp;
331 bool connected = dce_v11_0_hpd_sense(adev, hpd);
332
333 if (hpd >= adev->mode_info.num_hpd)
334 return;
335
336 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
337 if (connected)
338 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
339 else
340 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
342 }
343
344 /**
345 * dce_v11_0_hpd_init - hpd setup callback.
346 *
347 * @adev: amdgpu_device pointer
348 *
349 * Setup the hpd pins used by the card (evergreen+).
350 * Enable the pin, set the polarity, and enable the hpd interrupts.
351 */
dce_v11_0_hpd_init(struct amdgpu_device * adev)352 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
353 {
354 struct drm_device *dev = adev_to_drm(adev);
355 struct drm_connector *connector;
356 struct drm_connector_list_iter iter;
357 u32 tmp;
358
359 drm_connector_list_iter_begin(dev, &iter);
360 drm_for_each_connector_iter(connector, &iter) {
361 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
362
363 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
364 continue;
365
366 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
367 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
368 /* don't try to enable hpd on eDP or LVDS avoid breaking the
369 * aux dp channel on imac and help (but not completely fix)
370 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
371 * also avoid interrupt storms during dpms.
372 */
373 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
374 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
375 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
376 continue;
377 }
378
379 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
380 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
381 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
382
383 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
384 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
385 DC_HPD_CONNECT_INT_DELAY,
386 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
387 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
388 DC_HPD_DISCONNECT_INT_DELAY,
389 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
390 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
391
392 dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
393 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
394 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
395 }
396 drm_connector_list_iter_end(&iter);
397 }
398
399 /**
400 * dce_v11_0_hpd_fini - hpd tear down callback.
401 *
402 * @adev: amdgpu_device pointer
403 *
404 * Tear down the hpd pins used by the card (evergreen+).
405 * Disable the hpd interrupts.
406 */
dce_v11_0_hpd_fini(struct amdgpu_device * adev)407 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
408 {
409 struct drm_device *dev = adev_to_drm(adev);
410 struct drm_connector *connector;
411 struct drm_connector_list_iter iter;
412 u32 tmp;
413
414 drm_connector_list_iter_begin(dev, &iter);
415 drm_for_each_connector_iter(connector, &iter) {
416 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
417
418 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
419 continue;
420
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
424
425 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
426 }
427 drm_connector_list_iter_end(&iter);
428 }
429
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device * adev)430 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
431 {
432 return mmDC_GPIO_HPD_A;
433 }
434
dce_v11_0_is_display_hung(struct amdgpu_device * adev)435 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
436 {
437 u32 crtc_hung = 0;
438 u32 crtc_status[6];
439 u32 i, j, tmp;
440
441 for (i = 0; i < adev->mode_info.num_crtc; i++) {
442 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
443 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
444 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
445 crtc_hung |= (1 << i);
446 }
447 }
448
449 for (j = 0; j < 10; j++) {
450 for (i = 0; i < adev->mode_info.num_crtc; i++) {
451 if (crtc_hung & (1 << i)) {
452 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
453 if (tmp != crtc_status[i])
454 crtc_hung &= ~(1 << i);
455 }
456 }
457 if (crtc_hung == 0)
458 return false;
459 udelay(100);
460 }
461
462 return true;
463 }
464
dce_v11_0_set_vga_render_state(struct amdgpu_device * adev,bool render)465 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
466 bool render)
467 {
468 u32 tmp;
469
470 /* Lockout access through VGA aperture*/
471 tmp = RREG32(mmVGA_HDP_CONTROL);
472 if (render)
473 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
474 else
475 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
476 WREG32(mmVGA_HDP_CONTROL, tmp);
477
478 /* disable VGA render */
479 tmp = RREG32(mmVGA_RENDER_CONTROL);
480 if (render)
481 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
482 else
483 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
484 WREG32(mmVGA_RENDER_CONTROL, tmp);
485 }
486
dce_v11_0_get_num_crtc(struct amdgpu_device * adev)487 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
488 {
489 int num_crtc = 0;
490
491 switch (adev->asic_type) {
492 case CHIP_CARRIZO:
493 num_crtc = 3;
494 break;
495 case CHIP_STONEY:
496 num_crtc = 2;
497 break;
498 case CHIP_POLARIS10:
499 case CHIP_VEGAM:
500 num_crtc = 6;
501 break;
502 case CHIP_POLARIS11:
503 case CHIP_POLARIS12:
504 num_crtc = 5;
505 break;
506 default:
507 num_crtc = 0;
508 }
509 return num_crtc;
510 }
511
dce_v11_0_disable_dce(struct amdgpu_device * adev)512 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
513 {
514 /*Disable VGA render and enabled crtc, if has DCE engine*/
515 if (amdgpu_atombios_has_dce_engine_info(adev)) {
516 u32 tmp;
517 int crtc_enabled, i;
518
519 dce_v11_0_set_vga_render_state(adev, false);
520
521 /*Disable crtc*/
522 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
524 CRTC_CONTROL, CRTC_MASTER_EN);
525 if (crtc_enabled) {
526 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
527 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
528 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
529 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
530 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
531 }
532 }
533 }
534 }
535
dce_v11_0_program_fmt(struct drm_encoder * encoder)536 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
537 {
538 struct drm_device *dev = encoder->dev;
539 struct amdgpu_device *adev = drm_to_adev(dev);
540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
542 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
543 int bpc = 0;
544 u32 tmp = 0;
545 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
546
547 if (connector) {
548 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
549 bpc = amdgpu_connector_get_monitor_bpc(connector);
550 dither = amdgpu_connector->dither;
551 }
552
553 /* LVDS/eDP FMT is set up by atom */
554 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
555 return;
556
557 /* not needed for analog */
558 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
559 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
560 return;
561
562 if (bpc == 0)
563 return;
564
565 switch (bpc) {
566 case 6:
567 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
568 /* XXX sort out optimal dither settings */
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
573 } else {
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
576 }
577 break;
578 case 8:
579 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
580 /* XXX sort out optimal dither settings */
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
585 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
586 } else {
587 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
588 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
589 }
590 break;
591 case 10:
592 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
593 /* XXX sort out optimal dither settings */
594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
597 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
598 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
599 } else {
600 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
601 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
602 }
603 break;
604 default:
605 /* not needed */
606 break;
607 }
608
609 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
610 }
611
612
613 /* display watermark setup */
614 /**
615 * dce_v11_0_line_buffer_adjust - Set up the line buffer
616 *
617 * @adev: amdgpu_device pointer
618 * @amdgpu_crtc: the selected display controller
619 * @mode: the current display mode on the selected display
620 * controller
621 *
622 * Setup up the line buffer allocation for
623 * the selected display controller (CIK).
624 * Returns the line buffer size in pixels.
625 */
dce_v11_0_line_buffer_adjust(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,struct drm_display_mode * mode)626 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
627 struct amdgpu_crtc *amdgpu_crtc,
628 struct drm_display_mode *mode)
629 {
630 u32 tmp, buffer_alloc, i, mem_cfg;
631 u32 pipe_offset = amdgpu_crtc->crtc_id;
632 /*
633 * Line Buffer Setup
634 * There are 6 line buffers, one for each display controllers.
635 * There are 3 partitions per LB. Select the number of partitions
636 * to enable based on the display width. For display widths larger
637 * than 4096, you need use to use 2 display controllers and combine
638 * them using the stereo blender.
639 */
640 if (amdgpu_crtc->base.enabled && mode) {
641 if (mode->crtc_hdisplay < 1920) {
642 mem_cfg = 1;
643 buffer_alloc = 2;
644 } else if (mode->crtc_hdisplay < 2560) {
645 mem_cfg = 2;
646 buffer_alloc = 2;
647 } else if (mode->crtc_hdisplay < 4096) {
648 mem_cfg = 0;
649 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
650 } else {
651 DRM_DEBUG_KMS("Mode too big for LB!\n");
652 mem_cfg = 0;
653 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
654 }
655 } else {
656 mem_cfg = 1;
657 buffer_alloc = 0;
658 }
659
660 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
661 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
662 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
663
664 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
665 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
666 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
667
668 for (i = 0; i < adev->usec_timeout; i++) {
669 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
670 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
671 break;
672 udelay(1);
673 }
674
675 if (amdgpu_crtc->base.enabled && mode) {
676 switch (mem_cfg) {
677 case 0:
678 default:
679 return 4096 * 2;
680 case 1:
681 return 1920 * 2;
682 case 2:
683 return 2560 * 2;
684 }
685 }
686
687 /* controller not enabled, so no lb used */
688 return 0;
689 }
690
691 /**
692 * cik_get_number_of_dram_channels - get the number of dram channels
693 *
694 * @adev: amdgpu_device pointer
695 *
696 * Look up the number of video ram channels (CIK).
697 * Used for display watermark bandwidth calculations
698 * Returns the number of dram channels
699 */
cik_get_number_of_dram_channels(struct amdgpu_device * adev)700 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
701 {
702 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
703
704 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
705 case 0:
706 default:
707 return 1;
708 case 1:
709 return 2;
710 case 2:
711 return 4;
712 case 3:
713 return 8;
714 case 4:
715 return 3;
716 case 5:
717 return 6;
718 case 6:
719 return 10;
720 case 7:
721 return 12;
722 case 8:
723 return 16;
724 }
725 }
726
727 struct dce10_wm_params {
728 u32 dram_channels; /* number of dram channels */
729 u32 yclk; /* bandwidth per dram data pin in kHz */
730 u32 sclk; /* engine clock in kHz */
731 u32 disp_clk; /* display clock in kHz */
732 u32 src_width; /* viewport width */
733 u32 active_time; /* active display time in ns */
734 u32 blank_time; /* blank time in ns */
735 bool interlaced; /* mode is interlaced */
736 fixed20_12 vsc; /* vertical scale ratio */
737 u32 num_heads; /* number of active crtcs */
738 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
739 u32 lb_size; /* line buffer allocated to pipe */
740 u32 vtaps; /* vertical scaler taps */
741 };
742
743 /**
744 * dce_v11_0_dram_bandwidth - get the dram bandwidth
745 *
746 * @wm: watermark calculation data
747 *
748 * Calculate the raw dram bandwidth (CIK).
749 * Used for display watermark bandwidth calculations
750 * Returns the dram bandwidth in MBytes/s
751 */
dce_v11_0_dram_bandwidth(struct dce10_wm_params * wm)752 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
753 {
754 /* Calculate raw DRAM Bandwidth */
755 fixed20_12 dram_efficiency; /* 0.7 */
756 fixed20_12 yclk, dram_channels, bandwidth;
757 fixed20_12 a;
758
759 a.full = dfixed_const(1000);
760 yclk.full = dfixed_const(wm->yclk);
761 yclk.full = dfixed_div(yclk, a);
762 dram_channels.full = dfixed_const(wm->dram_channels * 4);
763 a.full = dfixed_const(10);
764 dram_efficiency.full = dfixed_const(7);
765 dram_efficiency.full = dfixed_div(dram_efficiency, a);
766 bandwidth.full = dfixed_mul(dram_channels, yclk);
767 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
768
769 return dfixed_trunc(bandwidth);
770 }
771
772 /**
773 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
774 *
775 * @wm: watermark calculation data
776 *
777 * Calculate the dram bandwidth used for display (CIK).
778 * Used for display watermark bandwidth calculations
779 * Returns the dram bandwidth for display in MBytes/s
780 */
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params * wm)781 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
782 {
783 /* Calculate DRAM Bandwidth and the part allocated to display. */
784 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
785 fixed20_12 yclk, dram_channels, bandwidth;
786 fixed20_12 a;
787
788 a.full = dfixed_const(1000);
789 yclk.full = dfixed_const(wm->yclk);
790 yclk.full = dfixed_div(yclk, a);
791 dram_channels.full = dfixed_const(wm->dram_channels * 4);
792 a.full = dfixed_const(10);
793 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
794 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
795 bandwidth.full = dfixed_mul(dram_channels, yclk);
796 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
797
798 return dfixed_trunc(bandwidth);
799 }
800
801 /**
802 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
803 *
804 * @wm: watermark calculation data
805 *
806 * Calculate the data return bandwidth used for display (CIK).
807 * Used for display watermark bandwidth calculations
808 * Returns the data return bandwidth in MBytes/s
809 */
dce_v11_0_data_return_bandwidth(struct dce10_wm_params * wm)810 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
811 {
812 /* Calculate the display Data return Bandwidth */
813 fixed20_12 return_efficiency; /* 0.8 */
814 fixed20_12 sclk, bandwidth;
815 fixed20_12 a;
816
817 a.full = dfixed_const(1000);
818 sclk.full = dfixed_const(wm->sclk);
819 sclk.full = dfixed_div(sclk, a);
820 a.full = dfixed_const(10);
821 return_efficiency.full = dfixed_const(8);
822 return_efficiency.full = dfixed_div(return_efficiency, a);
823 a.full = dfixed_const(32);
824 bandwidth.full = dfixed_mul(a, sclk);
825 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
826
827 return dfixed_trunc(bandwidth);
828 }
829
830 /**
831 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
832 *
833 * @wm: watermark calculation data
834 *
835 * Calculate the dmif bandwidth used for display (CIK).
836 * Used for display watermark bandwidth calculations
837 * Returns the dmif bandwidth in MBytes/s
838 */
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params * wm)839 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
840 {
841 /* Calculate the DMIF Request Bandwidth */
842 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
843 fixed20_12 disp_clk, bandwidth;
844 fixed20_12 a, b;
845
846 a.full = dfixed_const(1000);
847 disp_clk.full = dfixed_const(wm->disp_clk);
848 disp_clk.full = dfixed_div(disp_clk, a);
849 a.full = dfixed_const(32);
850 b.full = dfixed_mul(a, disp_clk);
851
852 a.full = dfixed_const(10);
853 disp_clk_request_efficiency.full = dfixed_const(8);
854 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
855
856 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
857
858 return dfixed_trunc(bandwidth);
859 }
860
861 /**
862 * dce_v11_0_available_bandwidth - get the min available bandwidth
863 *
864 * @wm: watermark calculation data
865 *
866 * Calculate the min available bandwidth used for display (CIK).
867 * Used for display watermark bandwidth calculations
868 * Returns the min available bandwidth in MBytes/s
869 */
dce_v11_0_available_bandwidth(struct dce10_wm_params * wm)870 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
871 {
872 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
873 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
874 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
875 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
876
877 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
878 }
879
880 /**
881 * dce_v11_0_average_bandwidth - get the average available bandwidth
882 *
883 * @wm: watermark calculation data
884 *
885 * Calculate the average available bandwidth used for display (CIK).
886 * Used for display watermark bandwidth calculations
887 * Returns the average available bandwidth in MBytes/s
888 */
dce_v11_0_average_bandwidth(struct dce10_wm_params * wm)889 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
890 {
891 /* Calculate the display mode Average Bandwidth
892 * DisplayMode should contain the source and destination dimensions,
893 * timing, etc.
894 */
895 fixed20_12 bpp;
896 fixed20_12 line_time;
897 fixed20_12 src_width;
898 fixed20_12 bandwidth;
899 fixed20_12 a;
900
901 a.full = dfixed_const(1000);
902 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
903 line_time.full = dfixed_div(line_time, a);
904 bpp.full = dfixed_const(wm->bytes_per_pixel);
905 src_width.full = dfixed_const(wm->src_width);
906 bandwidth.full = dfixed_mul(src_width, bpp);
907 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
908 bandwidth.full = dfixed_div(bandwidth, line_time);
909
910 return dfixed_trunc(bandwidth);
911 }
912
913 /**
914 * dce_v11_0_latency_watermark - get the latency watermark
915 *
916 * @wm: watermark calculation data
917 *
918 * Calculate the latency watermark (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns the latency watermark in ns
921 */
dce_v11_0_latency_watermark(struct dce10_wm_params * wm)922 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
923 {
924 /* First calculate the latency in ns */
925 u32 mc_latency = 2000; /* 2000 ns. */
926 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
927 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
928 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
929 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
930 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
931 (wm->num_heads * cursor_line_pair_return_time);
932 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
933 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
934 u32 tmp, dmif_size = 12288;
935 fixed20_12 a, b, c;
936
937 if (wm->num_heads == 0)
938 return 0;
939
940 a.full = dfixed_const(2);
941 b.full = dfixed_const(1);
942 if ((wm->vsc.full > a.full) ||
943 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
944 (wm->vtaps >= 5) ||
945 ((wm->vsc.full >= a.full) && wm->interlaced))
946 max_src_lines_per_dst_line = 4;
947 else
948 max_src_lines_per_dst_line = 2;
949
950 a.full = dfixed_const(available_bandwidth);
951 b.full = dfixed_const(wm->num_heads);
952 a.full = dfixed_div(a, b);
953 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
954 tmp = min(dfixed_trunc(a), tmp);
955
956 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
957
958 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
959 b.full = dfixed_const(1000);
960 c.full = dfixed_const(lb_fill_bw);
961 b.full = dfixed_div(c, b);
962 a.full = dfixed_div(a, b);
963 line_fill_time = dfixed_trunc(a);
964
965 if (line_fill_time < wm->active_time)
966 return latency;
967 else
968 return latency + (line_fill_time - wm->active_time);
969
970 }
971
972 /**
973 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
974 * average and available dram bandwidth
975 *
976 * @wm: watermark calculation data
977 *
978 * Check if the display average bandwidth fits in the display
979 * dram bandwidth (CIK).
980 * Used for display watermark bandwidth calculations
981 * Returns true if the display fits, false if not.
982 */
dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params * wm)983 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
984 {
985 if (dce_v11_0_average_bandwidth(wm) <=
986 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
987 return true;
988 else
989 return false;
990 }
991
992 /**
993 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
994 * average and available bandwidth
995 *
996 * @wm: watermark calculation data
997 *
998 * Check if the display average bandwidth fits in the display
999 * available bandwidth (CIK).
1000 * Used for display watermark bandwidth calculations
1001 * Returns true if the display fits, false if not.
1002 */
dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params * wm)1003 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1004 {
1005 if (dce_v11_0_average_bandwidth(wm) <=
1006 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1007 return true;
1008 else
1009 return false;
1010 }
1011
1012 /**
1013 * dce_v11_0_check_latency_hiding - check latency hiding
1014 *
1015 * @wm: watermark calculation data
1016 *
1017 * Check latency hiding (CIK).
1018 * Used for display watermark bandwidth calculations
1019 * Returns true if the display fits, false if not.
1020 */
dce_v11_0_check_latency_hiding(struct dce10_wm_params * wm)1021 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1022 {
1023 u32 lb_partitions = wm->lb_size / wm->src_width;
1024 u32 line_time = wm->active_time + wm->blank_time;
1025 u32 latency_tolerant_lines;
1026 u32 latency_hiding;
1027 fixed20_12 a;
1028
1029 a.full = dfixed_const(1);
1030 if (wm->vsc.full > a.full)
1031 latency_tolerant_lines = 1;
1032 else {
1033 if (lb_partitions <= (wm->vtaps + 1))
1034 latency_tolerant_lines = 1;
1035 else
1036 latency_tolerant_lines = 2;
1037 }
1038
1039 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1040
1041 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1042 return true;
1043 else
1044 return false;
1045 }
1046
1047 /**
1048 * dce_v11_0_program_watermarks - program display watermarks
1049 *
1050 * @adev: amdgpu_device pointer
1051 * @amdgpu_crtc: the selected display controller
1052 * @lb_size: line buffer size
1053 * @num_heads: number of display controllers in use
1054 *
1055 * Calculate and program the display watermarks for the
1056 * selected display controller (CIK).
1057 */
dce_v11_0_program_watermarks(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,u32 lb_size,u32 num_heads)1058 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1059 struct amdgpu_crtc *amdgpu_crtc,
1060 u32 lb_size, u32 num_heads)
1061 {
1062 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1063 struct dce10_wm_params wm_low, wm_high;
1064 u32 active_time;
1065 u32 line_time = 0;
1066 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1067 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1068
1069 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1070 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1071 (u32)mode->clock);
1072 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1073 (u32)mode->clock);
1074 line_time = min_t(u32, line_time, 65535);
1075
1076 /* watermark for high clocks */
1077 if (adev->pm.dpm_enabled) {
1078 wm_high.yclk =
1079 amdgpu_dpm_get_mclk(adev, false) * 10;
1080 wm_high.sclk =
1081 amdgpu_dpm_get_sclk(adev, false) * 10;
1082 } else {
1083 wm_high.yclk = adev->pm.current_mclk * 10;
1084 wm_high.sclk = adev->pm.current_sclk * 10;
1085 }
1086
1087 wm_high.disp_clk = mode->clock;
1088 wm_high.src_width = mode->crtc_hdisplay;
1089 wm_high.active_time = active_time;
1090 wm_high.blank_time = line_time - wm_high.active_time;
1091 wm_high.interlaced = false;
1092 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1093 wm_high.interlaced = true;
1094 wm_high.vsc = amdgpu_crtc->vsc;
1095 wm_high.vtaps = 1;
1096 if (amdgpu_crtc->rmx_type != RMX_OFF)
1097 wm_high.vtaps = 2;
1098 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1099 wm_high.lb_size = lb_size;
1100 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1101 wm_high.num_heads = num_heads;
1102
1103 /* set for high clocks */
1104 latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&wm_high), 65535);
1105
1106 /* possibly force display priority to high */
1107 /* should really do this at mode validation time... */
1108 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1109 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1110 !dce_v11_0_check_latency_hiding(&wm_high) ||
1111 (adev->mode_info.disp_priority == 2)) {
1112 DRM_DEBUG_KMS("force priority to high\n");
1113 }
1114
1115 /* watermark for low clocks */
1116 if (adev->pm.dpm_enabled) {
1117 wm_low.yclk =
1118 amdgpu_dpm_get_mclk(adev, true) * 10;
1119 wm_low.sclk =
1120 amdgpu_dpm_get_sclk(adev, true) * 10;
1121 } else {
1122 wm_low.yclk = adev->pm.current_mclk * 10;
1123 wm_low.sclk = adev->pm.current_sclk * 10;
1124 }
1125
1126 wm_low.disp_clk = mode->clock;
1127 wm_low.src_width = mode->crtc_hdisplay;
1128 wm_low.active_time = active_time;
1129 wm_low.blank_time = line_time - wm_low.active_time;
1130 wm_low.interlaced = false;
1131 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1132 wm_low.interlaced = true;
1133 wm_low.vsc = amdgpu_crtc->vsc;
1134 wm_low.vtaps = 1;
1135 if (amdgpu_crtc->rmx_type != RMX_OFF)
1136 wm_low.vtaps = 2;
1137 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1138 wm_low.lb_size = lb_size;
1139 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1140 wm_low.num_heads = num_heads;
1141
1142 /* set for low clocks */
1143 latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&wm_low), 65535);
1144
1145 /* possibly force display priority to high */
1146 /* should really do this at mode validation time... */
1147 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1148 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1149 !dce_v11_0_check_latency_hiding(&wm_low) ||
1150 (adev->mode_info.disp_priority == 2)) {
1151 DRM_DEBUG_KMS("force priority to high\n");
1152 }
1153 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1154 }
1155
1156 /* select wm A */
1157 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1158 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1159 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1160 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1161 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1162 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1163 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1164 /* select wm B */
1165 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1167 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1168 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1169 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1170 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1171 /* restore original selection */
1172 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1173
1174 /* save values for DPM */
1175 amdgpu_crtc->line_time = line_time;
1176 amdgpu_crtc->wm_high = latency_watermark_a;
1177 amdgpu_crtc->wm_low = latency_watermark_b;
1178 /* Save number of lines the linebuffer leads before the scanout */
1179 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1180 }
1181
1182 /**
1183 * dce_v11_0_bandwidth_update - program display watermarks
1184 *
1185 * @adev: amdgpu_device pointer
1186 *
1187 * Calculate and program the display watermarks and line
1188 * buffer allocation (CIK).
1189 */
dce_v11_0_bandwidth_update(struct amdgpu_device * adev)1190 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1191 {
1192 struct drm_display_mode *mode = NULL;
1193 u32 num_heads = 0, lb_size;
1194 int i;
1195
1196 amdgpu_display_update_priority(adev);
1197
1198 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1199 if (adev->mode_info.crtcs[i]->base.enabled)
1200 num_heads++;
1201 }
1202 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1203 mode = &adev->mode_info.crtcs[i]->base.mode;
1204 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1205 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1206 lb_size, num_heads);
1207 }
1208 }
1209
dce_v11_0_audio_get_connected_pins(struct amdgpu_device * adev)1210 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1211 {
1212 int i;
1213 u32 offset, tmp;
1214
1215 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1216 offset = adev->mode_info.audio.pin[i].offset;
1217 tmp = RREG32_AUDIO_ENDPT(offset,
1218 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1219 if (((tmp &
1220 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1221 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1222 adev->mode_info.audio.pin[i].connected = false;
1223 else
1224 adev->mode_info.audio.pin[i].connected = true;
1225 }
1226 }
1227
dce_v11_0_audio_get_pin(struct amdgpu_device * adev)1228 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1229 {
1230 int i;
1231
1232 dce_v11_0_audio_get_connected_pins(adev);
1233
1234 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1235 if (adev->mode_info.audio.pin[i].connected)
1236 return &adev->mode_info.audio.pin[i];
1237 }
1238 DRM_ERROR("No connected audio pins found!\n");
1239 return NULL;
1240 }
1241
dce_v11_0_afmt_audio_select_pin(struct drm_encoder * encoder)1242 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1243 {
1244 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1247 u32 tmp;
1248
1249 if (!dig || !dig->afmt || !dig->afmt->pin)
1250 return;
1251
1252 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1253 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1254 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1255 }
1256
dce_v11_0_audio_write_latency_fields(struct drm_encoder * encoder,struct drm_display_mode * mode)1257 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1258 struct drm_display_mode *mode)
1259 {
1260 struct drm_device *dev = encoder->dev;
1261 struct amdgpu_device *adev = drm_to_adev(dev);
1262 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1263 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1264 struct drm_connector *connector;
1265 struct drm_connector_list_iter iter;
1266 struct amdgpu_connector *amdgpu_connector = NULL;
1267 u32 tmp;
1268 int interlace = 0;
1269
1270 if (!dig || !dig->afmt || !dig->afmt->pin)
1271 return;
1272
1273 drm_connector_list_iter_begin(dev, &iter);
1274 drm_for_each_connector_iter(connector, &iter) {
1275 if (connector->encoder == encoder) {
1276 amdgpu_connector = to_amdgpu_connector(connector);
1277 break;
1278 }
1279 }
1280 drm_connector_list_iter_end(&iter);
1281
1282 if (!amdgpu_connector) {
1283 DRM_ERROR("Couldn't find encoder's connector\n");
1284 return;
1285 }
1286
1287 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1288 interlace = 1;
1289 if (connector->latency_present[interlace]) {
1290 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1291 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1292 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1293 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1294 } else {
1295 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1296 VIDEO_LIPSYNC, 0);
1297 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1298 AUDIO_LIPSYNC, 0);
1299 }
1300 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1301 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1302 }
1303
dce_v11_0_audio_write_speaker_allocation(struct drm_encoder * encoder)1304 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1305 {
1306 struct drm_device *dev = encoder->dev;
1307 struct amdgpu_device *adev = drm_to_adev(dev);
1308 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1309 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1310 struct drm_connector *connector;
1311 struct drm_connector_list_iter iter;
1312 struct amdgpu_connector *amdgpu_connector = NULL;
1313 u32 tmp;
1314 u8 *sadb = NULL;
1315 int sad_count;
1316
1317 if (!dig || !dig->afmt || !dig->afmt->pin)
1318 return;
1319
1320 drm_connector_list_iter_begin(dev, &iter);
1321 drm_for_each_connector_iter(connector, &iter) {
1322 if (connector->encoder == encoder) {
1323 amdgpu_connector = to_amdgpu_connector(connector);
1324 break;
1325 }
1326 }
1327 drm_connector_list_iter_end(&iter);
1328
1329 if (!amdgpu_connector) {
1330 DRM_ERROR("Couldn't find encoder's connector\n");
1331 return;
1332 }
1333
1334 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1335 if (sad_count < 0) {
1336 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1337 sad_count = 0;
1338 }
1339
1340 /* program the speaker allocation */
1341 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1342 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1343 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1344 DP_CONNECTION, 0);
1345 /* set HDMI mode */
1346 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1347 HDMI_CONNECTION, 1);
1348 if (sad_count)
1349 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1350 SPEAKER_ALLOCATION, sadb[0]);
1351 else
1352 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1353 SPEAKER_ALLOCATION, 5); /* stereo */
1354 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1355 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1356
1357 kfree(sadb);
1358 }
1359
dce_v11_0_audio_write_sad_regs(struct drm_encoder * encoder)1360 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1361 {
1362 struct drm_device *dev = encoder->dev;
1363 struct amdgpu_device *adev = drm_to_adev(dev);
1364 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1366 struct drm_connector *connector;
1367 struct drm_connector_list_iter iter;
1368 struct amdgpu_connector *amdgpu_connector = NULL;
1369 struct cea_sad *sads;
1370 int i, sad_count;
1371
1372 static const u16 eld_reg_to_type[][2] = {
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1379 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1380 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1381 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1382 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1383 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1384 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1385 };
1386
1387 if (!dig || !dig->afmt || !dig->afmt->pin)
1388 return;
1389
1390 drm_connector_list_iter_begin(dev, &iter);
1391 drm_for_each_connector_iter(connector, &iter) {
1392 if (connector->encoder == encoder) {
1393 amdgpu_connector = to_amdgpu_connector(connector);
1394 break;
1395 }
1396 }
1397 drm_connector_list_iter_end(&iter);
1398
1399 if (!amdgpu_connector) {
1400 DRM_ERROR("Couldn't find encoder's connector\n");
1401 return;
1402 }
1403
1404 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1405 if (sad_count < 0)
1406 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1407 if (sad_count <= 0)
1408 return;
1409 BUG_ON(!sads);
1410
1411 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1412 u32 tmp = 0;
1413 u8 stereo_freqs = 0;
1414 int max_channels = -1;
1415 int j;
1416
1417 for (j = 0; j < sad_count; j++) {
1418 struct cea_sad *sad = &sads[j];
1419
1420 if (sad->format == eld_reg_to_type[i][1]) {
1421 if (sad->channels > max_channels) {
1422 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1423 MAX_CHANNELS, sad->channels);
1424 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1425 DESCRIPTOR_BYTE_2, sad->byte2);
1426 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1427 SUPPORTED_FREQUENCIES, sad->freq);
1428 max_channels = sad->channels;
1429 }
1430
1431 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1432 stereo_freqs |= sad->freq;
1433 else
1434 break;
1435 }
1436 }
1437
1438 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1439 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1440 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1441 }
1442
1443 kfree(sads);
1444 }
1445
dce_v11_0_audio_enable(struct amdgpu_device * adev,struct amdgpu_audio_pin * pin,bool enable)1446 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1447 struct amdgpu_audio_pin *pin,
1448 bool enable)
1449 {
1450 if (!pin)
1451 return;
1452
1453 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1454 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1455 }
1456
1457 static const u32 pin_offsets[] =
1458 {
1459 AUD0_REGISTER_OFFSET,
1460 AUD1_REGISTER_OFFSET,
1461 AUD2_REGISTER_OFFSET,
1462 AUD3_REGISTER_OFFSET,
1463 AUD4_REGISTER_OFFSET,
1464 AUD5_REGISTER_OFFSET,
1465 AUD6_REGISTER_OFFSET,
1466 AUD7_REGISTER_OFFSET,
1467 };
1468
dce_v11_0_audio_init(struct amdgpu_device * adev)1469 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1470 {
1471 int i;
1472
1473 if (!amdgpu_audio)
1474 return 0;
1475
1476 adev->mode_info.audio.enabled = true;
1477
1478 switch (adev->asic_type) {
1479 case CHIP_CARRIZO:
1480 case CHIP_STONEY:
1481 adev->mode_info.audio.num_pins = 7;
1482 break;
1483 case CHIP_POLARIS10:
1484 case CHIP_VEGAM:
1485 adev->mode_info.audio.num_pins = 8;
1486 break;
1487 case CHIP_POLARIS11:
1488 case CHIP_POLARIS12:
1489 adev->mode_info.audio.num_pins = 6;
1490 break;
1491 default:
1492 return -EINVAL;
1493 }
1494
1495 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1496 adev->mode_info.audio.pin[i].channels = -1;
1497 adev->mode_info.audio.pin[i].rate = -1;
1498 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1499 adev->mode_info.audio.pin[i].status_bits = 0;
1500 adev->mode_info.audio.pin[i].category_code = 0;
1501 adev->mode_info.audio.pin[i].connected = false;
1502 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1503 adev->mode_info.audio.pin[i].id = i;
1504 /* disable audio. it will be set up later */
1505 /* XXX remove once we switch to ip funcs */
1506 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1507 }
1508
1509 return 0;
1510 }
1511
dce_v11_0_audio_fini(struct amdgpu_device * adev)1512 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1513 {
1514 if (!amdgpu_audio)
1515 return;
1516
1517 if (!adev->mode_info.audio.enabled)
1518 return;
1519
1520 adev->mode_info.audio.enabled = false;
1521 }
1522
1523 /*
1524 * update the N and CTS parameters for a given pixel clock rate
1525 */
dce_v11_0_afmt_update_ACR(struct drm_encoder * encoder,uint32_t clock)1526 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1527 {
1528 struct drm_device *dev = encoder->dev;
1529 struct amdgpu_device *adev = drm_to_adev(dev);
1530 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1531 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1532 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 u32 tmp;
1534
1535 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1536 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1537 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1538 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1539 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1540 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1541
1542 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1543 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1544 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1545 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1546 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1547 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1548
1549 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1550 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1551 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1552 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1553 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1554 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1555
1556 }
1557
1558 /*
1559 * build a HDMI Video Info Frame
1560 */
dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder * encoder,void * buffer,size_t size)1561 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1562 void *buffer, size_t size)
1563 {
1564 struct drm_device *dev = encoder->dev;
1565 struct amdgpu_device *adev = drm_to_adev(dev);
1566 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1567 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568 uint8_t *frame = buffer + 3;
1569 uint8_t *header = buffer;
1570
1571 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1572 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1573 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1574 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1575 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1576 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1577 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1578 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1579 }
1580
dce_v11_0_audio_set_dto(struct drm_encoder * encoder,u32 clock)1581 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1582 {
1583 struct drm_device *dev = encoder->dev;
1584 struct amdgpu_device *adev = drm_to_adev(dev);
1585 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1586 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1587 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1588 u32 dto_phase = 24 * 1000;
1589 u32 dto_modulo = clock;
1590 u32 tmp;
1591
1592 if (!dig || !dig->afmt)
1593 return;
1594
1595 /* XXX two dtos; generally use dto0 for hdmi */
1596 /* Express [24MHz / target pixel clock] as an exact rational
1597 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1598 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1599 */
1600 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1601 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1602 amdgpu_crtc->crtc_id);
1603 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1604 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1605 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1606 }
1607
1608 /*
1609 * update the info frames with the data from the current display mode
1610 */
dce_v11_0_afmt_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)1611 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1612 struct drm_display_mode *mode)
1613 {
1614 struct drm_device *dev = encoder->dev;
1615 struct amdgpu_device *adev = drm_to_adev(dev);
1616 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1617 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1618 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1619 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1620 struct hdmi_avi_infoframe frame;
1621 ssize_t err;
1622 u32 tmp;
1623 int bpc = 8;
1624
1625 if (!dig || !dig->afmt)
1626 return;
1627
1628 /* Silent, r600_hdmi_enable will raise WARN for us */
1629 if (!dig->afmt->enabled)
1630 return;
1631
1632 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1633 if (encoder->crtc) {
1634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1635 bpc = amdgpu_crtc->bpc;
1636 }
1637
1638 /* disable audio prior to setting up hw */
1639 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1640 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1641
1642 dce_v11_0_audio_set_dto(encoder, mode->clock);
1643
1644 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1645 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1646 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1647
1648 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1649
1650 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1651 switch (bpc) {
1652 case 0:
1653 case 6:
1654 case 8:
1655 case 16:
1656 default:
1657 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1658 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1659 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1660 connector->name, bpc);
1661 break;
1662 case 10:
1663 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1664 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1665 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1666 connector->name);
1667 break;
1668 case 12:
1669 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1670 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1671 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1672 connector->name);
1673 break;
1674 }
1675 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1676
1677 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1678 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1679 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1680 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1681 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1682
1683 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1684 /* enable audio info frames (frames won't be set until audio is enabled) */
1685 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1686 /* required for audio info values to be updated */
1687 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1688 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1689
1690 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1691 /* required for audio info values to be updated */
1692 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1693 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1694
1695 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1696 /* anything other than 0 */
1697 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1698 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1699
1700 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1701
1702 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1703 /* set the default audio delay */
1704 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1705 /* should be suffient for all audio modes and small enough for all hblanks */
1706 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1707 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1708
1709 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1710 /* allow 60958 channel status fields to be updated */
1711 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1712 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1713
1714 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1715 if (bpc > 8)
1716 /* clear SW CTS value */
1717 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1718 else
1719 /* select SW CTS value */
1720 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1721 /* allow hw to sent ACR packets when required */
1722 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1723 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1724
1725 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1726
1727 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1728 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1729 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1730
1731 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1732 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1733 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1734
1735 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1736 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1737 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1738 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1741 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1742 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1743
1744 dce_v11_0_audio_write_speaker_allocation(encoder);
1745
1746 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1747 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1748
1749 dce_v11_0_afmt_audio_select_pin(encoder);
1750 dce_v11_0_audio_write_sad_regs(encoder);
1751 dce_v11_0_audio_write_latency_fields(encoder, mode);
1752
1753 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1754 if (err < 0) {
1755 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1756 return;
1757 }
1758
1759 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1760 if (err < 0) {
1761 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1762 return;
1763 }
1764
1765 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1766
1767 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1768 /* enable AVI info frames */
1769 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1770 /* required for audio info values to be updated */
1771 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1772 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1773
1774 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1775 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1776 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1777
1778 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1779 /* send audio packets */
1780 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1781 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1782
1783 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1784 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1785 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1786 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1787
1788 /* enable audio after to setting up hw */
1789 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1790 }
1791
dce_v11_0_afmt_enable(struct drm_encoder * encoder,bool enable)1792 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1793 {
1794 struct drm_device *dev = encoder->dev;
1795 struct amdgpu_device *adev = drm_to_adev(dev);
1796 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1797 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1798
1799 if (!dig || !dig->afmt)
1800 return;
1801
1802 /* Silent, r600_hdmi_enable will raise WARN for us */
1803 if (enable && dig->afmt->enabled)
1804 return;
1805 if (!enable && !dig->afmt->enabled)
1806 return;
1807
1808 if (!enable && dig->afmt->pin) {
1809 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1810 dig->afmt->pin = NULL;
1811 }
1812
1813 dig->afmt->enabled = enable;
1814
1815 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1816 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1817 }
1818
dce_v11_0_afmt_init(struct amdgpu_device * adev)1819 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1820 {
1821 int i;
1822
1823 for (i = 0; i < adev->mode_info.num_dig; i++)
1824 adev->mode_info.afmt[i] = NULL;
1825
1826 /* DCE11 has audio blocks tied to DIG encoders */
1827 for (i = 0; i < adev->mode_info.num_dig; i++) {
1828 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1829 if (adev->mode_info.afmt[i]) {
1830 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1831 adev->mode_info.afmt[i]->id = i;
1832 } else {
1833 int j;
1834 for (j = 0; j < i; j++) {
1835 kfree(adev->mode_info.afmt[j]);
1836 adev->mode_info.afmt[j] = NULL;
1837 }
1838 return -ENOMEM;
1839 }
1840 }
1841 return 0;
1842 }
1843
dce_v11_0_afmt_fini(struct amdgpu_device * adev)1844 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1845 {
1846 int i;
1847
1848 for (i = 0; i < adev->mode_info.num_dig; i++) {
1849 kfree(adev->mode_info.afmt[i]);
1850 adev->mode_info.afmt[i] = NULL;
1851 }
1852 }
1853
1854 static const u32 vga_control_regs[6] =
1855 {
1856 mmD1VGA_CONTROL,
1857 mmD2VGA_CONTROL,
1858 mmD3VGA_CONTROL,
1859 mmD4VGA_CONTROL,
1860 mmD5VGA_CONTROL,
1861 mmD6VGA_CONTROL,
1862 };
1863
dce_v11_0_vga_enable(struct drm_crtc * crtc,bool enable)1864 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1865 {
1866 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1867 struct drm_device *dev = crtc->dev;
1868 struct amdgpu_device *adev = drm_to_adev(dev);
1869 u32 vga_control;
1870
1871 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1872 if (enable)
1873 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1874 else
1875 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1876 }
1877
dce_v11_0_grph_enable(struct drm_crtc * crtc,bool enable)1878 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1879 {
1880 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1881 struct drm_device *dev = crtc->dev;
1882 struct amdgpu_device *adev = drm_to_adev(dev);
1883
1884 if (enable)
1885 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1886 else
1887 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1888 }
1889
dce_v11_0_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1890 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1891 struct drm_framebuffer *fb,
1892 int x, int y, int atomic)
1893 {
1894 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1895 struct drm_device *dev = crtc->dev;
1896 struct amdgpu_device *adev = drm_to_adev(dev);
1897 struct drm_framebuffer *target_fb;
1898 struct drm_gem_object *obj;
1899 struct amdgpu_bo *abo;
1900 uint64_t fb_location, tiling_flags;
1901 uint32_t fb_format, fb_pitch_pixels;
1902 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1903 u32 pipe_config;
1904 u32 tmp, viewport_w, viewport_h;
1905 int r;
1906 bool bypass_lut = false;
1907
1908 /* no fb bound */
1909 if (!atomic && !crtc->primary->fb) {
1910 DRM_DEBUG_KMS("No FB bound\n");
1911 return 0;
1912 }
1913
1914 if (atomic)
1915 target_fb = fb;
1916 else
1917 target_fb = crtc->primary->fb;
1918
1919 /* If atomic, assume fb object is pinned & idle & fenced and
1920 * just update base pointers
1921 */
1922 obj = target_fb->obj[0];
1923 abo = gem_to_amdgpu_bo(obj);
1924 r = amdgpu_bo_reserve(abo, false);
1925 if (unlikely(r != 0))
1926 return r;
1927
1928 if (!atomic) {
1929 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1930 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1931 if (unlikely(r != 0)) {
1932 amdgpu_bo_unreserve(abo);
1933 return -EINVAL;
1934 }
1935 }
1936 fb_location = amdgpu_bo_gpu_offset(abo);
1937
1938 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1939 amdgpu_bo_unreserve(abo);
1940
1941 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1942
1943 switch (target_fb->format->format) {
1944 case DRM_FORMAT_C8:
1945 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1946 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1947 break;
1948 case DRM_FORMAT_XRGB4444:
1949 case DRM_FORMAT_ARGB4444:
1950 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1951 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1952 #ifdef __BIG_ENDIAN
1953 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1954 ENDIAN_8IN16);
1955 #endif
1956 break;
1957 case DRM_FORMAT_XRGB1555:
1958 case DRM_FORMAT_ARGB1555:
1959 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1960 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1961 #ifdef __BIG_ENDIAN
1962 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1963 ENDIAN_8IN16);
1964 #endif
1965 break;
1966 case DRM_FORMAT_BGRX5551:
1967 case DRM_FORMAT_BGRA5551:
1968 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1969 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1970 #ifdef __BIG_ENDIAN
1971 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1972 ENDIAN_8IN16);
1973 #endif
1974 break;
1975 case DRM_FORMAT_RGB565:
1976 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1977 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1978 #ifdef __BIG_ENDIAN
1979 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1980 ENDIAN_8IN16);
1981 #endif
1982 break;
1983 case DRM_FORMAT_XRGB8888:
1984 case DRM_FORMAT_ARGB8888:
1985 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1986 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1987 #ifdef __BIG_ENDIAN
1988 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1989 ENDIAN_8IN32);
1990 #endif
1991 break;
1992 case DRM_FORMAT_XRGB2101010:
1993 case DRM_FORMAT_ARGB2101010:
1994 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1995 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1996 #ifdef __BIG_ENDIAN
1997 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1998 ENDIAN_8IN32);
1999 #endif
2000 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2001 bypass_lut = true;
2002 break;
2003 case DRM_FORMAT_BGRX1010102:
2004 case DRM_FORMAT_BGRA1010102:
2005 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2006 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2007 #ifdef __BIG_ENDIAN
2008 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2009 ENDIAN_8IN32);
2010 #endif
2011 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2012 bypass_lut = true;
2013 break;
2014 case DRM_FORMAT_XBGR8888:
2015 case DRM_FORMAT_ABGR8888:
2016 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2017 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2018 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2019 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2020 #ifdef __BIG_ENDIAN
2021 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2022 ENDIAN_8IN32);
2023 #endif
2024 break;
2025 default:
2026 DRM_ERROR("Unsupported screen format %p4cc\n",
2027 &target_fb->format->format);
2028 return -EINVAL;
2029 }
2030
2031 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2032 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2033
2034 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2035 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2036 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2037 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2038 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2039
2040 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2041 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2042 ARRAY_2D_TILED_THIN1);
2043 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2044 tile_split);
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2046 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2047 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2048 mtaspect);
2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2050 ADDR_SURF_MICRO_TILING_DISPLAY);
2051 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2052 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2053 ARRAY_1D_TILED_THIN1);
2054 }
2055
2056 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2057 pipe_config);
2058
2059 dce_v11_0_vga_enable(crtc, false);
2060
2061 /* Make sure surface address is updated at vertical blank rather than
2062 * horizontal blank
2063 */
2064 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2065 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2066 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2067 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2068
2069 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2070 upper_32_bits(fb_location));
2071 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2072 upper_32_bits(fb_location));
2073 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2074 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2075 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2076 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2077 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2078 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2079
2080 /*
2081 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2082 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2083 * retain the full precision throughout the pipeline.
2084 */
2085 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2086 if (bypass_lut)
2087 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2088 else
2089 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2090 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2091
2092 if (bypass_lut)
2093 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2094
2095 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2096 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2097 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2098 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2099 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2100 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2101
2102 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2103 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2104
2105 dce_v11_0_grph_enable(crtc, true);
2106
2107 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2108 target_fb->height);
2109
2110 x &= ~3;
2111 y &= ~1;
2112 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2113 (x << 16) | y);
2114 viewport_w = crtc->mode.hdisplay;
2115 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2116 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2117 (viewport_w << 16) | viewport_h);
2118
2119 /* set pageflip to happen anywhere in vblank interval */
2120 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2121
2122 if (!atomic && fb && fb != crtc->primary->fb) {
2123 abo = gem_to_amdgpu_bo(fb->obj[0]);
2124 r = amdgpu_bo_reserve(abo, true);
2125 if (unlikely(r != 0))
2126 return r;
2127 amdgpu_bo_unpin(abo);
2128 amdgpu_bo_unreserve(abo);
2129 }
2130
2131 /* Bytes per pixel may have changed */
2132 dce_v11_0_bandwidth_update(adev);
2133
2134 return 0;
2135 }
2136
dce_v11_0_set_interleave(struct drm_crtc * crtc,struct drm_display_mode * mode)2137 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2138 struct drm_display_mode *mode)
2139 {
2140 struct drm_device *dev = crtc->dev;
2141 struct amdgpu_device *adev = drm_to_adev(dev);
2142 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2143 u32 tmp;
2144
2145 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2146 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2147 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2148 else
2149 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2150 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2151 }
2152
dce_v11_0_crtc_load_lut(struct drm_crtc * crtc)2153 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2154 {
2155 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2156 struct drm_device *dev = crtc->dev;
2157 struct amdgpu_device *adev = drm_to_adev(dev);
2158 u16 *r, *g, *b;
2159 int i;
2160 u32 tmp;
2161
2162 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2163
2164 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2165 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2166 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2167
2168 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2169 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2170 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2171
2172 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2173 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2174 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2177
2178 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2179 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2180 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2181
2182 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2183 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2184 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2185
2186 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2187 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2188
2189 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2190 r = crtc->gamma_store;
2191 g = r + crtc->gamma_size;
2192 b = g + crtc->gamma_size;
2193 for (i = 0; i < 256; i++) {
2194 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2195 ((*r++ & 0xffc0) << 14) |
2196 ((*g++ & 0xffc0) << 4) |
2197 (*b++ >> 6));
2198 }
2199
2200 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2201 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2202 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2203 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2204 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2205
2206 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2207 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2208 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2209
2210 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2211 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2212 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2213
2214 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2215 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2216 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2217
2218 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2219 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2220 /* XXX this only needs to be programmed once per crtc at startup,
2221 * not sure where the best place for it is
2222 */
2223 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2224 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2225 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2226 }
2227
dce_v11_0_pick_dig_encoder(struct drm_encoder * encoder)2228 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2229 {
2230 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2232
2233 switch (amdgpu_encoder->encoder_id) {
2234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2235 if (dig->linkb)
2236 return 1;
2237 else
2238 return 0;
2239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2240 if (dig->linkb)
2241 return 3;
2242 else
2243 return 2;
2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2245 if (dig->linkb)
2246 return 5;
2247 else
2248 return 4;
2249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2250 return 6;
2251 default:
2252 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2253 return 0;
2254 }
2255 }
2256
2257 /**
2258 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2259 *
2260 * @crtc: drm crtc
2261 *
2262 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2263 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2264 * monitors a dedicated PPLL must be used. If a particular board has
2265 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2266 * as there is no need to program the PLL itself. If we are not able to
2267 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2268 * avoid messing up an existing monitor.
2269 *
2270 * Asic specific PLL information
2271 *
2272 * DCE 10.x
2273 * Tonga
2274 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2275 * CI
2276 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2277 *
2278 */
dce_v11_0_pick_pll(struct drm_crtc * crtc)2279 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2280 {
2281 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282 struct drm_device *dev = crtc->dev;
2283 struct amdgpu_device *adev = drm_to_adev(dev);
2284 u32 pll_in_use;
2285 int pll;
2286
2287 if ((adev->asic_type == CHIP_POLARIS10) ||
2288 (adev->asic_type == CHIP_POLARIS11) ||
2289 (adev->asic_type == CHIP_POLARIS12) ||
2290 (adev->asic_type == CHIP_VEGAM)) {
2291 struct amdgpu_encoder *amdgpu_encoder =
2292 to_amdgpu_encoder(amdgpu_crtc->encoder);
2293 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2294
2295 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2296 return ATOM_DP_DTO;
2297
2298 switch (amdgpu_encoder->encoder_id) {
2299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2300 if (dig->linkb)
2301 return ATOM_COMBOPHY_PLL1;
2302 else
2303 return ATOM_COMBOPHY_PLL0;
2304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2305 if (dig->linkb)
2306 return ATOM_COMBOPHY_PLL3;
2307 else
2308 return ATOM_COMBOPHY_PLL2;
2309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2310 if (dig->linkb)
2311 return ATOM_COMBOPHY_PLL5;
2312 else
2313 return ATOM_COMBOPHY_PLL4;
2314 default:
2315 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2316 return ATOM_PPLL_INVALID;
2317 }
2318 }
2319
2320 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2321 if (adev->clock.dp_extclk)
2322 /* skip PPLL programming if using ext clock */
2323 return ATOM_PPLL_INVALID;
2324 else {
2325 /* use the same PPLL for all DP monitors */
2326 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2327 if (pll != ATOM_PPLL_INVALID)
2328 return pll;
2329 }
2330 } else {
2331 /* use the same PPLL for all monitors with the same clock */
2332 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2333 if (pll != ATOM_PPLL_INVALID)
2334 return pll;
2335 }
2336
2337 /* XXX need to determine what plls are available on each DCE11 part */
2338 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2339 if (adev->flags & AMD_IS_APU) {
2340 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2341 return ATOM_PPLL1;
2342 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2343 return ATOM_PPLL0;
2344 DRM_ERROR("unable to allocate a PPLL\n");
2345 return ATOM_PPLL_INVALID;
2346 } else {
2347 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2348 return ATOM_PPLL2;
2349 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2350 return ATOM_PPLL1;
2351 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2352 return ATOM_PPLL0;
2353 DRM_ERROR("unable to allocate a PPLL\n");
2354 return ATOM_PPLL_INVALID;
2355 }
2356 return ATOM_PPLL_INVALID;
2357 }
2358
dce_v11_0_lock_cursor(struct drm_crtc * crtc,bool lock)2359 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2360 {
2361 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2362 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2363 uint32_t cur_lock;
2364
2365 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2366 if (lock)
2367 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2368 else
2369 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2370 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2371 }
2372
dce_v11_0_hide_cursor(struct drm_crtc * crtc)2373 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2374 {
2375 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2376 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2377 u32 tmp;
2378
2379 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2380 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2381 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2382 }
2383
dce_v11_0_show_cursor(struct drm_crtc * crtc)2384 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2385 {
2386 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2387 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2388 u32 tmp;
2389
2390 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2391 upper_32_bits(amdgpu_crtc->cursor_addr));
2392 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2393 lower_32_bits(amdgpu_crtc->cursor_addr));
2394
2395 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2396 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2397 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2398 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2399 }
2400
dce_v11_0_cursor_move_locked(struct drm_crtc * crtc,int x,int y)2401 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2402 int x, int y)
2403 {
2404 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2406 int xorigin = 0, yorigin = 0;
2407
2408 amdgpu_crtc->cursor_x = x;
2409 amdgpu_crtc->cursor_y = y;
2410
2411 /* avivo cursor are offset into the total surface */
2412 x += crtc->x;
2413 y += crtc->y;
2414 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2415
2416 if (x < 0) {
2417 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2418 x = 0;
2419 }
2420 if (y < 0) {
2421 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2422 y = 0;
2423 }
2424
2425 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2426 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2427 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2428 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2429
2430 return 0;
2431 }
2432
dce_v11_0_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)2433 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2434 int x, int y)
2435 {
2436 int ret;
2437
2438 dce_v11_0_lock_cursor(crtc, true);
2439 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2440 dce_v11_0_lock_cursor(crtc, false);
2441
2442 return ret;
2443 }
2444
dce_v11_0_crtc_cursor_set2(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height,int32_t hot_x,int32_t hot_y)2445 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2446 struct drm_file *file_priv,
2447 uint32_t handle,
2448 uint32_t width,
2449 uint32_t height,
2450 int32_t hot_x,
2451 int32_t hot_y)
2452 {
2453 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2454 struct drm_gem_object *obj;
2455 struct amdgpu_bo *aobj;
2456 int ret;
2457
2458 if (!handle) {
2459 /* turn off cursor */
2460 dce_v11_0_hide_cursor(crtc);
2461 obj = NULL;
2462 goto unpin;
2463 }
2464
2465 if ((width > amdgpu_crtc->max_cursor_width) ||
2466 (height > amdgpu_crtc->max_cursor_height)) {
2467 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2468 return -EINVAL;
2469 }
2470
2471 obj = drm_gem_object_lookup(file_priv, handle);
2472 if (!obj) {
2473 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2474 return -ENOENT;
2475 }
2476
2477 aobj = gem_to_amdgpu_bo(obj);
2478 ret = amdgpu_bo_reserve(aobj, false);
2479 if (ret != 0) {
2480 drm_gem_object_put(obj);
2481 return ret;
2482 }
2483
2484 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2485 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2486 amdgpu_bo_unreserve(aobj);
2487 if (ret) {
2488 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2489 drm_gem_object_put(obj);
2490 return ret;
2491 }
2492 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2493
2494 dce_v11_0_lock_cursor(crtc, true);
2495
2496 if (width != amdgpu_crtc->cursor_width ||
2497 height != amdgpu_crtc->cursor_height ||
2498 hot_x != amdgpu_crtc->cursor_hot_x ||
2499 hot_y != amdgpu_crtc->cursor_hot_y) {
2500 int x, y;
2501
2502 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2503 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2504
2505 dce_v11_0_cursor_move_locked(crtc, x, y);
2506
2507 amdgpu_crtc->cursor_width = width;
2508 amdgpu_crtc->cursor_height = height;
2509 amdgpu_crtc->cursor_hot_x = hot_x;
2510 amdgpu_crtc->cursor_hot_y = hot_y;
2511 }
2512
2513 dce_v11_0_show_cursor(crtc);
2514 dce_v11_0_lock_cursor(crtc, false);
2515
2516 unpin:
2517 if (amdgpu_crtc->cursor_bo) {
2518 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2519 ret = amdgpu_bo_reserve(aobj, true);
2520 if (likely(ret == 0)) {
2521 amdgpu_bo_unpin(aobj);
2522 amdgpu_bo_unreserve(aobj);
2523 }
2524 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2525 }
2526
2527 amdgpu_crtc->cursor_bo = obj;
2528 return 0;
2529 }
2530
dce_v11_0_cursor_reset(struct drm_crtc * crtc)2531 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2532 {
2533 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2534
2535 if (amdgpu_crtc->cursor_bo) {
2536 dce_v11_0_lock_cursor(crtc, true);
2537
2538 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2539 amdgpu_crtc->cursor_y);
2540
2541 dce_v11_0_show_cursor(crtc);
2542
2543 dce_v11_0_lock_cursor(crtc, false);
2544 }
2545 }
2546
dce_v11_0_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)2547 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2548 u16 *blue, uint32_t size,
2549 struct drm_modeset_acquire_ctx *ctx)
2550 {
2551 dce_v11_0_crtc_load_lut(crtc);
2552
2553 return 0;
2554 }
2555
dce_v11_0_crtc_destroy(struct drm_crtc * crtc)2556 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2557 {
2558 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2559
2560 drm_crtc_cleanup(crtc);
2561 kfree(amdgpu_crtc);
2562 }
2563
2564 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2565 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2566 .cursor_move = dce_v11_0_crtc_cursor_move,
2567 .gamma_set = dce_v11_0_crtc_gamma_set,
2568 .set_config = amdgpu_display_crtc_set_config,
2569 .destroy = dce_v11_0_crtc_destroy,
2570 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2571 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2572 .enable_vblank = amdgpu_enable_vblank_kms,
2573 .disable_vblank = amdgpu_disable_vblank_kms,
2574 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2575 };
2576
dce_v11_0_crtc_dpms(struct drm_crtc * crtc,int mode)2577 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2578 {
2579 struct drm_device *dev = crtc->dev;
2580 struct amdgpu_device *adev = drm_to_adev(dev);
2581 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2582 unsigned type;
2583
2584 switch (mode) {
2585 case DRM_MODE_DPMS_ON:
2586 amdgpu_crtc->enabled = true;
2587 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2588 dce_v11_0_vga_enable(crtc, true);
2589 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2590 dce_v11_0_vga_enable(crtc, false);
2591 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2592 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2593 amdgpu_crtc->crtc_id);
2594 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2595 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2596 drm_crtc_vblank_on(crtc);
2597 dce_v11_0_crtc_load_lut(crtc);
2598 break;
2599 case DRM_MODE_DPMS_STANDBY:
2600 case DRM_MODE_DPMS_SUSPEND:
2601 case DRM_MODE_DPMS_OFF:
2602 drm_crtc_vblank_off(crtc);
2603 if (amdgpu_crtc->enabled) {
2604 dce_v11_0_vga_enable(crtc, true);
2605 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2606 dce_v11_0_vga_enable(crtc, false);
2607 }
2608 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2609 amdgpu_crtc->enabled = false;
2610 break;
2611 }
2612 /* adjust pm to dpms */
2613 amdgpu_dpm_compute_clocks(adev);
2614 }
2615
dce_v11_0_crtc_prepare(struct drm_crtc * crtc)2616 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2617 {
2618 /* disable crtc pair power gating before programming */
2619 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2620 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2621 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2622 }
2623
dce_v11_0_crtc_commit(struct drm_crtc * crtc)2624 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2625 {
2626 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2627 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2628 }
2629
dce_v11_0_crtc_disable(struct drm_crtc * crtc)2630 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2631 {
2632 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2633 struct drm_device *dev = crtc->dev;
2634 struct amdgpu_device *adev = drm_to_adev(dev);
2635 struct amdgpu_atom_ss ss;
2636 int i;
2637
2638 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2639 if (crtc->primary->fb) {
2640 int r;
2641 struct amdgpu_bo *abo;
2642
2643 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2644 r = amdgpu_bo_reserve(abo, true);
2645 if (unlikely(r))
2646 DRM_ERROR("failed to reserve abo before unpin\n");
2647 else {
2648 amdgpu_bo_unpin(abo);
2649 amdgpu_bo_unreserve(abo);
2650 }
2651 }
2652 /* disable the GRPH */
2653 dce_v11_0_grph_enable(crtc, false);
2654
2655 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2656
2657 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2658 if (adev->mode_info.crtcs[i] &&
2659 adev->mode_info.crtcs[i]->enabled &&
2660 i != amdgpu_crtc->crtc_id &&
2661 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2662 /* one other crtc is using this pll don't turn
2663 * off the pll
2664 */
2665 goto done;
2666 }
2667 }
2668
2669 switch (amdgpu_crtc->pll_id) {
2670 case ATOM_PPLL0:
2671 case ATOM_PPLL1:
2672 case ATOM_PPLL2:
2673 /* disable the ppll */
2674 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2675 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2676 break;
2677 case ATOM_COMBOPHY_PLL0:
2678 case ATOM_COMBOPHY_PLL1:
2679 case ATOM_COMBOPHY_PLL2:
2680 case ATOM_COMBOPHY_PLL3:
2681 case ATOM_COMBOPHY_PLL4:
2682 case ATOM_COMBOPHY_PLL5:
2683 /* disable the ppll */
2684 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2685 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2686 break;
2687 default:
2688 break;
2689 }
2690 done:
2691 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2692 amdgpu_crtc->adjusted_clock = 0;
2693 amdgpu_crtc->encoder = NULL;
2694 amdgpu_crtc->connector = NULL;
2695 }
2696
dce_v11_0_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2697 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2698 struct drm_display_mode *mode,
2699 struct drm_display_mode *adjusted_mode,
2700 int x, int y, struct drm_framebuffer *old_fb)
2701 {
2702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2703 struct drm_device *dev = crtc->dev;
2704 struct amdgpu_device *adev = drm_to_adev(dev);
2705
2706 if (!amdgpu_crtc->adjusted_clock)
2707 return -EINVAL;
2708
2709 if ((adev->asic_type == CHIP_POLARIS10) ||
2710 (adev->asic_type == CHIP_POLARIS11) ||
2711 (adev->asic_type == CHIP_POLARIS12) ||
2712 (adev->asic_type == CHIP_VEGAM)) {
2713 struct amdgpu_encoder *amdgpu_encoder =
2714 to_amdgpu_encoder(amdgpu_crtc->encoder);
2715 int encoder_mode =
2716 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2717
2718 /* SetPixelClock calculates the plls and ss values now */
2719 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2720 amdgpu_crtc->pll_id,
2721 encoder_mode, amdgpu_encoder->encoder_id,
2722 adjusted_mode->clock, 0, 0, 0, 0,
2723 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2724 } else {
2725 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2726 }
2727 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2728 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2729 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2730 amdgpu_atombios_crtc_scaler_setup(crtc);
2731 dce_v11_0_cursor_reset(crtc);
2732 /* update the hw version fpr dpm */
2733 amdgpu_crtc->hw_mode = *adjusted_mode;
2734
2735 return 0;
2736 }
2737
dce_v11_0_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2738 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2739 const struct drm_display_mode *mode,
2740 struct drm_display_mode *adjusted_mode)
2741 {
2742 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2743 struct drm_device *dev = crtc->dev;
2744 struct drm_encoder *encoder;
2745
2746 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2747 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2748 if (encoder->crtc == crtc) {
2749 amdgpu_crtc->encoder = encoder;
2750 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2751 break;
2752 }
2753 }
2754 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2755 amdgpu_crtc->encoder = NULL;
2756 amdgpu_crtc->connector = NULL;
2757 return false;
2758 }
2759 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2760 return false;
2761 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2762 return false;
2763 /* pick pll */
2764 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2765 /* if we can't get a PPLL for a non-DP encoder, fail */
2766 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2767 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2768 return false;
2769
2770 return true;
2771 }
2772
dce_v11_0_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)2773 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2774 struct drm_framebuffer *old_fb)
2775 {
2776 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2777 }
2778
dce_v11_0_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)2779 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y, enum mode_set_atomic state)
2782 {
2783 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2784 }
2785
2786 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2787 .dpms = dce_v11_0_crtc_dpms,
2788 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2789 .mode_set = dce_v11_0_crtc_mode_set,
2790 .mode_set_base = dce_v11_0_crtc_set_base,
2791 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2792 .prepare = dce_v11_0_crtc_prepare,
2793 .commit = dce_v11_0_crtc_commit,
2794 .disable = dce_v11_0_crtc_disable,
2795 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2796 };
2797
dce_v11_0_crtc_init(struct amdgpu_device * adev,int index)2798 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2799 {
2800 struct amdgpu_crtc *amdgpu_crtc;
2801
2802 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2803 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2804 if (amdgpu_crtc == NULL)
2805 return -ENOMEM;
2806
2807 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2808
2809 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2810 amdgpu_crtc->crtc_id = index;
2811 adev->mode_info.crtcs[index] = amdgpu_crtc;
2812
2813 amdgpu_crtc->max_cursor_width = 128;
2814 amdgpu_crtc->max_cursor_height = 128;
2815 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2816 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2817
2818 switch (amdgpu_crtc->crtc_id) {
2819 case 0:
2820 default:
2821 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2822 break;
2823 case 1:
2824 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2825 break;
2826 case 2:
2827 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2828 break;
2829 case 3:
2830 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2831 break;
2832 case 4:
2833 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2834 break;
2835 case 5:
2836 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2837 break;
2838 }
2839
2840 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2841 amdgpu_crtc->adjusted_clock = 0;
2842 amdgpu_crtc->encoder = NULL;
2843 amdgpu_crtc->connector = NULL;
2844 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2845
2846 return 0;
2847 }
2848
dce_v11_0_early_init(void * handle)2849 static int dce_v11_0_early_init(void *handle)
2850 {
2851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2852
2853 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2854 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2855
2856 dce_v11_0_set_display_funcs(adev);
2857
2858 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2859
2860 switch (adev->asic_type) {
2861 case CHIP_CARRIZO:
2862 adev->mode_info.num_hpd = 6;
2863 adev->mode_info.num_dig = 9;
2864 break;
2865 case CHIP_STONEY:
2866 adev->mode_info.num_hpd = 6;
2867 adev->mode_info.num_dig = 9;
2868 break;
2869 case CHIP_POLARIS10:
2870 case CHIP_VEGAM:
2871 adev->mode_info.num_hpd = 6;
2872 adev->mode_info.num_dig = 6;
2873 break;
2874 case CHIP_POLARIS11:
2875 case CHIP_POLARIS12:
2876 adev->mode_info.num_hpd = 5;
2877 adev->mode_info.num_dig = 5;
2878 break;
2879 default:
2880 /* FIXME: not supported yet */
2881 return -EINVAL;
2882 }
2883
2884 dce_v11_0_set_irq_funcs(adev);
2885
2886 return 0;
2887 }
2888
dce_v11_0_sw_init(void * handle)2889 static int dce_v11_0_sw_init(void *handle)
2890 {
2891 int r, i;
2892 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2893
2894 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2895 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2896 if (r)
2897 return r;
2898 }
2899
2900 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2901 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2902 if (r)
2903 return r;
2904 }
2905
2906 /* HPD hotplug */
2907 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2908 if (r)
2909 return r;
2910
2911 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2912
2913 adev_to_drm(adev)->mode_config.async_page_flip = true;
2914
2915 adev_to_drm(adev)->mode_config.max_width = 16384;
2916 adev_to_drm(adev)->mode_config.max_height = 16384;
2917
2918 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2919 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2920
2921 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2922
2923 r = amdgpu_display_modeset_create_props(adev);
2924 if (r)
2925 return r;
2926
2927 adev_to_drm(adev)->mode_config.max_width = 16384;
2928 adev_to_drm(adev)->mode_config.max_height = 16384;
2929
2930
2931 /* allocate crtcs */
2932 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2933 r = dce_v11_0_crtc_init(adev, i);
2934 if (r)
2935 return r;
2936 }
2937
2938 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2939 amdgpu_display_print_display_setup(adev_to_drm(adev));
2940 else
2941 return -EINVAL;
2942
2943 /* setup afmt */
2944 r = dce_v11_0_afmt_init(adev);
2945 if (r)
2946 return r;
2947
2948 r = dce_v11_0_audio_init(adev);
2949 if (r)
2950 return r;
2951
2952 /* Disable vblank IRQs aggressively for power-saving */
2953 /* XXX: can this be enabled for DC? */
2954 adev_to_drm(adev)->vblank_disable_immediate = true;
2955
2956 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2957 if (r)
2958 return r;
2959
2960 INIT_DELAYED_WORK(&adev->hotplug_work,
2961 amdgpu_display_hotplug_work_func);
2962
2963 drm_kms_helper_poll_init(adev_to_drm(adev));
2964
2965 adev->mode_info.mode_config_initialized = true;
2966 return 0;
2967 }
2968
dce_v11_0_sw_fini(void * handle)2969 static int dce_v11_0_sw_fini(void *handle)
2970 {
2971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2972
2973 drm_edid_free(adev->mode_info.bios_hardcoded_edid);
2974
2975 drm_kms_helper_poll_fini(adev_to_drm(adev));
2976
2977 dce_v11_0_audio_fini(adev);
2978
2979 dce_v11_0_afmt_fini(adev);
2980
2981 drm_mode_config_cleanup(adev_to_drm(adev));
2982 adev->mode_info.mode_config_initialized = false;
2983
2984 return 0;
2985 }
2986
dce_v11_0_hw_init(void * handle)2987 static int dce_v11_0_hw_init(void *handle)
2988 {
2989 int i;
2990 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2991
2992 dce_v11_0_init_golden_registers(adev);
2993
2994 /* disable vga render */
2995 dce_v11_0_set_vga_render_state(adev, false);
2996 /* init dig PHYs, disp eng pll */
2997 amdgpu_atombios_crtc_powergate_init(adev);
2998 amdgpu_atombios_encoder_init_dig(adev);
2999 if ((adev->asic_type == CHIP_POLARIS10) ||
3000 (adev->asic_type == CHIP_POLARIS11) ||
3001 (adev->asic_type == CHIP_POLARIS12) ||
3002 (adev->asic_type == CHIP_VEGAM)) {
3003 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3004 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3005 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3006 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3007 } else {
3008 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3009 }
3010
3011 /* initialize hpd */
3012 dce_v11_0_hpd_init(adev);
3013
3014 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3015 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3016 }
3017
3018 dce_v11_0_pageflip_interrupt_init(adev);
3019
3020 return 0;
3021 }
3022
dce_v11_0_hw_fini(void * handle)3023 static int dce_v11_0_hw_fini(void *handle)
3024 {
3025 int i;
3026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3027
3028 dce_v11_0_hpd_fini(adev);
3029
3030 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3031 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3032 }
3033
3034 dce_v11_0_pageflip_interrupt_fini(adev);
3035
3036 flush_delayed_work(&adev->hotplug_work);
3037
3038 return 0;
3039 }
3040
dce_v11_0_suspend(void * handle)3041 static int dce_v11_0_suspend(void *handle)
3042 {
3043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3044 int r;
3045
3046 r = amdgpu_display_suspend_helper(adev);
3047 if (r)
3048 return r;
3049
3050 adev->mode_info.bl_level =
3051 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3052
3053 return dce_v11_0_hw_fini(handle);
3054 }
3055
dce_v11_0_resume(void * handle)3056 static int dce_v11_0_resume(void *handle)
3057 {
3058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059 int ret;
3060
3061 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3062 adev->mode_info.bl_level);
3063
3064 ret = dce_v11_0_hw_init(handle);
3065
3066 /* turn on the BL */
3067 if (adev->mode_info.bl_encoder) {
3068 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3069 adev->mode_info.bl_encoder);
3070 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3071 bl_level);
3072 }
3073 if (ret)
3074 return ret;
3075
3076 return amdgpu_display_resume_helper(adev);
3077 }
3078
dce_v11_0_is_idle(void * handle)3079 static bool dce_v11_0_is_idle(void *handle)
3080 {
3081 return true;
3082 }
3083
dce_v11_0_wait_for_idle(void * handle)3084 static int dce_v11_0_wait_for_idle(void *handle)
3085 {
3086 return 0;
3087 }
3088
dce_v11_0_soft_reset(void * handle)3089 static int dce_v11_0_soft_reset(void *handle)
3090 {
3091 u32 srbm_soft_reset = 0, tmp;
3092 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3093
3094 if (dce_v11_0_is_display_hung(adev))
3095 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3096
3097 if (srbm_soft_reset) {
3098 tmp = RREG32(mmSRBM_SOFT_RESET);
3099 tmp |= srbm_soft_reset;
3100 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3101 WREG32(mmSRBM_SOFT_RESET, tmp);
3102 tmp = RREG32(mmSRBM_SOFT_RESET);
3103
3104 udelay(50);
3105
3106 tmp &= ~srbm_soft_reset;
3107 WREG32(mmSRBM_SOFT_RESET, tmp);
3108 tmp = RREG32(mmSRBM_SOFT_RESET);
3109
3110 /* Wait a little for things to settle down */
3111 udelay(50);
3112 }
3113 return 0;
3114 }
3115
dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)3116 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3117 int crtc,
3118 enum amdgpu_interrupt_state state)
3119 {
3120 u32 lb_interrupt_mask;
3121
3122 if (crtc >= adev->mode_info.num_crtc) {
3123 DRM_DEBUG("invalid crtc %d\n", crtc);
3124 return;
3125 }
3126
3127 switch (state) {
3128 case AMDGPU_IRQ_STATE_DISABLE:
3129 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3130 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3131 VBLANK_INTERRUPT_MASK, 0);
3132 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3133 break;
3134 case AMDGPU_IRQ_STATE_ENABLE:
3135 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3136 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3137 VBLANK_INTERRUPT_MASK, 1);
3138 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3139 break;
3140 default:
3141 break;
3142 }
3143 }
3144
dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)3145 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3146 int crtc,
3147 enum amdgpu_interrupt_state state)
3148 {
3149 u32 lb_interrupt_mask;
3150
3151 if (crtc >= adev->mode_info.num_crtc) {
3152 DRM_DEBUG("invalid crtc %d\n", crtc);
3153 return;
3154 }
3155
3156 switch (state) {
3157 case AMDGPU_IRQ_STATE_DISABLE:
3158 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3159 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3160 VLINE_INTERRUPT_MASK, 0);
3161 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3162 break;
3163 case AMDGPU_IRQ_STATE_ENABLE:
3164 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3165 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3166 VLINE_INTERRUPT_MASK, 1);
3167 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3168 break;
3169 default:
3170 break;
3171 }
3172 }
3173
dce_v11_0_set_hpd_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned hpd,enum amdgpu_interrupt_state state)3174 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3175 struct amdgpu_irq_src *source,
3176 unsigned hpd,
3177 enum amdgpu_interrupt_state state)
3178 {
3179 u32 tmp;
3180
3181 if (hpd >= adev->mode_info.num_hpd) {
3182 DRM_DEBUG("invalid hdp %d\n", hpd);
3183 return 0;
3184 }
3185
3186 switch (state) {
3187 case AMDGPU_IRQ_STATE_DISABLE:
3188 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3189 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3190 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3191 break;
3192 case AMDGPU_IRQ_STATE_ENABLE:
3193 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3194 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3195 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3196 break;
3197 default:
3198 break;
3199 }
3200
3201 return 0;
3202 }
3203
dce_v11_0_set_crtc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)3204 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3205 struct amdgpu_irq_src *source,
3206 unsigned type,
3207 enum amdgpu_interrupt_state state)
3208 {
3209 switch (type) {
3210 case AMDGPU_CRTC_IRQ_VBLANK1:
3211 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VBLANK2:
3214 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3215 break;
3216 case AMDGPU_CRTC_IRQ_VBLANK3:
3217 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3218 break;
3219 case AMDGPU_CRTC_IRQ_VBLANK4:
3220 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3221 break;
3222 case AMDGPU_CRTC_IRQ_VBLANK5:
3223 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3224 break;
3225 case AMDGPU_CRTC_IRQ_VBLANK6:
3226 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3227 break;
3228 case AMDGPU_CRTC_IRQ_VLINE1:
3229 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3230 break;
3231 case AMDGPU_CRTC_IRQ_VLINE2:
3232 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3233 break;
3234 case AMDGPU_CRTC_IRQ_VLINE3:
3235 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3236 break;
3237 case AMDGPU_CRTC_IRQ_VLINE4:
3238 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3239 break;
3240 case AMDGPU_CRTC_IRQ_VLINE5:
3241 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3242 break;
3243 case AMDGPU_CRTC_IRQ_VLINE6:
3244 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3245 break;
3246 default:
3247 break;
3248 }
3249 return 0;
3250 }
3251
dce_v11_0_set_pageflip_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3252 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3253 struct amdgpu_irq_src *src,
3254 unsigned type,
3255 enum amdgpu_interrupt_state state)
3256 {
3257 u32 reg;
3258
3259 if (type >= adev->mode_info.num_crtc) {
3260 DRM_ERROR("invalid pageflip crtc %d\n", type);
3261 return -EINVAL;
3262 }
3263
3264 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3265 if (state == AMDGPU_IRQ_STATE_DISABLE)
3266 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3267 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3268 else
3269 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3270 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3271
3272 return 0;
3273 }
3274
dce_v11_0_pageflip_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3275 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3276 struct amdgpu_irq_src *source,
3277 struct amdgpu_iv_entry *entry)
3278 {
3279 unsigned long flags;
3280 unsigned crtc_id;
3281 struct amdgpu_crtc *amdgpu_crtc;
3282 struct amdgpu_flip_work *works;
3283
3284 crtc_id = (entry->src_id - 8) >> 1;
3285 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3286
3287 if (crtc_id >= adev->mode_info.num_crtc) {
3288 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3289 return -EINVAL;
3290 }
3291
3292 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3293 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3294 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3295 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3296
3297 /* IRQ could occur when in initial stage */
3298 if(amdgpu_crtc == NULL)
3299 return 0;
3300
3301 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3302 works = amdgpu_crtc->pflip_works;
3303 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3304 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3305 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3306 amdgpu_crtc->pflip_status,
3307 AMDGPU_FLIP_SUBMITTED);
3308 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3309 return 0;
3310 }
3311
3312 /* page flip completed. clean up */
3313 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3314 amdgpu_crtc->pflip_works = NULL;
3315
3316 /* wakeup usersapce */
3317 if(works->event)
3318 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3319
3320 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3321
3322 drm_crtc_vblank_put(&amdgpu_crtc->base);
3323 schedule_work(&works->unpin_work);
3324
3325 return 0;
3326 }
3327
dce_v11_0_hpd_int_ack(struct amdgpu_device * adev,int hpd)3328 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3329 int hpd)
3330 {
3331 u32 tmp;
3332
3333 if (hpd >= adev->mode_info.num_hpd) {
3334 DRM_DEBUG("invalid hdp %d\n", hpd);
3335 return;
3336 }
3337
3338 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3339 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3341 }
3342
dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device * adev,int crtc)3343 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3344 int crtc)
3345 {
3346 u32 tmp;
3347
3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3349 DRM_DEBUG("invalid crtc %d\n", crtc);
3350 return;
3351 }
3352
3353 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3354 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3355 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3356 }
3357
dce_v11_0_crtc_vline_int_ack(struct amdgpu_device * adev,int crtc)3358 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3359 int crtc)
3360 {
3361 u32 tmp;
3362
3363 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3364 DRM_DEBUG("invalid crtc %d\n", crtc);
3365 return;
3366 }
3367
3368 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3369 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3370 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3371 }
3372
dce_v11_0_crtc_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3373 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3374 struct amdgpu_irq_src *source,
3375 struct amdgpu_iv_entry *entry)
3376 {
3377 unsigned crtc = entry->src_id - 1;
3378 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3379 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3380 crtc);
3381
3382 switch (entry->src_data[0]) {
3383 case 0: /* vblank */
3384 if (disp_int & interrupt_status_offsets[crtc].vblank)
3385 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3386 else
3387 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3388
3389 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3390 drm_handle_vblank(adev_to_drm(adev), crtc);
3391 }
3392 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3393
3394 break;
3395 case 1: /* vline */
3396 if (disp_int & interrupt_status_offsets[crtc].vline)
3397 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3398 else
3399 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3400
3401 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3402
3403 break;
3404 default:
3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3406 break;
3407 }
3408
3409 return 0;
3410 }
3411
dce_v11_0_hpd_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3412 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3413 struct amdgpu_irq_src *source,
3414 struct amdgpu_iv_entry *entry)
3415 {
3416 uint32_t disp_int, mask;
3417 unsigned hpd;
3418
3419 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3420 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3421 return 0;
3422 }
3423
3424 hpd = entry->src_data[0];
3425 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3426 mask = interrupt_status_offsets[hpd].hpd;
3427
3428 if (disp_int & mask) {
3429 dce_v11_0_hpd_int_ack(adev, hpd);
3430 schedule_delayed_work(&adev->hotplug_work, 0);
3431 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3432 }
3433
3434 return 0;
3435 }
3436
dce_v11_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3437 static int dce_v11_0_set_clockgating_state(void *handle,
3438 enum amd_clockgating_state state)
3439 {
3440 return 0;
3441 }
3442
dce_v11_0_set_powergating_state(void * handle,enum amd_powergating_state state)3443 static int dce_v11_0_set_powergating_state(void *handle,
3444 enum amd_powergating_state state)
3445 {
3446 return 0;
3447 }
3448
3449 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3450 .name = "dce_v11_0",
3451 .early_init = dce_v11_0_early_init,
3452 .late_init = NULL,
3453 .sw_init = dce_v11_0_sw_init,
3454 .sw_fini = dce_v11_0_sw_fini,
3455 .hw_init = dce_v11_0_hw_init,
3456 .hw_fini = dce_v11_0_hw_fini,
3457 .suspend = dce_v11_0_suspend,
3458 .resume = dce_v11_0_resume,
3459 .is_idle = dce_v11_0_is_idle,
3460 .wait_for_idle = dce_v11_0_wait_for_idle,
3461 .soft_reset = dce_v11_0_soft_reset,
3462 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3463 .set_powergating_state = dce_v11_0_set_powergating_state,
3464 .dump_ip_state = NULL,
3465 .print_ip_state = NULL,
3466 };
3467
3468 static void
dce_v11_0_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3469 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3470 struct drm_display_mode *mode,
3471 struct drm_display_mode *adjusted_mode)
3472 {
3473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3474
3475 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3476
3477 /* need to call this here rather than in prepare() since we need some crtc info */
3478 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3479
3480 /* set scaler clears this on some chips */
3481 dce_v11_0_set_interleave(encoder->crtc, mode);
3482
3483 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3484 dce_v11_0_afmt_enable(encoder, true);
3485 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3486 }
3487 }
3488
dce_v11_0_encoder_prepare(struct drm_encoder * encoder)3489 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3490 {
3491 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3492 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3493 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3494
3495 if ((amdgpu_encoder->active_device &
3496 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3497 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3498 ENCODER_OBJECT_ID_NONE)) {
3499 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3500 if (dig) {
3501 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3502 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3503 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3504 }
3505 }
3506
3507 amdgpu_atombios_scratch_regs_lock(adev, true);
3508
3509 if (connector) {
3510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3511
3512 /* select the clock/data port if it uses a router */
3513 if (amdgpu_connector->router.cd_valid)
3514 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3515
3516 /* turn eDP panel on for mode set */
3517 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3518 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3519 ATOM_TRANSMITTER_ACTION_POWER_ON);
3520 }
3521
3522 /* this is needed for the pll/ss setup to work correctly in some cases */
3523 amdgpu_atombios_encoder_set_crtc_source(encoder);
3524 /* set up the FMT blocks */
3525 dce_v11_0_program_fmt(encoder);
3526 }
3527
dce_v11_0_encoder_commit(struct drm_encoder * encoder)3528 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3529 {
3530 struct drm_device *dev = encoder->dev;
3531 struct amdgpu_device *adev = drm_to_adev(dev);
3532
3533 /* need to call this here as we need the crtc set up */
3534 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3535 amdgpu_atombios_scratch_regs_lock(adev, false);
3536 }
3537
dce_v11_0_encoder_disable(struct drm_encoder * encoder)3538 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3539 {
3540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3541 struct amdgpu_encoder_atom_dig *dig;
3542
3543 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3544
3545 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3546 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3547 dce_v11_0_afmt_enable(encoder, false);
3548 dig = amdgpu_encoder->enc_priv;
3549 dig->dig_encoder = -1;
3550 }
3551 amdgpu_encoder->active_device = 0;
3552 }
3553
3554 /* these are handled by the primary encoders */
dce_v11_0_ext_prepare(struct drm_encoder * encoder)3555 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3556 {
3557
3558 }
3559
dce_v11_0_ext_commit(struct drm_encoder * encoder)3560 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3561 {
3562
3563 }
3564
3565 static void
dce_v11_0_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3566 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3567 struct drm_display_mode *mode,
3568 struct drm_display_mode *adjusted_mode)
3569 {
3570
3571 }
3572
dce_v11_0_ext_disable(struct drm_encoder * encoder)3573 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3574 {
3575
3576 }
3577
3578 static void
dce_v11_0_ext_dpms(struct drm_encoder * encoder,int mode)3579 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3580 {
3581
3582 }
3583
3584 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3585 .dpms = dce_v11_0_ext_dpms,
3586 .prepare = dce_v11_0_ext_prepare,
3587 .mode_set = dce_v11_0_ext_mode_set,
3588 .commit = dce_v11_0_ext_commit,
3589 .disable = dce_v11_0_ext_disable,
3590 /* no detect for TMDS/LVDS yet */
3591 };
3592
3593 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3594 .dpms = amdgpu_atombios_encoder_dpms,
3595 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3596 .prepare = dce_v11_0_encoder_prepare,
3597 .mode_set = dce_v11_0_encoder_mode_set,
3598 .commit = dce_v11_0_encoder_commit,
3599 .disable = dce_v11_0_encoder_disable,
3600 .detect = amdgpu_atombios_encoder_dig_detect,
3601 };
3602
3603 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3604 .dpms = amdgpu_atombios_encoder_dpms,
3605 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3606 .prepare = dce_v11_0_encoder_prepare,
3607 .mode_set = dce_v11_0_encoder_mode_set,
3608 .commit = dce_v11_0_encoder_commit,
3609 .detect = amdgpu_atombios_encoder_dac_detect,
3610 };
3611
dce_v11_0_encoder_destroy(struct drm_encoder * encoder)3612 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3613 {
3614 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3615 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3616 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3617 kfree(amdgpu_encoder->enc_priv);
3618 drm_encoder_cleanup(encoder);
3619 kfree(amdgpu_encoder);
3620 }
3621
3622 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3623 .destroy = dce_v11_0_encoder_destroy,
3624 };
3625
dce_v11_0_encoder_add(struct amdgpu_device * adev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)3626 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3627 uint32_t encoder_enum,
3628 uint32_t supported_device,
3629 u16 caps)
3630 {
3631 struct drm_device *dev = adev_to_drm(adev);
3632 struct drm_encoder *encoder;
3633 struct amdgpu_encoder *amdgpu_encoder;
3634
3635 /* see if we already added it */
3636 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3637 amdgpu_encoder = to_amdgpu_encoder(encoder);
3638 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3639 amdgpu_encoder->devices |= supported_device;
3640 return;
3641 }
3642
3643 }
3644
3645 /* add a new one */
3646 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3647 if (!amdgpu_encoder)
3648 return;
3649
3650 encoder = &amdgpu_encoder->base;
3651 switch (adev->mode_info.num_crtc) {
3652 case 1:
3653 encoder->possible_crtcs = 0x1;
3654 break;
3655 case 2:
3656 default:
3657 encoder->possible_crtcs = 0x3;
3658 break;
3659 case 3:
3660 encoder->possible_crtcs = 0x7;
3661 break;
3662 case 4:
3663 encoder->possible_crtcs = 0xf;
3664 break;
3665 case 5:
3666 encoder->possible_crtcs = 0x1f;
3667 break;
3668 case 6:
3669 encoder->possible_crtcs = 0x3f;
3670 break;
3671 }
3672
3673 amdgpu_encoder->enc_priv = NULL;
3674
3675 amdgpu_encoder->encoder_enum = encoder_enum;
3676 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3677 amdgpu_encoder->devices = supported_device;
3678 amdgpu_encoder->rmx_type = RMX_OFF;
3679 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3680 amdgpu_encoder->is_ext_encoder = false;
3681 amdgpu_encoder->caps = caps;
3682
3683 switch (amdgpu_encoder->encoder_id) {
3684 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3685 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3686 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3687 DRM_MODE_ENCODER_DAC, NULL);
3688 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3689 break;
3690 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3691 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3692 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3693 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3694 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3695 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3696 amdgpu_encoder->rmx_type = RMX_FULL;
3697 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3698 DRM_MODE_ENCODER_LVDS, NULL);
3699 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3700 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3701 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3702 DRM_MODE_ENCODER_DAC, NULL);
3703 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3704 } else {
3705 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3706 DRM_MODE_ENCODER_TMDS, NULL);
3707 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3708 }
3709 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3710 break;
3711 case ENCODER_OBJECT_ID_SI170B:
3712 case ENCODER_OBJECT_ID_CH7303:
3713 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3714 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3715 case ENCODER_OBJECT_ID_TITFP513:
3716 case ENCODER_OBJECT_ID_VT1623:
3717 case ENCODER_OBJECT_ID_HDMI_SI1930:
3718 case ENCODER_OBJECT_ID_TRAVIS:
3719 case ENCODER_OBJECT_ID_NUTMEG:
3720 /* these are handled by the primary encoders */
3721 amdgpu_encoder->is_ext_encoder = true;
3722 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3723 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3724 DRM_MODE_ENCODER_LVDS, NULL);
3725 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3726 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3727 DRM_MODE_ENCODER_DAC, NULL);
3728 else
3729 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3730 DRM_MODE_ENCODER_TMDS, NULL);
3731 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3732 break;
3733 }
3734 }
3735
3736 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3737 .bandwidth_update = &dce_v11_0_bandwidth_update,
3738 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3739 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3740 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3741 .hpd_sense = &dce_v11_0_hpd_sense,
3742 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3743 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3744 .page_flip = &dce_v11_0_page_flip,
3745 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3746 .add_encoder = &dce_v11_0_encoder_add,
3747 .add_connector = &amdgpu_connector_add,
3748 };
3749
dce_v11_0_set_display_funcs(struct amdgpu_device * adev)3750 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3751 {
3752 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3753 }
3754
3755 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3756 .set = dce_v11_0_set_crtc_irq_state,
3757 .process = dce_v11_0_crtc_irq,
3758 };
3759
3760 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3761 .set = dce_v11_0_set_pageflip_irq_state,
3762 .process = dce_v11_0_pageflip_irq,
3763 };
3764
3765 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3766 .set = dce_v11_0_set_hpd_irq_state,
3767 .process = dce_v11_0_hpd_irq,
3768 };
3769
dce_v11_0_set_irq_funcs(struct amdgpu_device * adev)3770 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3771 {
3772 if (adev->mode_info.num_crtc > 0)
3773 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3774 else
3775 adev->crtc_irq.num_types = 0;
3776 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3777
3778 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3779 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3780
3781 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3782 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3783 }
3784
3785 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3786 {
3787 .type = AMD_IP_BLOCK_TYPE_DCE,
3788 .major = 11,
3789 .minor = 0,
3790 .rev = 0,
3791 .funcs = &dce_v11_0_ip_funcs,
3792 };
3793
3794 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3795 {
3796 .type = AMD_IP_BLOCK_TYPE_DCE,
3797 .major = 11,
3798 .minor = 2,
3799 .rev = 0,
3800 .funcs = &dce_v11_0_ip_funcs,
3801 };
3802