1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v4_0.h"
26 #include "amdgpu_ras.h"
27
28 #include "hdp/hdp_4_0_offset.h"
29 #include "hdp/hdp_4_0_sh_mask.h"
30 #include <uapi/linux/kfd_ioctl.h>
31
32 /* for Vega20 register name change */
33 #define mmHDP_MEM_POWER_CTRL 0x00d4
34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39
hdp_v4_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 struct amdgpu_ring *ring)
42 {
43 if (!ring || !ring->funcs->emit_wreg) {
44 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 /* We just need to read back a register to post the write.
46 * Reading back the remapped register causes problems on
47 * some platforms so just read back the memory size register.
48 */
49 if (adev->nbio.funcs->get_memsize)
50 adev->nbio.funcs->get_memsize(adev);
51 } else {
52 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
53 }
54 }
55
hdp_v4_0_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)56 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
57 struct amdgpu_ring *ring)
58 {
59 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) ||
60 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
61 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
62 return;
63
64 if (!ring || !ring->funcs->emit_wreg) {
65 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
66 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
67 } else {
68 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
69 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
70 }
71 }
72
hdp_v4_0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)73 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
74 void *ras_error_status)
75 {
76 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
77
78 err_data->ue_count = 0;
79 err_data->ce_count = 0;
80
81 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
82 return;
83
84 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
85 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
86 };
87
hdp_v4_0_reset_ras_error_count(struct amdgpu_device * adev)88 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
89 {
90 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
91 return;
92
93 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0))
94 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
95 else
96 /*read back hdp ras counter to reset it to 0 */
97 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
98 }
99
hdp_v4_0_update_clock_gating(struct amdgpu_device * adev,bool enable)100 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
101 bool enable)
102 {
103 uint32_t def, data;
104
105 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) ||
106 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) ||
107 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) ||
108 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) {
109 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
110
111 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
112 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
113 else
114 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
115
116 if (def != data)
117 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
118 } else {
119 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
120
121 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
122 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
123 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
124 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
125 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
126 else
127 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
128 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
129 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
130 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
131
132 if (def != data)
133 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
134 }
135 }
136
hdp_v4_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)137 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
138 u64 *flags)
139 {
140 int data;
141
142 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||
143 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) {
144 /* Default enabled */
145 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
146 return;
147 }
148 /* AMD_CG_SUPPORT_HDP_LS */
149 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
150 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
151 *flags |= AMD_CG_SUPPORT_HDP_LS;
152 }
153
hdp_v4_0_init_registers(struct amdgpu_device * adev)154 static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
155 {
156 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
157 case IP_VERSION(4, 2, 1):
158 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
159 break;
160 default:
161 break;
162 }
163
164 /* Do not program registers if VF */
165 if (amdgpu_sriov_vf(adev))
166 return;
167
168 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
169
170 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
171 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
172
173 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
174 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
175 }
176
177 struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
178 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
179 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
180 };
181
182 struct amdgpu_hdp_ras hdp_v4_0_ras = {
183 .ras_block = {
184 .hw_ops = &hdp_v4_0_ras_hw_ops,
185 },
186 };
187
188 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
189 .flush_hdp = hdp_v4_0_flush_hdp,
190 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
191 .update_clock_gating = hdp_v4_0_update_clock_gating,
192 .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
193 .init_registers = hdp_v4_0_init_registers,
194 };
195