1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v5_0.h"
26
27 #include "hdp/hdp_5_0_0_offset.h"
28 #include "hdp/hdp_5_0_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
30
hdp_v5_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)31 static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33 {
34 if (!ring || !ring->funcs->emit_wreg) {
35 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
36 /* We just need to read back a register to post the write.
37 * Reading back the remapped register causes problems on
38 * some platforms so just read back the memory size register.
39 */
40 if (adev->nbio.funcs->get_memsize)
41 adev->nbio.funcs->get_memsize(adev);
42 } else {
43 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
44 }
45 }
46
hdp_v5_0_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)47 static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
48 struct amdgpu_ring *ring)
49 {
50 if (!ring || !ring->funcs->emit_wreg) {
51 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
52 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
53 } else {
54 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
55 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
56 }
57 }
58
hdp_v5_0_update_mem_power_gating(struct amdgpu_device * adev,bool enable)59 static void hdp_v5_0_update_mem_power_gating(struct amdgpu_device *adev,
60 bool enable)
61 {
62 uint32_t hdp_clk_cntl, hdp_clk_cntl1;
63 uint32_t hdp_mem_pwr_cntl;
64
65 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
66 AMD_CG_SUPPORT_HDP_DS |
67 AMD_CG_SUPPORT_HDP_SD)))
68 return;
69
70 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
71 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
72
73 /* Before doing clock/power mode switch,
74 * forced on IPH & RC clock */
75 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
76 IPH_MEM_CLK_SOFT_OVERRIDE, 1);
77 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
78 RC_MEM_CLK_SOFT_OVERRIDE, 1);
79 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
80
81 /* HDP 5.0 doesn't support dynamic power mode switch,
82 * disable clock and power gating before any changing */
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
84 IPH_MEM_POWER_CTRL_EN, 0);
85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
86 IPH_MEM_POWER_LS_EN, 0);
87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
88 IPH_MEM_POWER_DS_EN, 0);
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
90 IPH_MEM_POWER_SD_EN, 0);
91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
92 RC_MEM_POWER_CTRL_EN, 0);
93 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
94 RC_MEM_POWER_LS_EN, 0);
95 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
96 RC_MEM_POWER_DS_EN, 0);
97 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
98 RC_MEM_POWER_SD_EN, 0);
99 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
100
101 /* Already disabled above. The actions below are for "enabled" only */
102 if (enable) {
103 /* only one clock gating mode (LS/DS/SD) can be enabled */
104 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
105 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
106 HDP_MEM_POWER_CTRL,
107 IPH_MEM_POWER_LS_EN, 1);
108 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
109 HDP_MEM_POWER_CTRL,
110 RC_MEM_POWER_LS_EN, 1);
111 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
112 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
113 HDP_MEM_POWER_CTRL,
114 IPH_MEM_POWER_DS_EN, 1);
115 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
116 HDP_MEM_POWER_CTRL,
117 RC_MEM_POWER_DS_EN, 1);
118 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
119 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
120 HDP_MEM_POWER_CTRL,
121 IPH_MEM_POWER_SD_EN, 1);
122 /* RC should not use shut down mode, fallback to ds or ls if allowed */
123 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS)
124 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
125 HDP_MEM_POWER_CTRL,
126 RC_MEM_POWER_DS_EN, 1);
127 else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)
128 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
129 HDP_MEM_POWER_CTRL,
130 RC_MEM_POWER_LS_EN, 1);
131 }
132
133 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
134 * be set for SRAM LS/DS/SD */
135 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
136 AMD_CG_SUPPORT_HDP_SD)) {
137 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
138 IPH_MEM_POWER_CTRL_EN, 1);
139 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
140 RC_MEM_POWER_CTRL_EN, 1);
141 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
142 }
143 }
144
145 /* disable IPH & RC clock override after clock/power mode changing */
146 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
147 IPH_MEM_CLK_SOFT_OVERRIDE, 0);
148 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
149 RC_MEM_CLK_SOFT_OVERRIDE, 0);
150 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
151 }
152
hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)153 static void hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
154 bool enable)
155 {
156 uint32_t hdp_clk_cntl;
157
158 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
159 return;
160
161 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
162
163 if (enable) {
164 hdp_clk_cntl &=
165 ~(uint32_t)
166 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
167 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
168 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
169 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
170 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
171 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
172 } else {
173 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
174 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
175 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
176 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
177 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
178 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
179 }
180
181 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
182 }
183
hdp_v5_0_update_clock_gating(struct amdgpu_device * adev,bool enable)184 static void hdp_v5_0_update_clock_gating(struct amdgpu_device *adev,
185 bool enable)
186 {
187 hdp_v5_0_update_mem_power_gating(adev, enable);
188 hdp_v5_0_update_medium_grain_clock_gating(adev, enable);
189 }
190
hdp_v5_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)191 static void hdp_v5_0_get_clockgating_state(struct amdgpu_device *adev,
192 u64 *flags)
193 {
194 uint32_t tmp;
195
196 /* AMD_CG_SUPPORT_HDP_MGCG */
197 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
198 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
199 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
200 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
201 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
202 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
203 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
204 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
205
206 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
207 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
208 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
209 *flags |= AMD_CG_SUPPORT_HDP_LS;
210 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
211 *flags |= AMD_CG_SUPPORT_HDP_DS;
212 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
213 *flags |= AMD_CG_SUPPORT_HDP_SD;
214 }
215
hdp_v5_0_init_registers(struct amdgpu_device * adev)216 static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
217 {
218 u32 tmp;
219
220 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
221 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
222 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
223 }
224
225 const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
226 .flush_hdp = hdp_v5_0_flush_hdp,
227 .invalidate_hdp = hdp_v5_0_invalidate_hdp,
228 .update_clock_gating = hdp_v5_0_update_clock_gating,
229 .get_clock_gating_state = hdp_v5_0_get_clockgating_state,
230 .init_registers = hdp_v5_0_init_registers,
231 };
232