1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v5_2.h"
26
27 #include "hdp/hdp_5_2_1_offset.h"
28 #include "hdp/hdp_5_2_1_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
30
hdp_v5_2_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)31 static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33 {
34 if (!ring || !ring->funcs->emit_wreg) {
35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
36 0);
37 if (amdgpu_sriov_vf(adev)) {
38 /* this is fine because SR_IOV doesn't remap the register */
39 RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
40 } else {
41 /* We just need to read back a register to post the write.
42 * Reading back the remapped register causes problems on
43 * some platforms so just read back the memory size register.
44 */
45 if (adev->nbio.funcs->get_memsize)
46 adev->nbio.funcs->get_memsize(adev);
47 }
48 } else {
49 amdgpu_ring_emit_wreg(ring,
50 (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
51 0);
52 }
53 }
54
hdp_v5_2_update_mem_power_gating(struct amdgpu_device * adev,bool enable)55 static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,
56 bool enable)
57 {
58 uint32_t hdp_clk_cntl;
59 uint32_t hdp_mem_pwr_cntl;
60
61 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
62 AMD_CG_SUPPORT_HDP_DS |
63 AMD_CG_SUPPORT_HDP_SD)))
64 return;
65
66 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
67 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
68
69 /* Before doing clock/power mode switch, forced on MEM clock */
70 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
71 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 1);
72 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
73 RC_MEM_CLK_SOFT_OVERRIDE, 1);
74 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
75
76 /* disable clock and power gating before any changing */
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
78 ATOMIC_MEM_POWER_CTRL_EN, 0);
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
80 ATOMIC_MEM_POWER_LS_EN, 0);
81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
82 ATOMIC_MEM_POWER_DS_EN, 0);
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
84 ATOMIC_MEM_POWER_SD_EN, 0);
85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
86 RC_MEM_POWER_CTRL_EN, 0);
87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
88 RC_MEM_POWER_LS_EN, 0);
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
90 RC_MEM_POWER_DS_EN, 0);
91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
92 RC_MEM_POWER_SD_EN, 0);
93 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
94
95 /* Already disabled above. The actions below are for "enabled" only */
96 if (enable) {
97 /* only one clock gating mode (LS/DS/SD) can be enabled */
98 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
100 HDP_MEM_POWER_CTRL,
101 ATOMIC_MEM_POWER_SD_EN, 1);
102 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
103 HDP_MEM_POWER_CTRL,
104 RC_MEM_POWER_SD_EN, 1);
105 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
107 HDP_MEM_POWER_CTRL,
108 ATOMIC_MEM_POWER_LS_EN, 1);
109 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
110 HDP_MEM_POWER_CTRL,
111 RC_MEM_POWER_LS_EN, 1);
112 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
114 HDP_MEM_POWER_CTRL,
115 ATOMIC_MEM_POWER_DS_EN, 1);
116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
117 HDP_MEM_POWER_CTRL,
118 RC_MEM_POWER_DS_EN, 1);
119 }
120
121 /* confirmed that ATOMIC/RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD */
122 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
123 AMD_CG_SUPPORT_HDP_SD)) {
124 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
125 ATOMIC_MEM_POWER_CTRL_EN, 1);
126 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
127 RC_MEM_POWER_CTRL_EN, 1);
128 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
129 }
130 }
131
132 /* disable MEM clock override after clock/power mode changing */
133 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
134 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 0);
135 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
136 RC_MEM_CLK_SOFT_OVERRIDE, 0);
137 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
138 }
139
hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)140 static void hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
141 bool enable)
142 {
143 uint32_t hdp_clk_cntl;
144
145 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
146 return;
147
148 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
149
150 if (enable) {
151 hdp_clk_cntl &=
152 ~(uint32_t)
153 (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
154 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
155 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
156 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
157 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
158 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
159 } else {
160 hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
161 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
162 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
163 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
164 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
165 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
166 }
167
168 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
169 }
170
hdp_v5_2_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)171 static void hdp_v5_2_get_clockgating_state(struct amdgpu_device *adev,
172 u64 *flags)
173 {
174 uint32_t tmp;
175
176 /* AMD_CG_SUPPORT_HDP_MGCG */
177 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
178 if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
179 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
180 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
181 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
182 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
183 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
184 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
185
186 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
187 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
188 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
189 *flags |= AMD_CG_SUPPORT_HDP_LS;
190 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
191 *flags |= AMD_CG_SUPPORT_HDP_DS;
192 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
193 *flags |= AMD_CG_SUPPORT_HDP_SD;
194 }
195
hdp_v5_2_update_clock_gating(struct amdgpu_device * adev,bool enable)196 static void hdp_v5_2_update_clock_gating(struct amdgpu_device *adev,
197 bool enable)
198 {
199 hdp_v5_2_update_mem_power_gating(adev, enable);
200 hdp_v5_2_update_medium_grain_clock_gating(adev, enable);
201 }
202
203 const struct amdgpu_hdp_funcs hdp_v5_2_funcs = {
204 .flush_hdp = hdp_v5_2_flush_hdp,
205 .update_clock_gating = hdp_v5_2_update_clock_gating,
206 .get_clock_gating_state = hdp_v5_2_get_clockgating_state,
207 };
208