1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v6_0.h"
26
27 #include "hdp/hdp_6_0_0_offset.h"
28 #include "hdp/hdp_6_0_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
30
31 #define regHDP_CLK_CNTL_V6_1 0xd5
32 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
33
hdp_v6_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)34 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
35 struct amdgpu_ring *ring)
36 {
37 if (!ring || !ring->funcs->emit_wreg) {
38 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
39 /* We just need to read back a register to post the write.
40 * Reading back the remapped register causes problems on
41 * some platforms so just read back the memory size register.
42 */
43 if (adev->nbio.funcs->get_memsize)
44 adev->nbio.funcs->get_memsize(adev);
45 } else {
46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
47 }
48 }
49
hdp_v6_0_update_clock_gating(struct amdgpu_device * adev,bool enable)50 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
51 bool enable)
52 {
53 uint32_t hdp_clk_cntl;
54 uint32_t hdp_mem_pwr_cntl;
55
56 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
57 AMD_CG_SUPPORT_HDP_DS |
58 AMD_CG_SUPPORT_HDP_SD)))
59 return;
60
61 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
62 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
63 else
64 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
65 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
66
67 /* Before doing clock/power mode switch,
68 * forced on IPH & RC clock */
69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
70 RC_MEM_CLK_SOFT_OVERRIDE, 1);
71 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
72 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
73 else
74 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
75
76 /* disable clock and power gating before any changing */
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
78 ATOMIC_MEM_POWER_CTRL_EN, 0);
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
80 ATOMIC_MEM_POWER_LS_EN, 0);
81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
82 ATOMIC_MEM_POWER_DS_EN, 0);
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
84 ATOMIC_MEM_POWER_SD_EN, 0);
85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
86 RC_MEM_POWER_CTRL_EN, 0);
87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
88 RC_MEM_POWER_LS_EN, 0);
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
90 RC_MEM_POWER_DS_EN, 0);
91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
92 RC_MEM_POWER_SD_EN, 0);
93 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
94
95 /* Already disabled above. The actions below are for "enabled" only */
96 if (enable) {
97 /* only one clock gating mode (LS/DS/SD) can be enabled */
98 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
100 HDP_MEM_POWER_CTRL,
101 ATOMIC_MEM_POWER_SD_EN, 1);
102 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
103 HDP_MEM_POWER_CTRL,
104 RC_MEM_POWER_SD_EN, 1);
105 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
107 HDP_MEM_POWER_CTRL,
108 ATOMIC_MEM_POWER_LS_EN, 1);
109 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
110 HDP_MEM_POWER_CTRL,
111 RC_MEM_POWER_LS_EN, 1);
112 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
114 HDP_MEM_POWER_CTRL,
115 ATOMIC_MEM_POWER_DS_EN, 1);
116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
117 HDP_MEM_POWER_CTRL,
118 RC_MEM_POWER_DS_EN, 1);
119 }
120
121 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
122 * be set for SRAM LS/DS/SD */
123 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
124 AMD_CG_SUPPORT_HDP_SD)) {
125 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
126 ATOMIC_MEM_POWER_CTRL_EN, 1);
127 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
128 RC_MEM_POWER_CTRL_EN, 1);
129 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
130 }
131 }
132
133 /* disable IPH & RC clock override after clock/power mode changing */
134 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
135 RC_MEM_CLK_SOFT_OVERRIDE, 0);
136 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
137 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
138 else
139 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
140 }
141
hdp_v6_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)142 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
143 u64 *flags)
144 {
145 uint32_t tmp;
146
147 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
148 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
149 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
150 *flags |= AMD_CG_SUPPORT_HDP_LS;
151 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
152 *flags |= AMD_CG_SUPPORT_HDP_DS;
153 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
154 *flags |= AMD_CG_SUPPORT_HDP_SD;
155 }
156
157 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
158 .flush_hdp = hdp_v6_0_flush_hdp,
159 .update_clock_gating = hdp_v6_0_update_clock_gating,
160 .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
161 };
162