1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "hdp_v7_0.h"
26
27 #include "hdp/hdp_7_0_0_offset.h"
28 #include "hdp/hdp_7_0_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
30
hdp_v7_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)31 static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33 {
34 if (!ring || !ring->funcs->emit_wreg) {
35 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
36 /* We just need to read back a register to post the write.
37 * Reading back the remapped register causes problems on
38 * some platforms so just read back the memory size register.
39 */
40 if (adev->nbio.funcs->get_memsize)
41 adev->nbio.funcs->get_memsize(adev);
42 } else {
43 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
44 }
45 }
46
hdp_v7_0_update_clock_gating(struct amdgpu_device * adev,bool enable)47 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
48 bool enable)
49 {
50 uint32_t hdp_clk_cntl, hdp_clk_cntl1;
51 uint32_t hdp_mem_pwr_cntl;
52
53 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
54 AMD_CG_SUPPORT_HDP_DS |
55 AMD_CG_SUPPORT_HDP_SD)))
56 return;
57
58 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
59 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
60
61 /* Before doing clock/power mode switch,
62 * forced on IPH & RC clock */
63 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
64 RC_MEM_CLK_SOFT_OVERRIDE, 1);
65 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
66
67 /* disable clock and power gating before any changing */
68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
69 ATOMIC_MEM_POWER_CTRL_EN, 0);
70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
71 ATOMIC_MEM_POWER_LS_EN, 0);
72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
73 ATOMIC_MEM_POWER_DS_EN, 0);
74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
75 ATOMIC_MEM_POWER_SD_EN, 0);
76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
77 RC_MEM_POWER_CTRL_EN, 0);
78 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
79 RC_MEM_POWER_LS_EN, 0);
80 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
81 RC_MEM_POWER_DS_EN, 0);
82 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
83 RC_MEM_POWER_SD_EN, 0);
84 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
85
86 /* Already disabled above. The actions below are for "enabled" only */
87 if (enable) {
88 /* only one clock gating mode (LS/DS/SD) can be enabled */
89 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
90 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
91 HDP_MEM_POWER_CTRL,
92 ATOMIC_MEM_POWER_SD_EN, 1);
93 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
94 HDP_MEM_POWER_CTRL,
95 RC_MEM_POWER_SD_EN, 1);
96 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
97 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
98 HDP_MEM_POWER_CTRL,
99 ATOMIC_MEM_POWER_LS_EN, 1);
100 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
101 HDP_MEM_POWER_CTRL,
102 RC_MEM_POWER_LS_EN, 1);
103 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
104 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
105 HDP_MEM_POWER_CTRL,
106 ATOMIC_MEM_POWER_DS_EN, 1);
107 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
108 HDP_MEM_POWER_CTRL,
109 RC_MEM_POWER_DS_EN, 1);
110 }
111
112 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
113 * be set for SRAM LS/DS/SD */
114 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
115 AMD_CG_SUPPORT_HDP_SD)) {
116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
117 ATOMIC_MEM_POWER_CTRL_EN, 1);
118 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
119 RC_MEM_POWER_CTRL_EN, 1);
120 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
121 }
122 }
123
124 /* disable IPH & RC clock override after clock/power mode changing */
125 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
126 RC_MEM_CLK_SOFT_OVERRIDE, 0);
127 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
128 }
129
hdp_v7_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)130 static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
131 u64 *flags)
132 {
133 uint32_t tmp;
134
135 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
136 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
137 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
138 *flags |= AMD_CG_SUPPORT_HDP_LS;
139 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
140 *flags |= AMD_CG_SUPPORT_HDP_DS;
141 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
142 *flags |= AMD_CG_SUPPORT_HDP_SD;
143 }
144
145 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
146 .flush_hdp = hdp_v7_0_flush_hdp,
147 .update_clock_gating = hdp_v7_0_update_clock_gating,
148 .get_clock_gating_state = hdp_v7_0_get_clockgating_state,
149 };
150