1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "amdgpu_jpeg.h"
26 #include "soc15.h"
27 #include "soc15d.h"
28 #include "jpeg_v2_0.h"
29 #include "jpeg_v4_0_3.h"
30 #include "mmsch_v4_0_3.h"
31
32 #include "vcn/vcn_4_0_3_offset.h"
33 #include "vcn/vcn_4_0_3_sh_mask.h"
34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
35
36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \
37 (offset & 0x1FFFF)
38
39 enum jpeg_engin_status {
40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2,
42 };
43
44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
46 static int jpeg_v4_0_3_set_powergating_state(void *handle,
47 enum amd_powergating_state state);
48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
50
51 static int amdgpu_ih_srcid_jpeg[] = {
52 VCN_4_0__SRCID__JPEG_DECODE,
53 VCN_4_0__SRCID__JPEG1_DECODE,
54 VCN_4_0__SRCID__JPEG2_DECODE,
55 VCN_4_0__SRCID__JPEG3_DECODE,
56 VCN_4_0__SRCID__JPEG4_DECODE,
57 VCN_4_0__SRCID__JPEG5_DECODE,
58 VCN_4_0__SRCID__JPEG6_DECODE,
59 VCN_4_0__SRCID__JPEG7_DECODE
60 };
61
jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device * adev)62 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
63 {
64 return amdgpu_sriov_vf(adev) ||
65 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4));
66 }
67
68 /**
69 * jpeg_v4_0_3_early_init - set function pointers
70 *
71 * @handle: amdgpu_device pointer
72 *
73 * Set ring and irq function pointers
74 */
jpeg_v4_0_3_early_init(void * handle)75 static int jpeg_v4_0_3_early_init(void *handle)
76 {
77 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
78
79 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;
80
81 jpeg_v4_0_3_set_dec_ring_funcs(adev);
82 jpeg_v4_0_3_set_irq_funcs(adev);
83 jpeg_v4_0_3_set_ras_funcs(adev);
84
85 return 0;
86 }
87
88 /**
89 * jpeg_v4_0_3_sw_init - sw init for JPEG block
90 *
91 * @handle: amdgpu_device pointer
92 *
93 * Load firmware and sw initialization
94 */
jpeg_v4_0_3_sw_init(void * handle)95 static int jpeg_v4_0_3_sw_init(void *handle)
96 {
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
98 struct amdgpu_ring *ring;
99 int i, j, r, jpeg_inst;
100
101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
102 /* JPEG TRAP */
103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
104 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
105 if (r)
106 return r;
107 }
108
109 r = amdgpu_jpeg_sw_init(adev);
110 if (r)
111 return r;
112
113 r = amdgpu_jpeg_resume(adev);
114 if (r)
115 return r;
116
117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
118 jpeg_inst = GET_INST(JPEG, i);
119
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
121 ring = &adev->jpeg.inst[i].ring_dec[j];
122 ring->use_doorbell = true;
123 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
124 if (!amdgpu_sriov_vf(adev)) {
125 ring->doorbell_index =
126 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
127 1 + j + 9 * jpeg_inst;
128 } else {
129 if (j < 4)
130 ring->doorbell_index =
131 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
132 4 + j + 32 * jpeg_inst;
133 else
134 ring->doorbell_index =
135 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
136 8 + j + 32 * jpeg_inst;
137 }
138 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
139 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
140 AMDGPU_RING_PRIO_DEFAULT, NULL);
141 if (r)
142 return r;
143
144 adev->jpeg.internal.jpeg_pitch[j] =
145 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
146 adev->jpeg.inst[i].external.jpeg_pitch[j] =
147 SOC15_REG_OFFSET1(
148 JPEG, jpeg_inst,
149 regUVD_JRBC0_UVD_JRBC_SCRATCH0,
150 (j ? (0x40 * j - 0xc80) : 0));
151 }
152 }
153
154 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
155 r = amdgpu_jpeg_ras_sw_init(adev);
156 if (r) {
157 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n");
158 return r;
159 }
160 }
161
162 return 0;
163 }
164
165 /**
166 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block
167 *
168 * @handle: amdgpu_device pointer
169 *
170 * JPEG suspend and free up sw allocation
171 */
jpeg_v4_0_3_sw_fini(void * handle)172 static int jpeg_v4_0_3_sw_fini(void *handle)
173 {
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175 int r;
176
177 r = amdgpu_jpeg_suspend(adev);
178 if (r)
179 return r;
180
181 r = amdgpu_jpeg_sw_fini(adev);
182
183 return r;
184 }
185
jpeg_v4_0_3_start_sriov(struct amdgpu_device * adev)186 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev)
187 {
188 struct amdgpu_ring *ring;
189 uint64_t ctx_addr;
190 uint32_t param, resp, expected;
191 uint32_t tmp, timeout;
192
193 struct amdgpu_mm_table *table = &adev->virt.mm_table;
194 uint32_t *table_loc;
195 uint32_t table_size;
196 uint32_t size, size_dw, item_offset;
197 uint32_t init_status;
198 int i, j, jpeg_inst;
199
200 struct mmsch_v4_0_cmd_direct_write
201 direct_wt = { {0} };
202 struct mmsch_v4_0_cmd_end end = { {0} };
203 struct mmsch_v4_0_3_init_header header;
204
205 direct_wt.cmd_header.command_type =
206 MMSCH_COMMAND__DIRECT_REG_WRITE;
207 end.cmd_header.command_type =
208 MMSCH_COMMAND__END;
209
210 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
211 jpeg_inst = GET_INST(JPEG, i);
212
213 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
214 header.version = MMSCH_VERSION;
215 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
216
217 table_loc = (uint32_t *)table->cpu_addr;
218 table_loc += header.total_size;
219
220 item_offset = header.total_size;
221
222 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) {
223 ring = &adev->jpeg.inst[i].ring_dec[j];
224 table_size = 0;
225
226 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
227 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
228 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
229 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));
230 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE);
231 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
232
233 if (j <= 3) {
234 header.mjpegdec0[j].table_offset = item_offset;
235 header.mjpegdec0[j].init_status = 0;
236 header.mjpegdec0[j].table_size = table_size;
237 } else {
238 header.mjpegdec1[j - 4].table_offset = item_offset;
239 header.mjpegdec1[j - 4].init_status = 0;
240 header.mjpegdec1[j - 4].table_size = table_size;
241 }
242 header.total_size += table_size;
243 item_offset += table_size;
244 }
245
246 MMSCH_V4_0_INSERT_END();
247
248 /* send init table to MMSCH */
249 size = sizeof(struct mmsch_v4_0_3_init_header);
250 table_loc = (uint32_t *)table->cpu_addr;
251 memcpy((void *)table_loc, &header, size);
252
253 ctx_addr = table->gpu_addr;
254 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
256
257 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
258 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
259 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
260 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);
261
262 size = header.total_size;
263 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size);
264
265 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0);
266
267 param = 0x00000001;
268 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param);
269 tmp = 0;
270 timeout = 1000;
271 resp = 0;
272 expected = MMSCH_VF_MAILBOX_RESP__OK;
273 init_status =
274 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status;
275 while (resp != expected) {
276 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);
277
278 if (resp != 0)
279 break;
280 udelay(10);
281 tmp = tmp + 10;
282 if (tmp >= timeout) {
283 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
284 " waiting for regMMSCH_VF_MAILBOX_RESP "\
285 "(expected=0x%08x, readback=0x%08x)\n",
286 tmp, expected, resp);
287 return -EBUSY;
288 }
289 }
290 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE &&
291 init_status != MMSCH_VF_ENGINE_STATUS__PASS)
292 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n",
293 resp, init_status);
294
295 }
296 return 0;
297 }
298
299 /**
300 * jpeg_v4_0_3_hw_init - start and test JPEG block
301 *
302 * @handle: amdgpu_device pointer
303 *
304 */
jpeg_v4_0_3_hw_init(void * handle)305 static int jpeg_v4_0_3_hw_init(void *handle)
306 {
307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
308 struct amdgpu_ring *ring;
309 int i, j, r, jpeg_inst;
310
311 if (amdgpu_sriov_vf(adev)) {
312 r = jpeg_v4_0_3_start_sriov(adev);
313 if (r)
314 return r;
315
316 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
317 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
318 ring = &adev->jpeg.inst[i].ring_dec[j];
319 ring->wptr = 0;
320 ring->wptr_old = 0;
321 jpeg_v4_0_3_dec_ring_set_wptr(ring);
322 ring->sched.ready = true;
323 }
324 }
325 } else {
326 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
327 jpeg_inst = GET_INST(JPEG, i);
328
329 ring = adev->jpeg.inst[i].ring_dec;
330
331 if (ring->use_doorbell)
332 adev->nbio.funcs->vcn_doorbell_range(
333 adev, ring->use_doorbell,
334 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
335 9 * jpeg_inst,
336 adev->jpeg.inst[i].aid_id);
337
338 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
339 ring = &adev->jpeg.inst[i].ring_dec[j];
340 if (ring->use_doorbell)
341 WREG32_SOC15_OFFSET(
342 VCN, GET_INST(VCN, i),
343 regVCN_JPEG_DB_CTRL,
344 (ring->pipe ? (ring->pipe - 0x15) : 0),
345 ring->doorbell_index
346 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
347 VCN_JPEG_DB_CTRL__EN_MASK);
348 r = amdgpu_ring_test_helper(ring);
349 if (r)
350 return r;
351 }
352 }
353 }
354
355 return 0;
356 }
357
358 /**
359 * jpeg_v4_0_3_hw_fini - stop the hardware block
360 *
361 * @handle: amdgpu_device pointer
362 *
363 * Stop the JPEG block, mark ring as not ready any more
364 */
jpeg_v4_0_3_hw_fini(void * handle)365 static int jpeg_v4_0_3_hw_fini(void *handle)
366 {
367 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
368 int ret = 0;
369
370 cancel_delayed_work_sync(&adev->jpeg.idle_work);
371
372 if (!amdgpu_sriov_vf(adev)) {
373 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
374 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
375 }
376
377 return ret;
378 }
379
380 /**
381 * jpeg_v4_0_3_suspend - suspend JPEG block
382 *
383 * @handle: amdgpu_device pointer
384 *
385 * HW fini and suspend JPEG block
386 */
jpeg_v4_0_3_suspend(void * handle)387 static int jpeg_v4_0_3_suspend(void *handle)
388 {
389 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
390 int r;
391
392 r = jpeg_v4_0_3_hw_fini(adev);
393 if (r)
394 return r;
395
396 r = amdgpu_jpeg_suspend(adev);
397
398 return r;
399 }
400
401 /**
402 * jpeg_v4_0_3_resume - resume JPEG block
403 *
404 * @handle: amdgpu_device pointer
405 *
406 * Resume firmware and hw init JPEG block
407 */
jpeg_v4_0_3_resume(void * handle)408 static int jpeg_v4_0_3_resume(void *handle)
409 {
410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
411 int r;
412
413 r = amdgpu_jpeg_resume(adev);
414 if (r)
415 return r;
416
417 r = jpeg_v4_0_3_hw_init(adev);
418
419 return r;
420 }
421
jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device * adev,int inst_idx)422 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
423 {
424 int i, jpeg_inst;
425 uint32_t data;
426
427 jpeg_inst = GET_INST(JPEG, inst_idx);
428 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);
429 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
430 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
431 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1));
432 } else {
433 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
434 }
435
436 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
437 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
438 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);
439
440 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);
441 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
442 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
443 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
444 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);
445 }
446
jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device * adev,int inst_idx)447 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
448 {
449 int i, jpeg_inst;
450 uint32_t data;
451
452 jpeg_inst = GET_INST(JPEG, inst_idx);
453 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);
454 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
455 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
456 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1);
457 } else {
458 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
459 }
460
461 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
462 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
463 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);
464
465 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);
466 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
467 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
468 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
469 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);
470 }
471
472 /**
473 * jpeg_v4_0_3_start - start JPEG block
474 *
475 * @adev: amdgpu_device pointer
476 *
477 * Setup and start the JPEG block
478 */
jpeg_v4_0_3_start(struct amdgpu_device * adev)479 static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
480 {
481 struct amdgpu_ring *ring;
482 int i, j, jpeg_inst;
483
484 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
485 jpeg_inst = GET_INST(JPEG, i);
486
487 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,
488 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
489 SOC15_WAIT_ON_RREG(
490 JPEG, jpeg_inst, regUVD_PGFSM_STATUS,
491 UVD_PGFSM_STATUS__UVDJ_PWR_ON
492 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
493 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
494
495 /* disable anti hang mechanism */
496 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
497 regUVD_JPEG_POWER_STATUS),
498 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
499
500 /* JPEG disable CGC */
501 jpeg_v4_0_3_disable_clock_gating(adev, i);
502
503 /* MJPEG global tiling registers */
504 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG,
505 adev->gfx.config.gb_addr_config);
506 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG,
507 adev->gfx.config.gb_addr_config);
508
509 /* enable JMI channel */
510 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,
511 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
512
513 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
514 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
515
516 ring = &adev->jpeg.inst[i].ring_dec[j];
517
518 /* enable System Interrupt for JRBC */
519 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
520 regJPEG_SYS_INT_EN),
521 JPEG_SYS_INT_EN__DJRBC0_MASK << j,
522 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j));
523
524 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
525 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID,
526 reg_offset, 0);
527 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
528 regUVD_JRBC0_UVD_JRBC_RB_CNTL,
529 reg_offset,
530 (0x00000001L | 0x00000002L));
531 WREG32_SOC15_OFFSET(
532 JPEG, jpeg_inst,
533 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,
534 reg_offset, lower_32_bits(ring->gpu_addr));
535 WREG32_SOC15_OFFSET(
536 JPEG, jpeg_inst,
537 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
538 reg_offset, upper_32_bits(ring->gpu_addr));
539 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
540 regUVD_JRBC0_UVD_JRBC_RB_RPTR,
541 reg_offset, 0);
542 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
543 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
544 reg_offset, 0);
545 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
546 regUVD_JRBC0_UVD_JRBC_RB_CNTL,
547 reg_offset, 0x00000002L);
548 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
549 regUVD_JRBC0_UVD_JRBC_RB_SIZE,
550 reg_offset, ring->ring_size / 4);
551 ring->wptr = RREG32_SOC15_OFFSET(
552 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR,
553 reg_offset);
554 }
555 }
556
557 return 0;
558 }
559
560 /**
561 * jpeg_v4_0_3_stop - stop JPEG block
562 *
563 * @adev: amdgpu_device pointer
564 *
565 * stop the JPEG block
566 */
jpeg_v4_0_3_stop(struct amdgpu_device * adev)567 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev)
568 {
569 int i, jpeg_inst;
570
571 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
572 jpeg_inst = GET_INST(JPEG, i);
573 /* reset JMI */
574 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),
575 UVD_JMI_CNTL__SOFT_RESET_MASK,
576 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
577
578 jpeg_v4_0_3_enable_clock_gating(adev, i);
579
580 /* enable anti hang mechanism */
581 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
582 regUVD_JPEG_POWER_STATUS),
583 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
584 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
585
586 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,
587 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
588 SOC15_WAIT_ON_RREG(
589 JPEG, jpeg_inst, regUVD_PGFSM_STATUS,
590 UVD_PGFSM_STATUS__UVDJ_PWR_OFF
591 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
592 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
593 }
594
595 return 0;
596 }
597
598 /**
599 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer
600 *
601 * @ring: amdgpu_ring pointer
602 *
603 * Returns the current hardware read pointer
604 */
jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring * ring)605 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring)
606 {
607 struct amdgpu_device *adev = ring->adev;
608
609 return RREG32_SOC15_OFFSET(
610 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,
611 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
612 }
613
614 /**
615 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer
616 *
617 * @ring: amdgpu_ring pointer
618 *
619 * Returns the current hardware write pointer
620 */
jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring * ring)621 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring)
622 {
623 struct amdgpu_device *adev = ring->adev;
624
625 if (ring->use_doorbell)
626 return adev->wb.wb[ring->wptr_offs];
627 else
628 return RREG32_SOC15_OFFSET(
629 JPEG, GET_INST(JPEG, ring->me),
630 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
631 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
632 }
633
jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring * ring)634 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
635 {
636 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled.
637 * This is a workaround to avoid any HDP flush through JPEG ring.
638 */
639 }
640
641 /**
642 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer
643 *
644 * @ring: amdgpu_ring pointer
645 *
646 * Commits the write pointer to the hardware
647 */
jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring * ring)648 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)
649 {
650 struct amdgpu_device *adev = ring->adev;
651
652 if (ring->use_doorbell) {
653 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
654 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
655 } else {
656 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),
657 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
658 (ring->pipe ? (0x40 * ring->pipe - 0xc80) :
659 0),
660 lower_32_bits(ring->wptr));
661 }
662 }
663
664 /**
665 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command
666 *
667 * @ring: amdgpu_ring pointer
668 *
669 * Write a start command to the ring.
670 */
jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring * ring)671 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
672 {
673 if (!amdgpu_sriov_vf(ring->adev)) {
674 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
675 0, 0, PACKETJ_TYPE0));
676 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
677
678 amdgpu_ring_write(ring,
679 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
680 0, PACKETJ_TYPE0));
681 amdgpu_ring_write(ring, 0x80004000);
682 }
683 }
684
685 /**
686 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command
687 *
688 * @ring: amdgpu_ring pointer
689 *
690 * Write a end command to the ring.
691 */
jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring * ring)692 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)
693 {
694 if (!amdgpu_sriov_vf(ring->adev)) {
695 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
696 0, 0, PACKETJ_TYPE0));
697 amdgpu_ring_write(ring, 0x62a04);
698
699 amdgpu_ring_write(ring,
700 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
701 0, PACKETJ_TYPE0));
702 amdgpu_ring_write(ring, 0x00004000);
703 }
704 }
705
706 /**
707 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command
708 *
709 * @ring: amdgpu_ring pointer
710 * @addr: address
711 * @seq: sequence number
712 * @flags: fence related flags
713 *
714 * Write a fence and a trap command to the ring.
715 */
jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)716 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
717 unsigned int flags)
718 {
719 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
720
721 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
722 0, 0, PACKETJ_TYPE0));
723 amdgpu_ring_write(ring, seq);
724
725 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
726 0, 0, PACKETJ_TYPE0));
727 amdgpu_ring_write(ring, seq);
728
729 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
730 0, 0, PACKETJ_TYPE0));
731 amdgpu_ring_write(ring, lower_32_bits(addr));
732
733 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
734 0, 0, PACKETJ_TYPE0));
735 amdgpu_ring_write(ring, upper_32_bits(addr));
736
737 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
738 0, 0, PACKETJ_TYPE0));
739 amdgpu_ring_write(ring, 0x8);
740
741 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
742 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
743 amdgpu_ring_write(ring, 0);
744
745 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
746 amdgpu_ring_write(ring, 0);
747
748 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
749 0, 0, PACKETJ_TYPE0));
750 amdgpu_ring_write(ring, 0x3fbc);
751
752 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
753 0, 0, PACKETJ_TYPE0));
754 amdgpu_ring_write(ring, 0x1);
755
756 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
757 amdgpu_ring_write(ring, 0);
758
759 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
760 amdgpu_ring_write(ring, 0);
761 }
762
763 /**
764 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer
765 *
766 * @ring: amdgpu_ring pointer
767 * @job: job to retrieve vmid from
768 * @ib: indirect buffer to execute
769 * @flags: unused
770 *
771 * Write ring commands to execute the indirect buffer.
772 */
jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)773 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
774 struct amdgpu_job *job,
775 struct amdgpu_ib *ib,
776 uint32_t flags)
777 {
778 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
779
780 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
781 0, 0, PACKETJ_TYPE0));
782
783 if (ring->funcs->parse_cs)
784 amdgpu_ring_write(ring, 0);
785 else
786 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
787
788 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
789 0, 0, PACKETJ_TYPE0));
790 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
791
792 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
793 0, 0, PACKETJ_TYPE0));
794 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
795
796 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
797 0, 0, PACKETJ_TYPE0));
798 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
799
800 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
801 0, 0, PACKETJ_TYPE0));
802 amdgpu_ring_write(ring, ib->length_dw);
803
804 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
805 0, 0, PACKETJ_TYPE0));
806 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
807
808 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
809 0, 0, PACKETJ_TYPE0));
810 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
811
812 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
813 amdgpu_ring_write(ring, 0);
814
815 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
816 0, 0, PACKETJ_TYPE0));
817 amdgpu_ring_write(ring, 0x01400200);
818
819 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
820 0, 0, PACKETJ_TYPE0));
821 amdgpu_ring_write(ring, 0x2);
822
823 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET,
824 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
825 amdgpu_ring_write(ring, 0x2);
826 }
827
jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)828 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
829 uint32_t val, uint32_t mask)
830 {
831 uint32_t reg_offset;
832
833 /* Use normalized offsets if required */
834 if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
835 reg = NORMALIZE_JPEG_REG_OFFSET(reg);
836
837 reg_offset = (reg << 2);
838
839 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
840 0, 0, PACKETJ_TYPE0));
841 amdgpu_ring_write(ring, 0x01400200);
842
843 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
844 0, 0, PACKETJ_TYPE0));
845 amdgpu_ring_write(ring, val);
846
847 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
848 0, 0, PACKETJ_TYPE0));
849 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
850 amdgpu_ring_write(ring, 0);
851 amdgpu_ring_write(ring,
852 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
853 } else {
854 amdgpu_ring_write(ring, reg_offset);
855 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
856 0, 0, PACKETJ_TYPE3));
857 }
858 amdgpu_ring_write(ring, mask);
859 }
860
jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)861 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
862 unsigned int vmid, uint64_t pd_addr)
863 {
864 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
865 uint32_t data0, data1, mask;
866
867 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
868
869 /* wait for register write */
870 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
871 data1 = lower_32_bits(pd_addr);
872 mask = 0xffffffff;
873 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask);
874 }
875
jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)876 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
877 {
878 uint32_t reg_offset;
879
880 /* Use normalized offsets if required */
881 if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
882 reg = NORMALIZE_JPEG_REG_OFFSET(reg);
883
884 reg_offset = (reg << 2);
885
886 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
887 0, 0, PACKETJ_TYPE0));
888 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
889 amdgpu_ring_write(ring, 0);
890 amdgpu_ring_write(ring,
891 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
892 } else {
893 amdgpu_ring_write(ring, reg_offset);
894 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
895 0, 0, PACKETJ_TYPE0));
896 }
897 amdgpu_ring_write(ring, val);
898 }
899
jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring * ring,uint32_t count)900 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
901 {
902 int i;
903
904 WARN_ON(ring->wptr % 2 || count % 2);
905
906 for (i = 0; i < count / 2; i++) {
907 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
908 amdgpu_ring_write(ring, 0);
909 }
910 }
911
jpeg_v4_0_3_is_idle(void * handle)912 static bool jpeg_v4_0_3_is_idle(void *handle)
913 {
914 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
915 bool ret = false;
916 int i, j;
917
918 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
919 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
920 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
921
922 ret &= ((RREG32_SOC15_OFFSET(
923 JPEG, GET_INST(JPEG, i),
924 regUVD_JRBC0_UVD_JRBC_STATUS,
925 reg_offset) &
926 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
927 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
928 }
929 }
930
931 return ret;
932 }
933
jpeg_v4_0_3_wait_for_idle(void * handle)934 static int jpeg_v4_0_3_wait_for_idle(void *handle)
935 {
936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
937 int ret = 0;
938 int i, j;
939
940 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
941 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
942 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
943
944 ret &= SOC15_WAIT_ON_RREG_OFFSET(
945 JPEG, GET_INST(JPEG, i),
946 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,
947 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
948 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
949 }
950 }
951 return ret;
952 }
953
jpeg_v4_0_3_set_clockgating_state(void * handle,enum amd_clockgating_state state)954 static int jpeg_v4_0_3_set_clockgating_state(void *handle,
955 enum amd_clockgating_state state)
956 {
957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
958 bool enable = state == AMD_CG_STATE_GATE;
959 int i;
960
961 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
962 if (enable) {
963 if (!jpeg_v4_0_3_is_idle(handle))
964 return -EBUSY;
965 jpeg_v4_0_3_enable_clock_gating(adev, i);
966 } else {
967 jpeg_v4_0_3_disable_clock_gating(adev, i);
968 }
969 }
970 return 0;
971 }
972
jpeg_v4_0_3_set_powergating_state(void * handle,enum amd_powergating_state state)973 static int jpeg_v4_0_3_set_powergating_state(void *handle,
974 enum amd_powergating_state state)
975 {
976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
977 int ret;
978
979 if (amdgpu_sriov_vf(adev)) {
980 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
981 return 0;
982 }
983
984 if (state == adev->jpeg.cur_state)
985 return 0;
986
987 if (state == AMD_PG_STATE_GATE)
988 ret = jpeg_v4_0_3_stop(adev);
989 else
990 ret = jpeg_v4_0_3_start(adev);
991
992 if (!ret)
993 adev->jpeg.cur_state = state;
994
995 return ret;
996 }
997
jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)998 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
999 struct amdgpu_irq_src *source,
1000 unsigned int type,
1001 enum amdgpu_interrupt_state state)
1002 {
1003 return 0;
1004 }
1005
jpeg_v4_0_3_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1006 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,
1007 struct amdgpu_irq_src *source,
1008 struct amdgpu_iv_entry *entry)
1009 {
1010 uint32_t i, inst;
1011
1012 i = node_id_to_phys_map[entry->node_id];
1013 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");
1014
1015 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
1016 if (adev->jpeg.inst[inst].aid_id == i)
1017 break;
1018
1019 if (inst >= adev->jpeg.num_jpeg_inst) {
1020 dev_WARN_ONCE(adev->dev, 1,
1021 "Interrupt received for unknown JPEG instance %d",
1022 entry->node_id);
1023 return 0;
1024 }
1025
1026 switch (entry->src_id) {
1027 case VCN_4_0__SRCID__JPEG_DECODE:
1028 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
1029 break;
1030 case VCN_4_0__SRCID__JPEG1_DECODE:
1031 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
1032 break;
1033 case VCN_4_0__SRCID__JPEG2_DECODE:
1034 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
1035 break;
1036 case VCN_4_0__SRCID__JPEG3_DECODE:
1037 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
1038 break;
1039 case VCN_4_0__SRCID__JPEG4_DECODE:
1040 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
1041 break;
1042 case VCN_4_0__SRCID__JPEG5_DECODE:
1043 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
1044 break;
1045 case VCN_4_0__SRCID__JPEG6_DECODE:
1046 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
1047 break;
1048 case VCN_4_0__SRCID__JPEG7_DECODE:
1049 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
1050 break;
1051 default:
1052 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
1053 entry->src_id, entry->src_data[0]);
1054 break;
1055 }
1056
1057 return 0;
1058 }
1059
1060 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
1061 .name = "jpeg_v4_0_3",
1062 .early_init = jpeg_v4_0_3_early_init,
1063 .late_init = NULL,
1064 .sw_init = jpeg_v4_0_3_sw_init,
1065 .sw_fini = jpeg_v4_0_3_sw_fini,
1066 .hw_init = jpeg_v4_0_3_hw_init,
1067 .hw_fini = jpeg_v4_0_3_hw_fini,
1068 .suspend = jpeg_v4_0_3_suspend,
1069 .resume = jpeg_v4_0_3_resume,
1070 .is_idle = jpeg_v4_0_3_is_idle,
1071 .wait_for_idle = jpeg_v4_0_3_wait_for_idle,
1072 .check_soft_reset = NULL,
1073 .pre_soft_reset = NULL,
1074 .soft_reset = NULL,
1075 .post_soft_reset = NULL,
1076 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
1077 .set_powergating_state = jpeg_v4_0_3_set_powergating_state,
1078 .dump_ip_state = NULL,
1079 .print_ip_state = NULL,
1080 };
1081
1082 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
1083 .type = AMDGPU_RING_TYPE_VCN_JPEG,
1084 .align_mask = 0xf,
1085 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
1086 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
1087 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
1088 .parse_cs = jpeg_v2_dec_ring_parse_cs,
1089 .emit_frame_size =
1090 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1091 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1092 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */
1093 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
1094 8 + 16,
1095 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */
1096 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
1097 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
1098 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
1099 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush,
1100 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
1101 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
1102 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
1103 .insert_start = jpeg_v4_0_3_dec_ring_insert_start,
1104 .insert_end = jpeg_v4_0_3_dec_ring_insert_end,
1105 .pad_ib = amdgpu_ring_generic_pad_ib,
1106 .begin_use = amdgpu_jpeg_ring_begin_use,
1107 .end_use = amdgpu_jpeg_ring_end_use,
1108 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
1109 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
1110 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1111 };
1112
jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device * adev)1113 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)
1114 {
1115 int i, j, jpeg_inst;
1116
1117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
1118 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
1119 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
1120 adev->jpeg.inst[i].ring_dec[j].me = i;
1121 adev->jpeg.inst[i].ring_dec[j].pipe = j;
1122 }
1123 jpeg_inst = GET_INST(JPEG, i);
1124 adev->jpeg.inst[i].aid_id =
1125 jpeg_inst / adev->jpeg.num_inst_per_aid;
1126 }
1127 }
1128
1129 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {
1130 .set = jpeg_v4_0_3_set_interrupt_state,
1131 .process = jpeg_v4_0_3_process_interrupt,
1132 };
1133
jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device * adev)1134 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
1135 {
1136 int i;
1137
1138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
1139 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
1140 }
1141 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;
1142 }
1143
1144 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = {
1145 .type = AMD_IP_BLOCK_TYPE_JPEG,
1146 .major = 4,
1147 .minor = 0,
1148 .rev = 3,
1149 .funcs = &jpeg_v4_0_3_ip_funcs,
1150 };
1151
1152 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = {
1153 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S),
1154 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"},
1155 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D),
1156 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"},
1157 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S),
1158 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"},
1159 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D),
1160 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"},
1161 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S),
1162 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"},
1163 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D),
1164 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"},
1165 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S),
1166 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"},
1167 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D),
1168 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"},
1169 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S),
1170 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"},
1171 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D),
1172 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"},
1173 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S),
1174 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"},
1175 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D),
1176 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"},
1177 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S),
1178 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"},
1179 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D),
1180 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"},
1181 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S),
1182 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"},
1183 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D),
1184 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"},
1185 };
1186
jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device * adev,uint32_t jpeg_inst,void * ras_err_status)1187 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
1188 uint32_t jpeg_inst,
1189 void *ras_err_status)
1190 {
1191 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
1192
1193 /* jpeg v4_0_3 only support uncorrectable errors */
1194 amdgpu_ras_inst_query_ras_error_count(adev,
1195 jpeg_v4_0_3_ue_reg_list,
1196 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
1197 NULL, 0, GET_INST(VCN, jpeg_inst),
1198 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1199 &err_data->ue_count);
1200 }
1201
jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device * adev,void * ras_err_status)1202 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
1203 void *ras_err_status)
1204 {
1205 uint32_t i;
1206
1207 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
1208 dev_warn(adev->dev, "JPEG RAS is not supported\n");
1209 return;
1210 }
1211
1212 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
1213 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
1214 }
1215
jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device * adev,uint32_t jpeg_inst)1216 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
1217 uint32_t jpeg_inst)
1218 {
1219 amdgpu_ras_inst_reset_ras_error_count(adev,
1220 jpeg_v4_0_3_ue_reg_list,
1221 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
1222 GET_INST(VCN, jpeg_inst));
1223 }
1224
jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device * adev)1225 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
1226 {
1227 uint32_t i;
1228
1229 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
1230 dev_warn(adev->dev, "JPEG RAS is not supported\n");
1231 return;
1232 }
1233
1234 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
1235 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i);
1236 }
1237
1238 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = {
1239 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count,
1240 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,
1241 };
1242
1243 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = {
1244 .ras_block = {
1245 .hw_ops = &jpeg_v4_0_3_ras_hw_ops,
1246 },
1247 };
1248
jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device * adev)1249 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1250 {
1251 adev->jpeg.ras = &jpeg_v4_0_3_ras;
1252 }
1253