1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc21.h"
29 #include "gfx_v11_0.h"
30 #include "gc/gc_11_0_0_offset.h"
31 #include "gc/gc_11_0_0_sh_mask.h"
32 #include "gc/gc_11_0_0_default.h"
33 #include "v11_structs.h"
34 #include "mes_v11_api_def.h"
35
36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
57
58 static int mes_v11_0_hw_init(void *handle);
59 static int mes_v11_0_hw_fini(void *handle);
60 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
61 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
62
63 #define MES_EOP_SIZE 2048
64 #define GFX_MES_DRAM_SIZE 0x80000
65
mes_v11_0_ring_set_wptr(struct amdgpu_ring * ring)66 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
67 {
68 struct amdgpu_device *adev = ring->adev;
69
70 if (ring->use_doorbell) {
71 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
72 ring->wptr);
73 WDOORBELL64(ring->doorbell_index, ring->wptr);
74 } else {
75 BUG();
76 }
77 }
78
mes_v11_0_ring_get_rptr(struct amdgpu_ring * ring)79 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
80 {
81 return *ring->rptr_cpu_addr;
82 }
83
mes_v11_0_ring_get_wptr(struct amdgpu_ring * ring)84 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
85 {
86 u64 wptr;
87
88 if (ring->use_doorbell)
89 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
90 else
91 BUG();
92 return wptr;
93 }
94
95 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
96 .type = AMDGPU_RING_TYPE_MES,
97 .align_mask = 1,
98 .nop = 0,
99 .support_64bit_ptrs = true,
100 .get_rptr = mes_v11_0_ring_get_rptr,
101 .get_wptr = mes_v11_0_ring_get_wptr,
102 .set_wptr = mes_v11_0_ring_set_wptr,
103 .insert_nop = amdgpu_ring_insert_nop,
104 };
105
106 static const char *mes_v11_0_opcodes[] = {
107 "SET_HW_RSRC",
108 "SET_SCHEDULING_CONFIG",
109 "ADD_QUEUE",
110 "REMOVE_QUEUE",
111 "PERFORM_YIELD",
112 "SET_GANG_PRIORITY_LEVEL",
113 "SUSPEND",
114 "RESUME",
115 "RESET",
116 "SET_LOG_BUFFER",
117 "CHANGE_GANG_PRORITY",
118 "QUERY_SCHEDULER_STATUS",
119 "PROGRAM_GDS",
120 "SET_DEBUG_VMID",
121 "MISC",
122 "UPDATE_ROOT_PAGE_TABLE",
123 "AMD_LOG",
124 "unused",
125 "unused",
126 "SET_HW_RSRC_1",
127 };
128
129 static const char *mes_v11_0_misc_opcodes[] = {
130 "WRITE_REG",
131 "INV_GART",
132 "QUERY_STATUS",
133 "READ_REG",
134 "WAIT_REG_MEM",
135 "SET_SHADER_DEBUGGER",
136 };
137
mes_v11_0_get_op_string(union MESAPI__MISC * x_pkt)138 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)
139 {
140 const char *op_str = NULL;
141
142 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))
143 op_str = mes_v11_0_opcodes[x_pkt->header.opcode];
144
145 return op_str;
146 }
147
mes_v11_0_get_misc_op_string(union MESAPI__MISC * x_pkt)148 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
149 {
150 const char *op_str = NULL;
151
152 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
153 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))
154 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode];
155
156 return op_str;
157 }
158
mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,void * pkt,int size,int api_status_off)159 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
160 void *pkt, int size,
161 int api_status_off)
162 {
163 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
164 signed long timeout = 2100000; /* 2100 ms */
165 struct amdgpu_device *adev = mes->adev;
166 struct amdgpu_ring *ring = &mes->ring[0];
167 struct MES_API_STATUS *api_status;
168 union MESAPI__MISC *x_pkt = pkt;
169 const char *op_str, *misc_op_str;
170 unsigned long flags;
171 u64 status_gpu_addr;
172 u32 seq, status_offset;
173 u64 *status_ptr;
174 signed long r;
175 int ret;
176
177 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
178 return -EINVAL;
179
180 if (amdgpu_emu_mode) {
181 timeout *= 100;
182 } else if (amdgpu_sriov_vf(adev)) {
183 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
184 timeout = 15 * 600 * 1000;
185 }
186
187 ret = amdgpu_device_wb_get(adev, &status_offset);
188 if (ret)
189 return ret;
190
191 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
192 status_ptr = (u64 *)&adev->wb.wb[status_offset];
193 *status_ptr = 0;
194
195 spin_lock_irqsave(&mes->ring_lock[0], flags);
196 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
197 if (r)
198 goto error_unlock_free;
199
200 seq = ++ring->fence_drv.sync_seq;
201 r = amdgpu_fence_wait_polling(ring,
202 seq - ring->fence_drv.num_fences_mask,
203 timeout);
204 if (r < 1)
205 goto error_undo;
206
207 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
208 api_status->api_completion_fence_addr = status_gpu_addr;
209 api_status->api_completion_fence_value = 1;
210
211 amdgpu_ring_write_multiple(ring, pkt, size / 4);
212
213 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
214 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
215 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
216 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
217 mes_status_pkt.api_status.api_completion_fence_addr =
218 ring->fence_drv.gpu_addr;
219 mes_status_pkt.api_status.api_completion_fence_value = seq;
220
221 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
222 sizeof(mes_status_pkt) / 4);
223
224 amdgpu_ring_commit(ring);
225 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
226
227 op_str = mes_v11_0_get_op_string(x_pkt);
228 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
229
230 if (misc_op_str)
231 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
232 misc_op_str);
233 else if (op_str)
234 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
235 else
236 dev_dbg(adev->dev, "MES msg=%d was emitted\n",
237 x_pkt->header.opcode);
238
239 r = amdgpu_fence_wait_polling(ring, seq, timeout);
240 if (r < 1 || !*status_ptr) {
241
242 if (misc_op_str)
243 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
244 op_str, misc_op_str);
245 else if (op_str)
246 dev_err(adev->dev, "MES failed to respond to msg=%s\n",
247 op_str);
248 else
249 dev_err(adev->dev, "MES failed to respond to msg=%d\n",
250 x_pkt->header.opcode);
251
252 while (halt_if_hws_hang)
253 schedule();
254
255 r = -ETIMEDOUT;
256 goto error_wb_free;
257 }
258
259 amdgpu_device_wb_free(adev, status_offset);
260 return 0;
261
262 error_undo:
263 dev_err(adev->dev, "MES ring buffer is full.\n");
264 amdgpu_ring_undo(ring);
265
266 error_unlock_free:
267 spin_unlock_irqrestore(&mes->ring_lock[0], flags);
268
269 error_wb_free:
270 amdgpu_device_wb_free(adev, status_offset);
271 return r;
272 }
273
convert_to_mes_queue_type(int queue_type)274 static int convert_to_mes_queue_type(int queue_type)
275 {
276 if (queue_type == AMDGPU_RING_TYPE_GFX)
277 return MES_QUEUE_TYPE_GFX;
278 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
279 return MES_QUEUE_TYPE_COMPUTE;
280 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
281 return MES_QUEUE_TYPE_SDMA;
282 else
283 BUG();
284 return -1;
285 }
286
mes_v11_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)287 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
288 struct mes_add_queue_input *input)
289 {
290 struct amdgpu_device *adev = mes->adev;
291 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
292 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
293 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
294
295 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
296
297 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
298 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
299 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
300
301 mes_add_queue_pkt.process_id = input->process_id;
302 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
303 mes_add_queue_pkt.process_va_start = input->process_va_start;
304 mes_add_queue_pkt.process_va_end = input->process_va_end;
305 mes_add_queue_pkt.process_quantum = input->process_quantum;
306 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
307 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
308 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
309 mes_add_queue_pkt.inprocess_gang_priority =
310 input->inprocess_gang_priority;
311 mes_add_queue_pkt.gang_global_priority_level =
312 input->gang_global_priority_level;
313 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
314 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
315
316 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
317 AMDGPU_MES_API_VERSION_SHIFT) >= 2)
318 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
319 else
320 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
321
322 mes_add_queue_pkt.queue_type =
323 convert_to_mes_queue_type(input->queue_type);
324 mes_add_queue_pkt.paging = input->paging;
325 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
326 mes_add_queue_pkt.gws_base = input->gws_base;
327 mes_add_queue_pkt.gws_size = input->gws_size;
328 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
329 mes_add_queue_pkt.tma_addr = input->tma_addr;
330 mes_add_queue_pkt.trap_en = input->trap_en;
331 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
332 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
333
334 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
335 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
336 mes_add_queue_pkt.gds_size = input->queue_size;
337
338 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
339
340 return mes_v11_0_submit_pkt_and_poll_completion(mes,
341 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
342 offsetof(union MESAPI__ADD_QUEUE, api_status));
343 }
344
mes_v11_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)345 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
346 struct mes_remove_queue_input *input)
347 {
348 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
349
350 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
351
352 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
353 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
354 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
355
356 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
357 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
358
359 return mes_v11_0_submit_pkt_and_poll_completion(mes,
360 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
361 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
362 }
363
mes_v11_0_reset_queue_mmio(struct amdgpu_mes * mes,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t vmid)364 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
365 uint32_t me_id, uint32_t pipe_id,
366 uint32_t queue_id, uint32_t vmid)
367 {
368 struct amdgpu_device *adev = mes->adev;
369 uint32_t value;
370 int i, r = 0;
371
372 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
373
374 if (queue_type == AMDGPU_RING_TYPE_GFX) {
375 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",
376 me_id, pipe_id, queue_id, vmid);
377
378 mutex_lock(&adev->gfx.reset_sem_mutex);
379 gfx_v11_0_request_gfx_index_mutex(adev, true);
380 /* all se allow writes */
381 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,
382 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
383 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
384 if (pipe_id == 0)
385 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
386 else
387 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
388 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);
389 gfx_v11_0_request_gfx_index_mutex(adev, false);
390 mutex_unlock(&adev->gfx.reset_sem_mutex);
391
392 mutex_lock(&adev->srbm_mutex);
393 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
394 /* wait till dequeue take effects */
395 for (i = 0; i < adev->usec_timeout; i++) {
396 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))
397 break;
398 udelay(1);
399 }
400 if (i >= adev->usec_timeout) {
401 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
402 r = -ETIMEDOUT;
403 }
404
405 soc21_grbm_select(adev, 0, 0, 0, 0);
406 mutex_unlock(&adev->srbm_mutex);
407 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
408 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n",
409 me_id, pipe_id, queue_id);
410 mutex_lock(&adev->srbm_mutex);
411 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);
412 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
413 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
414
415 /* wait till dequeue take effects */
416 for (i = 0; i < adev->usec_timeout; i++) {
417 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
418 break;
419 udelay(1);
420 }
421 if (i >= adev->usec_timeout) {
422 dev_err(adev->dev, "failed to wait on hqd deactivate\n");
423 r = -ETIMEDOUT;
424 }
425 soc21_grbm_select(adev, 0, 0, 0, 0);
426 mutex_unlock(&adev->srbm_mutex);
427 }
428
429 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
430 return r;
431 }
432
mes_v11_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)433 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,
434 struct mes_reset_queue_input *input)
435 {
436 if (input->use_mmio)
437 return mes_v11_0_reset_queue_mmio(mes, input->queue_type,
438 input->me_id, input->pipe_id,
439 input->queue_id, input->vmid);
440
441 union MESAPI__RESET mes_reset_queue_pkt;
442
443 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
444
445 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
446 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
447 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
448
449 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
450 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;
451 /*mes_reset_queue_pkt.reset_queue_only = 1;*/
452
453 return mes_v11_0_submit_pkt_and_poll_completion(mes,
454 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
455 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
456 }
457
mes_v11_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)458 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,
459 struct mes_map_legacy_queue_input *input)
460 {
461 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
462
463 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
464
465 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
466 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
467 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
468
469 mes_add_queue_pkt.pipe_id = input->pipe_id;
470 mes_add_queue_pkt.queue_id = input->queue_id;
471 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
472 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
473 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
474 mes_add_queue_pkt.queue_type =
475 convert_to_mes_queue_type(input->queue_type);
476 mes_add_queue_pkt.map_legacy_kq = 1;
477
478 return mes_v11_0_submit_pkt_and_poll_completion(mes,
479 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
480 offsetof(union MESAPI__ADD_QUEUE, api_status));
481 }
482
mes_v11_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)483 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
484 struct mes_unmap_legacy_queue_input *input)
485 {
486 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
487
488 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
489
490 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
491 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
492 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
493
494 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
495 mes_remove_queue_pkt.gang_context_addr = 0;
496
497 mes_remove_queue_pkt.pipe_id = input->pipe_id;
498 mes_remove_queue_pkt.queue_id = input->queue_id;
499
500 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
501 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
502 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
503 mes_remove_queue_pkt.tf_data =
504 lower_32_bits(input->trail_fence_data);
505 } else {
506 mes_remove_queue_pkt.unmap_legacy_queue = 1;
507 mes_remove_queue_pkt.queue_type =
508 convert_to_mes_queue_type(input->queue_type);
509 }
510
511 return mes_v11_0_submit_pkt_and_poll_completion(mes,
512 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
513 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
514 }
515
mes_v11_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)516 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
517 struct mes_suspend_gang_input *input)
518 {
519 union MESAPI__SUSPEND mes_suspend_gang_pkt;
520
521 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));
522
523 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
524 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;
525 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
526
527 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs;
528 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr;
529 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr;
530 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value;
531
532 return mes_v11_0_submit_pkt_and_poll_completion(mes,
533 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),
534 offsetof(union MESAPI__SUSPEND, api_status));
535 }
536
mes_v11_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)537 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
538 struct mes_resume_gang_input *input)
539 {
540 union MESAPI__RESUME mes_resume_gang_pkt;
541
542 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));
543
544 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
545 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;
546 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
547
548 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs;
549 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr;
550
551 return mes_v11_0_submit_pkt_and_poll_completion(mes,
552 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),
553 offsetof(union MESAPI__RESUME, api_status));
554 }
555
mes_v11_0_query_sched_status(struct amdgpu_mes * mes)556 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
557 {
558 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
559
560 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
561
562 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
563 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
564 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
565
566 return mes_v11_0_submit_pkt_and_poll_completion(mes,
567 &mes_status_pkt, sizeof(mes_status_pkt),
568 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
569 }
570
mes_v11_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)571 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
572 struct mes_misc_op_input *input)
573 {
574 union MESAPI__MISC misc_pkt;
575
576 memset(&misc_pkt, 0, sizeof(misc_pkt));
577
578 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
579 misc_pkt.header.opcode = MES_SCH_API_MISC;
580 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
581
582 switch (input->op) {
583 case MES_MISC_OP_READ_REG:
584 misc_pkt.opcode = MESAPI_MISC__READ_REG;
585 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
586 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
587 break;
588 case MES_MISC_OP_WRITE_REG:
589 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
590 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
591 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
592 break;
593 case MES_MISC_OP_WRM_REG_WAIT:
594 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
595 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
596 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
597 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
598 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
599 misc_pkt.wait_reg_mem.reg_offset2 = 0;
600 break;
601 case MES_MISC_OP_WRM_REG_WR_WAIT:
602 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
603 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
604 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
605 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
606 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
607 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
608 break;
609 case MES_MISC_OP_SET_SHADER_DEBUGGER:
610 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
611 misc_pkt.set_shader_debugger.process_context_addr =
612 input->set_shader_debugger.process_context_addr;
613 misc_pkt.set_shader_debugger.flags.u32all =
614 input->set_shader_debugger.flags.u32all;
615 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
616 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
617 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
618 input->set_shader_debugger.tcp_watch_cntl,
619 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
620 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
621 break;
622 default:
623 DRM_ERROR("unsupported misc op (%d) \n", input->op);
624 return -EINVAL;
625 }
626
627 return mes_v11_0_submit_pkt_and_poll_completion(mes,
628 &misc_pkt, sizeof(misc_pkt),
629 offsetof(union MESAPI__MISC, api_status));
630 }
631
mes_v11_0_set_hw_resources(struct amdgpu_mes * mes)632 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
633 {
634 int i;
635 struct amdgpu_device *adev = mes->adev;
636 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
637
638 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
639
640 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
641 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
642 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
643
644 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
645 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
646 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
647 mes_set_hw_res_pkt.paging_vmid = 0;
648 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0];
649 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
650 mes->query_status_fence_gpu_addr[0];
651
652 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
653 mes_set_hw_res_pkt.compute_hqd_mask[i] =
654 mes->compute_hqd_mask[i];
655
656 for (i = 0; i < MAX_GFX_PIPES; i++)
657 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
658
659 for (i = 0; i < MAX_SDMA_PIPES; i++)
660 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
661
662 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
663 mes_set_hw_res_pkt.aggregated_doorbells[i] =
664 mes->aggregated_doorbells[i];
665
666 for (i = 0; i < 5; i++) {
667 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
668 mes_set_hw_res_pkt.mmhub_base[i] =
669 adev->reg_offset[MMHUB_HWIP][0][i];
670 mes_set_hw_res_pkt.osssys_base[i] =
671 adev->reg_offset[OSSSYS_HWIP][0][i];
672 }
673
674 mes_set_hw_res_pkt.disable_reset = 1;
675 mes_set_hw_res_pkt.disable_mes_log = 1;
676 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
677 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
678 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
679 mes_set_hw_res_pkt.oversubscription_timer = 50;
680 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f)
681 mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
682 else
683 dev_info_once(mes->adev->dev,
684 "MES FW version must be >= 0x7f to enable LR compute workaround.\n");
685
686 if (amdgpu_mes_log_enable) {
687 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
688 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
689 mes->event_log_gpu_addr;
690 }
691
692 return mes_v11_0_submit_pkt_and_poll_completion(mes,
693 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
694 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
695 }
696
mes_v11_0_set_hw_resources_1(struct amdgpu_mes * mes)697 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
698 {
699 int size = 128 * AMDGPU_GPU_PAGE_SIZE;
700 int ret = 0;
701 struct amdgpu_device *adev = mes->adev;
702 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
703 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
704
705 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
706 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
707 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
708 mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
709
710 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
711 AMDGPU_GEM_DOMAIN_VRAM,
712 &mes->resource_1,
713 &mes->resource_1_gpu_addr,
714 &mes->resource_1_addr);
715 if (ret) {
716 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
717 return ret;
718 }
719
720 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
721 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size;
722 return mes_v11_0_submit_pkt_and_poll_completion(mes,
723 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
724 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
725 }
726
mes_v11_0_reset_legacy_queue(struct amdgpu_mes * mes,struct mes_reset_legacy_queue_input * input)727 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes,
728 struct mes_reset_legacy_queue_input *input)
729 {
730 union MESAPI__RESET mes_reset_queue_pkt;
731
732 if (input->use_mmio)
733 return mes_v11_0_reset_queue_mmio(mes, input->queue_type,
734 input->me_id, input->pipe_id,
735 input->queue_id, input->vmid);
736
737 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
738
739 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
740 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
741 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
742
743 mes_reset_queue_pkt.queue_type =
744 convert_to_mes_queue_type(input->queue_type);
745
746 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {
747 mes_reset_queue_pkt.reset_legacy_gfx = 1;
748 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
749 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
750 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
751 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
752 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
753 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
754 } else {
755 mes_reset_queue_pkt.reset_queue_only = 1;
756 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
757 }
758
759 return mes_v11_0_submit_pkt_and_poll_completion(mes,
760 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
761 offsetof(union MESAPI__RESET, api_status));
762 }
763
764 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
765 .add_hw_queue = mes_v11_0_add_hw_queue,
766 .remove_hw_queue = mes_v11_0_remove_hw_queue,
767 .map_legacy_queue = mes_v11_0_map_legacy_queue,
768 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
769 .suspend_gang = mes_v11_0_suspend_gang,
770 .resume_gang = mes_v11_0_resume_gang,
771 .misc_op = mes_v11_0_misc_op,
772 .reset_legacy_queue = mes_v11_0_reset_legacy_queue,
773 .reset_hw_queue = mes_v11_0_reset_hw_queue,
774 };
775
mes_v11_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)776 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
777 enum admgpu_mes_pipe pipe)
778 {
779 int r;
780 const struct mes_firmware_header_v1_0 *mes_hdr;
781 const __le32 *fw_data;
782 unsigned fw_size;
783
784 mes_hdr = (const struct mes_firmware_header_v1_0 *)
785 adev->mes.fw[pipe]->data;
786
787 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
788 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
789 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
790
791 r = amdgpu_bo_create_reserved(adev, fw_size,
792 PAGE_SIZE,
793 AMDGPU_GEM_DOMAIN_VRAM |
794 AMDGPU_GEM_DOMAIN_GTT,
795 &adev->mes.ucode_fw_obj[pipe],
796 &adev->mes.ucode_fw_gpu_addr[pipe],
797 (void **)&adev->mes.ucode_fw_ptr[pipe]);
798 if (r) {
799 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
800 return r;
801 }
802
803 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
804
805 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
806 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
807
808 return 0;
809 }
810
mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)811 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
812 enum admgpu_mes_pipe pipe)
813 {
814 int r;
815 const struct mes_firmware_header_v1_0 *mes_hdr;
816 const __le32 *fw_data;
817 unsigned fw_size;
818
819 mes_hdr = (const struct mes_firmware_header_v1_0 *)
820 adev->mes.fw[pipe]->data;
821
822 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
823 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
824 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
825
826 if (fw_size > GFX_MES_DRAM_SIZE) {
827 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
828 pipe, fw_size, GFX_MES_DRAM_SIZE);
829 return -EINVAL;
830 }
831
832 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
833 64 * 1024,
834 AMDGPU_GEM_DOMAIN_VRAM |
835 AMDGPU_GEM_DOMAIN_GTT,
836 &adev->mes.data_fw_obj[pipe],
837 &adev->mes.data_fw_gpu_addr[pipe],
838 (void **)&adev->mes.data_fw_ptr[pipe]);
839 if (r) {
840 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
841 return r;
842 }
843
844 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
845
846 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
847 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
848
849 return 0;
850 }
851
mes_v11_0_free_ucode_buffers(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)852 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
853 enum admgpu_mes_pipe pipe)
854 {
855 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
856 &adev->mes.data_fw_gpu_addr[pipe],
857 (void **)&adev->mes.data_fw_ptr[pipe]);
858
859 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
860 &adev->mes.ucode_fw_gpu_addr[pipe],
861 (void **)&adev->mes.ucode_fw_ptr[pipe]);
862 }
863
mes_v11_0_get_fw_version(struct amdgpu_device * adev)864 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
865 {
866 int pipe;
867
868 /* return early if we have already fetched these */
869 if (adev->mes.sched_version && adev->mes.kiq_version)
870 return;
871
872 /* get MES scheduler/KIQ versions */
873 mutex_lock(&adev->srbm_mutex);
874
875 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
876 soc21_grbm_select(adev, 3, pipe, 0, 0);
877
878 if (pipe == AMDGPU_MES_SCHED_PIPE)
879 adev->mes.sched_version =
880 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
881 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
882 adev->mes.kiq_version =
883 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
884 }
885
886 soc21_grbm_select(adev, 0, 0, 0, 0);
887 mutex_unlock(&adev->srbm_mutex);
888 }
889
mes_v11_0_enable(struct amdgpu_device * adev,bool enable)890 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
891 {
892 uint64_t ucode_addr;
893 uint32_t pipe, data = 0;
894
895 if (enable) {
896 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
897 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
898 data = REG_SET_FIELD(data, CP_MES_CNTL,
899 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
900 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
901
902 mutex_lock(&adev->srbm_mutex);
903 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
904 if (!adev->enable_mes_kiq &&
905 pipe == AMDGPU_MES_KIQ_PIPE)
906 continue;
907
908 soc21_grbm_select(adev, 3, pipe, 0, 0);
909
910 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
911 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
912 lower_32_bits(ucode_addr));
913 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
914 upper_32_bits(ucode_addr));
915 }
916 soc21_grbm_select(adev, 0, 0, 0, 0);
917 mutex_unlock(&adev->srbm_mutex);
918
919 /* unhalt MES and activate pipe0 */
920 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
921 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
922 adev->enable_mes_kiq ? 1 : 0);
923 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
924
925 if (amdgpu_emu_mode)
926 msleep(100);
927 else
928 udelay(500);
929 } else {
930 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
931 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
932 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
933 data = REG_SET_FIELD(data, CP_MES_CNTL,
934 MES_INVALIDATE_ICACHE, 1);
935 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
936 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
937 adev->enable_mes_kiq ? 1 : 0);
938 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
939 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
940 }
941 }
942
943 /* This function is for backdoor MES firmware */
mes_v11_0_load_microcode(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe,bool prime_icache)944 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
945 enum admgpu_mes_pipe pipe, bool prime_icache)
946 {
947 int r;
948 uint32_t data;
949 uint64_t ucode_addr;
950
951 mes_v11_0_enable(adev, false);
952
953 if (!adev->mes.fw[pipe])
954 return -EINVAL;
955
956 r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
957 if (r)
958 return r;
959
960 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
961 if (r) {
962 mes_v11_0_free_ucode_buffers(adev, pipe);
963 return r;
964 }
965
966 mutex_lock(&adev->srbm_mutex);
967 /* me=3, pipe=0, queue=0 */
968 soc21_grbm_select(adev, 3, pipe, 0, 0);
969
970 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
971
972 /* set ucode start address */
973 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
974 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
975 lower_32_bits(ucode_addr));
976 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
977 upper_32_bits(ucode_addr));
978
979 /* set ucode fimrware address */
980 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
981 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
982 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
983 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
984
985 /* set ucode instruction cache boundary to 2M-1 */
986 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
987
988 /* set ucode data firmware address */
989 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
990 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
991 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
992 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
993
994 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
995 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
996
997 if (prime_icache) {
998 /* invalidate ICACHE */
999 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1000 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
1001 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1002 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1003
1004 /* prime the ICACHE. */
1005 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
1006 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
1007 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
1008 }
1009
1010 soc21_grbm_select(adev, 0, 0, 0, 0);
1011 mutex_unlock(&adev->srbm_mutex);
1012
1013 return 0;
1014 }
1015
mes_v11_0_allocate_eop_buf(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1016 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
1017 enum admgpu_mes_pipe pipe)
1018 {
1019 int r;
1020 u32 *eop;
1021
1022 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
1023 AMDGPU_GEM_DOMAIN_GTT,
1024 &adev->mes.eop_gpu_obj[pipe],
1025 &adev->mes.eop_gpu_addr[pipe],
1026 (void **)&eop);
1027 if (r) {
1028 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
1029 return r;
1030 }
1031
1032 memset(eop, 0,
1033 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
1034
1035 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
1036 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1037
1038 return 0;
1039 }
1040
mes_v11_0_mqd_init(struct amdgpu_ring * ring)1041 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
1042 {
1043 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1044 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1045 uint32_t tmp;
1046
1047 memset(mqd, 0, sizeof(*mqd));
1048
1049 mqd->header = 0xC0310800;
1050 mqd->compute_pipelinestat_enable = 0x00000001;
1051 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1052 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1053 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1054 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1055 mqd->compute_misc_reserved = 0x00000007;
1056
1057 eop_base_addr = ring->eop_gpu_addr >> 8;
1058
1059 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1060 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1061 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1062 (order_base_2(MES_EOP_SIZE / 4) - 1));
1063
1064 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1065 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1066 mqd->cp_hqd_eop_control = tmp;
1067
1068 /* disable the queue if it's active */
1069 ring->wptr = 0;
1070 mqd->cp_hqd_pq_rptr = 0;
1071 mqd->cp_hqd_pq_wptr_lo = 0;
1072 mqd->cp_hqd_pq_wptr_hi = 0;
1073
1074 /* set the pointer to the MQD */
1075 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1076 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1077
1078 /* set MQD vmid to 0 */
1079 tmp = regCP_MQD_CONTROL_DEFAULT;
1080 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1081 mqd->cp_mqd_control = tmp;
1082
1083 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1084 hqd_gpu_addr = ring->gpu_addr >> 8;
1085 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1086 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1087
1088 /* set the wb address whether it's enabled or not */
1089 wb_gpu_addr = ring->rptr_gpu_addr;
1090 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1091 mqd->cp_hqd_pq_rptr_report_addr_hi =
1092 upper_32_bits(wb_gpu_addr) & 0xffff;
1093
1094 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1095 wb_gpu_addr = ring->wptr_gpu_addr;
1096 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1097 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1098
1099 /* set up the HQD, this is similar to CP_RB0_CNTL */
1100 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1102 (order_base_2(ring->ring_size / 4) - 1));
1103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1104 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1106 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1108 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1109 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1110 mqd->cp_hqd_pq_control = tmp;
1111
1112 /* enable doorbell */
1113 tmp = 0;
1114 if (ring->use_doorbell) {
1115 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1116 DOORBELL_OFFSET, ring->doorbell_index);
1117 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1118 DOORBELL_EN, 1);
1119 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1120 DOORBELL_SOURCE, 0);
1121 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1122 DOORBELL_HIT, 0);
1123 } else
1124 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1125 DOORBELL_EN, 0);
1126 mqd->cp_hqd_pq_doorbell_control = tmp;
1127
1128 mqd->cp_hqd_vmid = 0;
1129 /* activate the queue */
1130 mqd->cp_hqd_active = 1;
1131
1132 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1133 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1134 PRELOAD_SIZE, 0x55);
1135 mqd->cp_hqd_persistent_state = tmp;
1136
1137 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1138 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1139 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1140
1141 amdgpu_device_flush_hdp(ring->adev, NULL);
1142 return 0;
1143 }
1144
mes_v11_0_queue_init_register(struct amdgpu_ring * ring)1145 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
1146 {
1147 struct v11_compute_mqd *mqd = ring->mqd_ptr;
1148 struct amdgpu_device *adev = ring->adev;
1149 uint32_t data = 0;
1150
1151 mutex_lock(&adev->srbm_mutex);
1152 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1153
1154 /* set CP_HQD_VMID.VMID = 0. */
1155 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1156 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1157 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1158
1159 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1160 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1161 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1162 DOORBELL_EN, 0);
1163 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1164
1165 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1166 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1167 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1168
1169 /* set CP_MQD_CONTROL.VMID=0 */
1170 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1171 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1172 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1173
1174 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1175 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1176 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1177
1178 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1179 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1180 mqd->cp_hqd_pq_rptr_report_addr_lo);
1181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1182 mqd->cp_hqd_pq_rptr_report_addr_hi);
1183
1184 /* set CP_HQD_PQ_CONTROL */
1185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1186
1187 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1188 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1189 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1191 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1192
1193 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1194 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1195 mqd->cp_hqd_pq_doorbell_control);
1196
1197 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1198 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1199
1200 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1201 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1202
1203 soc21_grbm_select(adev, 0, 0, 0, 0);
1204 mutex_unlock(&adev->srbm_mutex);
1205 }
1206
mes_v11_0_kiq_enable_queue(struct amdgpu_device * adev)1207 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
1208 {
1209 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1210 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1211 int r;
1212
1213 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1214 return -EINVAL;
1215
1216 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1217 if (r) {
1218 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1219 return r;
1220 }
1221
1222 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1223
1224 return amdgpu_ring_test_helper(kiq_ring);
1225 }
1226
mes_v11_0_queue_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1227 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
1228 enum admgpu_mes_pipe pipe)
1229 {
1230 struct amdgpu_ring *ring;
1231 int r;
1232
1233 if (pipe == AMDGPU_MES_KIQ_PIPE)
1234 ring = &adev->gfx.kiq[0].ring;
1235 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1236 ring = &adev->mes.ring[0];
1237 else
1238 BUG();
1239
1240 if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
1241 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1242 *(ring->wptr_cpu_addr) = 0;
1243 *(ring->rptr_cpu_addr) = 0;
1244 amdgpu_ring_clear_ring(ring);
1245 }
1246
1247 r = mes_v11_0_mqd_init(ring);
1248 if (r)
1249 return r;
1250
1251 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1252 r = mes_v11_0_kiq_enable_queue(adev);
1253 if (r)
1254 return r;
1255 } else {
1256 mes_v11_0_queue_init_register(ring);
1257 }
1258
1259 return 0;
1260 }
1261
mes_v11_0_ring_init(struct amdgpu_device * adev)1262 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1263 {
1264 struct amdgpu_ring *ring;
1265
1266 ring = &adev->mes.ring[0];
1267
1268 ring->funcs = &mes_v11_0_ring_funcs;
1269
1270 ring->me = 3;
1271 ring->pipe = 0;
1272 ring->queue = 0;
1273
1274 ring->ring_obj = NULL;
1275 ring->use_doorbell = true;
1276 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1277 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1278 ring->no_scheduler = true;
1279 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1280
1281 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1282 AMDGPU_RING_PRIO_DEFAULT, NULL);
1283 }
1284
mes_v11_0_kiq_ring_init(struct amdgpu_device * adev)1285 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1286 {
1287 struct amdgpu_ring *ring;
1288
1289 spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1290
1291 ring = &adev->gfx.kiq[0].ring;
1292
1293 ring->me = 3;
1294 ring->pipe = 1;
1295 ring->queue = 0;
1296
1297 ring->adev = NULL;
1298 ring->ring_obj = NULL;
1299 ring->use_doorbell = true;
1300 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1301 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1302 ring->no_scheduler = true;
1303 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1304 ring->me, ring->pipe, ring->queue);
1305
1306 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1307 AMDGPU_RING_PRIO_DEFAULT, NULL);
1308 }
1309
mes_v11_0_mqd_sw_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1310 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1311 enum admgpu_mes_pipe pipe)
1312 {
1313 int r, mqd_size = sizeof(struct v11_compute_mqd);
1314 struct amdgpu_ring *ring;
1315
1316 if (pipe == AMDGPU_MES_KIQ_PIPE)
1317 ring = &adev->gfx.kiq[0].ring;
1318 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1319 ring = &adev->mes.ring[0];
1320 else
1321 BUG();
1322
1323 if (ring->mqd_obj)
1324 return 0;
1325
1326 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1327 AMDGPU_GEM_DOMAIN_VRAM |
1328 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1329 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1330 if (r) {
1331 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1332 return r;
1333 }
1334
1335 memset(ring->mqd_ptr, 0, mqd_size);
1336
1337 /* prepare MQD backup */
1338 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1339 if (!adev->mes.mqd_backup[pipe]) {
1340 dev_warn(adev->dev,
1341 "no memory to create MQD backup for ring %s\n",
1342 ring->name);
1343 return -ENOMEM;
1344 }
1345
1346 return 0;
1347 }
1348
mes_v11_0_sw_init(void * handle)1349 static int mes_v11_0_sw_init(void *handle)
1350 {
1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352 int pipe, r;
1353
1354 adev->mes.funcs = &mes_v11_0_funcs;
1355 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1356 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1357
1358 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1359
1360 r = amdgpu_mes_init(adev);
1361 if (r)
1362 return r;
1363
1364 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1365 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1366 continue;
1367
1368 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1369 if (r)
1370 return r;
1371
1372 r = mes_v11_0_mqd_sw_init(adev, pipe);
1373 if (r)
1374 return r;
1375 }
1376
1377 if (adev->enable_mes_kiq) {
1378 r = mes_v11_0_kiq_ring_init(adev);
1379 if (r)
1380 return r;
1381 }
1382
1383 r = mes_v11_0_ring_init(adev);
1384 if (r)
1385 return r;
1386
1387 return 0;
1388 }
1389
mes_v11_0_sw_fini(void * handle)1390 static int mes_v11_0_sw_fini(void *handle)
1391 {
1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393 int pipe;
1394
1395 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1396 kfree(adev->mes.mqd_backup[pipe]);
1397
1398 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1399 &adev->mes.eop_gpu_addr[pipe],
1400 NULL);
1401 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1402 }
1403
1404 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1405 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1406 &adev->gfx.kiq[0].ring.mqd_ptr);
1407
1408 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj,
1409 &adev->mes.ring[0].mqd_gpu_addr,
1410 &adev->mes.ring[0].mqd_ptr);
1411
1412 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1413 amdgpu_ring_fini(&adev->mes.ring[0]);
1414
1415 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1416 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1417 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1418 }
1419
1420 amdgpu_mes_fini(adev);
1421 return 0;
1422 }
1423
mes_v11_0_kiq_dequeue(struct amdgpu_ring * ring)1424 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1425 {
1426 uint32_t data;
1427 int i;
1428 struct amdgpu_device *adev = ring->adev;
1429
1430 mutex_lock(&adev->srbm_mutex);
1431 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1432
1433 /* disable the queue if it's active */
1434 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1435 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1436 for (i = 0; i < adev->usec_timeout; i++) {
1437 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1438 break;
1439 udelay(1);
1440 }
1441 }
1442 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1443 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1444 DOORBELL_EN, 0);
1445 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1446 DOORBELL_HIT, 1);
1447 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1448
1449 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1450
1451 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1452 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1453 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1454
1455 soc21_grbm_select(adev, 0, 0, 0, 0);
1456 mutex_unlock(&adev->srbm_mutex);
1457 }
1458
mes_v11_0_kiq_setting(struct amdgpu_ring * ring)1459 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1460 {
1461 uint32_t tmp;
1462 struct amdgpu_device *adev = ring->adev;
1463
1464 /* tell RLC which is KIQ queue */
1465 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1466 tmp &= 0xffffff00;
1467 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1468 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1469 tmp |= 0x80;
1470 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1471 }
1472
mes_v11_0_kiq_clear(struct amdgpu_device * adev)1473 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1474 {
1475 uint32_t tmp;
1476
1477 /* tell RLC which is KIQ dequeue */
1478 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1479 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1480 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1481 }
1482
mes_v11_0_kiq_hw_init(struct amdgpu_device * adev)1483 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1484 {
1485 int r = 0;
1486
1487 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1488
1489 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1490 if (r) {
1491 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1492 return r;
1493 }
1494
1495 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1496 if (r) {
1497 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1498 return r;
1499 }
1500
1501 }
1502
1503 mes_v11_0_enable(adev, true);
1504
1505 mes_v11_0_get_fw_version(adev);
1506
1507 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1508
1509 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1510 if (r)
1511 goto failure;
1512
1513 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
1514 adev->mes.enable_legacy_queue_map = true;
1515 else
1516 adev->mes.enable_legacy_queue_map = false;
1517
1518 if (adev->mes.enable_legacy_queue_map) {
1519 r = mes_v11_0_hw_init(adev);
1520 if (r)
1521 goto failure;
1522 }
1523
1524 return r;
1525
1526 failure:
1527 mes_v11_0_hw_fini(adev);
1528 return r;
1529 }
1530
mes_v11_0_kiq_hw_fini(struct amdgpu_device * adev)1531 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1532 {
1533 if (adev->mes.ring[0].sched.ready) {
1534 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]);
1535 adev->mes.ring[0].sched.ready = false;
1536 }
1537
1538 if (amdgpu_sriov_vf(adev)) {
1539 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1540 mes_v11_0_kiq_clear(adev);
1541 }
1542
1543 mes_v11_0_enable(adev, false);
1544
1545 return 0;
1546 }
1547
mes_v11_0_hw_init(void * handle)1548 static int mes_v11_0_hw_init(void *handle)
1549 {
1550 int r;
1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1552
1553 if (adev->mes.ring[0].sched.ready)
1554 goto out;
1555
1556 if (!adev->enable_mes_kiq) {
1557 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1558 r = mes_v11_0_load_microcode(adev,
1559 AMDGPU_MES_SCHED_PIPE, true);
1560 if (r) {
1561 DRM_ERROR("failed to MES fw, r=%d\n", r);
1562 return r;
1563 }
1564 }
1565
1566 mes_v11_0_enable(adev, true);
1567 }
1568
1569 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1570 if (r)
1571 goto failure;
1572
1573 r = mes_v11_0_set_hw_resources(&adev->mes);
1574 if (r)
1575 goto failure;
1576
1577 if (amdgpu_sriov_is_mes_info_enable(adev)) {
1578 r = mes_v11_0_set_hw_resources_1(&adev->mes);
1579 if (r) {
1580 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1581 goto failure;
1582 }
1583 }
1584
1585 r = mes_v11_0_query_sched_status(&adev->mes);
1586 if (r) {
1587 DRM_ERROR("MES is busy\n");
1588 goto failure;
1589 }
1590
1591 out:
1592 /*
1593 * Disable KIQ ring usage from the driver once MES is enabled.
1594 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1595 * with MES enabled.
1596 */
1597 adev->gfx.kiq[0].ring.sched.ready = false;
1598 adev->mes.ring[0].sched.ready = true;
1599
1600 return 0;
1601
1602 failure:
1603 mes_v11_0_hw_fini(adev);
1604 return r;
1605 }
1606
mes_v11_0_hw_fini(void * handle)1607 static int mes_v11_0_hw_fini(void *handle)
1608 {
1609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1610 if (amdgpu_sriov_is_mes_info_enable(adev)) {
1611 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
1612 &adev->mes.resource_1_addr);
1613 }
1614 return 0;
1615 }
1616
mes_v11_0_suspend(void * handle)1617 static int mes_v11_0_suspend(void *handle)
1618 {
1619 int r;
1620 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1621
1622 r = amdgpu_mes_suspend(adev);
1623 if (r)
1624 return r;
1625
1626 return mes_v11_0_hw_fini(adev);
1627 }
1628
mes_v11_0_resume(void * handle)1629 static int mes_v11_0_resume(void *handle)
1630 {
1631 int r;
1632 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1633
1634 r = mes_v11_0_hw_init(adev);
1635 if (r)
1636 return r;
1637
1638 return amdgpu_mes_resume(adev);
1639 }
1640
mes_v11_0_early_init(void * handle)1641 static int mes_v11_0_early_init(void *handle)
1642 {
1643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1644 int pipe, r;
1645
1646 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1647 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1648 continue;
1649 r = amdgpu_mes_init_microcode(adev, pipe);
1650 if (r)
1651 return r;
1652 }
1653
1654 return 0;
1655 }
1656
mes_v11_0_late_init(void * handle)1657 static int mes_v11_0_late_init(void *handle)
1658 {
1659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1660
1661 /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1662 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
1663 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))
1664 amdgpu_mes_self_test(adev);
1665
1666 return 0;
1667 }
1668
1669 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1670 .name = "mes_v11_0",
1671 .early_init = mes_v11_0_early_init,
1672 .late_init = mes_v11_0_late_init,
1673 .sw_init = mes_v11_0_sw_init,
1674 .sw_fini = mes_v11_0_sw_fini,
1675 .hw_init = mes_v11_0_hw_init,
1676 .hw_fini = mes_v11_0_hw_fini,
1677 .suspend = mes_v11_0_suspend,
1678 .resume = mes_v11_0_resume,
1679 .dump_ip_state = NULL,
1680 .print_ip_state = NULL,
1681 };
1682
1683 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1684 .type = AMD_IP_BLOCK_TYPE_MES,
1685 .major = 11,
1686 .minor = 0,
1687 .rev = 0,
1688 .funcs = &mes_v11_0_ip_funcs,
1689 };
1690