1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc21.h"
29 #include "gc/gc_12_0_0_offset.h"
30 #include "gc/gc_12_0_0_sh_mask.h"
31 #include "gc/gc_11_0_0_default.h"
32 #include "v12_structs.h"
33 #include "mes_v12_api_def.h"
34
35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");
41
42 static int mes_v12_0_hw_init(void *handle);
43 static int mes_v12_0_hw_fini(void *handle);
44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);
46
47 #define MES_EOP_SIZE 2048
48
mes_v12_0_ring_set_wptr(struct amdgpu_ring * ring)49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
50 {
51 struct amdgpu_device *adev = ring->adev;
52
53 if (ring->use_doorbell) {
54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
55 ring->wptr);
56 WDOORBELL64(ring->doorbell_index, ring->wptr);
57 } else {
58 BUG();
59 }
60 }
61
mes_v12_0_ring_get_rptr(struct amdgpu_ring * ring)62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
63 {
64 return *ring->rptr_cpu_addr;
65 }
66
mes_v12_0_ring_get_wptr(struct amdgpu_ring * ring)67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
68 {
69 u64 wptr;
70
71 if (ring->use_doorbell)
72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
73 else
74 BUG();
75 return wptr;
76 }
77
78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
79 .type = AMDGPU_RING_TYPE_MES,
80 .align_mask = 1,
81 .nop = 0,
82 .support_64bit_ptrs = true,
83 .get_rptr = mes_v12_0_ring_get_rptr,
84 .get_wptr = mes_v12_0_ring_get_wptr,
85 .set_wptr = mes_v12_0_ring_set_wptr,
86 .insert_nop = amdgpu_ring_insert_nop,
87 };
88
89 static const char *mes_v12_0_opcodes[] = {
90 "SET_HW_RSRC",
91 "SET_SCHEDULING_CONFIG",
92 "ADD_QUEUE",
93 "REMOVE_QUEUE",
94 "PERFORM_YIELD",
95 "SET_GANG_PRIORITY_LEVEL",
96 "SUSPEND",
97 "RESUME",
98 "RESET",
99 "SET_LOG_BUFFER",
100 "CHANGE_GANG_PRORITY",
101 "QUERY_SCHEDULER_STATUS",
102 "unused",
103 "SET_DEBUG_VMID",
104 "MISC",
105 "UPDATE_ROOT_PAGE_TABLE",
106 "AMD_LOG",
107 "SET_SE_MODE",
108 "SET_GANG_SUBMIT",
109 "SET_HW_RSRC_1",
110 };
111
112 static const char *mes_v12_0_misc_opcodes[] = {
113 "WRITE_REG",
114 "INV_GART",
115 "QUERY_STATUS",
116 "READ_REG",
117 "WAIT_REG_MEM",
118 "SET_SHADER_DEBUGGER",
119 "NOTIFY_WORK_ON_UNMAPPED_QUEUE",
120 "NOTIFY_TO_UNMAP_PROCESSES",
121 };
122
mes_v12_0_get_op_string(union MESAPI__MISC * x_pkt)123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
124 {
125 const char *op_str = NULL;
126
127 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
128 op_str = mes_v12_0_opcodes[x_pkt->header.opcode];
129
130 return op_str;
131 }
132
mes_v12_0_get_misc_op_string(union MESAPI__MISC * x_pkt)133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
134 {
135 const char *op_str = NULL;
136
137 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
138 (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
139 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];
140
141 return op_str;
142 }
143
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,int pipe,void * pkt,int size,int api_status_off)144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
145 int pipe, void *pkt, int size,
146 int api_status_off)
147 {
148 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
149 signed long timeout = 2100000; /* 2100 ms */
150 struct amdgpu_device *adev = mes->adev;
151 struct amdgpu_ring *ring = &mes->ring[pipe];
152 spinlock_t *ring_lock = &mes->ring_lock[pipe];
153 struct MES_API_STATUS *api_status;
154 union MESAPI__MISC *x_pkt = pkt;
155 const char *op_str, *misc_op_str;
156 unsigned long flags;
157 u64 status_gpu_addr;
158 u32 seq, status_offset;
159 u64 *status_ptr;
160 signed long r;
161 int ret;
162
163 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
164 return -EINVAL;
165
166 if (amdgpu_emu_mode) {
167 timeout *= 100;
168 } else if (amdgpu_sriov_vf(adev)) {
169 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
170 timeout = 15 * 600 * 1000;
171 }
172
173 ret = amdgpu_device_wb_get(adev, &status_offset);
174 if (ret)
175 return ret;
176
177 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
178 status_ptr = (u64 *)&adev->wb.wb[status_offset];
179 *status_ptr = 0;
180
181 spin_lock_irqsave(ring_lock, flags);
182 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
183 if (r)
184 goto error_unlock_free;
185
186 seq = ++ring->fence_drv.sync_seq;
187 r = amdgpu_fence_wait_polling(ring,
188 seq - ring->fence_drv.num_fences_mask,
189 timeout);
190 if (r < 1)
191 goto error_undo;
192
193 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
194 api_status->api_completion_fence_addr = status_gpu_addr;
195 api_status->api_completion_fence_value = 1;
196
197 amdgpu_ring_write_multiple(ring, pkt, size / 4);
198
199 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
200 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
201 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
202 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
203 mes_status_pkt.api_status.api_completion_fence_addr =
204 ring->fence_drv.gpu_addr;
205 mes_status_pkt.api_status.api_completion_fence_value = seq;
206
207 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
208 sizeof(mes_status_pkt) / 4);
209
210 amdgpu_ring_commit(ring);
211 spin_unlock_irqrestore(ring_lock, flags);
212
213 op_str = mes_v12_0_get_op_string(x_pkt);
214 misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
215
216 if (misc_op_str)
217 dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n",
218 pipe, op_str, misc_op_str);
219 else if (op_str)
220 dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n",
221 pipe, op_str);
222 else
223 dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n",
224 pipe, x_pkt->header.opcode);
225
226 r = amdgpu_fence_wait_polling(ring, seq, timeout);
227 if (r < 1 || !*status_ptr) {
228
229 if (misc_op_str)
230 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n",
231 pipe, op_str, misc_op_str);
232 else if (op_str)
233 dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n",
234 pipe, op_str);
235 else
236 dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n",
237 pipe, x_pkt->header.opcode);
238
239 while (halt_if_hws_hang)
240 schedule();
241
242 r = -ETIMEDOUT;
243 goto error_wb_free;
244 }
245
246 amdgpu_device_wb_free(adev, status_offset);
247 return 0;
248
249 error_undo:
250 dev_err(adev->dev, "MES ring buffer is full.\n");
251 amdgpu_ring_undo(ring);
252
253 error_unlock_free:
254 spin_unlock_irqrestore(ring_lock, flags);
255
256 error_wb_free:
257 amdgpu_device_wb_free(adev, status_offset);
258 return r;
259 }
260
convert_to_mes_queue_type(int queue_type)261 static int convert_to_mes_queue_type(int queue_type)
262 {
263 if (queue_type == AMDGPU_RING_TYPE_GFX)
264 return MES_QUEUE_TYPE_GFX;
265 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
266 return MES_QUEUE_TYPE_COMPUTE;
267 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
268 return MES_QUEUE_TYPE_SDMA;
269 else if (queue_type == AMDGPU_RING_TYPE_MES)
270 return MES_QUEUE_TYPE_SCHQ;
271 else
272 BUG();
273 return -1;
274 }
275
mes_v12_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)276 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
277 struct mes_add_queue_input *input)
278 {
279 struct amdgpu_device *adev = mes->adev;
280 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
281 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
282 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
283
284 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
285
286 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
287 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
288 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
289
290 mes_add_queue_pkt.process_id = input->process_id;
291 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
292 mes_add_queue_pkt.process_va_start = input->process_va_start;
293 mes_add_queue_pkt.process_va_end = input->process_va_end;
294 mes_add_queue_pkt.process_quantum = input->process_quantum;
295 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
296 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
297 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
298 mes_add_queue_pkt.inprocess_gang_priority =
299 input->inprocess_gang_priority;
300 mes_add_queue_pkt.gang_global_priority_level =
301 input->gang_global_priority_level;
302 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
303 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
304
305 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
306
307 mes_add_queue_pkt.queue_type =
308 convert_to_mes_queue_type(input->queue_type);
309 mes_add_queue_pkt.paging = input->paging;
310 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
311 mes_add_queue_pkt.gws_base = input->gws_base;
312 mes_add_queue_pkt.gws_size = input->gws_size;
313 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
314 mes_add_queue_pkt.tma_addr = input->tma_addr;
315 mes_add_queue_pkt.trap_en = input->trap_en;
316 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
317 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
318
319 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
320 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
321 mes_add_queue_pkt.gds_size = input->queue_size;
322
323 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
324 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
325 mes_add_queue_pkt.gds_size = input->queue_size;
326
327 return mes_v12_0_submit_pkt_and_poll_completion(mes,
328 AMDGPU_MES_SCHED_PIPE,
329 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
330 offsetof(union MESAPI__ADD_QUEUE, api_status));
331 }
332
mes_v12_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)333 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
334 struct mes_remove_queue_input *input)
335 {
336 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
337
338 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
339
340 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
341 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
342 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
343
344 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
345 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
346
347 return mes_v12_0_submit_pkt_and_poll_completion(mes,
348 AMDGPU_MES_SCHED_PIPE,
349 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
350 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
351 }
352
mes_v12_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)353 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
354 struct mes_reset_queue_input *input)
355 {
356 union MESAPI__RESET mes_reset_queue_pkt;
357 int pipe;
358
359 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
360
361 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
362 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
363 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
364
365 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
366 mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;
367 /*mes_reset_queue_pkt.reset_queue_only = 1;*/
368
369 if (mes->adev->enable_uni_mes)
370 pipe = AMDGPU_MES_KIQ_PIPE;
371 else
372 pipe = AMDGPU_MES_SCHED_PIPE;
373
374 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
375 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
376 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
377 }
378
mes_v12_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)379 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
380 struct mes_map_legacy_queue_input *input)
381 {
382 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
383 int pipe;
384
385 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
386
387 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
388 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
389 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
390
391 mes_add_queue_pkt.pipe_id = input->pipe_id;
392 mes_add_queue_pkt.queue_id = input->queue_id;
393 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
394 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
395 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
396 mes_add_queue_pkt.queue_type =
397 convert_to_mes_queue_type(input->queue_type);
398 mes_add_queue_pkt.map_legacy_kq = 1;
399
400 if (mes->adev->enable_uni_mes)
401 pipe = AMDGPU_MES_KIQ_PIPE;
402 else
403 pipe = AMDGPU_MES_SCHED_PIPE;
404
405 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
406 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
407 offsetof(union MESAPI__ADD_QUEUE, api_status));
408 }
409
mes_v12_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)410 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
411 struct mes_unmap_legacy_queue_input *input)
412 {
413 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
414 int pipe;
415
416 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
417
418 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
419 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
420 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
421
422 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
423 mes_remove_queue_pkt.gang_context_addr = 0;
424
425 mes_remove_queue_pkt.pipe_id = input->pipe_id;
426 mes_remove_queue_pkt.queue_id = input->queue_id;
427
428 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
429 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
430 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
431 mes_remove_queue_pkt.tf_data =
432 lower_32_bits(input->trail_fence_data);
433 } else {
434 mes_remove_queue_pkt.unmap_legacy_queue = 1;
435 mes_remove_queue_pkt.queue_type =
436 convert_to_mes_queue_type(input->queue_type);
437 }
438
439 if (mes->adev->enable_uni_mes)
440 pipe = AMDGPU_MES_KIQ_PIPE;
441 else
442 pipe = AMDGPU_MES_SCHED_PIPE;
443
444 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
445 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
446 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
447 }
448
mes_v12_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)449 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
450 struct mes_suspend_gang_input *input)
451 {
452 return 0;
453 }
454
mes_v12_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)455 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
456 struct mes_resume_gang_input *input)
457 {
458 return 0;
459 }
460
mes_v12_0_query_sched_status(struct amdgpu_mes * mes,int pipe)461 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)
462 {
463 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
464
465 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
466
467 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
468 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
469 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
470
471 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
472 &mes_status_pkt, sizeof(mes_status_pkt),
473 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
474 }
475
mes_v12_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)476 static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
477 struct mes_misc_op_input *input)
478 {
479 union MESAPI__MISC misc_pkt;
480 int pipe;
481
482 if (mes->adev->enable_uni_mes)
483 pipe = AMDGPU_MES_KIQ_PIPE;
484 else
485 pipe = AMDGPU_MES_SCHED_PIPE;
486
487 memset(&misc_pkt, 0, sizeof(misc_pkt));
488
489 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
490 misc_pkt.header.opcode = MES_SCH_API_MISC;
491 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
492
493 switch (input->op) {
494 case MES_MISC_OP_READ_REG:
495 misc_pkt.opcode = MESAPI_MISC__READ_REG;
496 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
497 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
498 break;
499 case MES_MISC_OP_WRITE_REG:
500 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
501 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
502 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
503 break;
504 case MES_MISC_OP_WRM_REG_WAIT:
505 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
506 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
507 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
508 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
509 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
510 misc_pkt.wait_reg_mem.reg_offset2 = 0;
511 break;
512 case MES_MISC_OP_WRM_REG_WR_WAIT:
513 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
514 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
515 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
516 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
517 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
518 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
519 break;
520 case MES_MISC_OP_SET_SHADER_DEBUGGER:
521 pipe = AMDGPU_MES_SCHED_PIPE;
522 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
523 misc_pkt.set_shader_debugger.process_context_addr =
524 input->set_shader_debugger.process_context_addr;
525 misc_pkt.set_shader_debugger.flags.u32all =
526 input->set_shader_debugger.flags.u32all;
527 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
528 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
529 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
530 input->set_shader_debugger.tcp_watch_cntl,
531 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
532 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
533 break;
534 default:
535 DRM_ERROR("unsupported misc op (%d) \n", input->op);
536 return -EINVAL;
537 }
538
539 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
540 &misc_pkt, sizeof(misc_pkt),
541 offsetof(union MESAPI__MISC, api_status));
542 }
543
mes_v12_0_set_hw_resources_1(struct amdgpu_mes * mes,int pipe)544 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
545 {
546 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
547
548 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
549
550 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
551 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
552 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
553 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
554
555 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
556 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
557 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
558 }
559
mes_v12_0_set_hw_resources(struct amdgpu_mes * mes,int pipe)560 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
561 {
562 int i;
563 struct amdgpu_device *adev = mes->adev;
564 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
565
566 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
567
568 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
569 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
570 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
571
572 if (pipe == AMDGPU_MES_SCHED_PIPE) {
573 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
574 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
575 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
576 mes_set_hw_res_pkt.paging_vmid = 0;
577
578 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
579 mes_set_hw_res_pkt.compute_hqd_mask[i] =
580 mes->compute_hqd_mask[i];
581
582 for (i = 0; i < MAX_GFX_PIPES; i++)
583 mes_set_hw_res_pkt.gfx_hqd_mask[i] =
584 mes->gfx_hqd_mask[i];
585
586 for (i = 0; i < MAX_SDMA_PIPES; i++)
587 mes_set_hw_res_pkt.sdma_hqd_mask[i] =
588 mes->sdma_hqd_mask[i];
589
590 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
591 mes_set_hw_res_pkt.aggregated_doorbells[i] =
592 mes->aggregated_doorbells[i];
593 }
594
595 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
596 mes->sch_ctx_gpu_addr[pipe];
597 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
598 mes->query_status_fence_gpu_addr[pipe];
599
600 for (i = 0; i < 5; i++) {
601 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
602 mes_set_hw_res_pkt.mmhub_base[i] =
603 adev->reg_offset[MMHUB_HWIP][0][i];
604 mes_set_hw_res_pkt.osssys_base[i] =
605 adev->reg_offset[OSSSYS_HWIP][0][i];
606 }
607
608 mes_set_hw_res_pkt.disable_reset = 1;
609 mes_set_hw_res_pkt.disable_mes_log = 1;
610 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
611 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
612 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
613 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82)
614 mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
615 else
616 dev_info_once(adev->dev,
617 "MES FW version must be >= 0x82 to enable LR compute workaround.\n");
618
619 /*
620 * Keep oversubscribe timer for sdma . When we have unmapped doorbell
621 * handling support, other queue will not use the oversubscribe timer.
622 * handling mode - 0: disabled; 1: basic version; 2: basic+ version
623 */
624 mes_set_hw_res_pkt.oversubscription_timer = 50;
625 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
626
627 if (amdgpu_mes_log_enable) {
628 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
629 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE;
630 }
631
632 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
633 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
634 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
635 }
636
mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes * mes)637 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
638 {
639 struct amdgpu_device *adev = mes->adev;
640 uint32_t data;
641
642 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
643 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
644 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
645 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
646 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
647 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
648 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
649 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
650
651 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
652 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
653 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
654 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
655 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
656 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
657 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
658 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
659
660 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
661 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
662 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
663 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
664 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
665 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
666 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
667 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
668
669 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
670 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
671 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
672 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
673 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
674 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
675 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
676 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
677
678 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
679 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
680 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
681 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
682 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
683 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
684 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
685 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
686
687 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
688 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
689 }
690
691
mes_v12_0_enable_unmapped_doorbell_handling(struct amdgpu_mes * mes,bool enable)692 static void mes_v12_0_enable_unmapped_doorbell_handling(
693 struct amdgpu_mes *mes, bool enable)
694 {
695 struct amdgpu_device *adev = mes->adev;
696 uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);
697
698 /*
699 * The default PROC_LSB settng is 0xc which means doorbell
700 * addr[16:12] gives the doorbell page number. For kfd, each
701 * process will use 2 pages of doorbell, we need to change the
702 * setting to 0xd
703 */
704 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
705 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
706
707 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
708
709 WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);
710 }
711
mes_v12_0_reset_legacy_queue(struct amdgpu_mes * mes,struct mes_reset_legacy_queue_input * input)712 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes,
713 struct mes_reset_legacy_queue_input *input)
714 {
715 union MESAPI__RESET mes_reset_queue_pkt;
716 int pipe;
717
718 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
719
720 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
721 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
722 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
723
724 mes_reset_queue_pkt.queue_type =
725 convert_to_mes_queue_type(input->queue_type);
726
727 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {
728 mes_reset_queue_pkt.reset_legacy_gfx = 1;
729 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
730 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
731 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
732 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
733 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
734 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
735 } else {
736 mes_reset_queue_pkt.reset_queue_only = 1;
737 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
738 }
739
740 if (mes->adev->enable_uni_mes)
741 pipe = AMDGPU_MES_KIQ_PIPE;
742 else
743 pipe = AMDGPU_MES_SCHED_PIPE;
744
745 return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
746 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
747 offsetof(union MESAPI__RESET, api_status));
748 }
749
750 static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
751 .add_hw_queue = mes_v12_0_add_hw_queue,
752 .remove_hw_queue = mes_v12_0_remove_hw_queue,
753 .map_legacy_queue = mes_v12_0_map_legacy_queue,
754 .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,
755 .suspend_gang = mes_v12_0_suspend_gang,
756 .resume_gang = mes_v12_0_resume_gang,
757 .misc_op = mes_v12_0_misc_op,
758 .reset_legacy_queue = mes_v12_0_reset_legacy_queue,
759 .reset_hw_queue = mes_v12_0_reset_hw_queue,
760 };
761
mes_v12_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)762 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
763 enum admgpu_mes_pipe pipe)
764 {
765 int r;
766 const struct mes_firmware_header_v1_0 *mes_hdr;
767 const __le32 *fw_data;
768 unsigned fw_size;
769
770 mes_hdr = (const struct mes_firmware_header_v1_0 *)
771 adev->mes.fw[pipe]->data;
772
773 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
774 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
775 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
776
777 r = amdgpu_bo_create_reserved(adev, fw_size,
778 PAGE_SIZE,
779 AMDGPU_GEM_DOMAIN_VRAM,
780 &adev->mes.ucode_fw_obj[pipe],
781 &adev->mes.ucode_fw_gpu_addr[pipe],
782 (void **)&adev->mes.ucode_fw_ptr[pipe]);
783 if (r) {
784 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
785 return r;
786 }
787
788 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
789
790 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
791 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
792
793 return 0;
794 }
795
mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)796 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
797 enum admgpu_mes_pipe pipe)
798 {
799 int r;
800 const struct mes_firmware_header_v1_0 *mes_hdr;
801 const __le32 *fw_data;
802 unsigned fw_size;
803
804 mes_hdr = (const struct mes_firmware_header_v1_0 *)
805 adev->mes.fw[pipe]->data;
806
807 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
808 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
809 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
810
811 r = amdgpu_bo_create_reserved(adev, fw_size,
812 64 * 1024,
813 AMDGPU_GEM_DOMAIN_VRAM,
814 &adev->mes.data_fw_obj[pipe],
815 &adev->mes.data_fw_gpu_addr[pipe],
816 (void **)&adev->mes.data_fw_ptr[pipe]);
817 if (r) {
818 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
819 return r;
820 }
821
822 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
823
824 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
825 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
826
827 return 0;
828 }
829
mes_v12_0_free_ucode_buffers(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)830 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
831 enum admgpu_mes_pipe pipe)
832 {
833 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
834 &adev->mes.data_fw_gpu_addr[pipe],
835 (void **)&adev->mes.data_fw_ptr[pipe]);
836
837 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
838 &adev->mes.ucode_fw_gpu_addr[pipe],
839 (void **)&adev->mes.ucode_fw_ptr[pipe]);
840 }
841
mes_v12_0_enable(struct amdgpu_device * adev,bool enable)842 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
843 {
844 uint64_t ucode_addr;
845 uint32_t pipe, data = 0;
846
847 if (enable) {
848 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
849 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
850 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
851 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
852
853 mutex_lock(&adev->srbm_mutex);
854 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
855 soc21_grbm_select(adev, 3, pipe, 0, 0);
856
857 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
858 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
859 lower_32_bits(ucode_addr));
860 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
861 upper_32_bits(ucode_addr));
862 }
863 soc21_grbm_select(adev, 0, 0, 0, 0);
864 mutex_unlock(&adev->srbm_mutex);
865
866 /* unhalt MES and activate pipe0 */
867 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
868 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
869 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
870
871 if (amdgpu_emu_mode)
872 msleep(100);
873 else if (adev->enable_uni_mes)
874 udelay(500);
875 else
876 udelay(50);
877 } else {
878 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
879 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
880 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
881 data = REG_SET_FIELD(data, CP_MES_CNTL,
882 MES_INVALIDATE_ICACHE, 1);
883 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
884 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
885 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
886 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
887 }
888 }
889
mes_v12_0_set_ucode_start_addr(struct amdgpu_device * adev)890 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
891 {
892 uint64_t ucode_addr;
893 int pipe;
894
895 mes_v12_0_enable(adev, false);
896
897 mutex_lock(&adev->srbm_mutex);
898 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
899 /* me=3, queue=0 */
900 soc21_grbm_select(adev, 3, pipe, 0, 0);
901
902 /* set ucode start address */
903 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
904 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
905 lower_32_bits(ucode_addr));
906 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
907 upper_32_bits(ucode_addr));
908
909 soc21_grbm_select(adev, 0, 0, 0, 0);
910 }
911 mutex_unlock(&adev->srbm_mutex);
912 }
913
914 /* This function is for backdoor MES firmware */
mes_v12_0_load_microcode(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe,bool prime_icache)915 static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
916 enum admgpu_mes_pipe pipe, bool prime_icache)
917 {
918 int r;
919 uint32_t data;
920
921 mes_v12_0_enable(adev, false);
922
923 if (!adev->mes.fw[pipe])
924 return -EINVAL;
925
926 r = mes_v12_0_allocate_ucode_buffer(adev, pipe);
927 if (r)
928 return r;
929
930 r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);
931 if (r) {
932 mes_v12_0_free_ucode_buffers(adev, pipe);
933 return r;
934 }
935
936 mutex_lock(&adev->srbm_mutex);
937 /* me=3, pipe=0, queue=0 */
938 soc21_grbm_select(adev, 3, pipe, 0, 0);
939
940 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
941
942 /* set ucode fimrware address */
943 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
944 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
945 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
946 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
947
948 /* set ucode instruction cache boundary to 2M-1 */
949 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
950
951 /* set ucode data firmware address */
952 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
953 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
954 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
955 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
956
957 /* Set data cache boundary CP_MES_MDBOUND_LO */
958 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
959
960 if (prime_icache) {
961 /* invalidate ICACHE */
962 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
963 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
964 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
965 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
966
967 /* prime the ICACHE. */
968 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
969 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
970 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
971 }
972
973 soc21_grbm_select(adev, 0, 0, 0, 0);
974 mutex_unlock(&adev->srbm_mutex);
975
976 return 0;
977 }
978
mes_v12_0_allocate_eop_buf(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)979 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
980 enum admgpu_mes_pipe pipe)
981 {
982 int r;
983 u32 *eop;
984
985 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
986 AMDGPU_GEM_DOMAIN_GTT,
987 &adev->mes.eop_gpu_obj[pipe],
988 &adev->mes.eop_gpu_addr[pipe],
989 (void **)&eop);
990 if (r) {
991 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
992 return r;
993 }
994
995 memset(eop, 0,
996 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
997
998 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
999 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1000
1001 return 0;
1002 }
1003
mes_v12_0_mqd_init(struct amdgpu_ring * ring)1004 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
1005 {
1006 struct v12_compute_mqd *mqd = ring->mqd_ptr;
1007 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1008 uint32_t tmp;
1009
1010 mqd->header = 0xC0310800;
1011 mqd->compute_pipelinestat_enable = 0x00000001;
1012 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1013 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1014 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1015 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1016 mqd->compute_misc_reserved = 0x00000007;
1017
1018 eop_base_addr = ring->eop_gpu_addr >> 8;
1019
1020 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1021 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1022 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1023 (order_base_2(MES_EOP_SIZE / 4) - 1));
1024
1025 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1026 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1027 mqd->cp_hqd_eop_control = tmp;
1028
1029 /* disable the queue if it's active */
1030 ring->wptr = 0;
1031 mqd->cp_hqd_pq_rptr = 0;
1032 mqd->cp_hqd_pq_wptr_lo = 0;
1033 mqd->cp_hqd_pq_wptr_hi = 0;
1034
1035 /* set the pointer to the MQD */
1036 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1037 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1038
1039 /* set MQD vmid to 0 */
1040 tmp = regCP_MQD_CONTROL_DEFAULT;
1041 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1042 mqd->cp_mqd_control = tmp;
1043
1044 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1045 hqd_gpu_addr = ring->gpu_addr >> 8;
1046 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1047 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1048
1049 /* set the wb address whether it's enabled or not */
1050 wb_gpu_addr = ring->rptr_gpu_addr;
1051 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1052 mqd->cp_hqd_pq_rptr_report_addr_hi =
1053 upper_32_bits(wb_gpu_addr) & 0xffff;
1054
1055 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1056 wb_gpu_addr = ring->wptr_gpu_addr;
1057 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1058 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1059
1060 /* set up the HQD, this is similar to CP_RB0_CNTL */
1061 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1063 (order_base_2(ring->ring_size / 4) - 1));
1064 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1065 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1066 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1067 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1068 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1069 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1070 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1071 mqd->cp_hqd_pq_control = tmp;
1072
1073 /* enable doorbell */
1074 tmp = 0;
1075 if (ring->use_doorbell) {
1076 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1077 DOORBELL_OFFSET, ring->doorbell_index);
1078 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1079 DOORBELL_EN, 1);
1080 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1081 DOORBELL_SOURCE, 0);
1082 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1083 DOORBELL_HIT, 0);
1084 } else {
1085 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1086 DOORBELL_EN, 0);
1087 }
1088 mqd->cp_hqd_pq_doorbell_control = tmp;
1089
1090 mqd->cp_hqd_vmid = 0;
1091 /* activate the queue */
1092 mqd->cp_hqd_active = 1;
1093
1094 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1095 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1096 PRELOAD_SIZE, 0x55);
1097 mqd->cp_hqd_persistent_state = tmp;
1098
1099 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1100 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1101 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1102
1103 /*
1104 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
1105 * doorbell handling. This is a reserved CP internal register can
1106 * not be accesss by others
1107 */
1108 mqd->reserved_184 = BIT(15);
1109
1110 return 0;
1111 }
1112
mes_v12_0_queue_init_register(struct amdgpu_ring * ring)1113 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
1114 {
1115 struct v12_compute_mqd *mqd = ring->mqd_ptr;
1116 struct amdgpu_device *adev = ring->adev;
1117 uint32_t data = 0;
1118
1119 mutex_lock(&adev->srbm_mutex);
1120 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1121
1122 /* set CP_HQD_VMID.VMID = 0. */
1123 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1124 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1125 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1126
1127 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1128 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1129 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1130 DOORBELL_EN, 0);
1131 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1132
1133 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1134 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1135 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1136
1137 /* set CP_MQD_CONTROL.VMID=0 */
1138 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1139 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1140 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1141
1142 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1143 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1144 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1145
1146 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1147 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1148 mqd->cp_hqd_pq_rptr_report_addr_lo);
1149 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1150 mqd->cp_hqd_pq_rptr_report_addr_hi);
1151
1152 /* set CP_HQD_PQ_CONTROL */
1153 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1154
1155 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1156 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1157 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1158 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1159 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1160
1161 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1162 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1163 mqd->cp_hqd_pq_doorbell_control);
1164
1165 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1166 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1167
1168 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1169 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1170
1171 soc21_grbm_select(adev, 0, 0, 0, 0);
1172 mutex_unlock(&adev->srbm_mutex);
1173 }
1174
mes_v12_0_kiq_enable_queue(struct amdgpu_device * adev)1175 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
1176 {
1177 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1178 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1179 int r;
1180
1181 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1182 return -EINVAL;
1183
1184 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1185 if (r) {
1186 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1187 return r;
1188 }
1189
1190 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1191
1192 r = amdgpu_ring_test_ring(kiq_ring);
1193 if (r) {
1194 DRM_ERROR("kfq enable failed\n");
1195 kiq_ring->sched.ready = false;
1196 }
1197 return r;
1198 }
1199
mes_v12_0_queue_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1200 static int mes_v12_0_queue_init(struct amdgpu_device *adev,
1201 enum admgpu_mes_pipe pipe)
1202 {
1203 struct amdgpu_ring *ring;
1204 int r;
1205
1206 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1207 ring = &adev->gfx.kiq[0].ring;
1208 else
1209 ring = &adev->mes.ring[pipe];
1210
1211 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&
1212 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1213 *(ring->wptr_cpu_addr) = 0;
1214 *(ring->rptr_cpu_addr) = 0;
1215 amdgpu_ring_clear_ring(ring);
1216 }
1217
1218 r = mes_v12_0_mqd_init(ring);
1219 if (r)
1220 return r;
1221
1222 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1223 if (adev->enable_uni_mes)
1224 r = amdgpu_mes_map_legacy_queue(adev, ring);
1225 else
1226 r = mes_v12_0_kiq_enable_queue(adev);
1227 if (r)
1228 return r;
1229 } else {
1230 mes_v12_0_queue_init_register(ring);
1231 }
1232
1233 if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||
1234 ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {
1235 /* get MES scheduler/KIQ versions */
1236 mutex_lock(&adev->srbm_mutex);
1237 soc21_grbm_select(adev, 3, pipe, 0, 0);
1238
1239 if (pipe == AMDGPU_MES_SCHED_PIPE)
1240 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1241 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1242 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1243
1244 soc21_grbm_select(adev, 0, 0, 0, 0);
1245 mutex_unlock(&adev->srbm_mutex);
1246 }
1247
1248 return 0;
1249 }
1250
mes_v12_0_ring_init(struct amdgpu_device * adev,int pipe)1251 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)
1252 {
1253 struct amdgpu_ring *ring;
1254
1255 ring = &adev->mes.ring[pipe];
1256
1257 ring->funcs = &mes_v12_0_ring_funcs;
1258
1259 ring->me = 3;
1260 ring->pipe = pipe;
1261 ring->queue = 0;
1262
1263 ring->ring_obj = NULL;
1264 ring->use_doorbell = true;
1265 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];
1266 ring->no_scheduler = true;
1267 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1268
1269 if (pipe == AMDGPU_MES_SCHED_PIPE)
1270 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1271 else
1272 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1273
1274 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1275 AMDGPU_RING_PRIO_DEFAULT, NULL);
1276 }
1277
mes_v12_0_kiq_ring_init(struct amdgpu_device * adev)1278 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
1279 {
1280 struct amdgpu_ring *ring;
1281
1282 spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1283
1284 ring = &adev->gfx.kiq[0].ring;
1285
1286 ring->me = 3;
1287 ring->pipe = 1;
1288 ring->queue = 0;
1289
1290 ring->adev = NULL;
1291 ring->ring_obj = NULL;
1292 ring->use_doorbell = true;
1293 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1294 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1295 ring->no_scheduler = true;
1296 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1297 ring->me, ring->pipe, ring->queue);
1298
1299 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1300 AMDGPU_RING_PRIO_DEFAULT, NULL);
1301 }
1302
mes_v12_0_mqd_sw_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1303 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
1304 enum admgpu_mes_pipe pipe)
1305 {
1306 int r, mqd_size = sizeof(struct v12_compute_mqd);
1307 struct amdgpu_ring *ring;
1308
1309 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1310 ring = &adev->gfx.kiq[0].ring;
1311 else
1312 ring = &adev->mes.ring[pipe];
1313
1314 if (ring->mqd_obj)
1315 return 0;
1316
1317 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1318 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1319 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1320 if (r) {
1321 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1322 return r;
1323 }
1324
1325 memset(ring->mqd_ptr, 0, mqd_size);
1326
1327 /* prepare MQD backup */
1328 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1329 if (!adev->mes.mqd_backup[pipe])
1330 dev_warn(adev->dev,
1331 "no memory to create MQD backup for ring %s\n",
1332 ring->name);
1333
1334 return 0;
1335 }
1336
mes_v12_0_sw_init(void * handle)1337 static int mes_v12_0_sw_init(void *handle)
1338 {
1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340 int pipe, r;
1341
1342 adev->mes.funcs = &mes_v12_0_funcs;
1343 adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1344 adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1345 adev->mes.enable_legacy_queue_map = true;
1346
1347 adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE;
1348
1349 r = amdgpu_mes_init(adev);
1350 if (r)
1351 return r;
1352
1353 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1354 r = mes_v12_0_allocate_eop_buf(adev, pipe);
1355 if (r)
1356 return r;
1357
1358 r = mes_v12_0_mqd_sw_init(adev, pipe);
1359 if (r)
1360 return r;
1361
1362 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1363 r = mes_v12_0_kiq_ring_init(adev);
1364 else
1365 r = mes_v12_0_ring_init(adev, pipe);
1366 if (r)
1367 return r;
1368 }
1369
1370 return 0;
1371 }
1372
mes_v12_0_sw_fini(void * handle)1373 static int mes_v12_0_sw_fini(void *handle)
1374 {
1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1376 int pipe;
1377
1378 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1379 kfree(adev->mes.mqd_backup[pipe]);
1380
1381 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1382 &adev->mes.eop_gpu_addr[pipe],
1383 NULL);
1384 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1385
1386 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
1387 amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,
1388 &adev->mes.ring[pipe].mqd_gpu_addr,
1389 &adev->mes.ring[pipe].mqd_ptr);
1390 amdgpu_ring_fini(&adev->mes.ring[pipe]);
1391 }
1392 }
1393
1394 if (!adev->enable_uni_mes) {
1395 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1396 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1397 &adev->gfx.kiq[0].ring.mqd_ptr);
1398 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1399 }
1400
1401 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1402 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1403 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1404 }
1405
1406 amdgpu_mes_fini(adev);
1407 return 0;
1408 }
1409
mes_v12_0_kiq_dequeue_sched(struct amdgpu_device * adev)1410 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1411 {
1412 uint32_t data;
1413 int i;
1414
1415 mutex_lock(&adev->srbm_mutex);
1416 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1417
1418 /* disable the queue if it's active */
1419 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1420 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1421 for (i = 0; i < adev->usec_timeout; i++) {
1422 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1423 break;
1424 udelay(1);
1425 }
1426 }
1427 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1428 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1429 DOORBELL_EN, 0);
1430 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1431 DOORBELL_HIT, 1);
1432 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1433
1434 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1435
1436 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1437 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1438 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1439
1440 soc21_grbm_select(adev, 0, 0, 0, 0);
1441 mutex_unlock(&adev->srbm_mutex);
1442
1443 adev->mes.ring[0].sched.ready = false;
1444 }
1445
mes_v12_0_kiq_setting(struct amdgpu_ring * ring)1446 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
1447 {
1448 uint32_t tmp;
1449 struct amdgpu_device *adev = ring->adev;
1450
1451 /* tell RLC which is KIQ queue */
1452 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1453 tmp &= 0xffffff00;
1454 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1455 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1456 tmp |= 0x80;
1457 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1458 }
1459
mes_v12_0_kiq_hw_init(struct amdgpu_device * adev)1460 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
1461 {
1462 int r = 0;
1463
1464 if (adev->enable_uni_mes)
1465 mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]);
1466 else
1467 mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);
1468
1469 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1470
1471 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1472 if (r) {
1473 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1474 return r;
1475 }
1476
1477 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1478 if (r) {
1479 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1480 return r;
1481 }
1482
1483 mes_v12_0_set_ucode_start_addr(adev);
1484
1485 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1486 mes_v12_0_set_ucode_start_addr(adev);
1487
1488 mes_v12_0_enable(adev, true);
1489
1490 r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1491 if (r)
1492 goto failure;
1493
1494 if (adev->enable_uni_mes) {
1495 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1496 if (r)
1497 goto failure;
1498
1499 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1500 }
1501
1502 if (adev->mes.enable_legacy_queue_map) {
1503 r = mes_v12_0_hw_init(adev);
1504 if (r)
1505 goto failure;
1506 }
1507
1508 return r;
1509
1510 failure:
1511 mes_v12_0_hw_fini(adev);
1512 return r;
1513 }
1514
mes_v12_0_kiq_hw_fini(struct amdgpu_device * adev)1515 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
1516 {
1517 if (adev->mes.ring[0].sched.ready) {
1518 if (adev->enable_uni_mes)
1519 amdgpu_mes_unmap_legacy_queue(adev,
1520 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE],
1521 RESET_QUEUES, 0, 0);
1522 else
1523 mes_v12_0_kiq_dequeue_sched(adev);
1524
1525 adev->mes.ring[0].sched.ready = false;
1526 }
1527
1528 mes_v12_0_enable(adev, false);
1529
1530 return 0;
1531 }
1532
mes_v12_0_hw_init(void * handle)1533 static int mes_v12_0_hw_init(void *handle)
1534 {
1535 int r;
1536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1537
1538 if (adev->mes.ring[0].sched.ready)
1539 goto out;
1540
1541 if (!adev->enable_mes_kiq) {
1542 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1543 r = mes_v12_0_load_microcode(adev,
1544 AMDGPU_MES_SCHED_PIPE, true);
1545 if (r) {
1546 DRM_ERROR("failed to MES fw, r=%d\n", r);
1547 return r;
1548 }
1549
1550 mes_v12_0_set_ucode_start_addr(adev);
1551
1552 } else if (adev->firmware.load_type ==
1553 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1554
1555 mes_v12_0_set_ucode_start_addr(adev);
1556 }
1557
1558 mes_v12_0_enable(adev, true);
1559 }
1560
1561 /* Enable the MES to handle doorbell ring on unmapped queue */
1562 mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);
1563
1564 r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1565 if (r)
1566 goto failure;
1567
1568 r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1569 if (r)
1570 goto failure;
1571
1572 if (adev->enable_uni_mes)
1573 mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1574
1575 mes_v12_0_init_aggregated_doorbell(&adev->mes);
1576
1577 r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1578 if (r) {
1579 DRM_ERROR("MES is busy\n");
1580 goto failure;
1581 }
1582
1583 out:
1584 /*
1585 * Disable KIQ ring usage from the driver once MES is enabled.
1586 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1587 * with MES enabled.
1588 */
1589 adev->gfx.kiq[0].ring.sched.ready = false;
1590 adev->mes.ring[0].sched.ready = true;
1591
1592 return 0;
1593
1594 failure:
1595 mes_v12_0_hw_fini(adev);
1596 return r;
1597 }
1598
mes_v12_0_hw_fini(void * handle)1599 static int mes_v12_0_hw_fini(void *handle)
1600 {
1601 return 0;
1602 }
1603
mes_v12_0_suspend(void * handle)1604 static int mes_v12_0_suspend(void *handle)
1605 {
1606 int r;
1607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608
1609 r = amdgpu_mes_suspend(adev);
1610 if (r)
1611 return r;
1612
1613 return mes_v12_0_hw_fini(adev);
1614 }
1615
mes_v12_0_resume(void * handle)1616 static int mes_v12_0_resume(void *handle)
1617 {
1618 int r;
1619 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1620
1621 r = mes_v12_0_hw_init(adev);
1622 if (r)
1623 return r;
1624
1625 return amdgpu_mes_resume(adev);
1626 }
1627
mes_v12_0_early_init(void * handle)1628 static int mes_v12_0_early_init(void *handle)
1629 {
1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1631 int pipe, r;
1632
1633 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1634 r = amdgpu_mes_init_microcode(adev, pipe);
1635 if (r)
1636 return r;
1637 }
1638
1639 return 0;
1640 }
1641
mes_v12_0_late_init(void * handle)1642 static int mes_v12_0_late_init(void *handle)
1643 {
1644 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1645
1646 /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1647 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
1648 amdgpu_mes_self_test(adev);
1649
1650 return 0;
1651 }
1652
1653 static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
1654 .name = "mes_v12_0",
1655 .early_init = mes_v12_0_early_init,
1656 .late_init = mes_v12_0_late_init,
1657 .sw_init = mes_v12_0_sw_init,
1658 .sw_fini = mes_v12_0_sw_fini,
1659 .hw_init = mes_v12_0_hw_init,
1660 .hw_fini = mes_v12_0_hw_fini,
1661 .suspend = mes_v12_0_suspend,
1662 .resume = mes_v12_0_resume,
1663 };
1664
1665 const struct amdgpu_ip_block_version mes_v12_0_ip_block = {
1666 .type = AMD_IP_BLOCK_TYPE_MES,
1667 .major = 12,
1668 .minor = 0,
1669 .rev = 0,
1670 .funcs = &mes_v12_0_ip_funcs,
1671 };
1672