1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "mmhub_v1_8.h"
25
26 #include "mmhub/mmhub_1_8_0_offset.h"
27 #include "mmhub/mmhub_1_8_0_sh_mask.h"
28 #include "vega10_enum.h"
29
30 #include "soc15_common.h"
31 #include "soc15.h"
32 #include "amdgpu_ras.h"
33
34 #define regVM_L2_CNTL3_DEFAULT 0x80100007
35 #define regVM_L2_CNTL4_DEFAULT 0x000000c1
36 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
37
mmhub_v1_8_get_fb_location(struct amdgpu_device * adev)38 static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)
39 {
40 u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
41 u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
42
43 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
44 base <<= 24;
45
46 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
47 top <<= 24;
48
49 adev->gmc.fb_start = base;
50 adev->gmc.fb_end = top;
51
52 return base;
53 }
54
mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)55 static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
56 uint64_t page_table_base)
57 {
58 struct amdgpu_vmhub *hub;
59 u32 inst_mask;
60 int i;
61
62 inst_mask = adev->aid_mask;
63 for_each_inst(i, inst_mask) {
64 hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
65 WREG32_SOC15_OFFSET(MMHUB, i,
66 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
67 hub->ctx_addr_distance * vmid,
68 lower_32_bits(page_table_base));
69
70 WREG32_SOC15_OFFSET(MMHUB, i,
71 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
72 hub->ctx_addr_distance * vmid,
73 upper_32_bits(page_table_base));
74 }
75 }
76
mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device * adev)77 static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
78 {
79 uint64_t pt_base;
80 u32 inst_mask;
81 int i;
82
83 if (adev->gmc.pdb0_bo)
84 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
85 else
86 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
87
88 mmhub_v1_8_setup_vm_pt_regs(adev, 0, pt_base);
89
90 /* If use GART for FB translation, vmid0 page table covers both
91 * vram and system memory (gart)
92 */
93 inst_mask = adev->aid_mask;
94 for_each_inst(i, inst_mask) {
95 if (adev->gmc.pdb0_bo) {
96 WREG32_SOC15(MMHUB, i,
97 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
98 (u32)(adev->gmc.fb_start >> 12));
99 WREG32_SOC15(MMHUB, i,
100 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
101 (u32)(adev->gmc.fb_start >> 44));
102
103 WREG32_SOC15(MMHUB, i,
104 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
105 (u32)(adev->gmc.gart_end >> 12));
106 WREG32_SOC15(MMHUB, i,
107 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
108 (u32)(adev->gmc.gart_end >> 44));
109
110 } else {
111 WREG32_SOC15(MMHUB, i,
112 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
113 (u32)(adev->gmc.gart_start >> 12));
114 WREG32_SOC15(MMHUB, i,
115 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
116 (u32)(adev->gmc.gart_start >> 44));
117
118 WREG32_SOC15(MMHUB, i,
119 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
120 (u32)(adev->gmc.gart_end >> 12));
121 WREG32_SOC15(MMHUB, i,
122 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
123 (u32)(adev->gmc.gart_end >> 44));
124 }
125 }
126 }
127
mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device * adev)128 static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
129 {
130 uint32_t tmp, inst_mask;
131 uint64_t value;
132 int i;
133
134 if (amdgpu_sriov_vf(adev))
135 return;
136
137 inst_mask = adev->aid_mask;
138 for_each_inst(i, inst_mask) {
139 /* Program the AGP BAR */
140 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
141 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
142 adev->gmc.agp_start >> 24);
143 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
144 adev->gmc.agp_end >> 24);
145
146 /* Program the system aperture low logical page number. */
147 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
148 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
149
150 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
151 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
152
153 /* In the case squeezing vram into GART aperture, we don't use
154 * FB aperture and AGP aperture. Disable them.
155 */
156 if (adev->gmc.pdb0_bo) {
157 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, 0xFFFFFF);
158 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP, 0);
159 WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_TOP, 0);
160 WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_BASE,
161 0x00FFFFFF);
162 WREG32_SOC15(MMHUB, i,
163 regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
164 0x3FFFFFFF);
165 WREG32_SOC15(MMHUB, i,
166 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
167 }
168
169 /* Set default page address. */
170 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
171 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
172 (u32)(value >> 12));
173 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
174 (u32)(value >> 44));
175
176 /* Program "protection fault". */
177 WREG32_SOC15(MMHUB, i,
178 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
179 (u32)(adev->dummy_page_addr >> 12));
180 WREG32_SOC15(MMHUB, i,
181 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
182 (u32)((u64)adev->dummy_page_addr >> 44));
183
184 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);
185 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
186 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
187 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
188 }
189 }
190
mmhub_v1_8_init_tlb_regs(struct amdgpu_device * adev)191 static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
192 {
193 uint32_t tmp, inst_mask;
194 int i;
195
196 /* Setup TLB control */
197 inst_mask = adev->aid_mask;
198 for_each_inst(i, inst_mask) {
199 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
200
201 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
202 1);
203 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
204 SYSTEM_ACCESS_MODE, 3);
205 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
206 ENABLE_ADVANCED_DRIVER_MODEL, 1);
207 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
208 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
209 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
210 MTYPE, MTYPE_UC);/* XXX for emulation. */
211 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
212
213 WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
214 }
215 }
216
217 /* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */
mmhub_v1_8_init_snoop_override_regs(struct amdgpu_device * adev)218 static void mmhub_v1_8_init_snoop_override_regs(struct amdgpu_device *adev)
219 {
220 uint32_t tmp, inst_mask;
221 int i, j;
222 uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -
223 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;
224
225 inst_mask = adev->aid_mask;
226 for_each_inst(i, inst_mask) {
227 for (j = 0; j < 5; j++) { /* DAGB instances */
228 tmp = RREG32_SOC15_OFFSET(MMHUB, i,
229 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance);
230 tmp |= (1 << 15); /* SDMA client is BIT15 */
231 WREG32_SOC15_OFFSET(MMHUB, i,
232 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance, tmp);
233
234 tmp = RREG32_SOC15_OFFSET(MMHUB, i,
235 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance);
236 tmp |= (1 << 15);
237 WREG32_SOC15_OFFSET(MMHUB, i,
238 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance, tmp);
239 }
240 }
241 }
242
mmhub_v1_8_init_cache_regs(struct amdgpu_device * adev)243 static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
244 {
245 uint32_t tmp, inst_mask;
246 int i;
247
248 if (amdgpu_sriov_vf(adev))
249 return;
250
251 /* Setup L2 cache */
252 inst_mask = adev->aid_mask;
253 for_each_inst(i, inst_mask) {
254 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
255 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
256 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
257 ENABLE_L2_FRAGMENT_PROCESSING, 1);
258 /* XXX for emulation, Refer to closed source code.*/
259 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
260 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
261 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,
262 0);
263 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
264 CONTEXT1_IDENTITY_ACCESS_MODE, 1);
265 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
266 IDENTITY_MODE_FRAGMENT_SIZE, 0);
267 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);
268
269 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);
270 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,
271 1);
272 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
273 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);
274
275 tmp = regVM_L2_CNTL3_DEFAULT;
276 if (adev->gmc.translate_further) {
277 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
278 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
279 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
280 } else {
281 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
282 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
283 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
284 }
285 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
286
287 tmp = regVM_L2_CNTL4_DEFAULT;
288 /* For AMD APP APUs setup WC memory */
289 if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {
290 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
291 VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
292 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
293 VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
294 } else {
295 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
296 VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
297 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
298 VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
299 }
300 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
301 }
302 }
303
mmhub_v1_8_enable_system_domain(struct amdgpu_device * adev)304 static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
305 {
306 uint32_t tmp, inst_mask;
307 int i;
308
309 inst_mask = adev->aid_mask;
310 for_each_inst(i, inst_mask) {
311 tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
312 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
313 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
314 adev->gmc.vmid0_page_table_depth);
315 tmp = REG_SET_FIELD(tmp,
316 VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
317 adev->gmc.vmid0_page_table_block_size);
318 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
319 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
320 WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);
321 }
322 }
323
mmhub_v1_8_disable_identity_aperture(struct amdgpu_device * adev)324 static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
325 {
326 u32 inst_mask;
327 int i;
328
329 if (amdgpu_sriov_vf(adev))
330 return;
331
332 inst_mask = adev->aid_mask;
333 for_each_inst(i, inst_mask) {
334 WREG32_SOC15(MMHUB, i,
335 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
336 0XFFFFFFFF);
337 WREG32_SOC15(MMHUB, i,
338 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
339 0x0000000F);
340
341 WREG32_SOC15(MMHUB, i,
342 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
343 0);
344 WREG32_SOC15(MMHUB, i,
345 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
346 0);
347
348 WREG32_SOC15(MMHUB, i,
349 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
350 WREG32_SOC15(MMHUB, i,
351 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
352 }
353 }
354
mmhub_v1_8_setup_vmid_config(struct amdgpu_device * adev)355 static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
356 {
357 struct amdgpu_vmhub *hub;
358 unsigned int num_level, block_size;
359 uint32_t tmp, inst_mask;
360 int i, j;
361
362 num_level = adev->vm_manager.num_level;
363 block_size = adev->vm_manager.block_size;
364 if (adev->gmc.translate_further)
365 num_level -= 1;
366 else
367 block_size -= 9;
368
369 inst_mask = adev->aid_mask;
370 for_each_inst(j, inst_mask) {
371 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
372 for (i = 0; i <= 14; i++) {
373 tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
374 i * hub->ctx_distance);
375 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
376 ENABLE_CONTEXT, 1);
377 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
378 PAGE_TABLE_DEPTH, num_level);
379 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
380 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
381 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
382 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
383 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
384 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
385 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
386 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
387 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
388 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
389 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
390 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
391 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
392 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
393 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
394 PAGE_TABLE_BLOCK_SIZE,
395 block_size);
396 /* On 9.4.3, XNACK can be enabled in the SQ
397 * per-process. Retry faults need to be enabled for
398 * that to work.
399 */
400 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
401 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1);
402 WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
403 i * hub->ctx_distance, tmp);
404 WREG32_SOC15_OFFSET(MMHUB, j,
405 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
406 i * hub->ctx_addr_distance, 0);
407 WREG32_SOC15_OFFSET(MMHUB, j,
408 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
409 i * hub->ctx_addr_distance, 0);
410 WREG32_SOC15_OFFSET(MMHUB, j,
411 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
412 i * hub->ctx_addr_distance,
413 lower_32_bits(adev->vm_manager.max_pfn - 1));
414 WREG32_SOC15_OFFSET(MMHUB, j,
415 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
416 i * hub->ctx_addr_distance,
417 upper_32_bits(adev->vm_manager.max_pfn - 1));
418 }
419 }
420 }
421
mmhub_v1_8_program_invalidation(struct amdgpu_device * adev)422 static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
423 {
424 struct amdgpu_vmhub *hub;
425 u32 i, j, inst_mask;
426
427 inst_mask = adev->aid_mask;
428 for_each_inst(j, inst_mask) {
429 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
430 for (i = 0; i < 18; ++i) {
431 WREG32_SOC15_OFFSET(MMHUB, j,
432 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
433 i * hub->eng_addr_distance, 0xffffffff);
434 WREG32_SOC15_OFFSET(MMHUB, j,
435 regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
436 i * hub->eng_addr_distance, 0x1f);
437 }
438 }
439 }
440
mmhub_v1_8_gart_enable(struct amdgpu_device * adev)441 static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
442 {
443 /* GART Enable. */
444 mmhub_v1_8_init_gart_aperture_regs(adev);
445 mmhub_v1_8_init_system_aperture_regs(adev);
446 mmhub_v1_8_init_tlb_regs(adev);
447 mmhub_v1_8_init_cache_regs(adev);
448 mmhub_v1_8_init_snoop_override_regs(adev);
449
450 mmhub_v1_8_enable_system_domain(adev);
451 mmhub_v1_8_disable_identity_aperture(adev);
452 mmhub_v1_8_setup_vmid_config(adev);
453 mmhub_v1_8_program_invalidation(adev);
454
455 return 0;
456 }
457
mmhub_v1_8_gart_disable(struct amdgpu_device * adev)458 static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
459 {
460 struct amdgpu_vmhub *hub;
461 u32 tmp;
462 u32 i, j, inst_mask;
463
464 /* Disable all tables */
465 inst_mask = adev->aid_mask;
466 for_each_inst(j, inst_mask) {
467 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
468 for (i = 0; i < 16; i++)
469 WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,
470 i * hub->ctx_distance, 0);
471
472 /* Setup TLB control */
473 tmp = RREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL);
474 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
475 0);
476 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
477 ENABLE_ADVANCED_DRIVER_MODEL, 0);
478 WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp);
479
480 if (!amdgpu_sriov_vf(adev)) {
481 /* Setup L2 cache */
482 tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);
483 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,
484 0);
485 WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);
486 WREG32_SOC15(MMHUB, j, regVM_L2_CNTL3, 0);
487 }
488 }
489 }
490
491 /**
492 * mmhub_v1_8_set_fault_enable_default - update GART/VM fault handling
493 *
494 * @adev: amdgpu_device pointer
495 * @value: true redirects VM faults to the default page
496 */
mmhub_v1_8_set_fault_enable_default(struct amdgpu_device * adev,bool value)497 static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
498 {
499 u32 tmp, inst_mask;
500 int i;
501
502 if (amdgpu_sriov_vf(adev))
503 return;
504
505 inst_mask = adev->aid_mask;
506 for_each_inst(i, inst_mask) {
507 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
508 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
509 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
510 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
511 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
512 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
513 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
514 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
515 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
516 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
517 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
518 value);
519 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
520 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
521 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
522 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
523 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
524 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
525 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
526 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
527 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
528 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
529 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
530 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
531 if (!value) {
532 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
533 CRASH_ON_NO_RETRY_FAULT, 1);
534 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
535 CRASH_ON_RETRY_FAULT, 1);
536 }
537
538 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
539 }
540 }
541
mmhub_v1_8_init(struct amdgpu_device * adev)542 static void mmhub_v1_8_init(struct amdgpu_device *adev)
543 {
544 struct amdgpu_vmhub *hub;
545 u32 inst_mask;
546 int i;
547
548 inst_mask = adev->aid_mask;
549 for_each_inst(i, inst_mask) {
550 hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
551
552 hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, i,
553 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
554 hub->ctx0_ptb_addr_hi32 = SOC15_REG_OFFSET(MMHUB, i,
555 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
556 hub->vm_inv_eng0_req =
557 SOC15_REG_OFFSET(MMHUB, i, regVM_INVALIDATE_ENG0_REQ);
558 hub->vm_inv_eng0_ack =
559 SOC15_REG_OFFSET(MMHUB, i, regVM_INVALIDATE_ENG0_ACK);
560 hub->vm_context0_cntl =
561 SOC15_REG_OFFSET(MMHUB, i, regVM_CONTEXT0_CNTL);
562 hub->vm_l2_pro_fault_status = SOC15_REG_OFFSET(MMHUB, i,
563 regVM_L2_PROTECTION_FAULT_STATUS);
564 hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(MMHUB, i,
565 regVM_L2_PROTECTION_FAULT_CNTL);
566
567 hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
568 hub->ctx_addr_distance =
569 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
570 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
571 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ -
572 regVM_INVALIDATE_ENG0_REQ;
573 hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
574 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
575 }
576 }
577
mmhub_v1_8_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)578 static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,
579 enum amd_clockgating_state state)
580 {
581 return 0;
582 }
583
mmhub_v1_8_get_clockgating(struct amdgpu_device * adev,u64 * flags)584 static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)
585 {
586
587 }
588
589 const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = {
590 .get_fb_location = mmhub_v1_8_get_fb_location,
591 .init = mmhub_v1_8_init,
592 .gart_enable = mmhub_v1_8_gart_enable,
593 .set_fault_enable_default = mmhub_v1_8_set_fault_enable_default,
594 .gart_disable = mmhub_v1_8_gart_disable,
595 .setup_vm_pt_regs = mmhub_v1_8_setup_vm_pt_regs,
596 .set_clockgating = mmhub_v1_8_set_clockgating,
597 .get_clockgating = mmhub_v1_8_get_clockgating,
598 };
599
600 static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ce_reg_list[] = {
601 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA0_CE_ERR_STATUS_LO, regMMEA0_CE_ERR_STATUS_HI),
602 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA0"},
603 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA1_CE_ERR_STATUS_LO, regMMEA1_CE_ERR_STATUS_HI),
604 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA1"},
605 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA2_CE_ERR_STATUS_LO, regMMEA2_CE_ERR_STATUS_HI),
606 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA2"},
607 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA3_CE_ERR_STATUS_LO, regMMEA3_CE_ERR_STATUS_HI),
608 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA3"},
609 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA4_CE_ERR_STATUS_LO, regMMEA4_CE_ERR_STATUS_HI),
610 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA4"},
611 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMM_CANE_CE_ERR_STATUS_LO, regMM_CANE_CE_ERR_STATUS_HI),
612 1, 0, "MM_CANE"},
613 };
614
615 static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ue_reg_list[] = {
616 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA0_UE_ERR_STATUS_LO, regMMEA0_UE_ERR_STATUS_HI),
617 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA0"},
618 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA1_UE_ERR_STATUS_LO, regMMEA1_UE_ERR_STATUS_HI),
619 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA1"},
620 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA2_UE_ERR_STATUS_LO, regMMEA2_UE_ERR_STATUS_HI),
621 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA2"},
622 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA3_UE_ERR_STATUS_LO, regMMEA3_UE_ERR_STATUS_HI),
623 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA3"},
624 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMMEA4_UE_ERR_STATUS_LO, regMMEA4_UE_ERR_STATUS_HI),
625 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA4"},
626 {AMDGPU_RAS_REG_ENTRY(MMHUB, 0, regMM_CANE_UE_ERR_STATUS_LO, regMM_CANE_UE_ERR_STATUS_HI),
627 1, 0, "MM_CANE"},
628 };
629
630 static const struct amdgpu_ras_memory_id_entry mmhub_v1_8_ras_memory_list[] = {
631 {AMDGPU_MMHUB_WGMI_PAGEMEM, "MMEA_WGMI_PAGEMEM"},
632 {AMDGPU_MMHUB_RGMI_PAGEMEM, "MMEA_RGMI_PAGEMEM"},
633 {AMDGPU_MMHUB_WDRAM_PAGEMEM, "MMEA_WDRAM_PAGEMEM"},
634 {AMDGPU_MMHUB_RDRAM_PAGEMEM, "MMEA_RDRAM_PAGEMEM"},
635 {AMDGPU_MMHUB_WIO_CMDMEM, "MMEA_WIO_CMDMEM"},
636 {AMDGPU_MMHUB_RIO_CMDMEM, "MMEA_RIO_CMDMEM"},
637 {AMDGPU_MMHUB_WGMI_CMDMEM, "MMEA_WGMI_CMDMEM"},
638 {AMDGPU_MMHUB_RGMI_CMDMEM, "MMEA_RGMI_CMDMEM"},
639 {AMDGPU_MMHUB_WDRAM_CMDMEM, "MMEA_WDRAM_CMDMEM"},
640 {AMDGPU_MMHUB_RDRAM_CMDMEM, "MMEA_RDRAM_CMDMEM"},
641 {AMDGPU_MMHUB_MAM_DMEM0, "MMEA_MAM_DMEM0"},
642 {AMDGPU_MMHUB_MAM_DMEM1, "MMEA_MAM_DMEM1"},
643 {AMDGPU_MMHUB_MAM_DMEM2, "MMEA_MAM_DMEM2"},
644 {AMDGPU_MMHUB_MAM_DMEM3, "MMEA_MAM_DMEM3"},
645 {AMDGPU_MMHUB_WRET_TAGMEM, "MMEA_WRET_TAGMEM"},
646 {AMDGPU_MMHUB_RRET_TAGMEM, "MMEA_RRET_TAGMEM"},
647 {AMDGPU_MMHUB_WIO_DATAMEM, "MMEA_WIO_DATAMEM"},
648 {AMDGPU_MMHUB_WGMI_DATAMEM, "MMEA_WGMI_DATAMEM"},
649 {AMDGPU_MMHUB_WDRAM_DATAMEM, "MMEA_WDRAM_DATAMEM"},
650 };
651
mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device * adev,uint32_t mmhub_inst,void * ras_err_status)652 static void mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device *adev,
653 uint32_t mmhub_inst,
654 void *ras_err_status)
655 {
656 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
657 unsigned long ue_count = 0, ce_count = 0;
658
659 /* NOTE: mmhub is converted by aid_mask and the range is 0-3,
660 * which can be used as die ID directly */
661 struct amdgpu_smuio_mcm_config_info mcm_info = {
662 .socket_id = adev->smuio.funcs->get_socket_id(adev),
663 .die_id = mmhub_inst,
664 };
665
666 amdgpu_ras_inst_query_ras_error_count(adev,
667 mmhub_v1_8_ce_reg_list,
668 ARRAY_SIZE(mmhub_v1_8_ce_reg_list),
669 mmhub_v1_8_ras_memory_list,
670 ARRAY_SIZE(mmhub_v1_8_ras_memory_list),
671 mmhub_inst,
672 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
673 &ce_count);
674 amdgpu_ras_inst_query_ras_error_count(adev,
675 mmhub_v1_8_ue_reg_list,
676 ARRAY_SIZE(mmhub_v1_8_ue_reg_list),
677 mmhub_v1_8_ras_memory_list,
678 ARRAY_SIZE(mmhub_v1_8_ras_memory_list),
679 mmhub_inst,
680 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
681 &ue_count);
682
683 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count);
684 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
685 }
686
mmhub_v1_8_query_ras_error_count(struct amdgpu_device * adev,void * ras_err_status)687 static void mmhub_v1_8_query_ras_error_count(struct amdgpu_device *adev,
688 void *ras_err_status)
689 {
690 uint32_t inst_mask;
691 uint32_t i;
692
693 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
694 dev_warn(adev->dev, "MMHUB RAS is not supported\n");
695 return;
696 }
697
698 inst_mask = adev->aid_mask;
699 for_each_inst(i, inst_mask)
700 mmhub_v1_8_inst_query_ras_error_count(adev, i, ras_err_status);
701 }
702
mmhub_v1_8_inst_reset_ras_error_count(struct amdgpu_device * adev,uint32_t mmhub_inst)703 static void mmhub_v1_8_inst_reset_ras_error_count(struct amdgpu_device *adev,
704 uint32_t mmhub_inst)
705 {
706 amdgpu_ras_inst_reset_ras_error_count(adev,
707 mmhub_v1_8_ce_reg_list,
708 ARRAY_SIZE(mmhub_v1_8_ce_reg_list),
709 mmhub_inst);
710 amdgpu_ras_inst_reset_ras_error_count(adev,
711 mmhub_v1_8_ue_reg_list,
712 ARRAY_SIZE(mmhub_v1_8_ue_reg_list),
713 mmhub_inst);
714 }
715
mmhub_v1_8_reset_ras_error_count(struct amdgpu_device * adev)716 static void mmhub_v1_8_reset_ras_error_count(struct amdgpu_device *adev)
717 {
718 uint32_t inst_mask;
719 uint32_t i;
720
721 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
722 dev_warn(adev->dev, "MMHUB RAS is not supported\n");
723 return;
724 }
725
726 inst_mask = adev->aid_mask;
727 for_each_inst(i, inst_mask)
728 mmhub_v1_8_inst_reset_ras_error_count(adev, i);
729 }
730
731 static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = {
732 .query_ras_error_count = mmhub_v1_8_query_ras_error_count,
733 .reset_ras_error_count = mmhub_v1_8_reset_ras_error_count,
734 };
735
mmhub_v1_8_aca_bank_parser(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)736 static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
737 enum aca_smu_type type, void *data)
738 {
739 struct aca_bank_info info;
740 u64 misc0;
741 int ret;
742
743 ret = aca_bank_info_decode(bank, &info);
744 if (ret)
745 return ret;
746
747 misc0 = bank->regs[ACA_REG_IDX_MISC0];
748 switch (type) {
749 case ACA_SMU_TYPE_UE:
750 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
751 1ULL);
752 break;
753 case ACA_SMU_TYPE_CE:
754 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE,
755 ACA_REG__MISC0__ERRCNT(misc0));
756 break;
757 default:
758 return -EINVAL;
759 }
760
761 return ret;
762 }
763
764 /* reference to smu driver if header file */
765 static int mmhub_v1_8_err_codes[] = {
766 0, 1, 2, 3, 4, /* CODE_DAGB0 - 4 */
767 5, 6, 7, 8, 9, /* CODE_EA0 - 4 */
768 10, /* CODE_UTCL2_ROUTER */
769 11, /* CODE_VML2 */
770 12, /* CODE_VML2_WALKER */
771 13, /* CODE_MMCANE */
772 };
773
mmhub_v1_8_aca_bank_is_valid(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)774 static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
775 enum aca_smu_type type, void *data)
776 {
777 u32 instlo;
778
779 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
780 instlo &= GENMASK(31, 1);
781
782 if (instlo != mmSMNAID_AID0_MCA_SMU)
783 return false;
784
785 if (aca_bank_check_error_codes(handle->adev, bank,
786 mmhub_v1_8_err_codes,
787 ARRAY_SIZE(mmhub_v1_8_err_codes)))
788 return false;
789
790 return true;
791 }
792
793 static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = {
794 .aca_bank_parser = mmhub_v1_8_aca_bank_parser,
795 .aca_bank_is_valid = mmhub_v1_8_aca_bank_is_valid,
796 };
797
798 static const struct aca_info mmhub_v1_8_aca_info = {
799 .hwip = ACA_HWIP_TYPE_SMU,
800 .mask = ACA_ERROR_UE_MASK,
801 .bank_ops = &mmhub_v1_8_aca_bank_ops,
802 };
803
mmhub_v1_8_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)804 static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
805 {
806 int r;
807
808 r = amdgpu_ras_block_late_init(adev, ras_block);
809 if (r)
810 return r;
811
812 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__MMHUB,
813 &mmhub_v1_8_aca_info, NULL);
814 if (r)
815 goto late_fini;
816
817 return 0;
818
819 late_fini:
820 amdgpu_ras_block_late_fini(adev, ras_block);
821
822 return r;
823 }
824
825 struct amdgpu_mmhub_ras mmhub_v1_8_ras = {
826 .ras_block = {
827 .hw_ops = &mmhub_v1_8_ras_hw_ops,
828 .ras_late_init = mmhub_v1_8_ras_late_init,
829 },
830 };
831