1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_9.h"
26 #include "amdgpu_ras.h"
27
28 #include "nbio/nbio_7_9_0_offset.h"
29 #include "nbio/nbio_7_9_0_sh_mask.h"
30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
31 #include <uapi/linux/kfd_ioctl.h>
32
33 #define NPS_MODE_MASK 0x000000FFL
34
nbio_v7_9_remap_hdp_registers(struct amdgpu_device * adev)35 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
36 {
37 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
38 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
39 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
41 }
42
nbio_v7_9_get_rev_id(struct amdgpu_device * adev)43 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
44 {
45 u32 tmp;
46
47 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));
48 /* If it is VF or subrevision holds a non-zero value, that should be used */
49 if (tmp || amdgpu_sriov_vf(adev))
50 return tmp;
51
52 /* If discovery subrev is not updated, use register version */
53 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
54 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
55 STRAP_ATI_REV_ID_DEV0_F0);
56
57 return tmp;
58 }
59
nbio_v7_9_mc_access_enable(struct amdgpu_device * adev,bool enable)60 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
61 {
62 if (enable)
63 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
64 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
65 else
66 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
67 }
68
nbio_v7_9_get_memsize(struct amdgpu_device * adev)69 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
70 {
71 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
72 }
73
nbio_v7_9_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)74 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
75 bool use_doorbell, int doorbell_index, int doorbell_size)
76 {
77 u32 doorbell_range = 0, doorbell_ctrl = 0;
78 int aid_id, dev_inst;
79
80 dev_inst = GET_INST(SDMA0, instance);
81 aid_id = adev->sdma.instance[instance].aid_id;
82
83 if (use_doorbell == false)
84 return;
85
86 doorbell_range =
87 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
88 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
89 doorbell_range =
90 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
91 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
92 doorbell_ctrl =
93 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
94 S2A_DOORBELL_PORT1_ENABLE, 1);
95 doorbell_ctrl =
96 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
97 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
98
99 switch (dev_inst % adev->sdma.num_inst_per_aid) {
100 case 0:
101 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
102 4 * aid_id, doorbell_range);
103
104 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
105 S2A_DOORBELL_ENTRY_1_CTRL,
106 S2A_DOORBELL_PORT1_AWID, 0xe);
107 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
108 S2A_DOORBELL_ENTRY_1_CTRL,
109 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
110 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
111 S2A_DOORBELL_ENTRY_1_CTRL,
112 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
113 0x1);
114 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
115 aid_id, doorbell_ctrl);
116 break;
117 case 1:
118 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
119 4 * aid_id, doorbell_range);
120
121 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
122 S2A_DOORBELL_ENTRY_1_CTRL,
123 S2A_DOORBELL_PORT1_AWID, 0x8);
124 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
125 S2A_DOORBELL_ENTRY_1_CTRL,
126 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
127 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
128 S2A_DOORBELL_ENTRY_1_CTRL,
129 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
130 0x2);
131 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
132 aid_id, doorbell_ctrl);
133 break;
134 case 2:
135 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
136 4 * aid_id, doorbell_range);
137
138 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
139 S2A_DOORBELL_ENTRY_1_CTRL,
140 S2A_DOORBELL_PORT1_AWID, 0x9);
141 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
142 S2A_DOORBELL_ENTRY_1_CTRL,
143 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
144 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
145 S2A_DOORBELL_ENTRY_1_CTRL,
146 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
147 0x8);
148 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
149 aid_id, doorbell_ctrl);
150 break;
151 case 3:
152 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
153 4 * aid_id, doorbell_range);
154
155 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
156 S2A_DOORBELL_ENTRY_1_CTRL,
157 S2A_DOORBELL_PORT1_AWID, 0xa);
158 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
159 S2A_DOORBELL_ENTRY_1_CTRL,
160 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
161 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
162 S2A_DOORBELL_ENTRY_1_CTRL,
163 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
164 0x9);
165 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
166 aid_id, doorbell_ctrl);
167 break;
168 default:
169 break;
170 }
171 }
172
nbio_v7_9_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)173 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
174 int doorbell_index, int instance)
175 {
176 u32 doorbell_range = 0, doorbell_ctrl = 0;
177 u32 aid_id = instance;
178
179 if (use_doorbell) {
180 doorbell_range = REG_SET_FIELD(doorbell_range,
181 DOORBELL0_CTRL_ENTRY_0,
182 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
183 doorbell_index);
184 doorbell_range = REG_SET_FIELD(doorbell_range,
185 DOORBELL0_CTRL_ENTRY_0,
186 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
187 0x9);
188 if (aid_id)
189 doorbell_range = REG_SET_FIELD(doorbell_range,
190 DOORBELL0_CTRL_ENTRY_0,
191 DOORBELL0_FENCE_ENABLE_ENTRY,
192 0x4);
193
194 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
195 S2A_DOORBELL_ENTRY_1_CTRL,
196 S2A_DOORBELL_PORT1_ENABLE, 1);
197 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
198 S2A_DOORBELL_ENTRY_1_CTRL,
199 S2A_DOORBELL_PORT1_AWID, 0x4);
200 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
201 S2A_DOORBELL_ENTRY_1_CTRL,
202 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
203 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
204 S2A_DOORBELL_ENTRY_1_CTRL,
205 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);
206 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
207 S2A_DOORBELL_ENTRY_1_CTRL,
208 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
209
210 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
211 aid_id, doorbell_range);
212 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
213 aid_id, doorbell_ctrl);
214 } else {
215 doorbell_range = REG_SET_FIELD(doorbell_range,
216 DOORBELL0_CTRL_ENTRY_0,
217 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
218 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
219 S2A_DOORBELL_ENTRY_1_CTRL,
220 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
221
222 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
223 aid_id, doorbell_range);
224 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
225 aid_id, doorbell_ctrl);
226 }
227 }
228
nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)229 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
230 bool enable)
231 {
232 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */
233 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
234 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
235 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
236 }
237
nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)238 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
239 bool enable)
240 {
241 u32 tmp = 0;
242
243 if (enable) {
244 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
245 DOORBELL_SELFRING_GPA_APER_EN, 1) |
246 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
247 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
248 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
249 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
250
251 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
252 lower_32_bits(adev->doorbell.base));
253 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
254 upper_32_bits(adev->doorbell.base));
255 }
256
257 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
258 }
259
nbio_v7_9_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)260 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
261 bool use_doorbell, int doorbell_index)
262 {
263 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
264
265 if (use_doorbell) {
266 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
267 DOORBELL0_CTRL_ENTRY_0,
268 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
269 doorbell_index);
270 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
271 DOORBELL0_CTRL_ENTRY_0,
272 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
273 0x8);
274
275 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
276 S2A_DOORBELL_ENTRY_1_CTRL,
277 S2A_DOORBELL_PORT1_ENABLE, 1);
278 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
279 S2A_DOORBELL_ENTRY_1_CTRL,
280 S2A_DOORBELL_PORT1_AWID, 0);
281 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
282 S2A_DOORBELL_ENTRY_1_CTRL,
283 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
284 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
285 S2A_DOORBELL_ENTRY_1_CTRL,
286 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
287 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
288 S2A_DOORBELL_ENTRY_1_CTRL,
289 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
290 } else {
291 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
292 DOORBELL0_CTRL_ENTRY_0,
293 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
294 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
295 S2A_DOORBELL_ENTRY_1_CTRL,
296 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
297 }
298
299 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
300 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
301 }
302
303
nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)304 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
305 bool enable)
306 {
307 }
308
nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)309 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
310 bool enable)
311 {
312 }
313
nbio_v7_9_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)314 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
315 u64 *flags)
316 {
317 }
318
nbio_v7_9_ih_control(struct amdgpu_device * adev)319 static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
320 {
321 u32 interrupt_cntl;
322
323 /* setup interrupt control */
324 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
325 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
326 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
327 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
328 */
329 interrupt_cntl =
330 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
331 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
332 interrupt_cntl =
333 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
334 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
335 }
336
nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device * adev)337 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
338 {
339 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
340 }
341
nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device * adev)342 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
343 {
344 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
345 }
346
nbio_v7_9_get_pcie_index_offset(struct amdgpu_device * adev)347 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
348 {
349 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
350 }
351
nbio_v7_9_get_pcie_data_offset(struct amdgpu_device * adev)352 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
353 {
354 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
355 }
356
nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device * adev)357 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
358 {
359 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
360 }
361
362 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
363 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
364 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
365 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
366 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
367 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
368 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
369 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
370 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
371 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
372 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
373 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
374 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
375 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
376 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
377 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
378 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
379 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
380 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
381 };
382
nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device * adev,bool enable)383 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
384 bool enable)
385 {
386 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
387 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
388 }
389
nbio_v7_9_get_compute_partition_mode(struct amdgpu_device * adev)390 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
391 {
392 u32 tmp, px;
393
394 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
395 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
396 PARTITION_MODE);
397
398 return px;
399 }
400
nbio_v7_9_get_memory_partition_mode(struct amdgpu_device * adev,u32 * supp_modes)401 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
402 u32 *supp_modes)
403 {
404 u32 tmp;
405
406 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
407 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
408
409 if (supp_modes) {
410 *supp_modes =
411 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
412 }
413
414 return ffs(tmp);
415 }
416
nbio_v7_9_init_registers(struct amdgpu_device * adev)417 static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
418 {
419 u32 inst_mask;
420 int i;
421
422 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
423 0xff & ~(adev->gfx.xcc_mask));
424
425 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
426
427 inst_mask = adev->aid_mask & ~1U;
428 for_each_inst(i, inst_mask) {
429 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
430 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
431
432 }
433
434 if (!amdgpu_sriov_vf(adev)) {
435 u32 baco_cntl;
436 for_each_inst(i, adev->aid_mask) {
437 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
438 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
439 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
440 baco_cntl &= ~(
441 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
442 BIF_BX0_BACO_CNTL__BACO_EN_MASK);
443 dev_dbg(adev->dev,
444 "Unsetting baco dummy mode %x",
445 baco_cntl);
446 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
447 baco_cntl);
448 }
449 }
450 }
451 }
452
453 #define MMIO_REG_HOLE_OFFSET 0x1A000
454
nbio_v7_9_set_reg_remap(struct amdgpu_device * adev)455 static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
456 {
457 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
458 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
459 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
460 } else {
461 adev->rmmio_remap.reg_offset =
462 SOC15_REG_OFFSET(
463 NBIO, 0,
464 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
465 << 2;
466 adev->rmmio_remap.bus_addr = 0;
467 }
468 }
469
470 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
471 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
472 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
473 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
474 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
475 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
476 .get_rev_id = nbio_v7_9_get_rev_id,
477 .mc_access_enable = nbio_v7_9_mc_access_enable,
478 .get_memsize = nbio_v7_9_get_memsize,
479 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
480 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
481 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
482 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
483 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
484 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
485 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
486 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
487 .get_clockgating_state = nbio_v7_9_get_clockgating_state,
488 .ih_control = nbio_v7_9_ih_control,
489 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
490 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
491 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
492 .init_registers = nbio_v7_9_init_registers,
493 .set_reg_remap = nbio_v7_9_set_reg_remap,
494 };
495
nbio_v7_9_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)496 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
497 void *ras_error_status)
498 {
499 }
500
nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device * adev)501 static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
502 {
503 uint32_t bif_doorbell_intr_cntl;
504 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
505 struct ras_err_data err_data;
506 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
507
508 if (amdgpu_ras_error_data_init(&err_data))
509 return;
510
511 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
512
513 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
514 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
515 /* driver has to clear the interrupt status when bif ring is disabled */
516 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
517 BIF_BX0_BIF_DOORBELL_INT_CNTL,
518 RAS_CNTLR_INTERRUPT_CLEAR, 1);
519 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
520
521 if (!ras->disable_ras_err_cnt_harvest) {
522 /*
523 * clear error status after ras_controller_intr
524 * according to hw team and count ue number
525 * for query
526 */
527 nbio_v7_9_query_ras_error_count(adev, &err_data);
528
529 /* logging on error cnt and printing for awareness */
530 obj->err_data.ue_count += err_data.ue_count;
531 obj->err_data.ce_count += err_data.ce_count;
532
533 if (err_data.ce_count)
534 dev_info(adev->dev, "%ld correctable hardware "
535 "errors detected in %s block\n",
536 obj->err_data.ce_count,
537 get_ras_block_str(adev->nbio.ras_if));
538
539 if (err_data.ue_count)
540 dev_info(adev->dev, "%ld uncorrectable hardware "
541 "errors detected in %s block\n",
542 obj->err_data.ue_count,
543 get_ras_block_str(adev->nbio.ras_if));
544 }
545
546 dev_info(adev->dev, "RAS controller interrupt triggered "
547 "by NBIF error\n");
548 }
549
550 amdgpu_ras_error_data_fini(&err_data);
551 }
552
nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device * adev)553 static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
554 {
555 uint32_t bif_doorbell_intr_cntl;
556
557 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
558
559 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
560 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
561 /* driver has to clear the interrupt status when bif ring is disabled */
562 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
563 BIF_BX0_BIF_DOORBELL_INT_CNTL,
564 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
565
566 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
567
568 amdgpu_ras_global_ras_isr(adev);
569 }
570 }
571
nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)572 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
573 struct amdgpu_irq_src *src,
574 unsigned type,
575 enum amdgpu_interrupt_state state)
576 {
577 /* Dummy function, there is no initialization operation in driver */
578
579 return 0;
580 }
581
nbio_v7_9_process_ras_controller_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)582 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
583 struct amdgpu_irq_src *source,
584 struct amdgpu_iv_entry *entry)
585 {
586 /* By design, the ih cookie for ras_controller_irq should be written
587 * to BIFring instead of general iv ring. However, due to known bif ring
588 * hw bug, it has to be disabled. There is no chance the process function
589 * will be involked. Just left it as a dummy one.
590 */
591 return 0;
592 }
593
nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)594 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
595 struct amdgpu_irq_src *src,
596 unsigned type,
597 enum amdgpu_interrupt_state state)
598 {
599 /* Dummy function, there is no initialization operation in driver */
600
601 return 0;
602 }
603
nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)604 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
605 struct amdgpu_irq_src *source,
606 struct amdgpu_iv_entry *entry)
607 {
608 /* By design, the ih cookie for err_event_athub_irq should be written
609 * to BIFring instead of general iv ring. However, due to known bif ring
610 * hw bug, it has to be disabled. There is no chance the process function
611 * will be involked. Just left it as a dummy one.
612 */
613 return 0;
614 }
615
616 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
617 .set = nbio_v7_9_set_ras_controller_irq_state,
618 .process = nbio_v7_9_process_ras_controller_irq,
619 };
620
621 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
622 .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
623 .process = nbio_v7_9_process_err_event_athub_irq,
624 };
625
nbio_v7_9_init_ras_controller_interrupt(struct amdgpu_device * adev)626 static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev)
627 {
628 int r;
629
630 /* init the irq funcs */
631 adev->nbio.ras_controller_irq.funcs =
632 &nbio_v7_9_ras_controller_irq_funcs;
633 adev->nbio.ras_controller_irq.num_types = 1;
634
635 /* register ras controller interrupt */
636 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
637 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
638 &adev->nbio.ras_controller_irq);
639
640 return r;
641 }
642
nbio_v7_9_init_ras_err_event_athub_interrupt(struct amdgpu_device * adev)643 static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
644 {
645
646 int r;
647
648 /* init the irq funcs */
649 adev->nbio.ras_err_event_athub_irq.funcs =
650 &nbio_v7_9_ras_err_event_athub_irq_funcs;
651 adev->nbio.ras_err_event_athub_irq.num_types = 1;
652
653 /* register ras err event athub interrupt */
654 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
655 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
656 &adev->nbio.ras_err_event_athub_irq);
657
658 return r;
659 }
660
661 const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = {
662 .query_ras_error_count = nbio_v7_9_query_ras_error_count,
663 };
664
665 struct amdgpu_nbio_ras nbio_v7_9_ras = {
666 .ras_block = {
667 .ras_comm = {
668 .name = "pcie_bif",
669 .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
670 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
671 },
672 .hw_ops = &nbio_v7_9_ras_hw_ops,
673 .ras_late_init = amdgpu_nbio_ras_late_init,
674 },
675 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring,
676 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
677 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt,
678 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt,
679 };
680