1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 #include "amdgpu_ras.h"
31
32 #include "mp/mp_13_0_2_offset.h"
33 #include "mp/mp_13_0_2_sh_mask.h"
34
35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
53 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
54 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
55 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
56 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
57 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
58 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
59 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
60 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
61 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
62 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
63 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
64
65 /* For large FW files the time to complete can be very long */
66 #define USBC_PD_POLLING_LIMIT_S 240
67
68 /* Read USB-PD from LFB */
69 #define GFX_CMD_USB_PD_USE_LFB 0x480
70
71 /* Retry times for vmbx ready wait */
72 #define PSP_VMBX_POLLING_LIMIT 3000
73
74 /* VBIOS gfl defines */
75 #define MBOX_READY_MASK 0x80000000
76 #define MBOX_STATUS_MASK 0x0000FFFF
77 #define MBOX_COMMAND_MASK 0x00FF0000
78 #define MBOX_READY_FLAG 0x80000000
79 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
80 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
81 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
82
83 /* memory training timeout define */
84 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
85
86 #define regMP1_PUB_SCRATCH0 0x3b10090
87
psp_v13_0_init_microcode(struct psp_context * psp)88 static int psp_v13_0_init_microcode(struct psp_context *psp)
89 {
90 struct amdgpu_device *adev = psp->adev;
91 char ucode_prefix[30];
92 int err = 0;
93
94 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
95
96 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
97 case IP_VERSION(13, 0, 2):
98 err = psp_init_sos_microcode(psp, ucode_prefix);
99 if (err)
100 return err;
101 /* It's not necessary to load ras ta on Guest side */
102 if (!amdgpu_sriov_vf(adev)) {
103 err = psp_init_ta_microcode(psp, ucode_prefix);
104 if (err)
105 return err;
106 }
107 break;
108 case IP_VERSION(13, 0, 1):
109 case IP_VERSION(13, 0, 3):
110 case IP_VERSION(13, 0, 5):
111 case IP_VERSION(13, 0, 8):
112 case IP_VERSION(13, 0, 11):
113 case IP_VERSION(14, 0, 0):
114 case IP_VERSION(14, 0, 1):
115 case IP_VERSION(14, 0, 4):
116 err = psp_init_toc_microcode(psp, ucode_prefix);
117 if (err)
118 return err;
119 err = psp_init_ta_microcode(psp, ucode_prefix);
120 if (err)
121 return err;
122 break;
123 case IP_VERSION(13, 0, 0):
124 case IP_VERSION(13, 0, 6):
125 case IP_VERSION(13, 0, 7):
126 case IP_VERSION(13, 0, 10):
127 case IP_VERSION(13, 0, 14):
128 err = psp_init_sos_microcode(psp, ucode_prefix);
129 if (err)
130 return err;
131 /* It's not necessary to load ras ta on Guest side */
132 err = psp_init_ta_microcode(psp, ucode_prefix);
133 if (err)
134 return err;
135 break;
136 default:
137 BUG();
138 }
139
140 return 0;
141 }
142
psp_v13_0_is_sos_alive(struct psp_context * psp)143 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
144 {
145 struct amdgpu_device *adev = psp->adev;
146 uint32_t sol_reg;
147
148 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
149
150 return sol_reg != 0x0;
151 }
152
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)153 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
154 {
155 struct amdgpu_device *adev = psp->adev;
156 int retry_loop, ret;
157
158 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
159 /* Wait for bootloader to signify that is
160 ready having bit 31 of C2PMSG_33 set to 1 */
161 ret = psp_wait_for(
162 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
163 0x80000000, 0xffffffff, false);
164
165 if (ret == 0)
166 break;
167 }
168
169 if (ret)
170 dev_warn(adev->dev, "Bootloader wait timed out");
171
172 return ret;
173 }
174
psp_v13_0_wait_for_bootloader(struct psp_context * psp)175 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
176 {
177 struct amdgpu_device *adev = psp->adev;
178 int retry_loop, retry_cnt, ret;
179
180 retry_cnt =
181 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
182 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?
183 PSP_VMBX_POLLING_LIMIT :
184 10;
185 /* Wait for bootloader to signify that it is ready having bit 31 of
186 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
187 * If there is an error in processing command, bits[7:0] will be set.
188 * This is applicable for PSP v13.0.6 and newer.
189 */
190 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
191 ret = psp_wait_for(
192 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
193 0x80000000, 0xffffffff, false);
194
195 if (ret == 0)
196 return 0;
197 }
198
199 return ret;
200 }
201
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)202 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
203 {
204 struct amdgpu_device *adev = psp->adev;
205 int ret;
206
207 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
208 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
209 ret = psp_v13_0_wait_for_vmbx_ready(psp);
210 if (ret)
211 amdgpu_ras_query_boot_status(adev, 4);
212
213 ret = psp_v13_0_wait_for_bootloader(psp);
214 if (ret)
215 amdgpu_ras_query_boot_status(adev, 4);
216
217 return ret;
218 }
219
220 return 0;
221 }
222
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)223 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
224 struct psp_bin_desc *bin_desc,
225 enum psp_bootloader_cmd bl_cmd)
226 {
227 int ret;
228 uint32_t psp_gfxdrv_command_reg = 0;
229 struct amdgpu_device *adev = psp->adev;
230
231 /* Check tOS sign of life register to confirm sys driver and sOS
232 * are already been loaded.
233 */
234 if (psp_v13_0_is_sos_alive(psp))
235 return 0;
236
237 ret = psp_v13_0_wait_for_bootloader(psp);
238 if (ret)
239 return ret;
240
241 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
242
243 /* Copy PSP KDB binary to memory */
244 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
245
246 /* Provide the PSP KDB to bootloader */
247 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
248 (uint32_t)(psp->fw_pri_mc_addr >> 20));
249 psp_gfxdrv_command_reg = bl_cmd;
250 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
251 psp_gfxdrv_command_reg);
252
253 ret = psp_v13_0_wait_for_bootloader(psp);
254
255 return ret;
256 }
257
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)258 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
259 {
260 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
261 }
262
psp_v13_0_bootloader_load_spl(struct psp_context * psp)263 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
264 {
265 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
266 }
267
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)268 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
269 {
270 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
271 }
272
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)273 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
274 {
275 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
276 }
277
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)278 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
279 {
280 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
281 }
282
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)283 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
284 {
285 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
286 }
287
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)288 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
289 {
290 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
291 }
292
psp_v13_0_init_sos_version(struct psp_context * psp)293 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
294 {
295 struct amdgpu_device *adev = psp->adev;
296
297 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
298 }
299
psp_v13_0_bootloader_load_sos(struct psp_context * psp)300 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
301 {
302 int ret;
303 unsigned int psp_gfxdrv_command_reg = 0;
304 struct amdgpu_device *adev = psp->adev;
305
306 /* Check sOS sign of life register to confirm sys driver and sOS
307 * are already been loaded.
308 */
309 if (psp_v13_0_is_sos_alive(psp)) {
310 psp_v13_0_init_sos_version(psp);
311 return 0;
312 }
313
314 ret = psp_v13_0_wait_for_bootloader(psp);
315 if (ret)
316 return ret;
317
318 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
319
320 /* Copy Secure OS binary to PSP memory */
321 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
322
323 /* Provide the PSP secure OS to bootloader */
324 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
325 (uint32_t)(psp->fw_pri_mc_addr >> 20));
326 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
327 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
328 psp_gfxdrv_command_reg);
329
330 /* there might be handshake issue with hardware which needs delay */
331 mdelay(20);
332 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
333 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
334 0, true);
335
336 if (!ret)
337 psp_v13_0_init_sos_version(psp);
338
339 return ret;
340 }
341
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)342 static int psp_v13_0_ring_stop(struct psp_context *psp,
343 enum psp_ring_type ring_type)
344 {
345 int ret = 0;
346 struct amdgpu_device *adev = psp->adev;
347
348 if (amdgpu_sriov_vf(adev)) {
349 /* Write the ring destroy command*/
350 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
351 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
352 /* there might be handshake issue with hardware which needs delay */
353 mdelay(20);
354 /* Wait for response flag (bit 31) */
355 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
356 0x80000000, 0x80000000, false);
357 } else {
358 /* Write the ring destroy command*/
359 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
360 GFX_CTRL_CMD_ID_DESTROY_RINGS);
361 /* there might be handshake issue with hardware which needs delay */
362 mdelay(20);
363 /* Wait for response flag (bit 31) */
364 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
365 0x80000000, 0x80000000, false);
366 }
367
368 return ret;
369 }
370
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)371 static int psp_v13_0_ring_create(struct psp_context *psp,
372 enum psp_ring_type ring_type)
373 {
374 int ret = 0;
375 unsigned int psp_ring_reg = 0;
376 struct psp_ring *ring = &psp->km_ring;
377 struct amdgpu_device *adev = psp->adev;
378
379 if (amdgpu_sriov_vf(adev)) {
380 ret = psp_v13_0_ring_stop(psp, ring_type);
381 if (ret) {
382 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
383 return ret;
384 }
385
386 /* Write low address of the ring to C2PMSG_102 */
387 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
388 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
389 /* Write high address of the ring to C2PMSG_103 */
390 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
391 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
392
393 /* Write the ring initialization command to C2PMSG_101 */
394 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
395 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
396
397 /* there might be handshake issue with hardware which needs delay */
398 mdelay(20);
399
400 /* Wait for response flag (bit 31) in C2PMSG_101 */
401 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
402 0x80000000, 0x8000FFFF, false);
403
404 } else {
405 /* Wait for sOS ready for ring creation */
406 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
407 0x80000000, 0x80000000, false);
408 if (ret) {
409 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
410 return ret;
411 }
412
413 /* Write low address of the ring to C2PMSG_69 */
414 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
415 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
416 /* Write high address of the ring to C2PMSG_70 */
417 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
418 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
419 /* Write size of ring to C2PMSG_71 */
420 psp_ring_reg = ring->ring_size;
421 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
422 /* Write the ring initialization command to C2PMSG_64 */
423 psp_ring_reg = ring_type;
424 psp_ring_reg = psp_ring_reg << 16;
425 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
426
427 /* there might be handshake issue with hardware which needs delay */
428 mdelay(20);
429
430 /* Wait for response flag (bit 31) in C2PMSG_64 */
431 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
432 0x80000000, 0x8000FFFF, false);
433 }
434
435 return ret;
436 }
437
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)438 static int psp_v13_0_ring_destroy(struct psp_context *psp,
439 enum psp_ring_type ring_type)
440 {
441 int ret = 0;
442 struct psp_ring *ring = &psp->km_ring;
443 struct amdgpu_device *adev = psp->adev;
444
445 ret = psp_v13_0_ring_stop(psp, ring_type);
446 if (ret)
447 DRM_ERROR("Fail to stop psp ring\n");
448
449 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
450 &ring->ring_mem_mc_addr,
451 (void **)&ring->ring_mem);
452
453 return ret;
454 }
455
psp_v13_0_ring_get_wptr(struct psp_context * psp)456 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
457 {
458 uint32_t data;
459 struct amdgpu_device *adev = psp->adev;
460
461 if (amdgpu_sriov_vf(adev))
462 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
463 else
464 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
465
466 return data;
467 }
468
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)469 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
470 {
471 struct amdgpu_device *adev = psp->adev;
472
473 if (amdgpu_sriov_vf(adev)) {
474 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
475 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
476 GFX_CTRL_CMD_ID_CONSUME_CMD);
477 } else
478 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
479 }
480
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)481 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
482 {
483 int ret;
484 int i;
485 uint32_t data_32;
486 int max_wait;
487 struct amdgpu_device *adev = psp->adev;
488
489 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
490 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
491 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
492
493 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
494 for (i = 0; i < max_wait; i++) {
495 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
496 0x80000000, 0x80000000, false);
497 if (ret == 0)
498 break;
499 }
500 if (i < max_wait)
501 ret = 0;
502 else
503 ret = -ETIME;
504
505 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
506 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
507 (ret == 0) ? "succeed" : "failed",
508 i, adev->usec_timeout/1000);
509 return ret;
510 }
511
512
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)513 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
514 {
515 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
516 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
517 struct amdgpu_device *adev = psp->adev;
518 uint32_t p2c_header[4];
519 uint32_t sz;
520 void *buf;
521 int ret, idx;
522
523 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
524 dev_dbg(adev->dev, "Memory training is not supported.\n");
525 return 0;
526 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
527 dev_err(adev->dev, "Memory training initialization failure.\n");
528 return -EINVAL;
529 }
530
531 if (psp_v13_0_is_sos_alive(psp)) {
532 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
533 return 0;
534 }
535
536 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
537 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
538 pcache[0], pcache[1], pcache[2], pcache[3],
539 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
540
541 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
542 dev_dbg(adev->dev, "Short training depends on restore.\n");
543 ops |= PSP_MEM_TRAIN_RESTORE;
544 }
545
546 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
547 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
548 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
549 ops |= PSP_MEM_TRAIN_SAVE;
550 }
551
552 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
553 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
554 pcache[3] == p2c_header[3])) {
555 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
556 ops |= PSP_MEM_TRAIN_SAVE;
557 }
558
559 if ((ops & PSP_MEM_TRAIN_SAVE) &&
560 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
561 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
562 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
563 }
564
565 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
566 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
567 ops |= PSP_MEM_TRAIN_SAVE;
568 }
569
570 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
571
572 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
573 /*
574 * Long training will encroach a certain amount on the bottom of VRAM;
575 * save the content from the bottom of VRAM to system memory
576 * before training, and restore it after training to avoid
577 * VRAM corruption.
578 */
579 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
580
581 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
582 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
583 adev->gmc.visible_vram_size,
584 adev->mman.aper_base_kaddr);
585 return -EINVAL;
586 }
587
588 buf = vmalloc(sz);
589 if (!buf) {
590 dev_err(adev->dev, "failed to allocate system memory.\n");
591 return -ENOMEM;
592 }
593
594 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
595 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
596 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
597 if (ret) {
598 DRM_ERROR("Send long training msg failed.\n");
599 vfree(buf);
600 drm_dev_exit(idx);
601 return ret;
602 }
603
604 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
605 amdgpu_device_flush_hdp(adev, NULL);
606 vfree(buf);
607 drm_dev_exit(idx);
608 } else {
609 vfree(buf);
610 return -ENODEV;
611 }
612 }
613
614 if (ops & PSP_MEM_TRAIN_SAVE) {
615 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
616 }
617
618 if (ops & PSP_MEM_TRAIN_RESTORE) {
619 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
620 }
621
622 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
623 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
624 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
625 if (ret) {
626 dev_err(adev->dev, "send training msg failed.\n");
627 return ret;
628 }
629 }
630 ctx->training_cnt++;
631 return 0;
632 }
633
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)634 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
635 {
636 struct amdgpu_device *adev = psp->adev;
637 uint32_t reg_status;
638 int ret, i = 0;
639
640 /*
641 * LFB address which is aligned to 1MB address and has to be
642 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
643 * register
644 */
645 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
646
647 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
648 0x80000000, 0x80000000, false);
649 if (ret)
650 return ret;
651
652 /* Fireup interrupt so PSP can pick up the address */
653 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
654
655 /* FW load takes very long time */
656 do {
657 msleep(1000);
658 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
659
660 if (reg_status & 0x80000000)
661 goto done;
662
663 } while (++i < USBC_PD_POLLING_LIMIT_S);
664
665 return -ETIME;
666 done:
667
668 if ((reg_status & 0xFFFF) != 0) {
669 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
670 reg_status & 0xFFFF);
671 return -EIO;
672 }
673
674 return 0;
675 }
676
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)677 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
678 {
679 struct amdgpu_device *adev = psp->adev;
680 int ret;
681
682 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
683
684 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
685 0x80000000, 0x80000000, false);
686 if (!ret)
687 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
688
689 return ret;
690 }
691
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)692 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
693 {
694 uint32_t reg_status = 0, reg_val = 0;
695 struct amdgpu_device *adev = psp->adev;
696 int ret;
697
698 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
699 reg_val |= (cmd << 16);
700 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
701
702 /* Ring the doorbell */
703 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
704
705 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
706 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
707 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
708 else
709 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
710 MBOX_READY_FLAG, MBOX_READY_MASK, false);
711 if (ret) {
712 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
713 return ret;
714 }
715
716 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
717 if ((reg_status & 0xFFFF) != 0) {
718 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
719 cmd, reg_status & 0xFFFF);
720 return -EIO;
721 }
722
723 return 0;
724 }
725
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)726 static int psp_v13_0_update_spirom(struct psp_context *psp,
727 uint64_t fw_pri_mc_addr)
728 {
729 struct amdgpu_device *adev = psp->adev;
730 int ret;
731
732 /* Confirm PSP is ready to start */
733 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
734 MBOX_READY_FLAG, MBOX_READY_MASK, false);
735 if (ret) {
736 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
737 return ret;
738 }
739
740 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
741
742 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
743 if (ret)
744 return ret;
745
746 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
747
748 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
749 if (ret)
750 return ret;
751
752 psp->vbflash_done = true;
753
754 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
755 if (ret)
756 return ret;
757
758 return 0;
759 }
760
psp_v13_0_vbflash_status(struct psp_context * psp)761 static int psp_v13_0_vbflash_status(struct psp_context *psp)
762 {
763 struct amdgpu_device *adev = psp->adev;
764
765 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
766 }
767
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)768 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
769 {
770 struct amdgpu_device *adev = psp->adev;
771
772 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
773 uint32_t reg_data;
774 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
775 * during MP1 triggered sync flood.
776 */
777 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
778 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
779
780 /* delay 1000ms for the mode1 reset for fatal error
781 * to be recovered back.
782 */
783 msleep(1000);
784 }
785
786 return 0;
787 }
788
psp_v13_0_get_ras_capability(struct psp_context * psp)789 static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
790 {
791 struct amdgpu_device *adev = psp->adev;
792 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
793 u32 reg_data;
794
795 /* query ras cap should be done from host side */
796 if (amdgpu_sriov_vf(adev))
797 return false;
798
799 if (!con)
800 return false;
801
802 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
803 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&
804 (!(adev->flags & AMD_IS_APU))) {
805 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
806 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
807 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
808 return true;
809 } else {
810 return false;
811 }
812 }
813
psp_v13_0_is_aux_sos_load_required(struct psp_context * psp)814 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
815 {
816 struct amdgpu_device *adev = psp->adev;
817 u32 pmfw_ver;
818
819 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
820 return false;
821
822 /* load 4e version of sos if pmfw version less than 85.115.0 */
823 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
824
825 return (pmfw_ver < 0x557300);
826 }
827
828 static const struct psp_funcs psp_v13_0_funcs = {
829 .init_microcode = psp_v13_0_init_microcode,
830 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
831 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
832 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
833 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
834 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
835 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
836 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
837 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
838 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
839 .ring_create = psp_v13_0_ring_create,
840 .ring_stop = psp_v13_0_ring_stop,
841 .ring_destroy = psp_v13_0_ring_destroy,
842 .ring_get_wptr = psp_v13_0_ring_get_wptr,
843 .ring_set_wptr = psp_v13_0_ring_set_wptr,
844 .mem_training = psp_v13_0_memory_training,
845 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
846 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
847 .update_spirom = psp_v13_0_update_spirom,
848 .vbflash_stat = psp_v13_0_vbflash_status,
849 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
850 .get_ras_capability = psp_v13_0_get_ras_capability,
851 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,
852 };
853
psp_v13_0_set_psp_funcs(struct psp_context * psp)854 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
855 {
856 psp->funcs = &psp_v13_0_funcs;
857 }
858