1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/amdgpu_drm.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
37 #include "atom.h"
38 #include "amd_pcie.h"
39
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
50
51 #include "soc15.h"
52 #include "soc15_common.h"
53 #include "gfx_v9_0.h"
54 #include "gmc_v9_0.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
57 #include "df_v1_7.h"
58 #include "df_v3_6.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
62 #include "hdp_v4_0.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
67 #include "uvd_v7_0.h"
68 #include "vce_v4_0.h"
69 #include "vcn_v1_0.h"
70 #include "vcn_v2_0.h"
71 #include "jpeg_v2_0.h"
72 #include "vcn_v2_5.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "amdgpu_vkms.h"
78 #include "mxgpu_ai.h"
79 #include "amdgpu_ras.h"
80 #include "amdgpu_xgmi.h"
81 #include <uapi/linux/kfd_ioctl.h>
82
83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88 static const struct amd_ip_funcs soc15_common_ip_funcs;
89
90 /* Vega, Raven, Arcturus */
91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92 {
93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
95 };
96
97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
98 {
99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 .codec_array = vega_video_codecs_encode_array,
101 };
102
103 /* Vega */
104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105 {
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 };
112
113 static const struct amdgpu_video_codecs vega_video_codecs_decode =
114 {
115 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
116 .codec_array = vega_video_codecs_decode_array,
117 };
118
119 /* Raven */
120 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
121 {
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
129 };
130
131 static const struct amdgpu_video_codecs rv_video_codecs_decode =
132 {
133 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
134 .codec_array = rv_video_codecs_decode_array,
135 };
136
137 /* Renoir, Arcturus */
138 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
139 {
140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
147 };
148
149 static const struct amdgpu_video_codecs rn_video_codecs_decode =
150 {
151 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
152 .codec_array = rn_video_codecs_decode_array,
153 };
154
155 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
161 };
162
163 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
164 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
165 .codec_array = vcn_4_0_3_video_codecs_decode_array,
166 };
167
168 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
169 .codec_count = 0,
170 .codec_array = NULL,
171 };
172
soc15_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)173 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
174 const struct amdgpu_video_codecs **codecs)
175 {
176 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
177 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
178 case IP_VERSION(4, 0, 0):
179 case IP_VERSION(4, 1, 0):
180 if (encode)
181 *codecs = &vega_video_codecs_encode;
182 else
183 *codecs = &vega_video_codecs_decode;
184 return 0;
185 default:
186 return -EINVAL;
187 }
188 } else {
189 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
190 case IP_VERSION(1, 0, 0):
191 case IP_VERSION(1, 0, 1):
192 if (encode)
193 *codecs = &vega_video_codecs_encode;
194 else
195 *codecs = &rv_video_codecs_decode;
196 return 0;
197 case IP_VERSION(2, 5, 0):
198 case IP_VERSION(2, 6, 0):
199 case IP_VERSION(2, 2, 0):
200 if (encode)
201 *codecs = &vega_video_codecs_encode;
202 else
203 *codecs = &rn_video_codecs_decode;
204 return 0;
205 case IP_VERSION(4, 0, 3):
206 if (encode)
207 *codecs = &vcn_4_0_3_video_codecs_encode;
208 else
209 *codecs = &vcn_4_0_3_video_codecs_decode;
210 return 0;
211 default:
212 return -EINVAL;
213 }
214 }
215 }
216
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)217 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
218 {
219 unsigned long flags, address, data;
220 u32 r;
221
222 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
223 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
224
225 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
226 WREG32(address, ((reg) & 0x1ff));
227 r = RREG32(data);
228 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
229 return r;
230 }
231
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)232 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
233 {
234 unsigned long flags, address, data;
235
236 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
237 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
238
239 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
240 WREG32(address, ((reg) & 0x1ff));
241 WREG32(data, (v));
242 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
243 }
244
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)245 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
246 {
247 unsigned long flags, address, data;
248 u32 r;
249
250 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
251 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
252
253 spin_lock_irqsave(&adev->didt_idx_lock, flags);
254 WREG32(address, (reg));
255 r = RREG32(data);
256 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
257 return r;
258 }
259
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)260 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
261 {
262 unsigned long flags, address, data;
263
264 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
265 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
266
267 spin_lock_irqsave(&adev->didt_idx_lock, flags);
268 WREG32(address, (reg));
269 WREG32(data, (v));
270 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
271 }
272
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)273 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
274 {
275 unsigned long flags;
276 u32 r;
277
278 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
279 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
280 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
281 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
282 return r;
283 }
284
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)285 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
286 {
287 unsigned long flags;
288
289 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
290 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
291 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
292 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
293 }
294
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)295 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
296 {
297 unsigned long flags;
298 u32 r;
299
300 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
301 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
302 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
303 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
304 return r;
305 }
306
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)307 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
308 {
309 unsigned long flags;
310
311 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
312 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
313 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
314 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
315 }
316
soc15_get_config_memsize(struct amdgpu_device * adev)317 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
318 {
319 return adev->nbio.funcs->get_memsize(adev);
320 }
321
soc15_get_xclk(struct amdgpu_device * adev)322 static u32 soc15_get_xclk(struct amdgpu_device *adev)
323 {
324 u32 reference_clock = adev->clock.spll.reference_freq;
325
326 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||
327 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||
328 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||
329 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
330 return 10000;
331 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||
332 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))
333 return reference_clock / 4;
334
335 return reference_clock;
336 }
337
338
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid,int xcc_id)339 void soc15_grbm_select(struct amdgpu_device *adev,
340 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
341 {
342 u32 grbm_gfx_cntl = 0;
343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
347
348 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
349 }
350
soc15_read_disabled_bios(struct amdgpu_device * adev)351 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
352 {
353 /* todo */
354 return false;
355 }
356
357 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
362 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
363 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
364 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
365 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
374 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
375 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
376 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
377 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
378 };
379
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)380 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
381 u32 sh_num, u32 reg_offset)
382 {
383 uint32_t val;
384
385 mutex_lock(&adev->grbm_idx_mutex);
386 if (se_num != 0xffffffff || sh_num != 0xffffffff)
387 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
388
389 val = RREG32(reg_offset);
390
391 if (se_num != 0xffffffff || sh_num != 0xffffffff)
392 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
393 mutex_unlock(&adev->grbm_idx_mutex);
394 return val;
395 }
396
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)397 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
398 bool indexed, u32 se_num,
399 u32 sh_num, u32 reg_offset)
400 {
401 if (indexed) {
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
403 } else {
404 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
405 return adev->gfx.config.gb_addr_config;
406 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
407 return adev->gfx.config.db_debug2;
408 return RREG32(reg_offset);
409 }
410 }
411
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)412 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
413 u32 sh_num, u32 reg_offset, u32 *value)
414 {
415 uint32_t i;
416 struct soc15_allowed_register_entry *en;
417
418 *value = 0;
419 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
420 en = &soc15_allowed_read_registers[i];
421 if (!adev->reg_offset[en->hwip][en->inst])
422 continue;
423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
424 + en->reg_offset))
425 continue;
426
427 *value = soc15_get_register_value(adev,
428 soc15_allowed_read_registers[i].grbm_indexed,
429 se_num, sh_num, reg_offset);
430 return 0;
431 }
432 return -EINVAL;
433 }
434
435
436 /**
437 * soc15_program_register_sequence - program an array of registers.
438 *
439 * @adev: amdgpu_device pointer
440 * @regs: pointer to the register array
441 * @array_size: size of the register array
442 *
443 * Programs an array or registers with and and or masks.
444 * This is a helper for setting golden registers.
445 */
446
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)447 void soc15_program_register_sequence(struct amdgpu_device *adev,
448 const struct soc15_reg_golden *regs,
449 const u32 array_size)
450 {
451 const struct soc15_reg_golden *entry;
452 u32 tmp, reg;
453 int i;
454
455 for (i = 0; i < array_size; ++i) {
456 entry = ®s[i];
457 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
458
459 if (entry->and_mask == 0xffffffff) {
460 tmp = entry->or_mask;
461 } else {
462 tmp = (entry->hwip == GC_HWIP) ?
463 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
464
465 tmp &= ~(entry->and_mask);
466 tmp |= (entry->or_mask & entry->and_mask);
467 }
468
469 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
470 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
471 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
472 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
473 WREG32_RLC(reg, tmp);
474 else
475 (entry->hwip == GC_HWIP) ?
476 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
477
478 }
479
480 }
481
soc15_asic_baco_reset(struct amdgpu_device * adev)482 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
483 {
484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
485 int ret = 0;
486
487 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
488 if (ras && adev->ras_enabled)
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
490
491 ret = amdgpu_dpm_baco_reset(adev);
492 if (ret)
493 return ret;
494
495 /* re-enable doorbell interrupt after BACO exit */
496 if (ras && adev->ras_enabled)
497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
498
499 return 0;
500 }
501
502 static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device * adev)503 soc15_asic_reset_method(struct amdgpu_device *adev)
504 {
505 int baco_reset = 0;
506 bool connected_to_cpu = false;
507 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
508
509 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
510 connected_to_cpu = true;
511
512 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
513 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
514 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
515 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
516 /* If connected to cpu, driver only support mode2 */
517 if (connected_to_cpu)
518 return AMD_RESET_METHOD_MODE2;
519 return amdgpu_reset_method;
520 }
521
522 if (amdgpu_reset_method != -1)
523 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
524 amdgpu_reset_method);
525
526 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
527 case IP_VERSION(10, 0, 0):
528 case IP_VERSION(10, 0, 1):
529 case IP_VERSION(12, 0, 0):
530 case IP_VERSION(12, 0, 1):
531 return AMD_RESET_METHOD_MODE2;
532 case IP_VERSION(9, 0, 0):
533 case IP_VERSION(11, 0, 2):
534 if (adev->asic_type == CHIP_VEGA20) {
535 if (adev->psp.sos.fw_version >= 0x80067)
536 baco_reset = amdgpu_dpm_is_baco_supported(adev);
537 /*
538 * 1. PMFW version > 0x284300: all cases use baco
539 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
540 */
541 if (ras && adev->ras_enabled &&
542 adev->pm.fw_version <= 0x283400)
543 baco_reset = 0;
544 } else {
545 baco_reset = amdgpu_dpm_is_baco_supported(adev);
546 }
547 break;
548 case IP_VERSION(13, 0, 2):
549 /*
550 * 1.connected to cpu: driver issue mode2 reset
551 * 2.discret gpu: driver issue mode1 reset
552 */
553 if (connected_to_cpu)
554 return AMD_RESET_METHOD_MODE2;
555 break;
556 case IP_VERSION(13, 0, 6):
557 case IP_VERSION(13, 0, 14):
558 /* Use gpu_recovery param to target a reset method.
559 * Enable triggering of GPU reset only if specified
560 * by module parameter.
561 */
562 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
563 return AMD_RESET_METHOD_MODE2;
564 else if (!(adev->flags & AMD_IS_APU))
565 return AMD_RESET_METHOD_MODE1;
566 else
567 return AMD_RESET_METHOD_MODE2;
568 default:
569 break;
570 }
571
572 if (baco_reset)
573 return AMD_RESET_METHOD_BACO;
574 else
575 return AMD_RESET_METHOD_MODE1;
576 }
577
soc15_need_reset_on_resume(struct amdgpu_device * adev)578 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
579 {
580 u32 sol_reg;
581
582 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
583
584 /* Will reset for the following suspend abort cases.
585 * 1) Only reset limit on APU side, dGPU hasn't checked yet.
586 * 2) S3 suspend abort and TOS already launched.
587 */
588 if (adev->flags & AMD_IS_APU && adev->in_s3 &&
589 !adev->suspend_complete &&
590 sol_reg)
591 return true;
592
593 return false;
594 }
595
soc15_asic_reset(struct amdgpu_device * adev)596 static int soc15_asic_reset(struct amdgpu_device *adev)
597 {
598 /* original raven doesn't have full asic reset */
599 /* On the latest Raven, the GPU reset can be performed
600 * successfully. So now, temporarily enable it for the
601 * S3 suspend abort case.
602 */
603 if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
604 (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
605 !soc15_need_reset_on_resume(adev))
606 return 0;
607
608 switch (soc15_asic_reset_method(adev)) {
609 case AMD_RESET_METHOD_PCI:
610 dev_info(adev->dev, "PCI reset\n");
611 return amdgpu_device_pci_reset(adev);
612 case AMD_RESET_METHOD_BACO:
613 dev_info(adev->dev, "BACO reset\n");
614 return soc15_asic_baco_reset(adev);
615 case AMD_RESET_METHOD_MODE2:
616 dev_info(adev->dev, "MODE2 reset\n");
617 return amdgpu_dpm_mode2_reset(adev);
618 default:
619 dev_info(adev->dev, "MODE1 reset\n");
620 return amdgpu_device_mode1_reset(adev);
621 }
622 }
623
soc15_supports_baco(struct amdgpu_device * adev)624 static int soc15_supports_baco(struct amdgpu_device *adev)
625 {
626 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
627 case IP_VERSION(9, 0, 0):
628 case IP_VERSION(11, 0, 2):
629 if (adev->asic_type == CHIP_VEGA20) {
630 if (adev->psp.sos.fw_version >= 0x80067)
631 return amdgpu_dpm_is_baco_supported(adev);
632 return 0;
633 } else {
634 return amdgpu_dpm_is_baco_supported(adev);
635 }
636 break;
637 default:
638 return 0;
639 }
640 }
641
642 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
643 u32 cntl_reg, u32 status_reg)
644 {
645 return 0;
646 }*/
647
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)648 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
649 {
650 /*int r;
651
652 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
653 if (r)
654 return r;
655
656 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
657 */
658 return 0;
659 }
660
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)661 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
662 {
663 /* todo */
664
665 return 0;
666 }
667
soc15_program_aspm(struct amdgpu_device * adev)668 static void soc15_program_aspm(struct amdgpu_device *adev)
669 {
670 if (!amdgpu_device_should_use_aspm(adev))
671 return;
672
673 if (adev->nbio.funcs->program_aspm)
674 adev->nbio.funcs->program_aspm(adev);
675 }
676
677 const struct amdgpu_ip_block_version vega10_common_ip_block =
678 {
679 .type = AMD_IP_BLOCK_TYPE_COMMON,
680 .major = 2,
681 .minor = 0,
682 .rev = 0,
683 .funcs = &soc15_common_ip_funcs,
684 };
685
soc15_reg_base_init(struct amdgpu_device * adev)686 static void soc15_reg_base_init(struct amdgpu_device *adev)
687 {
688 /* Set IP register base before any HW register access */
689 switch (adev->asic_type) {
690 case CHIP_VEGA10:
691 case CHIP_VEGA12:
692 case CHIP_RAVEN:
693 case CHIP_RENOIR:
694 vega10_reg_base_init(adev);
695 break;
696 case CHIP_VEGA20:
697 vega20_reg_base_init(adev);
698 break;
699 case CHIP_ARCTURUS:
700 arct_reg_base_init(adev);
701 break;
702 case CHIP_ALDEBARAN:
703 aldebaran_reg_base_init(adev);
704 break;
705 default:
706 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
707 break;
708 }
709 }
710
soc15_set_virt_ops(struct amdgpu_device * adev)711 void soc15_set_virt_ops(struct amdgpu_device *adev)
712 {
713 adev->virt.ops = &xgpu_ai_virt_ops;
714
715 /* init soc15 reg base early enough so we can
716 * request request full access for sriov before
717 * set_ip_blocks. */
718 soc15_reg_base_init(adev);
719 }
720
soc15_need_full_reset(struct amdgpu_device * adev)721 static bool soc15_need_full_reset(struct amdgpu_device *adev)
722 {
723 /* change this when we implement soft reset */
724 return true;
725 }
726
soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)727 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
728 uint64_t *count1)
729 {
730 uint32_t perfctr = 0;
731 uint64_t cnt0_of, cnt1_of;
732 int tmp;
733
734 /* This reports 0 on APUs, so return to avoid writing/reading registers
735 * that may or may not be different from their GPU counterparts
736 */
737 if (adev->flags & AMD_IS_APU)
738 return;
739
740 /* Set the 2 events that we wish to watch, defined above */
741 /* Reg 40 is # received msgs */
742 /* Reg 104 is # of posted requests sent */
743 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
744 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
745
746 /* Write to enable desired perf counters */
747 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
748 /* Zero out and enable the perf counters
749 * Write 0x5:
750 * Bit 0 = Start all counters(1)
751 * Bit 2 = Global counter reset enable(1)
752 */
753 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
754
755 msleep(1000);
756
757 /* Load the shadow and disable the perf counters
758 * Write 0x2:
759 * Bit 0 = Stop counters(0)
760 * Bit 1 = Load the shadow counters(1)
761 */
762 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
763
764 /* Read register values to get any >32bit overflow */
765 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
766 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
767 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
768
769 /* Get the values and add the overflow */
770 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
771 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
772 }
773
vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)774 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
775 uint64_t *count1)
776 {
777 uint32_t perfctr = 0;
778 uint64_t cnt0_of, cnt1_of;
779 int tmp;
780
781 /* This reports 0 on APUs, so return to avoid writing/reading registers
782 * that may or may not be different from their GPU counterparts
783 */
784 if (adev->flags & AMD_IS_APU)
785 return;
786
787 /* Set the 2 events that we wish to watch, defined above */
788 /* Reg 40 is # received msgs */
789 /* Reg 108 is # of posted requests sent on VG20 */
790 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
791 EVENT0_SEL, 40);
792 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
793 EVENT1_SEL, 108);
794
795 /* Write to enable desired perf counters */
796 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
797 /* Zero out and enable the perf counters
798 * Write 0x5:
799 * Bit 0 = Start all counters(1)
800 * Bit 2 = Global counter reset enable(1)
801 */
802 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
803
804 msleep(1000);
805
806 /* Load the shadow and disable the perf counters
807 * Write 0x2:
808 * Bit 0 = Stop counters(0)
809 * Bit 1 = Load the shadow counters(1)
810 */
811 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
812
813 /* Read register values to get any >32bit overflow */
814 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
815 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
816 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
817
818 /* Get the values and add the overflow */
819 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
820 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
821 }
822
soc15_need_reset_on_init(struct amdgpu_device * adev)823 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
824 {
825 u32 sol_reg;
826
827 /* CP hangs in IGT reloading test on RN, reset to WA */
828 if (adev->asic_type == CHIP_RENOIR)
829 return true;
830
831 /* Just return false for soc15 GPUs. Reset does not seem to
832 * be necessary.
833 */
834 if (!amdgpu_passthrough(adev))
835 return false;
836
837 if (adev->flags & AMD_IS_APU)
838 return false;
839
840 /* Check sOS sign of life register to confirm sys driver and sOS
841 * are already been loaded.
842 */
843 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
844 if (sol_reg)
845 return true;
846
847 return false;
848 }
849
soc15_get_pcie_replay_count(struct amdgpu_device * adev)850 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
851 {
852 uint64_t nak_r, nak_g;
853
854 /* Get the number of NAKs received and generated */
855 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
856 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
857
858 /* Add the total number of NAKs, i.e the number of replays */
859 return (nak_r + nak_g);
860 }
861
soc15_pre_asic_init(struct amdgpu_device * adev)862 static void soc15_pre_asic_init(struct amdgpu_device *adev)
863 {
864 gmc_v9_0_restore_registers(adev);
865 }
866
867 static const struct amdgpu_asic_funcs soc15_asic_funcs =
868 {
869 .read_disabled_bios = &soc15_read_disabled_bios,
870 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
871 .read_register = &soc15_read_register,
872 .reset = &soc15_asic_reset,
873 .reset_method = &soc15_asic_reset_method,
874 .get_xclk = &soc15_get_xclk,
875 .set_uvd_clocks = &soc15_set_uvd_clocks,
876 .set_vce_clocks = &soc15_set_vce_clocks,
877 .get_config_memsize = &soc15_get_config_memsize,
878 .need_full_reset = &soc15_need_full_reset,
879 .init_doorbell_index = &vega10_doorbell_index_init,
880 .get_pcie_usage = &soc15_get_pcie_usage,
881 .need_reset_on_init = &soc15_need_reset_on_init,
882 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
883 .supports_baco = &soc15_supports_baco,
884 .pre_asic_init = &soc15_pre_asic_init,
885 .query_video_codecs = &soc15_query_video_codecs,
886 };
887
888 static const struct amdgpu_asic_funcs vega20_asic_funcs =
889 {
890 .read_disabled_bios = &soc15_read_disabled_bios,
891 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
892 .read_register = &soc15_read_register,
893 .reset = &soc15_asic_reset,
894 .reset_method = &soc15_asic_reset_method,
895 .get_xclk = &soc15_get_xclk,
896 .set_uvd_clocks = &soc15_set_uvd_clocks,
897 .set_vce_clocks = &soc15_set_vce_clocks,
898 .get_config_memsize = &soc15_get_config_memsize,
899 .need_full_reset = &soc15_need_full_reset,
900 .init_doorbell_index = &vega20_doorbell_index_init,
901 .get_pcie_usage = &vega20_get_pcie_usage,
902 .need_reset_on_init = &soc15_need_reset_on_init,
903 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
904 .supports_baco = &soc15_supports_baco,
905 .pre_asic_init = &soc15_pre_asic_init,
906 .query_video_codecs = &soc15_query_video_codecs,
907 };
908
909 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
910 {
911 .read_disabled_bios = &soc15_read_disabled_bios,
912 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
913 .read_register = &soc15_read_register,
914 .reset = &soc15_asic_reset,
915 .reset_method = &soc15_asic_reset_method,
916 .get_xclk = &soc15_get_xclk,
917 .set_uvd_clocks = &soc15_set_uvd_clocks,
918 .set_vce_clocks = &soc15_set_vce_clocks,
919 .get_config_memsize = &soc15_get_config_memsize,
920 .need_full_reset = &soc15_need_full_reset,
921 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
922 .need_reset_on_init = &soc15_need_reset_on_init,
923 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
924 .supports_baco = &soc15_supports_baco,
925 .pre_asic_init = &soc15_pre_asic_init,
926 .query_video_codecs = &soc15_query_video_codecs,
927 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
928 .get_reg_state = &aqua_vanjaram_get_reg_state,
929 };
930
soc15_common_early_init(void * handle)931 static int soc15_common_early_init(void *handle)
932 {
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934
935 adev->nbio.funcs->set_reg_remap(adev);
936 adev->smc_rreg = NULL;
937 adev->smc_wreg = NULL;
938 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
939 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
940 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
941 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
942 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
943 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
944 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
945 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
946 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
947 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
948 adev->didt_rreg = &soc15_didt_rreg;
949 adev->didt_wreg = &soc15_didt_wreg;
950 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
951 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
952 adev->se_cac_rreg = &soc15_se_cac_rreg;
953 adev->se_cac_wreg = &soc15_se_cac_wreg;
954
955 adev->rev_id = amdgpu_device_get_rev_id(adev);
956 adev->external_rev_id = 0xFF;
957 /* TODO: split the GC and PG flags based on the relevant IP version for which
958 * they are relevant.
959 */
960 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
961 case IP_VERSION(9, 0, 1):
962 adev->asic_funcs = &soc15_asic_funcs;
963 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
964 AMD_CG_SUPPORT_GFX_MGLS |
965 AMD_CG_SUPPORT_GFX_RLC_LS |
966 AMD_CG_SUPPORT_GFX_CP_LS |
967 AMD_CG_SUPPORT_GFX_3D_CGCG |
968 AMD_CG_SUPPORT_GFX_3D_CGLS |
969 AMD_CG_SUPPORT_GFX_CGCG |
970 AMD_CG_SUPPORT_GFX_CGLS |
971 AMD_CG_SUPPORT_BIF_MGCG |
972 AMD_CG_SUPPORT_BIF_LS |
973 AMD_CG_SUPPORT_HDP_LS |
974 AMD_CG_SUPPORT_DRM_MGCG |
975 AMD_CG_SUPPORT_DRM_LS |
976 AMD_CG_SUPPORT_ROM_MGCG |
977 AMD_CG_SUPPORT_DF_MGCG |
978 AMD_CG_SUPPORT_SDMA_MGCG |
979 AMD_CG_SUPPORT_SDMA_LS |
980 AMD_CG_SUPPORT_MC_MGCG |
981 AMD_CG_SUPPORT_MC_LS;
982 adev->pg_flags = 0;
983 adev->external_rev_id = 0x1;
984 break;
985 case IP_VERSION(9, 2, 1):
986 adev->asic_funcs = &soc15_asic_funcs;
987 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
988 AMD_CG_SUPPORT_GFX_MGLS |
989 AMD_CG_SUPPORT_GFX_CGCG |
990 AMD_CG_SUPPORT_GFX_CGLS |
991 AMD_CG_SUPPORT_GFX_3D_CGCG |
992 AMD_CG_SUPPORT_GFX_3D_CGLS |
993 AMD_CG_SUPPORT_GFX_CP_LS |
994 AMD_CG_SUPPORT_MC_LS |
995 AMD_CG_SUPPORT_MC_MGCG |
996 AMD_CG_SUPPORT_SDMA_MGCG |
997 AMD_CG_SUPPORT_SDMA_LS |
998 AMD_CG_SUPPORT_BIF_MGCG |
999 AMD_CG_SUPPORT_BIF_LS |
1000 AMD_CG_SUPPORT_HDP_MGCG |
1001 AMD_CG_SUPPORT_HDP_LS |
1002 AMD_CG_SUPPORT_ROM_MGCG |
1003 AMD_CG_SUPPORT_VCE_MGCG |
1004 AMD_CG_SUPPORT_UVD_MGCG;
1005 adev->pg_flags = 0;
1006 adev->external_rev_id = adev->rev_id + 0x14;
1007 break;
1008 case IP_VERSION(9, 4, 0):
1009 adev->asic_funcs = &vega20_asic_funcs;
1010 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1011 AMD_CG_SUPPORT_GFX_MGLS |
1012 AMD_CG_SUPPORT_GFX_CGCG |
1013 AMD_CG_SUPPORT_GFX_CGLS |
1014 AMD_CG_SUPPORT_GFX_3D_CGCG |
1015 AMD_CG_SUPPORT_GFX_3D_CGLS |
1016 AMD_CG_SUPPORT_GFX_CP_LS |
1017 AMD_CG_SUPPORT_MC_LS |
1018 AMD_CG_SUPPORT_MC_MGCG |
1019 AMD_CG_SUPPORT_SDMA_MGCG |
1020 AMD_CG_SUPPORT_SDMA_LS |
1021 AMD_CG_SUPPORT_BIF_MGCG |
1022 AMD_CG_SUPPORT_BIF_LS |
1023 AMD_CG_SUPPORT_HDP_MGCG |
1024 AMD_CG_SUPPORT_HDP_LS |
1025 AMD_CG_SUPPORT_ROM_MGCG |
1026 AMD_CG_SUPPORT_VCE_MGCG |
1027 AMD_CG_SUPPORT_UVD_MGCG;
1028 adev->pg_flags = 0;
1029 adev->external_rev_id = adev->rev_id + 0x28;
1030 break;
1031 case IP_VERSION(9, 1, 0):
1032 case IP_VERSION(9, 2, 2):
1033 adev->asic_funcs = &soc15_asic_funcs;
1034
1035 if (adev->rev_id >= 0x8)
1036 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1037
1038 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1039 adev->external_rev_id = adev->rev_id + 0x79;
1040 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1041 adev->external_rev_id = adev->rev_id + 0x41;
1042 else if (adev->rev_id == 1)
1043 adev->external_rev_id = adev->rev_id + 0x20;
1044 else
1045 adev->external_rev_id = adev->rev_id + 0x01;
1046
1047 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1048 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1049 AMD_CG_SUPPORT_GFX_MGLS |
1050 AMD_CG_SUPPORT_GFX_CP_LS |
1051 AMD_CG_SUPPORT_GFX_3D_CGCG |
1052 AMD_CG_SUPPORT_GFX_3D_CGLS |
1053 AMD_CG_SUPPORT_GFX_CGCG |
1054 AMD_CG_SUPPORT_GFX_CGLS |
1055 AMD_CG_SUPPORT_BIF_LS |
1056 AMD_CG_SUPPORT_HDP_LS |
1057 AMD_CG_SUPPORT_MC_MGCG |
1058 AMD_CG_SUPPORT_MC_LS |
1059 AMD_CG_SUPPORT_SDMA_MGCG |
1060 AMD_CG_SUPPORT_SDMA_LS |
1061 AMD_CG_SUPPORT_VCN_MGCG;
1062
1063 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1064 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1065 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1066 AMD_CG_SUPPORT_GFX_MGLS |
1067 AMD_CG_SUPPORT_GFX_CP_LS |
1068 AMD_CG_SUPPORT_GFX_3D_CGLS |
1069 AMD_CG_SUPPORT_GFX_CGCG |
1070 AMD_CG_SUPPORT_GFX_CGLS |
1071 AMD_CG_SUPPORT_BIF_LS |
1072 AMD_CG_SUPPORT_HDP_LS |
1073 AMD_CG_SUPPORT_MC_MGCG |
1074 AMD_CG_SUPPORT_MC_LS |
1075 AMD_CG_SUPPORT_SDMA_MGCG |
1076 AMD_CG_SUPPORT_SDMA_LS |
1077 AMD_CG_SUPPORT_VCN_MGCG;
1078
1079 /*
1080 * MMHUB PG needs to be disabled for Picasso for
1081 * stability reasons.
1082 */
1083 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1084 AMD_PG_SUPPORT_VCN;
1085 } else {
1086 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1087 AMD_CG_SUPPORT_GFX_MGLS |
1088 AMD_CG_SUPPORT_GFX_RLC_LS |
1089 AMD_CG_SUPPORT_GFX_CP_LS |
1090 AMD_CG_SUPPORT_GFX_3D_CGLS |
1091 AMD_CG_SUPPORT_GFX_CGCG |
1092 AMD_CG_SUPPORT_GFX_CGLS |
1093 AMD_CG_SUPPORT_BIF_MGCG |
1094 AMD_CG_SUPPORT_BIF_LS |
1095 AMD_CG_SUPPORT_HDP_MGCG |
1096 AMD_CG_SUPPORT_HDP_LS |
1097 AMD_CG_SUPPORT_DRM_MGCG |
1098 AMD_CG_SUPPORT_DRM_LS |
1099 AMD_CG_SUPPORT_MC_MGCG |
1100 AMD_CG_SUPPORT_MC_LS |
1101 AMD_CG_SUPPORT_SDMA_MGCG |
1102 AMD_CG_SUPPORT_SDMA_LS |
1103 AMD_CG_SUPPORT_VCN_MGCG;
1104
1105 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1106 }
1107 break;
1108 case IP_VERSION(9, 4, 1):
1109 adev->asic_funcs = &vega20_asic_funcs;
1110 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1111 AMD_CG_SUPPORT_GFX_MGLS |
1112 AMD_CG_SUPPORT_GFX_CGCG |
1113 AMD_CG_SUPPORT_GFX_CGLS |
1114 AMD_CG_SUPPORT_GFX_CP_LS |
1115 AMD_CG_SUPPORT_HDP_MGCG |
1116 AMD_CG_SUPPORT_HDP_LS |
1117 AMD_CG_SUPPORT_SDMA_MGCG |
1118 AMD_CG_SUPPORT_SDMA_LS |
1119 AMD_CG_SUPPORT_MC_MGCG |
1120 AMD_CG_SUPPORT_MC_LS |
1121 AMD_CG_SUPPORT_IH_CG |
1122 AMD_CG_SUPPORT_VCN_MGCG |
1123 AMD_CG_SUPPORT_JPEG_MGCG;
1124 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1125 adev->external_rev_id = adev->rev_id + 0x32;
1126 break;
1127 case IP_VERSION(9, 3, 0):
1128 adev->asic_funcs = &soc15_asic_funcs;
1129
1130 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1131 adev->external_rev_id = adev->rev_id + 0x91;
1132 else
1133 adev->external_rev_id = adev->rev_id + 0xa1;
1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1135 AMD_CG_SUPPORT_GFX_MGLS |
1136 AMD_CG_SUPPORT_GFX_3D_CGCG |
1137 AMD_CG_SUPPORT_GFX_3D_CGLS |
1138 AMD_CG_SUPPORT_GFX_CGCG |
1139 AMD_CG_SUPPORT_GFX_CGLS |
1140 AMD_CG_SUPPORT_GFX_CP_LS |
1141 AMD_CG_SUPPORT_MC_MGCG |
1142 AMD_CG_SUPPORT_MC_LS |
1143 AMD_CG_SUPPORT_SDMA_MGCG |
1144 AMD_CG_SUPPORT_SDMA_LS |
1145 AMD_CG_SUPPORT_BIF_LS |
1146 AMD_CG_SUPPORT_HDP_LS |
1147 AMD_CG_SUPPORT_VCN_MGCG |
1148 AMD_CG_SUPPORT_JPEG_MGCG |
1149 AMD_CG_SUPPORT_IH_CG |
1150 AMD_CG_SUPPORT_ATHUB_LS |
1151 AMD_CG_SUPPORT_ATHUB_MGCG |
1152 AMD_CG_SUPPORT_DF_MGCG;
1153 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1154 AMD_PG_SUPPORT_VCN |
1155 AMD_PG_SUPPORT_JPEG |
1156 AMD_PG_SUPPORT_VCN_DPG;
1157 break;
1158 case IP_VERSION(9, 4, 2):
1159 adev->asic_funcs = &vega20_asic_funcs;
1160 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1161 AMD_CG_SUPPORT_GFX_MGLS |
1162 AMD_CG_SUPPORT_GFX_CP_LS |
1163 AMD_CG_SUPPORT_HDP_LS |
1164 AMD_CG_SUPPORT_SDMA_MGCG |
1165 AMD_CG_SUPPORT_SDMA_LS |
1166 AMD_CG_SUPPORT_IH_CG |
1167 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1168 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1169 adev->external_rev_id = adev->rev_id + 0x3c;
1170 break;
1171 case IP_VERSION(9, 4, 3):
1172 case IP_VERSION(9, 4, 4):
1173 adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1174 adev->cg_flags =
1175 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1176 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
1177 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
1178 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
1179 AMD_CG_SUPPORT_IH_CG;
1180 adev->pg_flags =
1181 AMD_PG_SUPPORT_VCN |
1182 AMD_PG_SUPPORT_VCN_DPG |
1183 AMD_PG_SUPPORT_JPEG;
1184 /*TODO: need a new external_rev_id for GC 9.4.4? */
1185 adev->external_rev_id = adev->rev_id + 0x46;
1186 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
1187 adev->external_rev_id = adev->rev_id + 0x50;
1188 break;
1189 default:
1190 /* FIXME: not supported yet */
1191 return -EINVAL;
1192 }
1193
1194 if (amdgpu_sriov_vf(adev)) {
1195 amdgpu_virt_init_setting(adev);
1196 xgpu_ai_mailbox_set_irq_funcs(adev);
1197 }
1198
1199 return 0;
1200 }
1201
soc15_common_late_init(void * handle)1202 static int soc15_common_late_init(void *handle)
1203 {
1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1205
1206 if (amdgpu_sriov_vf(adev))
1207 xgpu_ai_mailbox_get_irq(adev);
1208
1209 /* Enable selfring doorbell aperture late because doorbell BAR
1210 * aperture will change if resize BAR successfully in gmc sw_init.
1211 */
1212 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1213
1214 return 0;
1215 }
1216
soc15_common_sw_init(void * handle)1217 static int soc15_common_sw_init(void *handle)
1218 {
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221 if (amdgpu_sriov_vf(adev))
1222 xgpu_ai_mailbox_add_irq_id(adev);
1223
1224 if (adev->df.funcs &&
1225 adev->df.funcs->sw_init)
1226 adev->df.funcs->sw_init(adev);
1227
1228 return 0;
1229 }
1230
soc15_common_sw_fini(void * handle)1231 static int soc15_common_sw_fini(void *handle)
1232 {
1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235 if (adev->df.funcs &&
1236 adev->df.funcs->sw_fini)
1237 adev->df.funcs->sw_fini(adev);
1238 return 0;
1239 }
1240
soc15_sdma_doorbell_range_init(struct amdgpu_device * adev)1241 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1242 {
1243 int i;
1244
1245 /* sdma doorbell range is programed by hypervisor */
1246 if (!amdgpu_sriov_vf(adev)) {
1247 for (i = 0; i < adev->sdma.num_instances; i++) {
1248 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1249 true, adev->doorbell_index.sdma_engine[i] << 1,
1250 adev->doorbell_index.sdma_doorbell_range);
1251 }
1252 }
1253 }
1254
soc15_common_hw_init(void * handle)1255 static int soc15_common_hw_init(void *handle)
1256 {
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258
1259 /* enable aspm */
1260 soc15_program_aspm(adev);
1261 /* setup nbio registers */
1262 adev->nbio.funcs->init_registers(adev);
1263 /* remap HDP registers to a hole in mmio space,
1264 * for the purpose of expose those registers
1265 * to process space
1266 */
1267 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1268 adev->nbio.funcs->remap_hdp_registers(adev);
1269
1270 /* enable the doorbell aperture */
1271 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1272
1273 /* HW doorbell routing policy: doorbell writing not
1274 * in SDMA/IH/MM/ACV range will be routed to CP. So
1275 * we need to init SDMA doorbell range prior
1276 * to CP ip block init and ring test. IH already
1277 * happens before CP.
1278 */
1279 soc15_sdma_doorbell_range_init(adev);
1280
1281 return 0;
1282 }
1283
soc15_common_hw_fini(void * handle)1284 static int soc15_common_hw_fini(void *handle)
1285 {
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287
1288 /* Disable the doorbell aperture and selfring doorbell aperture
1289 * separately in hw_fini because soc15_enable_doorbell_aperture
1290 * has been removed and there is no need to delay disabling
1291 * selfring doorbell.
1292 */
1293 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1294 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1295
1296 if (amdgpu_sriov_vf(adev))
1297 xgpu_ai_mailbox_put_irq(adev);
1298
1299 if ((!amdgpu_sriov_vf(adev)) &&
1300 adev->nbio.ras_if &&
1301 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1302 if (adev->nbio.ras &&
1303 adev->nbio.ras->init_ras_controller_interrupt)
1304 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1305 if (adev->nbio.ras &&
1306 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1307 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1308 }
1309
1310 return 0;
1311 }
1312
soc15_common_suspend(void * handle)1313 static int soc15_common_suspend(void *handle)
1314 {
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317 return soc15_common_hw_fini(adev);
1318 }
1319
soc15_common_resume(void * handle)1320 static int soc15_common_resume(void *handle)
1321 {
1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
1324 if (soc15_need_reset_on_resume(adev)) {
1325 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");
1326 soc15_asic_reset(adev);
1327 }
1328 return soc15_common_hw_init(adev);
1329 }
1330
soc15_common_is_idle(void * handle)1331 static bool soc15_common_is_idle(void *handle)
1332 {
1333 return true;
1334 }
1335
soc15_common_wait_for_idle(void * handle)1336 static int soc15_common_wait_for_idle(void *handle)
1337 {
1338 return 0;
1339 }
1340
soc15_common_soft_reset(void * handle)1341 static int soc15_common_soft_reset(void *handle)
1342 {
1343 return 0;
1344 }
1345
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)1346 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1347 {
1348 uint32_t def, data;
1349
1350 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1351
1352 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1353 data &= ~(0x01000000 |
1354 0x02000000 |
1355 0x04000000 |
1356 0x08000000 |
1357 0x10000000 |
1358 0x20000000 |
1359 0x40000000 |
1360 0x80000000);
1361 else
1362 data |= (0x01000000 |
1363 0x02000000 |
1364 0x04000000 |
1365 0x08000000 |
1366 0x10000000 |
1367 0x20000000 |
1368 0x40000000 |
1369 0x80000000);
1370
1371 if (def != data)
1372 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1373 }
1374
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1375 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1376 {
1377 uint32_t def, data;
1378
1379 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1380
1381 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1382 data |= 1;
1383 else
1384 data &= ~1;
1385
1386 if (def != data)
1387 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1388 }
1389
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1390 static int soc15_common_set_clockgating_state(void *handle,
1391 enum amd_clockgating_state state)
1392 {
1393 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1394
1395 if (amdgpu_sriov_vf(adev))
1396 return 0;
1397
1398 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1399 case IP_VERSION(6, 1, 0):
1400 case IP_VERSION(6, 2, 0):
1401 case IP_VERSION(7, 4, 0):
1402 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1403 state == AMD_CG_STATE_GATE);
1404 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1405 state == AMD_CG_STATE_GATE);
1406 adev->hdp.funcs->update_clock_gating(adev,
1407 state == AMD_CG_STATE_GATE);
1408 soc15_update_drm_clock_gating(adev,
1409 state == AMD_CG_STATE_GATE);
1410 soc15_update_drm_light_sleep(adev,
1411 state == AMD_CG_STATE_GATE);
1412 adev->smuio.funcs->update_rom_clock_gating(adev,
1413 state == AMD_CG_STATE_GATE);
1414 adev->df.funcs->update_medium_grain_clock_gating(adev,
1415 state == AMD_CG_STATE_GATE);
1416 break;
1417 case IP_VERSION(7, 0, 0):
1418 case IP_VERSION(7, 0, 1):
1419 case IP_VERSION(2, 5, 0):
1420 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1421 state == AMD_CG_STATE_GATE);
1422 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1423 state == AMD_CG_STATE_GATE);
1424 adev->hdp.funcs->update_clock_gating(adev,
1425 state == AMD_CG_STATE_GATE);
1426 soc15_update_drm_clock_gating(adev,
1427 state == AMD_CG_STATE_GATE);
1428 soc15_update_drm_light_sleep(adev,
1429 state == AMD_CG_STATE_GATE);
1430 break;
1431 case IP_VERSION(7, 4, 1):
1432 case IP_VERSION(7, 4, 4):
1433 adev->hdp.funcs->update_clock_gating(adev,
1434 state == AMD_CG_STATE_GATE);
1435 break;
1436 default:
1437 break;
1438 }
1439 return 0;
1440 }
1441
soc15_common_get_clockgating_state(void * handle,u64 * flags)1442 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1443 {
1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445 int data;
1446
1447 if (amdgpu_sriov_vf(adev))
1448 *flags = 0;
1449
1450 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1451 adev->nbio.funcs->get_clockgating_state(adev, flags);
1452
1453 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1454 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1455
1456 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
1457 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&
1458 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {
1459 /* AMD_CG_SUPPORT_DRM_MGCG */
1460 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1461 if (!(data & 0x01000000))
1462 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1463
1464 /* AMD_CG_SUPPORT_DRM_LS */
1465 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1466 if (data & 0x1)
1467 *flags |= AMD_CG_SUPPORT_DRM_LS;
1468 }
1469
1470 /* AMD_CG_SUPPORT_ROM_MGCG */
1471 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1472 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1473
1474 if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1475 adev->df.funcs->get_clockgating_state(adev, flags);
1476 }
1477
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)1478 static int soc15_common_set_powergating_state(void *handle,
1479 enum amd_powergating_state state)
1480 {
1481 /* todo */
1482 return 0;
1483 }
1484
1485 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1486 .name = "soc15_common",
1487 .early_init = soc15_common_early_init,
1488 .late_init = soc15_common_late_init,
1489 .sw_init = soc15_common_sw_init,
1490 .sw_fini = soc15_common_sw_fini,
1491 .hw_init = soc15_common_hw_init,
1492 .hw_fini = soc15_common_hw_fini,
1493 .suspend = soc15_common_suspend,
1494 .resume = soc15_common_resume,
1495 .is_idle = soc15_common_is_idle,
1496 .wait_for_idle = soc15_common_wait_for_idle,
1497 .soft_reset = soc15_common_soft_reset,
1498 .set_clockgating_state = soc15_common_set_clockgating_state,
1499 .set_powergating_state = soc15_common_set_powergating_state,
1500 .get_clockgating_state= soc15_common_get_clockgating_state,
1501 .dump_ip_state = NULL,
1502 .print_ip_state = NULL,
1503 };
1504