1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
36 #include "atom.h"
37 #include "amd_pcie.h"
38
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15_common.h"
45 #include "soc21.h"
46 #include "mxgpu_nv.h"
47
48 static const struct amd_ip_funcs soc21_common_ip_funcs;
49
50 /* SOC21 */
51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55 };
56
57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60 };
61
62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
65 };
66
67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70 };
71
72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78 };
79
80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85 };
86
87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90 };
91
92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
95 };
96
97 /* SRIOV SOC21, not const since data is controlled by host */
98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102 };
103
104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107 };
108
109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112 };
113
114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117 };
118
119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
125 };
126
127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
132 };
133
134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
137 };
138
139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
142 };
143
soc21_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)144 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
145 const struct amdgpu_video_codecs **codecs)
146 {
147 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
148 return -EINVAL;
149
150 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
151 case IP_VERSION(4, 0, 0):
152 case IP_VERSION(4, 0, 2):
153 case IP_VERSION(4, 0, 4):
154 case IP_VERSION(4, 0, 5):
155 if (amdgpu_sriov_vf(adev)) {
156 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
157 !amdgpu_sriov_is_av1_support(adev)) {
158 if (encode)
159 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
160 else
161 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
162 } else {
163 if (encode)
164 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
165 else
166 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
167 }
168 } else {
169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
170 if (encode)
171 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
172 else
173 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
174 } else {
175 if (encode)
176 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
177 else
178 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
179 }
180 }
181 return 0;
182 case IP_VERSION(4, 0, 6):
183 if (encode)
184 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
185 else
186 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
187 return 0;
188 default:
189 return -EINVAL;
190 }
191 }
192
soc21_didt_rreg(struct amdgpu_device * adev,u32 reg)193 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
194 {
195 unsigned long flags, address, data;
196 u32 r;
197
198 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
199 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
200
201 spin_lock_irqsave(&adev->didt_idx_lock, flags);
202 WREG32(address, (reg));
203 r = RREG32(data);
204 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
205 return r;
206 }
207
soc21_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)208 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209 {
210 unsigned long flags, address, data;
211
212 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
213 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
214
215 spin_lock_irqsave(&adev->didt_idx_lock, flags);
216 WREG32(address, (reg));
217 WREG32(data, (v));
218 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
219 }
220
soc21_get_config_memsize(struct amdgpu_device * adev)221 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
222 {
223 return adev->nbio.funcs->get_memsize(adev);
224 }
225
soc21_get_xclk(struct amdgpu_device * adev)226 static u32 soc21_get_xclk(struct amdgpu_device *adev)
227 {
228 return adev->clock.spll.reference_freq;
229 }
230
231
soc21_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)232 void soc21_grbm_select(struct amdgpu_device *adev,
233 u32 me, u32 pipe, u32 queue, u32 vmid)
234 {
235 u32 grbm_gfx_cntl = 0;
236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
237 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
238 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
239 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
240
241 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
242 }
243
soc21_read_disabled_bios(struct amdgpu_device * adev)244 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
245 {
246 /* todo */
247 return false;
248 }
249
250 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
251 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
252 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
253 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
254 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
255 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
256 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
257 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
258 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
259 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
260 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
261 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
262 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
263 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
264 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
265 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
266 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
267 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
268 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
269 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
270 };
271
soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)272 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
273 u32 sh_num, u32 reg_offset)
274 {
275 uint32_t val;
276
277 mutex_lock(&adev->grbm_idx_mutex);
278 if (se_num != 0xffffffff || sh_num != 0xffffffff)
279 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
280
281 val = RREG32(reg_offset);
282
283 if (se_num != 0xffffffff || sh_num != 0xffffffff)
284 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
285 mutex_unlock(&adev->grbm_idx_mutex);
286 return val;
287 }
288
soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)289 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
290 bool indexed, u32 se_num,
291 u32 sh_num, u32 reg_offset)
292 {
293 if (indexed) {
294 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
295 } else {
296 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
297 return adev->gfx.config.gb_addr_config;
298 return RREG32(reg_offset);
299 }
300 }
301
soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)302 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
303 u32 sh_num, u32 reg_offset, u32 *value)
304 {
305 uint32_t i;
306 struct soc15_allowed_register_entry *en;
307
308 *value = 0;
309 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
310 en = &soc21_allowed_read_registers[i];
311 if (!adev->reg_offset[en->hwip][en->inst])
312 continue;
313 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
314 + en->reg_offset))
315 continue;
316
317 *value = soc21_get_register_value(adev,
318 soc21_allowed_read_registers[i].grbm_indexed,
319 se_num, sh_num, reg_offset);
320 return 0;
321 }
322 return -EINVAL;
323 }
324
325 #if 0
326 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
327 {
328 u32 i;
329 int ret = 0;
330
331 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
332
333 /* disable BM */
334 pci_clear_master(adev->pdev);
335
336 amdgpu_device_cache_pci_state(adev->pdev);
337
338 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
339 dev_info(adev->dev, "GPU smu mode1 reset\n");
340 ret = amdgpu_dpm_mode1_reset(adev);
341 } else {
342 dev_info(adev->dev, "GPU psp mode1 reset\n");
343 ret = psp_gpu_reset(adev);
344 }
345
346 if (ret)
347 dev_err(adev->dev, "GPU mode1 reset failed\n");
348 amdgpu_device_load_pci_state(adev->pdev);
349
350 /* wait for asic to come out of reset */
351 for (i = 0; i < adev->usec_timeout; i++) {
352 u32 memsize = adev->nbio.funcs->get_memsize(adev);
353
354 if (memsize != 0xffffffff)
355 break;
356 udelay(1);
357 }
358
359 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
360
361 return ret;
362 }
363 #endif
364
365 static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device * adev)366 soc21_asic_reset_method(struct amdgpu_device *adev)
367 {
368 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
369 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
370 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
371 return amdgpu_reset_method;
372
373 if (amdgpu_reset_method != -1)
374 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
375 amdgpu_reset_method);
376
377 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
378 case IP_VERSION(13, 0, 0):
379 case IP_VERSION(13, 0, 7):
380 case IP_VERSION(13, 0, 10):
381 return AMD_RESET_METHOD_MODE1;
382 case IP_VERSION(13, 0, 4):
383 case IP_VERSION(13, 0, 11):
384 case IP_VERSION(14, 0, 0):
385 case IP_VERSION(14, 0, 1):
386 case IP_VERSION(14, 0, 4):
387 return AMD_RESET_METHOD_MODE2;
388 default:
389 if (amdgpu_dpm_is_baco_supported(adev))
390 return AMD_RESET_METHOD_BACO;
391 else
392 return AMD_RESET_METHOD_MODE1;
393 }
394 }
395
soc21_asic_reset(struct amdgpu_device * adev)396 static int soc21_asic_reset(struct amdgpu_device *adev)
397 {
398 int ret = 0;
399
400 switch (soc21_asic_reset_method(adev)) {
401 case AMD_RESET_METHOD_PCI:
402 dev_info(adev->dev, "PCI reset\n");
403 ret = amdgpu_device_pci_reset(adev);
404 break;
405 case AMD_RESET_METHOD_BACO:
406 dev_info(adev->dev, "BACO reset\n");
407 ret = amdgpu_dpm_baco_reset(adev);
408 break;
409 case AMD_RESET_METHOD_MODE2:
410 dev_info(adev->dev, "MODE2 reset\n");
411 ret = amdgpu_dpm_mode2_reset(adev);
412 break;
413 default:
414 dev_info(adev->dev, "MODE1 reset\n");
415 ret = amdgpu_device_mode1_reset(adev);
416 break;
417 }
418
419 return ret;
420 }
421
soc21_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)422 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
423 {
424 /* todo */
425 return 0;
426 }
427
soc21_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)428 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
429 {
430 /* todo */
431 return 0;
432 }
433
soc21_program_aspm(struct amdgpu_device * adev)434 static void soc21_program_aspm(struct amdgpu_device *adev)
435 {
436 if (!amdgpu_device_should_use_aspm(adev))
437 return;
438
439 if (adev->nbio.funcs->program_aspm)
440 adev->nbio.funcs->program_aspm(adev);
441 }
442
443 const struct amdgpu_ip_block_version soc21_common_ip_block = {
444 .type = AMD_IP_BLOCK_TYPE_COMMON,
445 .major = 1,
446 .minor = 0,
447 .rev = 0,
448 .funcs = &soc21_common_ip_funcs,
449 };
450
soc21_need_full_reset(struct amdgpu_device * adev)451 static bool soc21_need_full_reset(struct amdgpu_device *adev)
452 {
453 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
454 case IP_VERSION(11, 0, 0):
455 case IP_VERSION(11, 0, 2):
456 case IP_VERSION(11, 0, 3):
457 default:
458 return true;
459 }
460 }
461
soc21_need_reset_on_init(struct amdgpu_device * adev)462 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
463 {
464 u32 sol_reg;
465
466 if (adev->flags & AMD_IS_APU)
467 return false;
468
469 /* Check sOS sign of life register to confirm sys driver and sOS
470 * are already been loaded.
471 */
472 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
473 if (sol_reg)
474 return true;
475
476 return false;
477 }
478
soc21_init_doorbell_index(struct amdgpu_device * adev)479 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
480 {
481 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
482 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
483 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
484 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
485 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
486 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
487 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
488 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
489 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
490 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
491 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
492 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
493 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
494 adev->doorbell_index.gfx_userqueue_start =
495 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
496 adev->doorbell_index.gfx_userqueue_end =
497 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
498 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
499 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
500 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
501 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
502 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
503 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
504 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
505 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
506 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
507 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
508 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
509 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
510
511 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
512 adev->doorbell_index.sdma_doorbell_range = 20;
513 }
514
soc21_pre_asic_init(struct amdgpu_device * adev)515 static void soc21_pre_asic_init(struct amdgpu_device *adev)
516 {
517 }
518
soc21_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)519 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
520 bool enter)
521 {
522 if (enter)
523 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
524 else
525 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
526
527 if (adev->gfx.funcs->update_perfmon_mgcg)
528 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
529
530 return 0;
531 }
532
533 static const struct amdgpu_asic_funcs soc21_asic_funcs = {
534 .read_disabled_bios = &soc21_read_disabled_bios,
535 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
536 .read_register = &soc21_read_register,
537 .reset = &soc21_asic_reset,
538 .reset_method = &soc21_asic_reset_method,
539 .get_xclk = &soc21_get_xclk,
540 .set_uvd_clocks = &soc21_set_uvd_clocks,
541 .set_vce_clocks = &soc21_set_vce_clocks,
542 .get_config_memsize = &soc21_get_config_memsize,
543 .init_doorbell_index = &soc21_init_doorbell_index,
544 .need_full_reset = &soc21_need_full_reset,
545 .need_reset_on_init = &soc21_need_reset_on_init,
546 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
547 .supports_baco = &amdgpu_dpm_is_baco_supported,
548 .pre_asic_init = &soc21_pre_asic_init,
549 .query_video_codecs = &soc21_query_video_codecs,
550 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
551 };
552
soc21_common_early_init(void * handle)553 static int soc21_common_early_init(void *handle)
554 {
555 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
556
557 adev->nbio.funcs->set_reg_remap(adev);
558 adev->smc_rreg = NULL;
559 adev->smc_wreg = NULL;
560 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
561 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
562 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
563 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
564 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
565 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
566
567 /* TODO: will add them during VCN v2 implementation */
568 adev->uvd_ctx_rreg = NULL;
569 adev->uvd_ctx_wreg = NULL;
570
571 adev->didt_rreg = &soc21_didt_rreg;
572 adev->didt_wreg = &soc21_didt_wreg;
573
574 adev->asic_funcs = &soc21_asic_funcs;
575
576 adev->rev_id = amdgpu_device_get_rev_id(adev);
577 adev->external_rev_id = 0xff;
578 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
579 case IP_VERSION(11, 0, 0):
580 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
581 AMD_CG_SUPPORT_GFX_CGLS |
582 #if 0
583 AMD_CG_SUPPORT_GFX_3D_CGCG |
584 AMD_CG_SUPPORT_GFX_3D_CGLS |
585 #endif
586 AMD_CG_SUPPORT_GFX_MGCG |
587 AMD_CG_SUPPORT_REPEATER_FGCG |
588 AMD_CG_SUPPORT_GFX_FGCG |
589 AMD_CG_SUPPORT_GFX_PERF_CLK |
590 AMD_CG_SUPPORT_VCN_MGCG |
591 AMD_CG_SUPPORT_JPEG_MGCG |
592 AMD_CG_SUPPORT_ATHUB_MGCG |
593 AMD_CG_SUPPORT_ATHUB_LS |
594 AMD_CG_SUPPORT_MC_MGCG |
595 AMD_CG_SUPPORT_MC_LS |
596 AMD_CG_SUPPORT_IH_CG |
597 AMD_CG_SUPPORT_HDP_SD;
598 adev->pg_flags = AMD_PG_SUPPORT_VCN |
599 AMD_PG_SUPPORT_VCN_DPG |
600 AMD_PG_SUPPORT_JPEG |
601 AMD_PG_SUPPORT_ATHUB |
602 AMD_PG_SUPPORT_MMHUB;
603 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
604 break;
605 case IP_VERSION(11, 0, 2):
606 adev->cg_flags =
607 AMD_CG_SUPPORT_GFX_CGCG |
608 AMD_CG_SUPPORT_GFX_CGLS |
609 AMD_CG_SUPPORT_REPEATER_FGCG |
610 AMD_CG_SUPPORT_VCN_MGCG |
611 AMD_CG_SUPPORT_JPEG_MGCG |
612 AMD_CG_SUPPORT_ATHUB_MGCG |
613 AMD_CG_SUPPORT_ATHUB_LS |
614 AMD_CG_SUPPORT_IH_CG |
615 AMD_CG_SUPPORT_HDP_SD;
616 adev->pg_flags =
617 AMD_PG_SUPPORT_VCN |
618 AMD_PG_SUPPORT_VCN_DPG |
619 AMD_PG_SUPPORT_JPEG |
620 AMD_PG_SUPPORT_ATHUB |
621 AMD_PG_SUPPORT_MMHUB;
622 adev->external_rev_id = adev->rev_id + 0x10;
623 break;
624 case IP_VERSION(11, 0, 1):
625 adev->cg_flags =
626 AMD_CG_SUPPORT_GFX_CGCG |
627 AMD_CG_SUPPORT_GFX_CGLS |
628 AMD_CG_SUPPORT_GFX_MGCG |
629 AMD_CG_SUPPORT_GFX_FGCG |
630 AMD_CG_SUPPORT_REPEATER_FGCG |
631 AMD_CG_SUPPORT_GFX_PERF_CLK |
632 AMD_CG_SUPPORT_MC_MGCG |
633 AMD_CG_SUPPORT_MC_LS |
634 AMD_CG_SUPPORT_HDP_MGCG |
635 AMD_CG_SUPPORT_HDP_LS |
636 AMD_CG_SUPPORT_ATHUB_MGCG |
637 AMD_CG_SUPPORT_ATHUB_LS |
638 AMD_CG_SUPPORT_IH_CG |
639 AMD_CG_SUPPORT_BIF_MGCG |
640 AMD_CG_SUPPORT_BIF_LS |
641 AMD_CG_SUPPORT_VCN_MGCG |
642 AMD_CG_SUPPORT_JPEG_MGCG;
643 adev->pg_flags =
644 AMD_PG_SUPPORT_GFX_PG |
645 AMD_PG_SUPPORT_VCN |
646 AMD_PG_SUPPORT_VCN_DPG |
647 AMD_PG_SUPPORT_JPEG;
648 adev->external_rev_id = adev->rev_id + 0x1;
649 break;
650 case IP_VERSION(11, 0, 3):
651 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
652 AMD_CG_SUPPORT_JPEG_MGCG |
653 AMD_CG_SUPPORT_GFX_CGCG |
654 AMD_CG_SUPPORT_GFX_CGLS |
655 AMD_CG_SUPPORT_REPEATER_FGCG |
656 AMD_CG_SUPPORT_GFX_MGCG |
657 AMD_CG_SUPPORT_HDP_SD |
658 AMD_CG_SUPPORT_ATHUB_MGCG |
659 AMD_CG_SUPPORT_ATHUB_LS;
660 adev->pg_flags = AMD_PG_SUPPORT_VCN |
661 AMD_PG_SUPPORT_VCN_DPG |
662 AMD_PG_SUPPORT_JPEG;
663 adev->external_rev_id = adev->rev_id + 0x20;
664 break;
665 case IP_VERSION(11, 0, 4):
666 adev->cg_flags =
667 AMD_CG_SUPPORT_GFX_CGCG |
668 AMD_CG_SUPPORT_GFX_CGLS |
669 AMD_CG_SUPPORT_GFX_MGCG |
670 AMD_CG_SUPPORT_GFX_FGCG |
671 AMD_CG_SUPPORT_REPEATER_FGCG |
672 AMD_CG_SUPPORT_GFX_PERF_CLK |
673 AMD_CG_SUPPORT_MC_MGCG |
674 AMD_CG_SUPPORT_MC_LS |
675 AMD_CG_SUPPORT_HDP_MGCG |
676 AMD_CG_SUPPORT_HDP_LS |
677 AMD_CG_SUPPORT_ATHUB_MGCG |
678 AMD_CG_SUPPORT_ATHUB_LS |
679 AMD_CG_SUPPORT_IH_CG |
680 AMD_CG_SUPPORT_BIF_MGCG |
681 AMD_CG_SUPPORT_BIF_LS |
682 AMD_CG_SUPPORT_VCN_MGCG |
683 AMD_CG_SUPPORT_JPEG_MGCG;
684 adev->pg_flags = AMD_PG_SUPPORT_VCN |
685 AMD_PG_SUPPORT_VCN_DPG |
686 AMD_PG_SUPPORT_GFX_PG |
687 AMD_PG_SUPPORT_JPEG;
688 adev->external_rev_id = adev->rev_id + 0x80;
689 break;
690 case IP_VERSION(11, 5, 0):
691 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
692 AMD_CG_SUPPORT_JPEG_MGCG |
693 AMD_CG_SUPPORT_GFX_CGCG |
694 AMD_CG_SUPPORT_GFX_CGLS |
695 AMD_CG_SUPPORT_GFX_MGCG |
696 AMD_CG_SUPPORT_GFX_FGCG |
697 AMD_CG_SUPPORT_REPEATER_FGCG |
698 AMD_CG_SUPPORT_GFX_PERF_CLK |
699 AMD_CG_SUPPORT_GFX_3D_CGCG |
700 AMD_CG_SUPPORT_GFX_3D_CGLS |
701 AMD_CG_SUPPORT_MC_MGCG |
702 AMD_CG_SUPPORT_MC_LS |
703 AMD_CG_SUPPORT_HDP_LS |
704 AMD_CG_SUPPORT_HDP_DS |
705 AMD_CG_SUPPORT_HDP_SD |
706 AMD_CG_SUPPORT_ATHUB_MGCG |
707 AMD_CG_SUPPORT_ATHUB_LS |
708 AMD_CG_SUPPORT_IH_CG |
709 AMD_CG_SUPPORT_BIF_MGCG |
710 AMD_CG_SUPPORT_BIF_LS;
711 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
712 AMD_PG_SUPPORT_JPEG_DPG |
713 AMD_PG_SUPPORT_VCN |
714 AMD_PG_SUPPORT_JPEG |
715 AMD_PG_SUPPORT_GFX_PG;
716 if (adev->rev_id == 0)
717 adev->external_rev_id = 0x1;
718 else
719 adev->external_rev_id = adev->rev_id + 0x10;
720 break;
721 case IP_VERSION(11, 5, 1):
722 adev->cg_flags =
723 AMD_CG_SUPPORT_GFX_CGCG |
724 AMD_CG_SUPPORT_GFX_CGLS |
725 AMD_CG_SUPPORT_GFX_MGCG |
726 AMD_CG_SUPPORT_GFX_FGCG |
727 AMD_CG_SUPPORT_REPEATER_FGCG |
728 AMD_CG_SUPPORT_GFX_PERF_CLK |
729 AMD_CG_SUPPORT_GFX_3D_CGCG |
730 AMD_CG_SUPPORT_GFX_3D_CGLS |
731 AMD_CG_SUPPORT_MC_MGCG |
732 AMD_CG_SUPPORT_MC_LS |
733 AMD_CG_SUPPORT_HDP_LS |
734 AMD_CG_SUPPORT_HDP_DS |
735 AMD_CG_SUPPORT_HDP_SD |
736 AMD_CG_SUPPORT_ATHUB_MGCG |
737 AMD_CG_SUPPORT_ATHUB_LS |
738 AMD_CG_SUPPORT_IH_CG |
739 AMD_CG_SUPPORT_BIF_MGCG |
740 AMD_CG_SUPPORT_BIF_LS |
741 AMD_CG_SUPPORT_VCN_MGCG |
742 AMD_CG_SUPPORT_JPEG_MGCG;
743 adev->pg_flags =
744 AMD_PG_SUPPORT_GFX_PG |
745 AMD_PG_SUPPORT_VCN |
746 AMD_PG_SUPPORT_VCN_DPG |
747 AMD_PG_SUPPORT_JPEG;
748 adev->external_rev_id = adev->rev_id + 0xc1;
749 break;
750 case IP_VERSION(11, 5, 2):
751 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
752 AMD_CG_SUPPORT_JPEG_MGCG |
753 AMD_CG_SUPPORT_GFX_CGCG |
754 AMD_CG_SUPPORT_GFX_CGLS |
755 AMD_CG_SUPPORT_GFX_MGCG |
756 AMD_CG_SUPPORT_GFX_FGCG |
757 AMD_CG_SUPPORT_REPEATER_FGCG |
758 AMD_CG_SUPPORT_GFX_PERF_CLK |
759 AMD_CG_SUPPORT_GFX_3D_CGCG |
760 AMD_CG_SUPPORT_GFX_3D_CGLS |
761 AMD_CG_SUPPORT_MC_MGCG |
762 AMD_CG_SUPPORT_MC_LS |
763 AMD_CG_SUPPORT_HDP_LS |
764 AMD_CG_SUPPORT_HDP_DS |
765 AMD_CG_SUPPORT_HDP_SD |
766 AMD_CG_SUPPORT_ATHUB_MGCG |
767 AMD_CG_SUPPORT_ATHUB_LS |
768 AMD_CG_SUPPORT_IH_CG |
769 AMD_CG_SUPPORT_BIF_MGCG |
770 AMD_CG_SUPPORT_BIF_LS;
771 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
772 AMD_PG_SUPPORT_VCN |
773 AMD_PG_SUPPORT_JPEG_DPG |
774 AMD_PG_SUPPORT_JPEG |
775 AMD_PG_SUPPORT_GFX_PG;
776 adev->external_rev_id = adev->rev_id + 0x40;
777 break;
778 default:
779 /* FIXME: not supported yet */
780 return -EINVAL;
781 }
782
783 if (amdgpu_sriov_vf(adev)) {
784 amdgpu_virt_init_setting(adev);
785 xgpu_nv_mailbox_set_irq_funcs(adev);
786 }
787
788 return 0;
789 }
790
soc21_common_late_init(void * handle)791 static int soc21_common_late_init(void *handle)
792 {
793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
794
795 if (amdgpu_sriov_vf(adev)) {
796 xgpu_nv_mailbox_get_irq(adev);
797 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
798 !amdgpu_sriov_is_av1_support(adev)) {
799 amdgpu_virt_update_sriov_video_codec(adev,
800 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
801 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
802 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
803 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
804 } else {
805 amdgpu_virt_update_sriov_video_codec(adev,
806 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
807 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
808 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
809 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
810 }
811 } else {
812 if (adev->nbio.ras &&
813 adev->nbio.ras_err_event_athub_irq.funcs)
814 /* don't need to fail gpu late init
815 * if enabling athub_err_event interrupt failed
816 * nbio v4_3 only support fatal error hanlding
817 * just enable the interrupt directly */
818 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
819 }
820
821 /* Enable selfring doorbell aperture late because doorbell BAR
822 * aperture will change if resize BAR successfully in gmc sw_init.
823 */
824 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
825
826 return 0;
827 }
828
soc21_common_sw_init(void * handle)829 static int soc21_common_sw_init(void *handle)
830 {
831 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
832
833 if (amdgpu_sriov_vf(adev))
834 xgpu_nv_mailbox_add_irq_id(adev);
835
836 return 0;
837 }
838
soc21_common_sw_fini(void * handle)839 static int soc21_common_sw_fini(void *handle)
840 {
841 return 0;
842 }
843
soc21_common_hw_init(void * handle)844 static int soc21_common_hw_init(void *handle)
845 {
846 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
847
848 /* enable aspm */
849 soc21_program_aspm(adev);
850 /* setup nbio registers */
851 adev->nbio.funcs->init_registers(adev);
852 /* remap HDP registers to a hole in mmio space,
853 * for the purpose of expose those registers
854 * to process space
855 */
856 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
857 adev->nbio.funcs->remap_hdp_registers(adev);
858 /* enable the doorbell aperture */
859 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
860
861 return 0;
862 }
863
soc21_common_hw_fini(void * handle)864 static int soc21_common_hw_fini(void *handle)
865 {
866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
867
868 /* Disable the doorbell aperture and selfring doorbell aperture
869 * separately in hw_fini because soc21_enable_doorbell_aperture
870 * has been removed and there is no need to delay disabling
871 * selfring doorbell.
872 */
873 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
874 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
875
876 if (amdgpu_sriov_vf(adev)) {
877 xgpu_nv_mailbox_put_irq(adev);
878 } else {
879 if (adev->nbio.ras &&
880 adev->nbio.ras_err_event_athub_irq.funcs)
881 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
882 }
883
884 return 0;
885 }
886
soc21_common_suspend(void * handle)887 static int soc21_common_suspend(void *handle)
888 {
889 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
890
891 return soc21_common_hw_fini(adev);
892 }
893
soc21_need_reset_on_resume(struct amdgpu_device * adev)894 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
895 {
896 u32 sol_reg1, sol_reg2;
897
898 /* Will reset for the following suspend abort cases.
899 * 1) Only reset dGPU side.
900 * 2) S3 suspend got aborted and TOS is active.
901 */
902 if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
903 !adev->suspend_complete) {
904 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
905 msleep(100);
906 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
907
908 return (sol_reg1 != sol_reg2);
909 }
910
911 return false;
912 }
913
soc21_common_resume(void * handle)914 static int soc21_common_resume(void *handle)
915 {
916 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
917
918 if (soc21_need_reset_on_resume(adev)) {
919 dev_info(adev->dev, "S3 suspend aborted, resetting...");
920 soc21_asic_reset(adev);
921 }
922
923 return soc21_common_hw_init(adev);
924 }
925
soc21_common_is_idle(void * handle)926 static bool soc21_common_is_idle(void *handle)
927 {
928 return true;
929 }
930
soc21_common_wait_for_idle(void * handle)931 static int soc21_common_wait_for_idle(void *handle)
932 {
933 return 0;
934 }
935
soc21_common_soft_reset(void * handle)936 static int soc21_common_soft_reset(void *handle)
937 {
938 return 0;
939 }
940
soc21_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)941 static int soc21_common_set_clockgating_state(void *handle,
942 enum amd_clockgating_state state)
943 {
944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
945
946 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
947 case IP_VERSION(4, 3, 0):
948 case IP_VERSION(4, 3, 1):
949 case IP_VERSION(7, 7, 0):
950 case IP_VERSION(7, 7, 1):
951 case IP_VERSION(7, 11, 0):
952 case IP_VERSION(7, 11, 1):
953 case IP_VERSION(7, 11, 3):
954 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
955 state == AMD_CG_STATE_GATE);
956 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
957 state == AMD_CG_STATE_GATE);
958 adev->hdp.funcs->update_clock_gating(adev,
959 state == AMD_CG_STATE_GATE);
960 break;
961 default:
962 break;
963 }
964 return 0;
965 }
966
soc21_common_set_powergating_state(void * handle,enum amd_powergating_state state)967 static int soc21_common_set_powergating_state(void *handle,
968 enum amd_powergating_state state)
969 {
970 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
971
972 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
973 case IP_VERSION(6, 0, 0):
974 case IP_VERSION(6, 0, 2):
975 adev->lsdma.funcs->update_memory_power_gating(adev,
976 state == AMD_PG_STATE_GATE);
977 break;
978 default:
979 break;
980 }
981
982 return 0;
983 }
984
soc21_common_get_clockgating_state(void * handle,u64 * flags)985 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
986 {
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988
989 adev->nbio.funcs->get_clockgating_state(adev, flags);
990
991 adev->hdp.funcs->get_clock_gating_state(adev, flags);
992 }
993
994 static const struct amd_ip_funcs soc21_common_ip_funcs = {
995 .name = "soc21_common",
996 .early_init = soc21_common_early_init,
997 .late_init = soc21_common_late_init,
998 .sw_init = soc21_common_sw_init,
999 .sw_fini = soc21_common_sw_fini,
1000 .hw_init = soc21_common_hw_init,
1001 .hw_fini = soc21_common_hw_fini,
1002 .suspend = soc21_common_suspend,
1003 .resume = soc21_common_resume,
1004 .is_idle = soc21_common_is_idle,
1005 .wait_for_idle = soc21_common_wait_for_idle,
1006 .soft_reset = soc21_common_soft_reset,
1007 .set_clockgating_state = soc21_common_set_clockgating_state,
1008 .set_powergating_state = soc21_common_set_powergating_state,
1009 .get_clockgating_state = soc21_common_get_clockgating_state,
1010 .dump_ip_state = NULL,
1011 .print_ip_state = NULL,
1012 };
1013