1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "amdgpu_pm.h"
30 #include "soc15.h"
31 #include "soc15d.h"
32 #include "vcn_v2_0.h"
33 #include "mmsch_v1_0.h"
34 #include "vcn_v2_5.h"
35
36 #include "vcn/vcn_2_5_offset.h"
37 #include "vcn/vcn_2_5_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
43
44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51
52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
56
57 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2
58
59 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
94 };
95
96 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
97 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
98 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
99 static int vcn_v2_5_set_powergating_state(void *handle,
100 enum amd_powergating_state state);
101 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
102 int inst_idx, struct dpg_pause_state *new_state);
103 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
104 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
105
106 static int amdgpu_ih_clientid_vcns[] = {
107 SOC15_IH_CLIENTID_VCN,
108 SOC15_IH_CLIENTID_VCN1
109 };
110
111 /**
112 * vcn_v2_5_early_init - set function pointers and load microcode
113 *
114 * @handle: amdgpu_device pointer
115 *
116 * Set ring and irq function pointers
117 * Load microcode from filesystem
118 */
vcn_v2_5_early_init(void * handle)119 static int vcn_v2_5_early_init(void *handle)
120 {
121 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
122
123 if (amdgpu_sriov_vf(adev)) {
124 adev->vcn.num_vcn_inst = 2;
125 adev->vcn.harvest_config = 0;
126 adev->vcn.num_enc_rings = 1;
127 } else {
128 u32 harvest;
129 int i;
130
131 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
132 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
133 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
134 adev->vcn.harvest_config |= 1 << i;
135 }
136 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
137 AMDGPU_VCN_HARVEST_VCN1))
138 /* both instances are harvested, disable the block */
139 return -ENOENT;
140
141 adev->vcn.num_enc_rings = 2;
142 }
143
144 vcn_v2_5_set_dec_ring_funcs(adev);
145 vcn_v2_5_set_enc_ring_funcs(adev);
146 vcn_v2_5_set_irq_funcs(adev);
147 vcn_v2_5_set_ras_funcs(adev);
148
149 return amdgpu_vcn_early_init(adev);
150 }
151
152 /**
153 * vcn_v2_5_sw_init - sw init for VCN block
154 *
155 * @handle: amdgpu_device pointer
156 *
157 * Load firmware and sw initialization
158 */
vcn_v2_5_sw_init(void * handle)159 static int vcn_v2_5_sw_init(void *handle)
160 {
161 struct amdgpu_ring *ring;
162 int i, j, r;
163 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
164 uint32_t *ptr;
165 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
166
167 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
168 if (adev->vcn.harvest_config & (1 << j))
169 continue;
170 /* VCN DEC TRAP */
171 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
172 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
173 if (r)
174 return r;
175
176 /* VCN ENC TRAP */
177 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
178 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
179 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
180 if (r)
181 return r;
182 }
183
184 /* VCN POISON TRAP */
185 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
186 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
187 if (r)
188 return r;
189 }
190
191 r = amdgpu_vcn_sw_init(adev);
192 if (r)
193 return r;
194
195 amdgpu_vcn_setup_ucode(adev);
196
197 r = amdgpu_vcn_resume(adev);
198 if (r)
199 return r;
200
201 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
202 volatile struct amdgpu_fw_shared *fw_shared;
203
204 if (adev->vcn.harvest_config & (1 << j))
205 continue;
206 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
207 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
208 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
209 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
210 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
211 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
212
213 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
214 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
215 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
216 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
217 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
218 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
219 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
220 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
221 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
222 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
223
224 ring = &adev->vcn.inst[j].ring_dec;
225 ring->use_doorbell = true;
226
227 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
228 (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
229
230 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
231 ring->vm_hub = AMDGPU_MMHUB1(0);
232 else
233 ring->vm_hub = AMDGPU_MMHUB0(0);
234
235 sprintf(ring->name, "vcn_dec_%d", j);
236 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
237 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
238 if (r)
239 return r;
240
241 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
242 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
243
244 ring = &adev->vcn.inst[j].ring_enc[i];
245 ring->use_doorbell = true;
246
247 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
248 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
249
250 if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
251 IP_VERSION(2, 5, 0))
252 ring->vm_hub = AMDGPU_MMHUB1(0);
253 else
254 ring->vm_hub = AMDGPU_MMHUB0(0);
255
256 sprintf(ring->name, "vcn_enc_%d.%d", j, i);
257 r = amdgpu_ring_init(adev, ring, 512,
258 &adev->vcn.inst[j].irq, 0,
259 hw_prio, NULL);
260 if (r)
261 return r;
262 }
263
264 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
265 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
266
267 if (amdgpu_vcnfw_log)
268 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
269 }
270
271 if (amdgpu_sriov_vf(adev)) {
272 r = amdgpu_virt_alloc_mm_table(adev);
273 if (r)
274 return r;
275 }
276
277 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
278 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
279
280 r = amdgpu_vcn_ras_sw_init(adev);
281 if (r)
282 return r;
283
284 /* Allocate memory for VCN IP Dump buffer */
285 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
286 if (!ptr) {
287 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
288 adev->vcn.ip_dump = NULL;
289 } else {
290 adev->vcn.ip_dump = ptr;
291 }
292
293 return 0;
294 }
295
296 /**
297 * vcn_v2_5_sw_fini - sw fini for VCN block
298 *
299 * @handle: amdgpu_device pointer
300 *
301 * VCN suspend and free up sw allocation
302 */
vcn_v2_5_sw_fini(void * handle)303 static int vcn_v2_5_sw_fini(void *handle)
304 {
305 int i, r, idx;
306 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
307 volatile struct amdgpu_fw_shared *fw_shared;
308
309 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
310 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
311 if (adev->vcn.harvest_config & (1 << i))
312 continue;
313 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
314 fw_shared->present_flag_0 = 0;
315 }
316 drm_dev_exit(idx);
317 }
318
319
320 if (amdgpu_sriov_vf(adev))
321 amdgpu_virt_free_mm_table(adev);
322
323 r = amdgpu_vcn_suspend(adev);
324 if (r)
325 return r;
326
327 r = amdgpu_vcn_sw_fini(adev);
328
329 kfree(adev->vcn.ip_dump);
330
331 return r;
332 }
333
334 /**
335 * vcn_v2_5_hw_init - start and test VCN block
336 *
337 * @handle: amdgpu_device pointer
338 *
339 * Initialize the hardware, boot up the VCPU and do some testing
340 */
vcn_v2_5_hw_init(void * handle)341 static int vcn_v2_5_hw_init(void *handle)
342 {
343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
344 struct amdgpu_ring *ring;
345 int i, j, r = 0;
346
347 if (amdgpu_sriov_vf(adev))
348 r = vcn_v2_5_sriov_start(adev);
349
350 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
351 if (adev->vcn.harvest_config & (1 << j))
352 continue;
353
354 if (amdgpu_sriov_vf(adev)) {
355 adev->vcn.inst[j].ring_enc[0].sched.ready = true;
356 adev->vcn.inst[j].ring_enc[1].sched.ready = false;
357 adev->vcn.inst[j].ring_enc[2].sched.ready = false;
358 adev->vcn.inst[j].ring_dec.sched.ready = true;
359 } else {
360
361 ring = &adev->vcn.inst[j].ring_dec;
362
363 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
364 ring->doorbell_index, j);
365
366 r = amdgpu_ring_test_helper(ring);
367 if (r)
368 return r;
369
370 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
371 ring = &adev->vcn.inst[j].ring_enc[i];
372 r = amdgpu_ring_test_helper(ring);
373 if (r)
374 return r;
375 }
376 }
377 }
378
379 return r;
380 }
381
382 /**
383 * vcn_v2_5_hw_fini - stop the hardware block
384 *
385 * @handle: amdgpu_device pointer
386 *
387 * Stop the VCN block, mark ring as not ready any more
388 */
vcn_v2_5_hw_fini(void * handle)389 static int vcn_v2_5_hw_fini(void *handle)
390 {
391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
392 int i;
393
394 cancel_delayed_work_sync(&adev->vcn.idle_work);
395
396 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
397 if (adev->vcn.harvest_config & (1 << i))
398 continue;
399
400 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
401 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
402 RREG32_SOC15(VCN, i, mmUVD_STATUS)))
403 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
404
405 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
406 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
407 }
408
409 return 0;
410 }
411
412 /**
413 * vcn_v2_5_suspend - suspend VCN block
414 *
415 * @handle: amdgpu_device pointer
416 *
417 * HW fini and suspend VCN block
418 */
vcn_v2_5_suspend(void * handle)419 static int vcn_v2_5_suspend(void *handle)
420 {
421 int r;
422 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
423
424 r = vcn_v2_5_hw_fini(adev);
425 if (r)
426 return r;
427
428 r = amdgpu_vcn_suspend(adev);
429
430 return r;
431 }
432
433 /**
434 * vcn_v2_5_resume - resume VCN block
435 *
436 * @handle: amdgpu_device pointer
437 *
438 * Resume firmware and hw init VCN block
439 */
vcn_v2_5_resume(void * handle)440 static int vcn_v2_5_resume(void *handle)
441 {
442 int r;
443 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
444
445 r = amdgpu_vcn_resume(adev);
446 if (r)
447 return r;
448
449 r = vcn_v2_5_hw_init(adev);
450
451 return r;
452 }
453
454 /**
455 * vcn_v2_5_mc_resume - memory controller programming
456 *
457 * @adev: amdgpu_device pointer
458 *
459 * Let the VCN memory controller know it's offsets
460 */
vcn_v2_5_mc_resume(struct amdgpu_device * adev)461 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
462 {
463 uint32_t size;
464 uint32_t offset;
465 int i;
466
467 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
468 if (adev->vcn.harvest_config & (1 << i))
469 continue;
470
471 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
472 /* cache window 0: fw */
473 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
474 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
475 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
476 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
477 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
478 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
479 offset = 0;
480 } else {
481 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
482 lower_32_bits(adev->vcn.inst[i].gpu_addr));
483 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
484 upper_32_bits(adev->vcn.inst[i].gpu_addr));
485 offset = size;
486 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,
487 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
488 }
489 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);
490
491 /* cache window 1: stack */
492 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
493 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
494 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
495 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
496 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
497 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
498
499 /* cache window 2: context */
500 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
501 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
502 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
503 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
504 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
505 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
506
507 /* non-cache window */
508 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
509 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
510 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
511 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
512 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
513 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,
514 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
515 }
516 }
517
vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)518 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
519 {
520 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
521 uint32_t offset;
522
523 /* cache window 0: fw */
524 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
525 if (!indirect) {
526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
527 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
528 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
530 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
531 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
533 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
534 } else {
535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
536 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
538 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
540 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
541 }
542 offset = 0;
543 } else {
544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
545 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
546 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
548 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
549 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
550 offset = size;
551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
552 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),
553 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
554 }
555
556 if (!indirect)
557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
558 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
559 else
560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
561 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
562
563 /* cache window 1: stack */
564 if (!indirect) {
565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
566 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
569 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
572 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
573 } else {
574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
575 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
577 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
579 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
580 }
581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
582 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
583
584 /* cache window 2: context */
585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
586 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
587 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
589 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
590 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
592 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
593 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
594 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
595
596 /* non-cache window */
597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
598 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
599 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
601 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
602 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
604 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
605 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
606 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),
607 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
608
609 /* VCN global tiling registers */
610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
611 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
612 }
613
614 /**
615 * vcn_v2_5_disable_clock_gating - disable VCN clock gating
616 *
617 * @adev: amdgpu_device pointer
618 *
619 * Disable clock gating for VCN block
620 */
vcn_v2_5_disable_clock_gating(struct amdgpu_device * adev)621 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
622 {
623 uint32_t data;
624 int i;
625
626 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
627 if (adev->vcn.harvest_config & (1 << i))
628 continue;
629 /* UVD disable CGC */
630 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
631 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
632 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
633 else
634 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
635 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
636 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
637 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
638
639 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
640 data &= ~(UVD_CGC_GATE__SYS_MASK
641 | UVD_CGC_GATE__UDEC_MASK
642 | UVD_CGC_GATE__MPEG2_MASK
643 | UVD_CGC_GATE__REGS_MASK
644 | UVD_CGC_GATE__RBC_MASK
645 | UVD_CGC_GATE__LMI_MC_MASK
646 | UVD_CGC_GATE__LMI_UMC_MASK
647 | UVD_CGC_GATE__IDCT_MASK
648 | UVD_CGC_GATE__MPRD_MASK
649 | UVD_CGC_GATE__MPC_MASK
650 | UVD_CGC_GATE__LBSI_MASK
651 | UVD_CGC_GATE__LRBBM_MASK
652 | UVD_CGC_GATE__UDEC_RE_MASK
653 | UVD_CGC_GATE__UDEC_CM_MASK
654 | UVD_CGC_GATE__UDEC_IT_MASK
655 | UVD_CGC_GATE__UDEC_DB_MASK
656 | UVD_CGC_GATE__UDEC_MP_MASK
657 | UVD_CGC_GATE__WCB_MASK
658 | UVD_CGC_GATE__VCPU_MASK
659 | UVD_CGC_GATE__MMSCH_MASK);
660
661 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
662
663 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
664
665 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
666 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
667 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
668 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
669 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
670 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
671 | UVD_CGC_CTRL__SYS_MODE_MASK
672 | UVD_CGC_CTRL__UDEC_MODE_MASK
673 | UVD_CGC_CTRL__MPEG2_MODE_MASK
674 | UVD_CGC_CTRL__REGS_MODE_MASK
675 | UVD_CGC_CTRL__RBC_MODE_MASK
676 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
677 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
678 | UVD_CGC_CTRL__IDCT_MODE_MASK
679 | UVD_CGC_CTRL__MPRD_MODE_MASK
680 | UVD_CGC_CTRL__MPC_MODE_MASK
681 | UVD_CGC_CTRL__LBSI_MODE_MASK
682 | UVD_CGC_CTRL__LRBBM_MODE_MASK
683 | UVD_CGC_CTRL__WCB_MODE_MASK
684 | UVD_CGC_CTRL__VCPU_MODE_MASK
685 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
686 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
687
688 /* turn on */
689 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
690 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
691 | UVD_SUVD_CGC_GATE__SIT_MASK
692 | UVD_SUVD_CGC_GATE__SMP_MASK
693 | UVD_SUVD_CGC_GATE__SCM_MASK
694 | UVD_SUVD_CGC_GATE__SDB_MASK
695 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
696 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
697 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
698 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
699 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
700 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
701 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
702 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
703 | UVD_SUVD_CGC_GATE__SCLR_MASK
704 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
705 | UVD_SUVD_CGC_GATE__ENT_MASK
706 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
707 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
708 | UVD_SUVD_CGC_GATE__SITE_MASK
709 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
710 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
711 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
712 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
713 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
714 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
715
716 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
717 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
718 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
719 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
720 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
721 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
722 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
723 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
724 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
725 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
726 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
727 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
728 }
729 }
730
vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,int inst_idx,uint8_t indirect)731 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
732 uint8_t sram_sel, int inst_idx, uint8_t indirect)
733 {
734 uint32_t reg_data = 0;
735
736 /* enable sw clock gating control */
737 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
738 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
739 else
740 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
741 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
742 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
743 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
744 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
745 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
746 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
747 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
748 UVD_CGC_CTRL__SYS_MODE_MASK |
749 UVD_CGC_CTRL__UDEC_MODE_MASK |
750 UVD_CGC_CTRL__MPEG2_MODE_MASK |
751 UVD_CGC_CTRL__REGS_MODE_MASK |
752 UVD_CGC_CTRL__RBC_MODE_MASK |
753 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
754 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
755 UVD_CGC_CTRL__IDCT_MODE_MASK |
756 UVD_CGC_CTRL__MPRD_MODE_MASK |
757 UVD_CGC_CTRL__MPC_MODE_MASK |
758 UVD_CGC_CTRL__LBSI_MODE_MASK |
759 UVD_CGC_CTRL__LRBBM_MODE_MASK |
760 UVD_CGC_CTRL__WCB_MODE_MASK |
761 UVD_CGC_CTRL__VCPU_MODE_MASK |
762 UVD_CGC_CTRL__MMSCH_MODE_MASK);
763 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
764 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
765
766 /* turn off clock gating */
767 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
768 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
769
770 /* turn on SUVD clock gating */
771 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
772 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
773
774 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
775 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
776 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
777 }
778
779 /**
780 * vcn_v2_5_enable_clock_gating - enable VCN clock gating
781 *
782 * @adev: amdgpu_device pointer
783 *
784 * Enable clock gating for VCN block
785 */
vcn_v2_5_enable_clock_gating(struct amdgpu_device * adev)786 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
787 {
788 uint32_t data = 0;
789 int i;
790
791 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
792 if (adev->vcn.harvest_config & (1 << i))
793 continue;
794 /* enable UVD CGC */
795 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
796 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
797 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
798 else
799 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
800 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
801 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
802 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
803
804 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
805 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
806 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
807 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
808 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
809 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
810 | UVD_CGC_CTRL__SYS_MODE_MASK
811 | UVD_CGC_CTRL__UDEC_MODE_MASK
812 | UVD_CGC_CTRL__MPEG2_MODE_MASK
813 | UVD_CGC_CTRL__REGS_MODE_MASK
814 | UVD_CGC_CTRL__RBC_MODE_MASK
815 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
816 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
817 | UVD_CGC_CTRL__IDCT_MODE_MASK
818 | UVD_CGC_CTRL__MPRD_MODE_MASK
819 | UVD_CGC_CTRL__MPC_MODE_MASK
820 | UVD_CGC_CTRL__LBSI_MODE_MASK
821 | UVD_CGC_CTRL__LRBBM_MODE_MASK
822 | UVD_CGC_CTRL__WCB_MODE_MASK
823 | UVD_CGC_CTRL__VCPU_MODE_MASK);
824 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
825
826 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
827 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
828 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
829 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
830 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
831 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
832 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
833 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
834 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
835 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
836 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
837 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
838 }
839 }
840
vcn_v2_6_enable_ras(struct amdgpu_device * adev,int inst_idx,bool indirect)841 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
842 bool indirect)
843 {
844 uint32_t tmp;
845
846 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0))
847 return;
848
849 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
850 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
851 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
852 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
853 WREG32_SOC15_DPG_MODE(inst_idx,
854 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL),
855 tmp, 0, indirect);
856
857 tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
858 WREG32_SOC15_DPG_MODE(inst_idx,
859 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN),
860 tmp, 0, indirect);
861
862 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
863 WREG32_SOC15_DPG_MODE(inst_idx,
864 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN),
865 tmp, 0, indirect);
866 }
867
vcn_v2_5_start_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)868 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
869 {
870 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
871 struct amdgpu_ring *ring;
872 uint32_t rb_bufsz, tmp;
873
874 /* disable register anti-hang mechanism */
875 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
876 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
877 /* enable dynamic power gating mode */
878 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
879 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
880 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
881 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
882
883 if (indirect)
884 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
885
886 /* enable clock gating */
887 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
888
889 /* enable VCPU clock */
890 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
891 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
892 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
893 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
894 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
895
896 /* disable master interupt */
897 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
898 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
899
900 /* setup mmUVD_LMI_CTRL */
901 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
902 UVD_LMI_CTRL__REQ_MODE_MASK |
903 UVD_LMI_CTRL__CRC_RESET_MASK |
904 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
905 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
906 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
907 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
908 0x00100000L);
909 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
910 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
911
912 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
913 VCN, 0, mmUVD_MPC_CNTL),
914 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
915
916 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
917 VCN, 0, mmUVD_MPC_SET_MUXA0),
918 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
919 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
920 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
921 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
922
923 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
924 VCN, 0, mmUVD_MPC_SET_MUXB0),
925 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
926 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
927 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
928 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
929
930 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
931 VCN, 0, mmUVD_MPC_SET_MUX),
932 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
933 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
934 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
935
936 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
937
938 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
939 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
940 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
941 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
942
943 /* enable LMI MC and UMC channels */
944 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
945 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
946
947 vcn_v2_6_enable_ras(adev, inst_idx, indirect);
948
949 /* unblock VCPU register access */
950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
951 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
952
953 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
954 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
955 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
956 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
957
958 /* enable master interrupt */
959 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
960 VCN, 0, mmUVD_MASTINT_EN),
961 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
962
963 if (indirect)
964 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
965
966 ring = &adev->vcn.inst[inst_idx].ring_dec;
967 /* force RBC into idle state */
968 rb_bufsz = order_base_2(ring->ring_size);
969 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
970 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
971 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
972 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
973 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
974 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
975
976 /* Stall DPG before WPTR/RPTR reset */
977 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
978 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
979 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
980 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
981
982 /* set the write pointer delay */
983 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
984
985 /* set the wb address */
986 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
987 (upper_32_bits(ring->gpu_addr) >> 2));
988
989 /* program the RB_BASE for ring buffer */
990 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
991 lower_32_bits(ring->gpu_addr));
992 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
993 upper_32_bits(ring->gpu_addr));
994
995 /* Initialize the ring buffer's read and write pointers */
996 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
997
998 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
999
1000 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1001 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1002 lower_32_bits(ring->wptr));
1003
1004 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1005 /* Unstall DPG */
1006 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1007 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1008
1009 return 0;
1010 }
1011
vcn_v2_5_start(struct amdgpu_device * adev)1012 static int vcn_v2_5_start(struct amdgpu_device *adev)
1013 {
1014 struct amdgpu_ring *ring;
1015 uint32_t rb_bufsz, tmp;
1016 int i, j, k, r;
1017
1018 if (adev->pm.dpm_enabled)
1019 amdgpu_dpm_enable_uvd(adev, true);
1020
1021 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1022 if (adev->vcn.harvest_config & (1 << i))
1023 continue;
1024 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1025 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1026 continue;
1027 }
1028
1029 /* disable register anti-hang mechanism */
1030 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
1031 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1032
1033 /* set uvd status busy */
1034 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1035 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1036 }
1037
1038 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1039 return 0;
1040
1041 /*SW clock gating */
1042 vcn_v2_5_disable_clock_gating(adev);
1043
1044 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1045 if (adev->vcn.harvest_config & (1 << i))
1046 continue;
1047 /* enable VCPU clock */
1048 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1049 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1050
1051 /* disable master interrupt */
1052 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1053 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1054
1055 /* setup mmUVD_LMI_CTRL */
1056 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1057 tmp &= ~0xff;
1058 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
1059 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1060 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1061 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1062 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1063
1064 /* setup mmUVD_MPC_CNTL */
1065 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1066 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1067 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1068 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1069
1070 /* setup UVD_MPC_SET_MUXA0 */
1071 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1072 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1073 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1074 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1075 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1076
1077 /* setup UVD_MPC_SET_MUXB0 */
1078 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1079 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1080 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1081 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1082 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1083
1084 /* setup mmUVD_MPC_SET_MUX */
1085 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1086 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1087 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1088 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1089 }
1090
1091 vcn_v2_5_mc_resume(adev);
1092
1093 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1094 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1095 if (adev->vcn.harvest_config & (1 << i))
1096 continue;
1097 /* VCN global tiling registers */
1098 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1099 adev->gfx.config.gb_addr_config);
1100 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1101 adev->gfx.config.gb_addr_config);
1102
1103 /* enable LMI MC and UMC channels */
1104 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1105 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1106
1107 /* unblock VCPU register access */
1108 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1109 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1110
1111 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1112 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1113
1114 for (k = 0; k < 10; ++k) {
1115 uint32_t status;
1116
1117 for (j = 0; j < 100; ++j) {
1118 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1119 if (status & 2)
1120 break;
1121 if (amdgpu_emu_mode == 1)
1122 msleep(500);
1123 else
1124 mdelay(10);
1125 }
1126 r = 0;
1127 if (status & 2)
1128 break;
1129
1130 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1132 UVD_VCPU_CNTL__BLK_RST_MASK,
1133 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1134 mdelay(10);
1135 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1136 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1137
1138 mdelay(10);
1139 r = -1;
1140 }
1141
1142 if (r) {
1143 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1144 return r;
1145 }
1146
1147 /* enable master interrupt */
1148 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1149 UVD_MASTINT_EN__VCPU_EN_MASK,
1150 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1151
1152 /* clear the busy bit of VCN_STATUS */
1153 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1154 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1155
1156 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1157
1158 ring = &adev->vcn.inst[i].ring_dec;
1159 /* force RBC into idle state */
1160 rb_bufsz = order_base_2(ring->ring_size);
1161 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1162 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1163 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1164 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1165 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1166 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1167
1168 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1169 /* program the RB_BASE for ring buffer */
1170 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1171 lower_32_bits(ring->gpu_addr));
1172 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1173 upper_32_bits(ring->gpu_addr));
1174
1175 /* Initialize the ring buffer's read and write pointers */
1176 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1177
1178 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1179 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1180 lower_32_bits(ring->wptr));
1181 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1182
1183 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1184 ring = &adev->vcn.inst[i].ring_enc[0];
1185 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1186 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1187 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1188 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1189 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1190 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1191
1192 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1193 ring = &adev->vcn.inst[i].ring_enc[1];
1194 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1195 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1196 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1197 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1198 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1199 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1200 }
1201
1202 return 0;
1203 }
1204
vcn_v2_5_mmsch_start(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1205 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1206 struct amdgpu_mm_table *table)
1207 {
1208 uint32_t data = 0, loop = 0, size = 0;
1209 uint64_t addr = table->gpu_addr;
1210 struct mmsch_v1_1_init_header *header = NULL;
1211
1212 header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1213 size = header->total_size;
1214
1215 /*
1216 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1217 * memory descriptor location
1218 */
1219 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1220 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1221
1222 /* 2, update vmid of descriptor */
1223 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1224 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1225 /* use domain0 for MM scheduler */
1226 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1227 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data);
1228
1229 /* 3, notify mmsch about the size of this descriptor */
1230 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1231
1232 /* 4, set resp to zero */
1233 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1234
1235 /*
1236 * 5, kick off the initialization and wait until
1237 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1238 */
1239 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1240
1241 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1242 loop = 10;
1243 while ((data & 0x10000002) != 0x10000002) {
1244 udelay(100);
1245 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1246 loop--;
1247 if (!loop)
1248 break;
1249 }
1250
1251 if (!loop) {
1252 dev_err(adev->dev,
1253 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",
1254 data);
1255 return -EBUSY;
1256 }
1257
1258 return 0;
1259 }
1260
vcn_v2_5_sriov_start(struct amdgpu_device * adev)1261 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1262 {
1263 struct amdgpu_ring *ring;
1264 uint32_t offset, size, tmp, i, rb_bufsz;
1265 uint32_t table_size = 0;
1266 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1267 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1268 struct mmsch_v1_0_cmd_end end = { { 0 } };
1269 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1270 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1271
1272 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1273 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1274 end.cmd_header.command_type = MMSCH_COMMAND__END;
1275
1276 header->version = MMSCH_VERSION;
1277 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1278 init_table += header->total_size;
1279
1280 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1281 header->eng[i].table_offset = header->total_size;
1282 header->eng[i].init_status = 0;
1283 header->eng[i].table_size = 0;
1284
1285 table_size = 0;
1286
1287 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(
1288 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
1289 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1290
1291 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
1292 /* mc resume*/
1293 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1294 MMSCH_V1_0_INSERT_DIRECT_WT(
1295 SOC15_REG_OFFSET(VCN, i,
1296 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1297 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1298 MMSCH_V1_0_INSERT_DIRECT_WT(
1299 SOC15_REG_OFFSET(VCN, i,
1300 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1301 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1302 offset = 0;
1303 MMSCH_V1_0_INSERT_DIRECT_WT(
1304 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
1305 } else {
1306 MMSCH_V1_0_INSERT_DIRECT_WT(
1307 SOC15_REG_OFFSET(VCN, i,
1308 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1309 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1310 MMSCH_V1_0_INSERT_DIRECT_WT(
1311 SOC15_REG_OFFSET(VCN, i,
1312 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1313 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1314 offset = size;
1315 MMSCH_V1_0_INSERT_DIRECT_WT(
1316 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
1317 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1318 }
1319
1320 MMSCH_V1_0_INSERT_DIRECT_WT(
1321 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),
1322 size);
1323 MMSCH_V1_0_INSERT_DIRECT_WT(
1324 SOC15_REG_OFFSET(VCN, i,
1325 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1326 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1327 MMSCH_V1_0_INSERT_DIRECT_WT(
1328 SOC15_REG_OFFSET(VCN, i,
1329 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1330 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1331 MMSCH_V1_0_INSERT_DIRECT_WT(
1332 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
1333 0);
1334 MMSCH_V1_0_INSERT_DIRECT_WT(
1335 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),
1336 AMDGPU_VCN_STACK_SIZE);
1337 MMSCH_V1_0_INSERT_DIRECT_WT(
1338 SOC15_REG_OFFSET(VCN, i,
1339 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1340 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1341 AMDGPU_VCN_STACK_SIZE));
1342 MMSCH_V1_0_INSERT_DIRECT_WT(
1343 SOC15_REG_OFFSET(VCN, i,
1344 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1345 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1346 AMDGPU_VCN_STACK_SIZE));
1347 MMSCH_V1_0_INSERT_DIRECT_WT(
1348 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),
1349 0);
1350 MMSCH_V1_0_INSERT_DIRECT_WT(
1351 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
1352 AMDGPU_VCN_CONTEXT_SIZE);
1353
1354 ring = &adev->vcn.inst[i].ring_enc[0];
1355 ring->wptr = 0;
1356
1357 MMSCH_V1_0_INSERT_DIRECT_WT(
1358 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),
1359 lower_32_bits(ring->gpu_addr));
1360 MMSCH_V1_0_INSERT_DIRECT_WT(
1361 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),
1362 upper_32_bits(ring->gpu_addr));
1363 MMSCH_V1_0_INSERT_DIRECT_WT(
1364 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),
1365 ring->ring_size / 4);
1366
1367 ring = &adev->vcn.inst[i].ring_dec;
1368 ring->wptr = 0;
1369 MMSCH_V1_0_INSERT_DIRECT_WT(
1370 SOC15_REG_OFFSET(VCN, i,
1371 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1372 lower_32_bits(ring->gpu_addr));
1373 MMSCH_V1_0_INSERT_DIRECT_WT(
1374 SOC15_REG_OFFSET(VCN, i,
1375 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1376 upper_32_bits(ring->gpu_addr));
1377
1378 /* force RBC into idle state */
1379 rb_bufsz = order_base_2(ring->ring_size);
1380 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1381 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1382 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1383 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1384 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1385 MMSCH_V1_0_INSERT_DIRECT_WT(
1386 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
1387
1388 /* add end packet */
1389 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
1390 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1391 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1392
1393 /* refine header */
1394 header->eng[i].table_size = table_size;
1395 header->total_size += table_size;
1396 }
1397
1398 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1399 }
1400
vcn_v2_5_stop_dpg_mode(struct amdgpu_device * adev,int inst_idx)1401 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1402 {
1403 uint32_t tmp;
1404
1405 /* Wait for power status to be 1 */
1406 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1407 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1408
1409 /* wait for read ptr to be equal to write ptr */
1410 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1411 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1412
1413 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1414 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1415
1416 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1417 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1418
1419 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1420 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1421
1422 /* disable dynamic power gating mode */
1423 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1424 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1425
1426 return 0;
1427 }
1428
vcn_v2_5_stop(struct amdgpu_device * adev)1429 static int vcn_v2_5_stop(struct amdgpu_device *adev)
1430 {
1431 uint32_t tmp;
1432 int i, r = 0;
1433
1434 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1435 if (adev->vcn.harvest_config & (1 << i))
1436 continue;
1437 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1438 r = vcn_v2_5_stop_dpg_mode(adev, i);
1439 continue;
1440 }
1441
1442 /* wait for vcn idle */
1443 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1444 if (r)
1445 return r;
1446
1447 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1448 UVD_LMI_STATUS__READ_CLEAN_MASK |
1449 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1450 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1451 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1452 if (r)
1453 return r;
1454
1455 /* block LMI UMC channel */
1456 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1457 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1458 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1459
1460 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1461 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1462 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1463 if (r)
1464 return r;
1465
1466 /* block VCPU register access */
1467 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1468 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1469 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1470
1471 /* reset VCPU */
1472 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1473 UVD_VCPU_CNTL__BLK_RST_MASK,
1474 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1475
1476 /* disable VCPU clock */
1477 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1478 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1479
1480 /* clear status */
1481 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1482
1483 vcn_v2_5_enable_clock_gating(adev);
1484
1485 /* enable register anti-hang mechanism */
1486 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
1487 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
1488 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1489 }
1490
1491 if (adev->pm.dpm_enabled)
1492 amdgpu_dpm_enable_uvd(adev, false);
1493
1494 return 0;
1495 }
1496
vcn_v2_5_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1497 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1498 int inst_idx, struct dpg_pause_state *new_state)
1499 {
1500 struct amdgpu_ring *ring;
1501 uint32_t reg_data = 0;
1502 int ret_code = 0;
1503
1504 /* pause/unpause if state is changed */
1505 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1506 DRM_DEBUG("dpg pause state changed %d -> %d",
1507 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1508 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1509 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1510
1511 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1512 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1513 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1514
1515 if (!ret_code) {
1516 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1517
1518 /* pause DPG */
1519 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1520 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1521
1522 /* wait for ACK */
1523 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1524 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1525 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1526
1527 /* Stall DPG before WPTR/RPTR reset */
1528 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1529 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1530 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1531
1532 /* Restore */
1533 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1534 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1535 ring->wptr = 0;
1536 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1537 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1538 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1539 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1540 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1541 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1542
1543 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1544 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1545 ring->wptr = 0;
1546 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1547 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1548 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1549 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1550 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1551 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1552
1553 /* Unstall DPG */
1554 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1555 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1556
1557 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1558 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1559 }
1560 } else {
1561 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1562 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1563 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1564 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1565 }
1566 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1567 }
1568
1569 return 0;
1570 }
1571
1572 /**
1573 * vcn_v2_5_dec_ring_get_rptr - get read pointer
1574 *
1575 * @ring: amdgpu_ring pointer
1576 *
1577 * Returns the current hardware read pointer
1578 */
vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring * ring)1579 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1580 {
1581 struct amdgpu_device *adev = ring->adev;
1582
1583 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1584 }
1585
1586 /**
1587 * vcn_v2_5_dec_ring_get_wptr - get write pointer
1588 *
1589 * @ring: amdgpu_ring pointer
1590 *
1591 * Returns the current hardware write pointer
1592 */
vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring * ring)1593 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1594 {
1595 struct amdgpu_device *adev = ring->adev;
1596
1597 if (ring->use_doorbell)
1598 return *ring->wptr_cpu_addr;
1599 else
1600 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1601 }
1602
1603 /**
1604 * vcn_v2_5_dec_ring_set_wptr - set write pointer
1605 *
1606 * @ring: amdgpu_ring pointer
1607 *
1608 * Commits the write pointer to the hardware
1609 */
vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring * ring)1610 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1611 {
1612 struct amdgpu_device *adev = ring->adev;
1613
1614 if (ring->use_doorbell) {
1615 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1616 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1617 } else {
1618 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1619 }
1620 }
1621
1622 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1623 .type = AMDGPU_RING_TYPE_VCN_DEC,
1624 .align_mask = 0xf,
1625 .secure_submission_supported = true,
1626 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1627 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1628 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1629 .emit_frame_size =
1630 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1631 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1632 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1633 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1634 6,
1635 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1636 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1637 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1638 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1639 .test_ring = vcn_v2_0_dec_ring_test_ring,
1640 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1641 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1642 .insert_start = vcn_v2_0_dec_ring_insert_start,
1643 .insert_end = vcn_v2_0_dec_ring_insert_end,
1644 .pad_ib = amdgpu_ring_generic_pad_ib,
1645 .begin_use = amdgpu_vcn_ring_begin_use,
1646 .end_use = amdgpu_vcn_ring_end_use,
1647 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1648 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1649 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1650 };
1651
1652 /**
1653 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1654 *
1655 * @ring: amdgpu_ring pointer
1656 *
1657 * Returns the current hardware enc read pointer
1658 */
vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring * ring)1659 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1660 {
1661 struct amdgpu_device *adev = ring->adev;
1662
1663 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1664 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1665 else
1666 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1667 }
1668
1669 /**
1670 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1671 *
1672 * @ring: amdgpu_ring pointer
1673 *
1674 * Returns the current hardware enc write pointer
1675 */
vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring * ring)1676 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1677 {
1678 struct amdgpu_device *adev = ring->adev;
1679
1680 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1681 if (ring->use_doorbell)
1682 return *ring->wptr_cpu_addr;
1683 else
1684 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1685 } else {
1686 if (ring->use_doorbell)
1687 return *ring->wptr_cpu_addr;
1688 else
1689 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1690 }
1691 }
1692
1693 /**
1694 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1695 *
1696 * @ring: amdgpu_ring pointer
1697 *
1698 * Commits the enc write pointer to the hardware
1699 */
vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring * ring)1700 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1701 {
1702 struct amdgpu_device *adev = ring->adev;
1703
1704 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1705 if (ring->use_doorbell) {
1706 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1707 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1708 } else {
1709 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1710 }
1711 } else {
1712 if (ring->use_doorbell) {
1713 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1714 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1715 } else {
1716 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1717 }
1718 }
1719 }
1720
1721 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1722 .type = AMDGPU_RING_TYPE_VCN_ENC,
1723 .align_mask = 0x3f,
1724 .nop = VCN_ENC_CMD_NO_OP,
1725 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1726 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1727 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1728 .emit_frame_size =
1729 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1730 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1731 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1732 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1733 1, /* vcn_v2_0_enc_ring_insert_end */
1734 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1735 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1736 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1737 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1738 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1739 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1740 .insert_nop = amdgpu_ring_insert_nop,
1741 .insert_end = vcn_v2_0_enc_ring_insert_end,
1742 .pad_ib = amdgpu_ring_generic_pad_ib,
1743 .begin_use = amdgpu_vcn_ring_begin_use,
1744 .end_use = amdgpu_vcn_ring_end_use,
1745 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1746 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1747 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1748 };
1749
vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device * adev)1750 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1751 {
1752 int i;
1753
1754 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1755 if (adev->vcn.harvest_config & (1 << i))
1756 continue;
1757 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1758 adev->vcn.inst[i].ring_dec.me = i;
1759 }
1760 }
1761
vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device * adev)1762 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1763 {
1764 int i, j;
1765
1766 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1767 if (adev->vcn.harvest_config & (1 << j))
1768 continue;
1769 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1770 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1771 adev->vcn.inst[j].ring_enc[i].me = j;
1772 }
1773 }
1774 }
1775
vcn_v2_5_is_idle(void * handle)1776 static bool vcn_v2_5_is_idle(void *handle)
1777 {
1778 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1779 int i, ret = 1;
1780
1781 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1782 if (adev->vcn.harvest_config & (1 << i))
1783 continue;
1784 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1785 }
1786
1787 return ret;
1788 }
1789
vcn_v2_5_wait_for_idle(void * handle)1790 static int vcn_v2_5_wait_for_idle(void *handle)
1791 {
1792 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1793 int i, ret = 0;
1794
1795 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1796 if (adev->vcn.harvest_config & (1 << i))
1797 continue;
1798 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1799 UVD_STATUS__IDLE);
1800 if (ret)
1801 return ret;
1802 }
1803
1804 return ret;
1805 }
1806
vcn_v2_5_set_clockgating_state(void * handle,enum amd_clockgating_state state)1807 static int vcn_v2_5_set_clockgating_state(void *handle,
1808 enum amd_clockgating_state state)
1809 {
1810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1811 bool enable = (state == AMD_CG_STATE_GATE);
1812
1813 if (amdgpu_sriov_vf(adev))
1814 return 0;
1815
1816 if (enable) {
1817 if (!vcn_v2_5_is_idle(handle))
1818 return -EBUSY;
1819 vcn_v2_5_enable_clock_gating(adev);
1820 } else {
1821 vcn_v2_5_disable_clock_gating(adev);
1822 }
1823
1824 return 0;
1825 }
1826
vcn_v2_5_set_powergating_state(void * handle,enum amd_powergating_state state)1827 static int vcn_v2_5_set_powergating_state(void *handle,
1828 enum amd_powergating_state state)
1829 {
1830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1831 int ret;
1832
1833 if (amdgpu_sriov_vf(adev))
1834 return 0;
1835
1836 if(state == adev->vcn.cur_state)
1837 return 0;
1838
1839 if (state == AMD_PG_STATE_GATE)
1840 ret = vcn_v2_5_stop(adev);
1841 else
1842 ret = vcn_v2_5_start(adev);
1843
1844 if(!ret)
1845 adev->vcn.cur_state = state;
1846
1847 return ret;
1848 }
1849
vcn_v2_5_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1850 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1851 struct amdgpu_irq_src *source,
1852 unsigned type,
1853 enum amdgpu_interrupt_state state)
1854 {
1855 return 0;
1856 }
1857
vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)1858 static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
1859 struct amdgpu_irq_src *source,
1860 unsigned int type,
1861 enum amdgpu_interrupt_state state)
1862 {
1863 return 0;
1864 }
1865
vcn_v2_5_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1866 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1867 struct amdgpu_irq_src *source,
1868 struct amdgpu_iv_entry *entry)
1869 {
1870 uint32_t ip_instance;
1871
1872 switch (entry->client_id) {
1873 case SOC15_IH_CLIENTID_VCN:
1874 ip_instance = 0;
1875 break;
1876 case SOC15_IH_CLIENTID_VCN1:
1877 ip_instance = 1;
1878 break;
1879 default:
1880 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1881 return 0;
1882 }
1883
1884 DRM_DEBUG("IH: VCN TRAP\n");
1885
1886 switch (entry->src_id) {
1887 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1888 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1889 break;
1890 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1891 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1892 break;
1893 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1894 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1895 break;
1896 default:
1897 DRM_ERROR("Unhandled interrupt: %d %d\n",
1898 entry->src_id, entry->src_data[0]);
1899 break;
1900 }
1901
1902 return 0;
1903 }
1904
1905 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1906 .set = vcn_v2_5_set_interrupt_state,
1907 .process = vcn_v2_5_process_interrupt,
1908 };
1909
1910 static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = {
1911 .set = vcn_v2_6_set_ras_interrupt_state,
1912 .process = amdgpu_vcn_process_poison_irq,
1913 };
1914
vcn_v2_5_set_irq_funcs(struct amdgpu_device * adev)1915 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1916 {
1917 int i;
1918
1919 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1920 if (adev->vcn.harvest_config & (1 << i))
1921 continue;
1922 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1923 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1924
1925 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
1926 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
1927 }
1928 }
1929
vcn_v2_5_print_ip_state(void * handle,struct drm_printer * p)1930 static void vcn_v2_5_print_ip_state(void *handle, struct drm_printer *p)
1931 {
1932 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1933 int i, j;
1934 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
1935 uint32_t inst_off, is_powered;
1936
1937 if (!adev->vcn.ip_dump)
1938 return;
1939
1940 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1941 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1942 if (adev->vcn.harvest_config & (1 << i)) {
1943 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1944 continue;
1945 }
1946
1947 inst_off = i * reg_count;
1948 is_powered = (adev->vcn.ip_dump[inst_off] &
1949 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1950
1951 if (is_powered) {
1952 drm_printf(p, "\nActive Instance:VCN%d\n", i);
1953 for (j = 0; j < reg_count; j++)
1954 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
1955 adev->vcn.ip_dump[inst_off + j]);
1956 } else {
1957 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1958 }
1959 }
1960 }
1961
vcn_v2_5_dump_ip_state(void * handle)1962 static void vcn_v2_5_dump_ip_state(void *handle)
1963 {
1964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1965 int i, j;
1966 bool is_powered;
1967 uint32_t inst_off;
1968 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
1969
1970 if (!adev->vcn.ip_dump)
1971 return;
1972
1973 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1974 if (adev->vcn.harvest_config & (1 << i))
1975 continue;
1976
1977 inst_off = i * reg_count;
1978 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1979 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
1980 is_powered = (adev->vcn.ip_dump[inst_off] &
1981 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1982
1983 if (is_powered)
1984 for (j = 1; j < reg_count; j++)
1985 adev->vcn.ip_dump[inst_off + j] =
1986 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
1987 }
1988 }
1989
1990 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1991 .name = "vcn_v2_5",
1992 .early_init = vcn_v2_5_early_init,
1993 .late_init = NULL,
1994 .sw_init = vcn_v2_5_sw_init,
1995 .sw_fini = vcn_v2_5_sw_fini,
1996 .hw_init = vcn_v2_5_hw_init,
1997 .hw_fini = vcn_v2_5_hw_fini,
1998 .suspend = vcn_v2_5_suspend,
1999 .resume = vcn_v2_5_resume,
2000 .is_idle = vcn_v2_5_is_idle,
2001 .wait_for_idle = vcn_v2_5_wait_for_idle,
2002 .check_soft_reset = NULL,
2003 .pre_soft_reset = NULL,
2004 .soft_reset = NULL,
2005 .post_soft_reset = NULL,
2006 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
2007 .set_powergating_state = vcn_v2_5_set_powergating_state,
2008 .dump_ip_state = vcn_v2_5_dump_ip_state,
2009 .print_ip_state = vcn_v2_5_print_ip_state,
2010 };
2011
2012 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
2013 .name = "vcn_v2_6",
2014 .early_init = vcn_v2_5_early_init,
2015 .late_init = NULL,
2016 .sw_init = vcn_v2_5_sw_init,
2017 .sw_fini = vcn_v2_5_sw_fini,
2018 .hw_init = vcn_v2_5_hw_init,
2019 .hw_fini = vcn_v2_5_hw_fini,
2020 .suspend = vcn_v2_5_suspend,
2021 .resume = vcn_v2_5_resume,
2022 .is_idle = vcn_v2_5_is_idle,
2023 .wait_for_idle = vcn_v2_5_wait_for_idle,
2024 .check_soft_reset = NULL,
2025 .pre_soft_reset = NULL,
2026 .soft_reset = NULL,
2027 .post_soft_reset = NULL,
2028 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
2029 .set_powergating_state = vcn_v2_5_set_powergating_state,
2030 .dump_ip_state = vcn_v2_5_dump_ip_state,
2031 .print_ip_state = vcn_v2_5_print_ip_state,
2032 };
2033
2034 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
2035 {
2036 .type = AMD_IP_BLOCK_TYPE_VCN,
2037 .major = 2,
2038 .minor = 5,
2039 .rev = 0,
2040 .funcs = &vcn_v2_5_ip_funcs,
2041 };
2042
2043 const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
2044 {
2045 .type = AMD_IP_BLOCK_TYPE_VCN,
2046 .major = 2,
2047 .minor = 6,
2048 .rev = 0,
2049 .funcs = &vcn_v2_6_ip_funcs,
2050 };
2051
vcn_v2_6_query_poison_by_instance(struct amdgpu_device * adev,uint32_t instance,uint32_t sub_block)2052 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
2053 uint32_t instance, uint32_t sub_block)
2054 {
2055 uint32_t poison_stat = 0, reg_value = 0;
2056
2057 switch (sub_block) {
2058 case AMDGPU_VCN_V2_6_VCPU_VCODEC:
2059 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);
2060 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2061 break;
2062 default:
2063 break;
2064 }
2065
2066 if (poison_stat)
2067 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2068 instance, sub_block);
2069
2070 return poison_stat;
2071 }
2072
vcn_v2_6_query_poison_status(struct amdgpu_device * adev)2073 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
2074 {
2075 uint32_t inst, sub;
2076 uint32_t poison_stat = 0;
2077
2078 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2079 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++)
2080 poison_stat +=
2081 vcn_v2_6_query_poison_by_instance(adev, inst, sub);
2082
2083 return !!poison_stat;
2084 }
2085
2086 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
2087 .query_poison_status = vcn_v2_6_query_poison_status,
2088 };
2089
2090 static struct amdgpu_vcn_ras vcn_v2_6_ras = {
2091 .ras_block = {
2092 .hw_ops = &vcn_v2_6_ras_hw_ops,
2093 .ras_late_init = amdgpu_vcn_ras_late_init,
2094 },
2095 };
2096
vcn_v2_5_set_ras_funcs(struct amdgpu_device * adev)2097 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
2098 {
2099 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2100 case IP_VERSION(2, 6, 0):
2101 adev->vcn.ras = &vcn_v2_6_ras;
2102 break;
2103 default:
2104 break;
2105 }
2106 }
2107