1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include "amdgpu.h"
26 #include "amdgpu_vcn.h"
27 #include "amdgpu_pm.h"
28 #include "amdgpu_cs.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "soc15_hw_ip.h"
32 #include "vcn_v2_0.h"
33 #include "mmsch_v4_0.h"
34 #include "vcn_v4_0_5.h"
35
36 #include "vcn/vcn_4_0_5_offset.h"
37 #include "vcn/vcn_4_0_5_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
39
40 #include <drm/drm_drv.h>
41
42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
46
47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
48 #define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000)
49 #define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000)
50
51 #define VCN_HARVEST_MMSCH 0
52
53 #define RDECODE_MSG_CREATE 0x00000000
54 #define RDECODE_MESSAGE_CREATE 0x00000001
55
56 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = {
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
89 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
90 };
91
92 static int amdgpu_ih_clientid_vcns[] = {
93 SOC15_IH_CLIENTID_VCN,
94 SOC15_IH_CLIENTID_VCN1
95 };
96
97 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
98 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
99 static int vcn_v4_0_5_set_powergating_state(void *handle,
100 enum amd_powergating_state state);
101 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
102 int inst_idx, struct dpg_pause_state *new_state);
103 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);
104
105 /**
106 * vcn_v4_0_5_early_init - set function pointers and load microcode
107 *
108 * @handle: amdgpu_device pointer
109 *
110 * Set ring and irq function pointers
111 * Load microcode from filesystem
112 */
vcn_v4_0_5_early_init(void * handle)113 static int vcn_v4_0_5_early_init(void *handle)
114 {
115 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
116
117 /* re-use enc ring as unified ring */
118 adev->vcn.num_enc_rings = 1;
119 vcn_v4_0_5_set_unified_ring_funcs(adev);
120 vcn_v4_0_5_set_irq_funcs(adev);
121
122 return amdgpu_vcn_early_init(adev);
123 }
124
125 /**
126 * vcn_v4_0_5_sw_init - sw init for VCN block
127 *
128 * @handle: amdgpu_device pointer
129 *
130 * Load firmware and sw initialization
131 */
vcn_v4_0_5_sw_init(void * handle)132 static int vcn_v4_0_5_sw_init(void *handle)
133 {
134 struct amdgpu_ring *ring;
135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
136 int i, r;
137 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
138 uint32_t *ptr;
139
140 r = amdgpu_vcn_sw_init(adev);
141 if (r)
142 return r;
143
144 amdgpu_vcn_setup_ucode(adev);
145
146 r = amdgpu_vcn_resume(adev);
147 if (r)
148 return r;
149
150 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
151 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
152
153 if (adev->vcn.harvest_config & (1 << i))
154 continue;
155
156 atomic_set(&adev->vcn.inst[i].sched_score, 0);
157
158 /* VCN UNIFIED TRAP */
159 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
160 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
161 if (r)
162 return r;
163
164 /* VCN POISON TRAP */
165 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
166 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
167 if (r)
168 return r;
169
170 ring = &adev->vcn.inst[i].ring_enc[0];
171 ring->use_doorbell = true;
172 if (amdgpu_sriov_vf(adev))
173 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
174 i * (adev->vcn.num_enc_rings + 1) + 1;
175 else
176 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
177 2 + 8 * i;
178 ring->vm_hub = AMDGPU_MMHUB0(0);
179 sprintf(ring->name, "vcn_unified_%d", i);
180
181 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
182 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
183 if (r)
184 return r;
185
186 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
187 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
188 fw_shared->sq.is_enabled = 1;
189
190 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
191 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
192 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
193
194 if (amdgpu_sriov_vf(adev))
195 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
196
197 if (amdgpu_vcnfw_log)
198 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
199 }
200
201 if (amdgpu_sriov_vf(adev)) {
202 r = amdgpu_virt_alloc_mm_table(adev);
203 if (r)
204 return r;
205 }
206
207 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
208 adev->vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;
209
210 /* Allocate memory for VCN IP Dump buffer */
211 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
212 if (!ptr) {
213 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
214 adev->vcn.ip_dump = NULL;
215 } else {
216 adev->vcn.ip_dump = ptr;
217 }
218 return 0;
219 }
220
221 /**
222 * vcn_v4_0_5_sw_fini - sw fini for VCN block
223 *
224 * @handle: amdgpu_device pointer
225 *
226 * VCN suspend and free up sw allocation
227 */
vcn_v4_0_5_sw_fini(void * handle)228 static int vcn_v4_0_5_sw_fini(void *handle)
229 {
230 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
231 int i, r, idx;
232
233 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
234 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
235 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
236
237 if (adev->vcn.harvest_config & (1 << i))
238 continue;
239
240 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
241 fw_shared->present_flag_0 = 0;
242 fw_shared->sq.is_enabled = 0;
243 }
244
245 drm_dev_exit(idx);
246 }
247
248 if (amdgpu_sriov_vf(adev))
249 amdgpu_virt_free_mm_table(adev);
250
251 r = amdgpu_vcn_suspend(adev);
252 if (r)
253 return r;
254
255 r = amdgpu_vcn_sw_fini(adev);
256
257 kfree(adev->vcn.ip_dump);
258
259 return r;
260 }
261
262 /**
263 * vcn_v4_0_5_hw_init - start and test VCN block
264 *
265 * @handle: amdgpu_device pointer
266 *
267 * Initialize the hardware, boot up the VCPU and do some testing
268 */
vcn_v4_0_5_hw_init(void * handle)269 static int vcn_v4_0_5_hw_init(void *handle)
270 {
271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
272 struct amdgpu_ring *ring;
273 int i, r;
274
275 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
276 if (adev->vcn.harvest_config & (1 << i))
277 continue;
278
279 ring = &adev->vcn.inst[i].ring_enc[0];
280
281 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
282 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
283
284 r = amdgpu_ring_test_helper(ring);
285 if (r)
286 return r;
287 }
288
289 return 0;
290 }
291
292 /**
293 * vcn_v4_0_5_hw_fini - stop the hardware block
294 *
295 * @handle: amdgpu_device pointer
296 *
297 * Stop the VCN block, mark ring as not ready any more
298 */
vcn_v4_0_5_hw_fini(void * handle)299 static int vcn_v4_0_5_hw_fini(void *handle)
300 {
301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
302 int i;
303
304 cancel_delayed_work_sync(&adev->vcn.idle_work);
305
306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
307 if (adev->vcn.harvest_config & (1 << i))
308 continue;
309 if (!amdgpu_sriov_vf(adev)) {
310 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
311 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
312 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
313 vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
314 }
315 }
316 }
317
318 return 0;
319 }
320
321 /**
322 * vcn_v4_0_5_suspend - suspend VCN block
323 *
324 * @handle: amdgpu_device pointer
325 *
326 * HW fini and suspend VCN block
327 */
vcn_v4_0_5_suspend(void * handle)328 static int vcn_v4_0_5_suspend(void *handle)
329 {
330 int r;
331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
332
333 r = vcn_v4_0_5_hw_fini(adev);
334 if (r)
335 return r;
336
337 r = amdgpu_vcn_suspend(adev);
338
339 return r;
340 }
341
342 /**
343 * vcn_v4_0_5_resume - resume VCN block
344 *
345 * @handle: amdgpu_device pointer
346 *
347 * Resume firmware and hw init VCN block
348 */
vcn_v4_0_5_resume(void * handle)349 static int vcn_v4_0_5_resume(void *handle)
350 {
351 int r;
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353
354 r = amdgpu_vcn_resume(adev);
355 if (r)
356 return r;
357
358 r = vcn_v4_0_5_hw_init(adev);
359
360 return r;
361 }
362
363 /**
364 * vcn_v4_0_5_mc_resume - memory controller programming
365 *
366 * @adev: amdgpu_device pointer
367 * @inst: instance number
368 *
369 * Let the VCN memory controller know it's offsets
370 */
vcn_v4_0_5_mc_resume(struct amdgpu_device * adev,int inst)371 static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
372 {
373 uint32_t offset, size;
374 const struct common_firmware_header *hdr;
375
376 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
377 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
378
379 /* cache window 0: fw */
380 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
381 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
382 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
383 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
384 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
385 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
386 offset = 0;
387 } else {
388 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
389 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
391 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
392 offset = size;
393 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
394 }
395 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
396
397 /* cache window 1: stack */
398 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
399 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
400 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
401 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
402 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
403 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
404
405 /* cache window 2: context */
406 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
407 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
408 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
409 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
410 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
411 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
412
413 /* non-cache window */
414 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
415 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
416 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
417 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
418 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
419 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
420 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
421 }
422
423 /**
424 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
425 *
426 * @adev: amdgpu_device pointer
427 * @inst_idx: instance number index
428 * @indirect: indirectly write sram
429 *
430 * Let the VCN memory controller know it's offsets with dpg mode
431 */
vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)432 static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
433 {
434 uint32_t offset, size;
435 const struct common_firmware_header *hdr;
436
437 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
438 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
439
440 /* cache window 0: fw */
441 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
442 if (!indirect) {
443 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
444 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
445 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo),
446 0, indirect);
447 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
449 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi),
450 0, indirect);
451 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
452 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
453 } else {
454 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
455 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
457 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
459 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
460 }
461 offset = 0;
462 } else {
463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
464 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
465 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
467 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
468 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
469 offset = size;
470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
471 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
472 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
473 }
474
475 if (!indirect)
476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
477 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
478 else
479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
480 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
481
482 /* cache window 1: stack */
483 if (!indirect) {
484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
485 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
486 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
489 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
490 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
491 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
492 } else {
493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
494 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
498 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
499 }
500
501 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
502 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
503
504 /* cache window 2: context */
505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
506 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
507 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
508 0, indirect);
509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
510 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
511 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
512 0, indirect);
513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
514 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
516 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
517
518 /* non-cache window */
519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
520 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
521 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
523 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
524 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
526 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
528 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
529 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
530
531 /* VCN global tiling registers */
532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
533 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
534 adev->gfx.config.gb_addr_config, 0, indirect);
535 }
536
537 /**
538 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
539 *
540 * @adev: amdgpu_device pointer
541 * @inst: instance number
542 *
543 * Disable static power gating for VCN block
544 */
vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device * adev,int inst)545 static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)
546 {
547 uint32_t data = 0;
548
549 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
550 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
551 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
552 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0,
553 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
554 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
555 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
556 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
557 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT,
558 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
559 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
560 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
561 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
562 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT,
563 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
564 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
565 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
566 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
567 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT,
568 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
569 } else {
570 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
571 1 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
572 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
573 0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
574 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
575 1 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
576 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
577 0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
578 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
579 1 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
580 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
581 0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
582 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
583 1 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
584 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
585 0, UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
586 }
587
588 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
589 data &= ~0x103;
590 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
591 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
592 UVD_POWER_STATUS__UVD_PG_EN_MASK;
593 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
594 }
595
596 /**
597 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating
598 *
599 * @adev: amdgpu_device pointer
600 * @inst: instance number
601 *
602 * Enable static power gating for VCN block
603 */
vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device * adev,int inst)604 static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)
605 {
606 uint32_t data;
607
608 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
609 /* Before power off, this indicator has to be turned on */
610 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
611 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
612 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
613 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
614
615 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
616 2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
617 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
618 1 << UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT,
619 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK);
620 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
621 2 << UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT);
622 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
623 1 << UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT,
624 UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
625 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
626 2 << UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
627 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
628 1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT,
629 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
630 WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
631 2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT);
632 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
633 1 << UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT,
634 UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
635 }
636 }
637
638 /**
639 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating
640 *
641 * @adev: amdgpu_device pointer
642 * @inst: instance number
643 *
644 * Disable clock gating for VCN block
645 */
vcn_v4_0_5_disable_clock_gating(struct amdgpu_device * adev,int inst)646 static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
647 {
648 uint32_t data;
649
650 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
651 return;
652
653 /* VCN disable CGC */
654 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
655 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
656 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
657 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
658 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
659
660 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
661 data &= ~(UVD_CGC_GATE__SYS_MASK
662 | UVD_CGC_GATE__UDEC_MASK
663 | UVD_CGC_GATE__MPEG2_MASK
664 | UVD_CGC_GATE__REGS_MASK
665 | UVD_CGC_GATE__RBC_MASK
666 | UVD_CGC_GATE__LMI_MC_MASK
667 | UVD_CGC_GATE__LMI_UMC_MASK
668 | UVD_CGC_GATE__IDCT_MASK
669 | UVD_CGC_GATE__MPRD_MASK
670 | UVD_CGC_GATE__MPC_MASK
671 | UVD_CGC_GATE__LBSI_MASK
672 | UVD_CGC_GATE__LRBBM_MASK
673 | UVD_CGC_GATE__UDEC_RE_MASK
674 | UVD_CGC_GATE__UDEC_CM_MASK
675 | UVD_CGC_GATE__UDEC_IT_MASK
676 | UVD_CGC_GATE__UDEC_DB_MASK
677 | UVD_CGC_GATE__UDEC_MP_MASK
678 | UVD_CGC_GATE__WCB_MASK
679 | UVD_CGC_GATE__VCPU_MASK
680 | UVD_CGC_GATE__MMSCH_MASK);
681
682 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
683 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
684
685 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
686 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
687 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
688 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
689 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
690 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
691 | UVD_CGC_CTRL__SYS_MODE_MASK
692 | UVD_CGC_CTRL__UDEC_MODE_MASK
693 | UVD_CGC_CTRL__MPEG2_MODE_MASK
694 | UVD_CGC_CTRL__REGS_MODE_MASK
695 | UVD_CGC_CTRL__RBC_MODE_MASK
696 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
697 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
698 | UVD_CGC_CTRL__IDCT_MODE_MASK
699 | UVD_CGC_CTRL__MPRD_MODE_MASK
700 | UVD_CGC_CTRL__MPC_MODE_MASK
701 | UVD_CGC_CTRL__LBSI_MODE_MASK
702 | UVD_CGC_CTRL__LRBBM_MODE_MASK
703 | UVD_CGC_CTRL__WCB_MODE_MASK
704 | UVD_CGC_CTRL__VCPU_MODE_MASK
705 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
706 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
707
708 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
709 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
710 | UVD_SUVD_CGC_GATE__SIT_MASK
711 | UVD_SUVD_CGC_GATE__SMP_MASK
712 | UVD_SUVD_CGC_GATE__SCM_MASK
713 | UVD_SUVD_CGC_GATE__SDB_MASK
714 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
715 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
716 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
717 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
718 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
719 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
720 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
721 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
722 | UVD_SUVD_CGC_GATE__SCLR_MASK
723 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
724 | UVD_SUVD_CGC_GATE__ENT_MASK
725 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
726 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
727 | UVD_SUVD_CGC_GATE__SITE_MASK
728 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
729 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
730 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
731 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
732 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
733 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
734
735 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
736 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
737 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
738 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
739 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
740 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
741 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
742 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
743 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
744 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
745 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
746 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
747 }
748
749 /**
750 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
751 *
752 * @adev: amdgpu_device pointer
753 * @sram_sel: sram select
754 * @inst_idx: instance number index
755 * @indirect: indirectly write sram
756 *
757 * Disable clock gating for VCN block with dpg mode
758 */
vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,int inst_idx,uint8_t indirect)759 static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
760 int inst_idx, uint8_t indirect)
761 {
762 uint32_t reg_data = 0;
763
764 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
765 return;
766
767 /* enable sw clock gating control */
768 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
769 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
770 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
771 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
772 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
773 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
774 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
775 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
776 UVD_CGC_CTRL__SYS_MODE_MASK |
777 UVD_CGC_CTRL__UDEC_MODE_MASK |
778 UVD_CGC_CTRL__MPEG2_MODE_MASK |
779 UVD_CGC_CTRL__REGS_MODE_MASK |
780 UVD_CGC_CTRL__RBC_MODE_MASK |
781 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
782 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
783 UVD_CGC_CTRL__IDCT_MODE_MASK |
784 UVD_CGC_CTRL__MPRD_MODE_MASK |
785 UVD_CGC_CTRL__MPC_MODE_MASK |
786 UVD_CGC_CTRL__LBSI_MODE_MASK |
787 UVD_CGC_CTRL__LRBBM_MODE_MASK |
788 UVD_CGC_CTRL__WCB_MODE_MASK |
789 UVD_CGC_CTRL__VCPU_MODE_MASK);
790 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
791 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
792
793 /* turn off clock gating */
794 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
795 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
796
797 /* turn on SUVD clock gating */
798 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
799 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
800
801 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
802 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
803 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
804 }
805
806 /**
807 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
808 *
809 * @adev: amdgpu_device pointer
810 * @inst: instance number
811 *
812 * Enable clock gating for VCN block
813 */
vcn_v4_0_5_enable_clock_gating(struct amdgpu_device * adev,int inst)814 static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
815 {
816 uint32_t data;
817
818 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
819 return;
820
821 /* enable VCN CGC */
822 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
823 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
824 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
825 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
826 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
827
828 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
829 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
830 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
831 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
832 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
833 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
834 | UVD_CGC_CTRL__SYS_MODE_MASK
835 | UVD_CGC_CTRL__UDEC_MODE_MASK
836 | UVD_CGC_CTRL__MPEG2_MODE_MASK
837 | UVD_CGC_CTRL__REGS_MODE_MASK
838 | UVD_CGC_CTRL__RBC_MODE_MASK
839 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
840 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
841 | UVD_CGC_CTRL__IDCT_MODE_MASK
842 | UVD_CGC_CTRL__MPRD_MODE_MASK
843 | UVD_CGC_CTRL__MPC_MODE_MASK
844 | UVD_CGC_CTRL__LBSI_MODE_MASK
845 | UVD_CGC_CTRL__LRBBM_MODE_MASK
846 | UVD_CGC_CTRL__WCB_MODE_MASK
847 | UVD_CGC_CTRL__VCPU_MODE_MASK
848 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
849 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
850
851 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
852 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
853 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
854 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
855 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
856 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
857 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
858 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
859 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
860 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
861 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
862 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
863 }
864
865 /**
866 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode
867 *
868 * @adev: amdgpu_device pointer
869 * @inst_idx: instance number index
870 * @indirect: indirectly write sram
871 *
872 * Start VCN block with dpg mode
873 */
vcn_v4_0_5_start_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)874 static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
875 {
876 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
877 struct amdgpu_ring *ring;
878 uint32_t tmp;
879
880 /* disable register anti-hang mechanism */
881 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
882 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
883 /* enable dynamic power gating mode */
884 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
885 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
886 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
887 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
888
889 if (indirect)
890 adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
891 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
892
893 /* enable clock gating */
894 vcn_v4_0_5_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
895
896 /* enable VCPU clock */
897 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
898 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
899 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
900 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
901
902 /* disable master interrupt */
903 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
904 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
905
906 /* setup regUVD_LMI_CTRL */
907 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
908 UVD_LMI_CTRL__REQ_MODE_MASK |
909 UVD_LMI_CTRL__CRC_RESET_MASK |
910 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
911 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
912 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
913 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
914 0x00100000L);
915 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
916 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
917
918 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
919 VCN, inst_idx, regUVD_MPC_CNTL),
920 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
921
922 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
923 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
924 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
925 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
926 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
927 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
928
929 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
930 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
931 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
932 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
933 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
934 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
935
936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
937 VCN, inst_idx, regUVD_MPC_SET_MUX),
938 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
939 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
940 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
941
942 vcn_v4_0_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
943
944 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
945 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
947 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
948
949 /* enable LMI MC and UMC channels */
950 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
951 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
952 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
953
954 /* enable master interrupt */
955 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
956 VCN, inst_idx, regUVD_MASTINT_EN),
957 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
958
959 if (indirect)
960 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
961
962 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
963
964 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
965 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
966 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
967
968 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
969 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
970 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
971 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
972 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
973 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
974
975 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
976 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
977 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
978
979 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
980 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
981 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
982 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
983
984 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
985 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
986 VCN_RB1_DB_CTRL__EN_MASK);
987
988 /* Keeping one read-back to ensure all register writes are done, otherwise
989 * it may introduce race conditions */
990 RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
991
992 return 0;
993 }
994
995
996 /**
997 * vcn_v4_0_5_start - VCN start
998 *
999 * @adev: amdgpu_device pointer
1000 *
1001 * Start VCN block
1002 */
vcn_v4_0_5_start(struct amdgpu_device * adev)1003 static int vcn_v4_0_5_start(struct amdgpu_device *adev)
1004 {
1005 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1006 struct amdgpu_ring *ring;
1007 uint32_t tmp;
1008 int i, j, k, r;
1009
1010 if (adev->pm.dpm_enabled)
1011 amdgpu_dpm_enable_uvd(adev, true);
1012
1013 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1014 if (adev->vcn.harvest_config & (1 << i))
1015 continue;
1016
1017 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1018
1019 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1020 r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1021 continue;
1022 }
1023
1024 /* disable VCN power gating */
1025 vcn_v4_0_5_disable_static_power_gating(adev, i);
1026
1027 /* set VCN status busy */
1028 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1029 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1030
1031 /*SW clock gating */
1032 vcn_v4_0_5_disable_clock_gating(adev, i);
1033
1034 /* enable VCPU clock */
1035 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1036 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1037
1038 /* disable master interrupt */
1039 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1040 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1041
1042 /* enable LMI MC and UMC channels */
1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1044 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1045
1046 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1047 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1048 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1049 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1050
1051 /* setup regUVD_LMI_CTRL */
1052 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1053 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1054 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1055 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1056 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1057 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1058
1059 /* setup regUVD_MPC_CNTL */
1060 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1061 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1062 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1063 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1064
1065 /* setup UVD_MPC_SET_MUXA0 */
1066 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1067 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1068 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1069 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1070 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1071
1072 /* setup UVD_MPC_SET_MUXB0 */
1073 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1074 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1075 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1076 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1077 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1078
1079 /* setup UVD_MPC_SET_MUX */
1080 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1081 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1082 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1083 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1084
1085 vcn_v4_0_5_mc_resume(adev, i);
1086
1087 /* VCN global tiling registers */
1088 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1089 adev->gfx.config.gb_addr_config);
1090
1091 /* unblock VCPU register access */
1092 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1093 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1094
1095 /* release VCPU reset to boot */
1096 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1097 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1098
1099 for (j = 0; j < 10; ++j) {
1100 uint32_t status;
1101
1102 for (k = 0; k < 100; ++k) {
1103 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1104 if (status & 2)
1105 break;
1106 mdelay(10);
1107 if (amdgpu_emu_mode == 1)
1108 msleep(1);
1109 }
1110
1111 if (amdgpu_emu_mode == 1) {
1112 r = -1;
1113 if (status & 2) {
1114 r = 0;
1115 break;
1116 }
1117 } else {
1118 r = 0;
1119 if (status & 2)
1120 break;
1121
1122 dev_err(adev->dev,
1123 "VCN[%d] is not responding, trying to reset VCPU!!!\n", i);
1124 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1125 UVD_VCPU_CNTL__BLK_RST_MASK,
1126 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1127 mdelay(10);
1128 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1129 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1130
1131 mdelay(10);
1132 r = -1;
1133 }
1134 }
1135
1136 if (r) {
1137 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1138 return r;
1139 }
1140
1141 /* enable master interrupt */
1142 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1143 UVD_MASTINT_EN__VCPU_EN_MASK,
1144 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1145
1146 /* clear the busy bit of VCN_STATUS */
1147 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1148 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1149
1150 ring = &adev->vcn.inst[i].ring_enc[0];
1151 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1152 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1153 VCN_RB1_DB_CTRL__EN_MASK);
1154
1155 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1156 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1157 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1158
1159 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1160 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1161 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1162 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1163 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1164 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1165
1166 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1167 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1168 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1169
1170 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1171 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1172 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1173 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1174
1175 /* Keeping one read-back to ensure all register writes are done, otherwise
1176 * it may introduce race conditions */
1177 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1178 }
1179
1180 return 0;
1181 }
1182
1183 /**
1184 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode
1185 *
1186 * @adev: amdgpu_device pointer
1187 * @inst_idx: instance number index
1188 *
1189 * Stop VCN block with dpg mode
1190 */
vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device * adev,int inst_idx)1191 static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1192 {
1193 uint32_t tmp;
1194
1195 /* Wait for power status to be 1 */
1196 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1197 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1198
1199 /* wait for read ptr to be equal to write ptr */
1200 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1201 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1202
1203 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1204 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1205
1206 /* disable dynamic power gating mode */
1207 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1208 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1209 }
1210
1211 /**
1212 * vcn_v4_0_5_stop - VCN stop
1213 *
1214 * @adev: amdgpu_device pointer
1215 *
1216 * Stop VCN block
1217 */
vcn_v4_0_5_stop(struct amdgpu_device * adev)1218 static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
1219 {
1220 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1221 uint32_t tmp;
1222 int i, r = 0;
1223
1224 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1225 if (adev->vcn.harvest_config & (1 << i))
1226 continue;
1227
1228 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1229 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1230
1231 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1232 vcn_v4_0_5_stop_dpg_mode(adev, i);
1233 continue;
1234 }
1235
1236 /* wait for vcn idle */
1237 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1238 if (r)
1239 return r;
1240
1241 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1242 UVD_LMI_STATUS__READ_CLEAN_MASK |
1243 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1244 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1245 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1246 if (r)
1247 return r;
1248
1249 /* disable LMI UMC channel */
1250 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1251 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1252 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1253 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1254 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1255 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1256 if (r)
1257 return r;
1258
1259 /* block VCPU register access */
1260 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1261 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1262 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1263
1264 /* reset VCPU */
1265 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1266 UVD_VCPU_CNTL__BLK_RST_MASK,
1267 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1268
1269 /* disable VCPU clock */
1270 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1271 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1272
1273 /* apply soft reset */
1274 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1275 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1276 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1277 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1278 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1279 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1280
1281 /* clear status */
1282 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1283
1284 /* apply HW clock gating */
1285 vcn_v4_0_5_enable_clock_gating(adev, i);
1286
1287 /* enable VCN power gating */
1288 vcn_v4_0_5_enable_static_power_gating(adev, i);
1289 }
1290
1291 if (adev->pm.dpm_enabled)
1292 amdgpu_dpm_enable_uvd(adev, false);
1293
1294 return 0;
1295 }
1296
1297 /**
1298 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode
1299 *
1300 * @adev: amdgpu_device pointer
1301 * @inst_idx: instance number index
1302 * @new_state: pause state
1303 *
1304 * Pause dpg mode for VCN block
1305 */
vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1306 static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1307 struct dpg_pause_state *new_state)
1308 {
1309 uint32_t reg_data = 0;
1310 int ret_code;
1311
1312 /* pause/unpause if state is changed */
1313 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1314 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1315 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1316 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1317 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1318
1319 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1320 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1321 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1322
1323 if (!ret_code) {
1324 /* pause DPG */
1325 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1326 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1327
1328 /* wait for ACK */
1329 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1330 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1331 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1332
1333 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1334 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1335 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1336 }
1337 } else {
1338 /* unpause dpg, no need to wait */
1339 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1340 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1341 }
1342 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1343 }
1344
1345 return 0;
1346 }
1347
1348 /**
1349 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer
1350 *
1351 * @ring: amdgpu_ring pointer
1352 *
1353 * Returns the current hardware unified read pointer
1354 */
vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring * ring)1355 static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct amdgpu_ring *ring)
1356 {
1357 struct amdgpu_device *adev = ring->adev;
1358
1359 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1360 DRM_ERROR("wrong ring id is identified in %s", __func__);
1361
1362 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1363 }
1364
1365 /**
1366 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer
1367 *
1368 * @ring: amdgpu_ring pointer
1369 *
1370 * Returns the current hardware unified write pointer
1371 */
vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring * ring)1372 static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct amdgpu_ring *ring)
1373 {
1374 struct amdgpu_device *adev = ring->adev;
1375
1376 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1377 DRM_ERROR("wrong ring id is identified in %s", __func__);
1378
1379 if (ring->use_doorbell)
1380 return *ring->wptr_cpu_addr;
1381 else
1382 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1383 }
1384
1385 /**
1386 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer
1387 *
1388 * @ring: amdgpu_ring pointer
1389 *
1390 * Commits the enc write pointer to the hardware
1391 */
vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring * ring)1392 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring)
1393 {
1394 struct amdgpu_device *adev = ring->adev;
1395
1396 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1397 DRM_ERROR("wrong ring id is identified in %s", __func__);
1398
1399 if (ring->use_doorbell) {
1400 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1401 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1402 } else {
1403 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1404 }
1405 }
1406
1407 static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
1408 .type = AMDGPU_RING_TYPE_VCN_ENC,
1409 .align_mask = 0x3f,
1410 .nop = VCN_ENC_CMD_NO_OP,
1411 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr,
1412 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr,
1413 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr,
1414 .emit_frame_size =
1415 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1416 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1417 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1418 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1419 1, /* vcn_v2_0_enc_ring_insert_end */
1420 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1421 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1422 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1423 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1424 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1425 .test_ib = amdgpu_vcn_unified_ring_test_ib,
1426 .insert_nop = amdgpu_ring_insert_nop,
1427 .insert_end = vcn_v2_0_enc_ring_insert_end,
1428 .pad_ib = amdgpu_ring_generic_pad_ib,
1429 .begin_use = amdgpu_vcn_ring_begin_use,
1430 .end_use = amdgpu_vcn_ring_end_use,
1431 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1432 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1433 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1434 };
1435
1436 /**
1437 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions
1438 *
1439 * @adev: amdgpu_device pointer
1440 *
1441 * Set unified ring functions
1442 */
vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device * adev)1443 static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
1444 {
1445 int i;
1446
1447 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1448 if (adev->vcn.harvest_config & (1 << i))
1449 continue;
1450
1451 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
1452 adev->vcn.inst[i].ring_enc[0].me = i;
1453 }
1454 }
1455
1456 /**
1457 * vcn_v4_0_5_is_idle - check VCN block is idle
1458 *
1459 * @handle: amdgpu_device pointer
1460 *
1461 * Check whether VCN block is idle
1462 */
vcn_v4_0_5_is_idle(void * handle)1463 static bool vcn_v4_0_5_is_idle(void *handle)
1464 {
1465 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466 int i, ret = 1;
1467
1468 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1469 if (adev->vcn.harvest_config & (1 << i))
1470 continue;
1471
1472 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1473 }
1474
1475 return ret;
1476 }
1477
1478 /**
1479 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle
1480 *
1481 * @handle: amdgpu_device pointer
1482 *
1483 * Wait for VCN block idle
1484 */
vcn_v4_0_5_wait_for_idle(void * handle)1485 static int vcn_v4_0_5_wait_for_idle(void *handle)
1486 {
1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1488 int i, ret = 0;
1489
1490 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1491 if (adev->vcn.harvest_config & (1 << i))
1492 continue;
1493
1494 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1495 UVD_STATUS__IDLE);
1496 if (ret)
1497 return ret;
1498 }
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state
1505 *
1506 * @handle: amdgpu_device pointer
1507 * @state: clock gating state
1508 *
1509 * Set VCN block clockgating state
1510 */
vcn_v4_0_5_set_clockgating_state(void * handle,enum amd_clockgating_state state)1511 static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1512 {
1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1514 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1515 int i;
1516
1517 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1518 if (adev->vcn.harvest_config & (1 << i))
1519 continue;
1520
1521 if (enable) {
1522 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1523 return -EBUSY;
1524 vcn_v4_0_5_enable_clock_gating(adev, i);
1525 } else {
1526 vcn_v4_0_5_disable_clock_gating(adev, i);
1527 }
1528 }
1529
1530 return 0;
1531 }
1532
1533 /**
1534 * vcn_v4_0_5_set_powergating_state - set VCN block powergating state
1535 *
1536 * @handle: amdgpu_device pointer
1537 * @state: power gating state
1538 *
1539 * Set VCN block powergating state
1540 */
vcn_v4_0_5_set_powergating_state(void * handle,enum amd_powergating_state state)1541 static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
1542 {
1543 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1544 int ret;
1545
1546 if (state == adev->vcn.cur_state)
1547 return 0;
1548
1549 if (state == AMD_PG_STATE_GATE)
1550 ret = vcn_v4_0_5_stop(adev);
1551 else
1552 ret = vcn_v4_0_5_start(adev);
1553
1554 if (!ret)
1555 adev->vcn.cur_state = state;
1556
1557 return ret;
1558 }
1559
1560 /**
1561 * vcn_v4_0_5_process_interrupt - process VCN block interrupt
1562 *
1563 * @adev: amdgpu_device pointer
1564 * @source: interrupt sources
1565 * @entry: interrupt entry from clients and sources
1566 *
1567 * Process VCN block interrupt
1568 */
vcn_v4_0_5_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1569 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1570 struct amdgpu_iv_entry *entry)
1571 {
1572 uint32_t ip_instance;
1573
1574 switch (entry->client_id) {
1575 case SOC15_IH_CLIENTID_VCN:
1576 ip_instance = 0;
1577 break;
1578 case SOC15_IH_CLIENTID_VCN1:
1579 ip_instance = 1;
1580 break;
1581 default:
1582 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1583 return 0;
1584 }
1585
1586 DRM_DEBUG("IH: VCN TRAP\n");
1587
1588 switch (entry->src_id) {
1589 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1590 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1591 break;
1592 case VCN_4_0__SRCID_UVD_POISON:
1593 amdgpu_vcn_process_poison_irq(adev, source, entry);
1594 break;
1595 default:
1596 DRM_ERROR("Unhandled interrupt: %d %d\n",
1597 entry->src_id, entry->src_data[0]);
1598 break;
1599 }
1600
1601 return 0;
1602 }
1603
1604 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = {
1605 .process = vcn_v4_0_5_process_interrupt,
1606 };
1607
1608 /**
1609 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions
1610 *
1611 * @adev: amdgpu_device pointer
1612 *
1613 * Set VCN block interrupt irq functions
1614 */
vcn_v4_0_5_set_irq_funcs(struct amdgpu_device * adev)1615 static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
1616 {
1617 int i;
1618
1619 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1620 if (adev->vcn.harvest_config & (1 << i))
1621 continue;
1622
1623 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1624 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;
1625 }
1626 }
1627
vcn_v4_0_5_print_ip_state(void * handle,struct drm_printer * p)1628 static void vcn_v4_0_5_print_ip_state(void *handle, struct drm_printer *p)
1629 {
1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1631 int i, j;
1632 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
1633 uint32_t inst_off, is_powered;
1634
1635 if (!adev->vcn.ip_dump)
1636 return;
1637
1638 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1639 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1640 if (adev->vcn.harvest_config & (1 << i)) {
1641 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1642 continue;
1643 }
1644
1645 inst_off = i * reg_count;
1646 is_powered = (adev->vcn.ip_dump[inst_off] &
1647 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1648
1649 if (is_powered) {
1650 drm_printf(p, "\nActive Instance:VCN%d\n", i);
1651 for (j = 0; j < reg_count; j++)
1652 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
1653 adev->vcn.ip_dump[inst_off + j]);
1654 } else {
1655 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1656 }
1657 }
1658 }
1659
vcn_v4_0_5_dump_ip_state(void * handle)1660 static void vcn_v4_0_5_dump_ip_state(void *handle)
1661 {
1662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1663 int i, j;
1664 bool is_powered;
1665 uint32_t inst_off;
1666 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
1667
1668 if (!adev->vcn.ip_dump)
1669 return;
1670
1671 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1672 if (adev->vcn.harvest_config & (1 << i))
1673 continue;
1674
1675 inst_off = i * reg_count;
1676 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1677 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
1678 is_powered = (adev->vcn.ip_dump[inst_off] &
1679 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1680
1681 if (is_powered)
1682 for (j = 1; j < reg_count; j++)
1683 adev->vcn.ip_dump[inst_off + j] =
1684 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
1685 i));
1686 }
1687 }
1688
1689 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
1690 .name = "vcn_v4_0_5",
1691 .early_init = vcn_v4_0_5_early_init,
1692 .late_init = NULL,
1693 .sw_init = vcn_v4_0_5_sw_init,
1694 .sw_fini = vcn_v4_0_5_sw_fini,
1695 .hw_init = vcn_v4_0_5_hw_init,
1696 .hw_fini = vcn_v4_0_5_hw_fini,
1697 .suspend = vcn_v4_0_5_suspend,
1698 .resume = vcn_v4_0_5_resume,
1699 .is_idle = vcn_v4_0_5_is_idle,
1700 .wait_for_idle = vcn_v4_0_5_wait_for_idle,
1701 .check_soft_reset = NULL,
1702 .pre_soft_reset = NULL,
1703 .soft_reset = NULL,
1704 .post_soft_reset = NULL,
1705 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
1706 .set_powergating_state = vcn_v4_0_5_set_powergating_state,
1707 .dump_ip_state = vcn_v4_0_5_dump_ip_state,
1708 .print_ip_state = vcn_v4_0_5_print_ip_state,
1709 };
1710
1711 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
1712 .type = AMD_IP_BLOCK_TYPE_VCN,
1713 .major = 4,
1714 .minor = 0,
1715 .rev = 5,
1716 .funcs = &vcn_v4_0_5_ip_funcs,
1717 };
1718