1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2015-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/pci.h>
25 #include <linux/acpi.h>
26 #include "kfd_crat.h"
27 #include "kfd_priv.h"
28 #include "kfd_topology.h"
29 #include "amdgpu.h"
30 #include "amdgpu_amdkfd.h"
31
32 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
33 * GPU processor ID are expressed with Bit[31]=1.
34 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
35 * used in the CRAT.
36 */
37 static uint32_t gpu_processor_id_low = 0x80001000;
38
39 /* Return the next available gpu_processor_id and increment it for next GPU
40 * @total_cu_count - Total CUs present in the GPU including ones
41 * masked off
42 */
get_and_inc_gpu_processor_id(unsigned int total_cu_count)43 static inline unsigned int get_and_inc_gpu_processor_id(
44 unsigned int total_cu_count)
45 {
46 int current_id = gpu_processor_id_low;
47
48 gpu_processor_id_low += total_cu_count;
49 return current_id;
50 }
51
52
53 static struct kfd_gpu_cache_info kaveri_cache_info[] = {
54 {
55 /* TCP L1 Cache per CU */
56 .cache_size = 16,
57 .cache_level = 1,
58 .cache_line_size = 64,
59 .flags = (CRAT_CACHE_FLAGS_ENABLED |
60 CRAT_CACHE_FLAGS_DATA_CACHE |
61 CRAT_CACHE_FLAGS_SIMD_CACHE),
62 .num_cu_shared = 1,
63 },
64 {
65 /* Scalar L1 Instruction Cache (in SQC module) per bank */
66 .cache_size = 16,
67 .cache_level = 1,
68 .cache_line_size = 64,
69 .flags = (CRAT_CACHE_FLAGS_ENABLED |
70 CRAT_CACHE_FLAGS_INST_CACHE |
71 CRAT_CACHE_FLAGS_SIMD_CACHE),
72 .num_cu_shared = 2,
73 },
74 {
75 /* Scalar L1 Data Cache (in SQC module) per bank */
76 .cache_size = 8,
77 .cache_level = 1,
78 .cache_line_size = 64,
79 .flags = (CRAT_CACHE_FLAGS_ENABLED |
80 CRAT_CACHE_FLAGS_DATA_CACHE |
81 CRAT_CACHE_FLAGS_SIMD_CACHE),
82 .num_cu_shared = 2,
83 },
84
85 /* TODO: Add L2 Cache information */
86 };
87
88
89 static struct kfd_gpu_cache_info carrizo_cache_info[] = {
90 {
91 /* TCP L1 Cache per CU */
92 .cache_size = 16,
93 .cache_level = 1,
94 .cache_line_size = 64,
95 .flags = (CRAT_CACHE_FLAGS_ENABLED |
96 CRAT_CACHE_FLAGS_DATA_CACHE |
97 CRAT_CACHE_FLAGS_SIMD_CACHE),
98 .num_cu_shared = 1,
99 },
100 {
101 /* Scalar L1 Instruction Cache (in SQC module) per bank */
102 .cache_size = 32,
103 .cache_level = 1,
104 .cache_line_size = 64,
105 .flags = (CRAT_CACHE_FLAGS_ENABLED |
106 CRAT_CACHE_FLAGS_INST_CACHE |
107 CRAT_CACHE_FLAGS_SIMD_CACHE),
108 .num_cu_shared = 4,
109 },
110 {
111 /* Scalar L1 Data Cache (in SQC module) per bank. */
112 .cache_size = 16,
113 .cache_level = 1,
114 .cache_line_size = 64,
115 .flags = (CRAT_CACHE_FLAGS_ENABLED |
116 CRAT_CACHE_FLAGS_DATA_CACHE |
117 CRAT_CACHE_FLAGS_SIMD_CACHE),
118 .num_cu_shared = 4,
119 },
120
121 /* TODO: Add L2 Cache information */
122 };
123
124 #define hawaii_cache_info kaveri_cache_info
125 #define tonga_cache_info carrizo_cache_info
126 #define fiji_cache_info carrizo_cache_info
127 #define polaris10_cache_info carrizo_cache_info
128 #define polaris11_cache_info carrizo_cache_info
129 #define polaris12_cache_info carrizo_cache_info
130 #define vegam_cache_info carrizo_cache_info
131
132 /* NOTE: L1 cache information has been updated and L2/L3
133 * cache information has been added for Vega10 and
134 * newer ASICs. The unit for cache_size is KiB.
135 * In future, check & update cache details
136 * for every new ASIC is required.
137 */
138
139 static struct kfd_gpu_cache_info vega10_cache_info[] = {
140 {
141 /* TCP L1 Cache per CU */
142 .cache_size = 16,
143 .cache_level = 1,
144 .cache_line_size = 64,
145 .flags = (CRAT_CACHE_FLAGS_ENABLED |
146 CRAT_CACHE_FLAGS_DATA_CACHE |
147 CRAT_CACHE_FLAGS_SIMD_CACHE),
148 .num_cu_shared = 1,
149 },
150 {
151 /* Scalar L1 Instruction Cache per SQC */
152 .cache_size = 32,
153 .cache_level = 1,
154 .cache_line_size = 64,
155 .flags = (CRAT_CACHE_FLAGS_ENABLED |
156 CRAT_CACHE_FLAGS_INST_CACHE |
157 CRAT_CACHE_FLAGS_SIMD_CACHE),
158 .num_cu_shared = 3,
159 },
160 {
161 /* Scalar L1 Data Cache per SQC */
162 .cache_size = 16,
163 .cache_level = 1,
164 .cache_line_size = 64,
165 .flags = (CRAT_CACHE_FLAGS_ENABLED |
166 CRAT_CACHE_FLAGS_DATA_CACHE |
167 CRAT_CACHE_FLAGS_SIMD_CACHE),
168 .num_cu_shared = 3,
169 },
170 {
171 /* L2 Data Cache per GPU (Total Tex Cache) */
172 .cache_size = 4096,
173 .cache_level = 2,
174 .cache_line_size = 64,
175 .flags = (CRAT_CACHE_FLAGS_ENABLED |
176 CRAT_CACHE_FLAGS_DATA_CACHE |
177 CRAT_CACHE_FLAGS_SIMD_CACHE),
178 .num_cu_shared = 16,
179 },
180 };
181
182 static struct kfd_gpu_cache_info raven_cache_info[] = {
183 {
184 /* TCP L1 Cache per CU */
185 .cache_size = 16,
186 .cache_level = 1,
187 .cache_line_size = 64,
188 .flags = (CRAT_CACHE_FLAGS_ENABLED |
189 CRAT_CACHE_FLAGS_DATA_CACHE |
190 CRAT_CACHE_FLAGS_SIMD_CACHE),
191 .num_cu_shared = 1,
192 },
193 {
194 /* Scalar L1 Instruction Cache per SQC */
195 .cache_size = 32,
196 .cache_level = 1,
197 .cache_line_size = 64,
198 .flags = (CRAT_CACHE_FLAGS_ENABLED |
199 CRAT_CACHE_FLAGS_INST_CACHE |
200 CRAT_CACHE_FLAGS_SIMD_CACHE),
201 .num_cu_shared = 3,
202 },
203 {
204 /* Scalar L1 Data Cache per SQC */
205 .cache_size = 16,
206 .cache_level = 1,
207 .cache_line_size = 64,
208 .flags = (CRAT_CACHE_FLAGS_ENABLED |
209 CRAT_CACHE_FLAGS_DATA_CACHE |
210 CRAT_CACHE_FLAGS_SIMD_CACHE),
211 .num_cu_shared = 3,
212 },
213 {
214 /* L2 Data Cache per GPU (Total Tex Cache) */
215 .cache_size = 1024,
216 .cache_level = 2,
217 .cache_line_size = 64,
218 .flags = (CRAT_CACHE_FLAGS_ENABLED |
219 CRAT_CACHE_FLAGS_DATA_CACHE |
220 CRAT_CACHE_FLAGS_SIMD_CACHE),
221 .num_cu_shared = 11,
222 },
223 };
224
225 static struct kfd_gpu_cache_info renoir_cache_info[] = {
226 {
227 /* TCP L1 Cache per CU */
228 .cache_size = 16,
229 .cache_level = 1,
230 .cache_line_size = 64,
231 .flags = (CRAT_CACHE_FLAGS_ENABLED |
232 CRAT_CACHE_FLAGS_DATA_CACHE |
233 CRAT_CACHE_FLAGS_SIMD_CACHE),
234 .num_cu_shared = 1,
235 },
236 {
237 /* Scalar L1 Instruction Cache per SQC */
238 .cache_size = 32,
239 .cache_level = 1,
240 .cache_line_size = 64,
241 .flags = (CRAT_CACHE_FLAGS_ENABLED |
242 CRAT_CACHE_FLAGS_INST_CACHE |
243 CRAT_CACHE_FLAGS_SIMD_CACHE),
244 .num_cu_shared = 3,
245 },
246 {
247 /* Scalar L1 Data Cache per SQC */
248 .cache_size = 16,
249 .cache_level = 1,
250 .cache_line_size = 64,
251 .flags = (CRAT_CACHE_FLAGS_ENABLED |
252 CRAT_CACHE_FLAGS_DATA_CACHE |
253 CRAT_CACHE_FLAGS_SIMD_CACHE),
254 .num_cu_shared = 3,
255 },
256 {
257 /* L2 Data Cache per GPU (Total Tex Cache) */
258 .cache_size = 1024,
259 .cache_level = 2,
260 .cache_line_size = 64,
261 .flags = (CRAT_CACHE_FLAGS_ENABLED |
262 CRAT_CACHE_FLAGS_DATA_CACHE |
263 CRAT_CACHE_FLAGS_SIMD_CACHE),
264 .num_cu_shared = 8,
265 },
266 };
267
268 static struct kfd_gpu_cache_info vega12_cache_info[] = {
269 {
270 /* TCP L1 Cache per CU */
271 .cache_size = 16,
272 .cache_level = 1,
273 .cache_line_size = 64,
274 .flags = (CRAT_CACHE_FLAGS_ENABLED |
275 CRAT_CACHE_FLAGS_DATA_CACHE |
276 CRAT_CACHE_FLAGS_SIMD_CACHE),
277 .num_cu_shared = 1,
278 },
279 {
280 /* Scalar L1 Instruction Cache per SQC */
281 .cache_size = 32,
282 .cache_level = 1,
283 .cache_line_size = 64,
284 .flags = (CRAT_CACHE_FLAGS_ENABLED |
285 CRAT_CACHE_FLAGS_INST_CACHE |
286 CRAT_CACHE_FLAGS_SIMD_CACHE),
287 .num_cu_shared = 3,
288 },
289 {
290 /* Scalar L1 Data Cache per SQC */
291 .cache_size = 16,
292 .cache_level = 1,
293 .cache_line_size = 64,
294 .flags = (CRAT_CACHE_FLAGS_ENABLED |
295 CRAT_CACHE_FLAGS_DATA_CACHE |
296 CRAT_CACHE_FLAGS_SIMD_CACHE),
297 .num_cu_shared = 3,
298 },
299 {
300 /* L2 Data Cache per GPU (Total Tex Cache) */
301 .cache_size = 2048,
302 .cache_level = 2,
303 .cache_line_size = 64,
304 .flags = (CRAT_CACHE_FLAGS_ENABLED |
305 CRAT_CACHE_FLAGS_DATA_CACHE |
306 CRAT_CACHE_FLAGS_SIMD_CACHE),
307 .num_cu_shared = 5,
308 },
309 };
310
311 static struct kfd_gpu_cache_info vega20_cache_info[] = {
312 {
313 /* TCP L1 Cache per CU */
314 .cache_size = 16,
315 .cache_level = 1,
316 .cache_line_size = 64,
317 .flags = (CRAT_CACHE_FLAGS_ENABLED |
318 CRAT_CACHE_FLAGS_DATA_CACHE |
319 CRAT_CACHE_FLAGS_SIMD_CACHE),
320 .num_cu_shared = 1,
321 },
322 {
323 /* Scalar L1 Instruction Cache per SQC */
324 .cache_size = 32,
325 .cache_level = 1,
326 .cache_line_size = 64,
327 .flags = (CRAT_CACHE_FLAGS_ENABLED |
328 CRAT_CACHE_FLAGS_INST_CACHE |
329 CRAT_CACHE_FLAGS_SIMD_CACHE),
330 .num_cu_shared = 3,
331 },
332 {
333 /* Scalar L1 Data Cache per SQC */
334 .cache_size = 16,
335 .cache_level = 1,
336 .cache_line_size = 64,
337 .flags = (CRAT_CACHE_FLAGS_ENABLED |
338 CRAT_CACHE_FLAGS_DATA_CACHE |
339 CRAT_CACHE_FLAGS_SIMD_CACHE),
340 .num_cu_shared = 3,
341 },
342 {
343 /* L2 Data Cache per GPU (Total Tex Cache) */
344 .cache_size = 8192,
345 .cache_level = 2,
346 .cache_line_size = 64,
347 .flags = (CRAT_CACHE_FLAGS_ENABLED |
348 CRAT_CACHE_FLAGS_DATA_CACHE |
349 CRAT_CACHE_FLAGS_SIMD_CACHE),
350 .num_cu_shared = 16,
351 },
352 };
353
354 static struct kfd_gpu_cache_info aldebaran_cache_info[] = {
355 {
356 /* TCP L1 Cache per CU */
357 .cache_size = 16,
358 .cache_level = 1,
359 .cache_line_size = 64,
360 .flags = (CRAT_CACHE_FLAGS_ENABLED |
361 CRAT_CACHE_FLAGS_DATA_CACHE |
362 CRAT_CACHE_FLAGS_SIMD_CACHE),
363 .num_cu_shared = 1,
364 },
365 {
366 /* Scalar L1 Instruction Cache per SQC */
367 .cache_size = 32,
368 .cache_level = 1,
369 .cache_line_size = 64,
370 .flags = (CRAT_CACHE_FLAGS_ENABLED |
371 CRAT_CACHE_FLAGS_INST_CACHE |
372 CRAT_CACHE_FLAGS_SIMD_CACHE),
373 .num_cu_shared = 2,
374 },
375 {
376 /* Scalar L1 Data Cache per SQC */
377 .cache_size = 16,
378 .cache_level = 1,
379 .cache_line_size = 64,
380 .flags = (CRAT_CACHE_FLAGS_ENABLED |
381 CRAT_CACHE_FLAGS_DATA_CACHE |
382 CRAT_CACHE_FLAGS_SIMD_CACHE),
383 .num_cu_shared = 2,
384 },
385 {
386 /* L2 Data Cache per GPU (Total Tex Cache) */
387 .cache_size = 8192,
388 .cache_level = 2,
389 .cache_line_size = 128,
390 .flags = (CRAT_CACHE_FLAGS_ENABLED |
391 CRAT_CACHE_FLAGS_DATA_CACHE |
392 CRAT_CACHE_FLAGS_SIMD_CACHE),
393 .num_cu_shared = 14,
394 },
395 };
396
397 static struct kfd_gpu_cache_info navi10_cache_info[] = {
398 {
399 /* TCP L1 Cache per CU */
400 .cache_size = 16,
401 .cache_level = 1,
402 .cache_line_size = 128,
403 .flags = (CRAT_CACHE_FLAGS_ENABLED |
404 CRAT_CACHE_FLAGS_DATA_CACHE |
405 CRAT_CACHE_FLAGS_SIMD_CACHE),
406 .num_cu_shared = 1,
407 },
408 {
409 /* Scalar L1 Instruction Cache per SQC */
410 .cache_size = 32,
411 .cache_level = 1,
412 .cache_line_size = 64,
413 .flags = (CRAT_CACHE_FLAGS_ENABLED |
414 CRAT_CACHE_FLAGS_INST_CACHE |
415 CRAT_CACHE_FLAGS_SIMD_CACHE),
416 .num_cu_shared = 2,
417 },
418 {
419 /* Scalar L1 Data Cache per SQC */
420 .cache_size = 16,
421 .cache_level = 1,
422 .cache_line_size = 64,
423 .flags = (CRAT_CACHE_FLAGS_ENABLED |
424 CRAT_CACHE_FLAGS_DATA_CACHE |
425 CRAT_CACHE_FLAGS_SIMD_CACHE),
426 .num_cu_shared = 2,
427 },
428 {
429 /* GL1 Data Cache per SA */
430 .cache_size = 128,
431 .cache_level = 1,
432 .cache_line_size = 128,
433 .flags = (CRAT_CACHE_FLAGS_ENABLED |
434 CRAT_CACHE_FLAGS_DATA_CACHE |
435 CRAT_CACHE_FLAGS_SIMD_CACHE),
436 .num_cu_shared = 10,
437 },
438 {
439 /* L2 Data Cache per GPU (Total Tex Cache) */
440 .cache_size = 4096,
441 .cache_level = 2,
442 .cache_line_size = 128,
443 .flags = (CRAT_CACHE_FLAGS_ENABLED |
444 CRAT_CACHE_FLAGS_DATA_CACHE |
445 CRAT_CACHE_FLAGS_SIMD_CACHE),
446 .num_cu_shared = 10,
447 },
448 };
449
450 static struct kfd_gpu_cache_info vangogh_cache_info[] = {
451 {
452 /* TCP L1 Cache per CU */
453 .cache_size = 16,
454 .cache_level = 1,
455 .cache_line_size = 128,
456 .flags = (CRAT_CACHE_FLAGS_ENABLED |
457 CRAT_CACHE_FLAGS_DATA_CACHE |
458 CRAT_CACHE_FLAGS_SIMD_CACHE),
459 .num_cu_shared = 1,
460 },
461 {
462 /* Scalar L1 Instruction Cache per SQC */
463 .cache_size = 32,
464 .cache_level = 1,
465 .cache_line_size = 64,
466 .flags = (CRAT_CACHE_FLAGS_ENABLED |
467 CRAT_CACHE_FLAGS_INST_CACHE |
468 CRAT_CACHE_FLAGS_SIMD_CACHE),
469 .num_cu_shared = 2,
470 },
471 {
472 /* Scalar L1 Data Cache per SQC */
473 .cache_size = 16,
474 .cache_level = 1,
475 .cache_line_size = 64,
476 .flags = (CRAT_CACHE_FLAGS_ENABLED |
477 CRAT_CACHE_FLAGS_DATA_CACHE |
478 CRAT_CACHE_FLAGS_SIMD_CACHE),
479 .num_cu_shared = 2,
480 },
481 {
482 /* GL1 Data Cache per SA */
483 .cache_size = 128,
484 .cache_level = 1,
485 .cache_line_size = 128,
486 .flags = (CRAT_CACHE_FLAGS_ENABLED |
487 CRAT_CACHE_FLAGS_DATA_CACHE |
488 CRAT_CACHE_FLAGS_SIMD_CACHE),
489 .num_cu_shared = 8,
490 },
491 {
492 /* L2 Data Cache per GPU (Total Tex Cache) */
493 .cache_size = 1024,
494 .cache_level = 2,
495 .cache_line_size = 128,
496 .flags = (CRAT_CACHE_FLAGS_ENABLED |
497 CRAT_CACHE_FLAGS_DATA_CACHE |
498 CRAT_CACHE_FLAGS_SIMD_CACHE),
499 .num_cu_shared = 8,
500 },
501 };
502
503 static struct kfd_gpu_cache_info navi14_cache_info[] = {
504 {
505 /* TCP L1 Cache per CU */
506 .cache_size = 16,
507 .cache_level = 1,
508 .cache_line_size = 128,
509 .flags = (CRAT_CACHE_FLAGS_ENABLED |
510 CRAT_CACHE_FLAGS_DATA_CACHE |
511 CRAT_CACHE_FLAGS_SIMD_CACHE),
512 .num_cu_shared = 1,
513 },
514 {
515 /* Scalar L1 Instruction Cache per SQC */
516 .cache_size = 32,
517 .cache_level = 1,
518 .cache_line_size = 64,
519 .flags = (CRAT_CACHE_FLAGS_ENABLED |
520 CRAT_CACHE_FLAGS_INST_CACHE |
521 CRAT_CACHE_FLAGS_SIMD_CACHE),
522 .num_cu_shared = 2,
523 },
524 {
525 /* Scalar L1 Data Cache per SQC */
526 .cache_size = 16,
527 .cache_level = 1,
528 .cache_line_size = 64,
529 .flags = (CRAT_CACHE_FLAGS_ENABLED |
530 CRAT_CACHE_FLAGS_DATA_CACHE |
531 CRAT_CACHE_FLAGS_SIMD_CACHE),
532 .num_cu_shared = 2,
533 },
534 {
535 /* GL1 Data Cache per SA */
536 .cache_size = 128,
537 .cache_level = 1,
538 .cache_line_size = 128,
539 .flags = (CRAT_CACHE_FLAGS_ENABLED |
540 CRAT_CACHE_FLAGS_DATA_CACHE |
541 CRAT_CACHE_FLAGS_SIMD_CACHE),
542 .num_cu_shared = 12,
543 },
544 {
545 /* L2 Data Cache per GPU (Total Tex Cache) */
546 .cache_size = 2048,
547 .cache_level = 2,
548 .cache_line_size = 128,
549 .flags = (CRAT_CACHE_FLAGS_ENABLED |
550 CRAT_CACHE_FLAGS_DATA_CACHE |
551 CRAT_CACHE_FLAGS_SIMD_CACHE),
552 .num_cu_shared = 12,
553 },
554 };
555
556 static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = {
557 {
558 /* TCP L1 Cache per CU */
559 .cache_size = 16,
560 .cache_level = 1,
561 .cache_line_size = 128,
562 .flags = (CRAT_CACHE_FLAGS_ENABLED |
563 CRAT_CACHE_FLAGS_DATA_CACHE |
564 CRAT_CACHE_FLAGS_SIMD_CACHE),
565 .num_cu_shared = 1,
566 },
567 {
568 /* Scalar L1 Instruction Cache per SQC */
569 .cache_size = 32,
570 .cache_level = 1,
571 .cache_line_size = 64,
572 .flags = (CRAT_CACHE_FLAGS_ENABLED |
573 CRAT_CACHE_FLAGS_INST_CACHE |
574 CRAT_CACHE_FLAGS_SIMD_CACHE),
575 .num_cu_shared = 2,
576 },
577 {
578 /* Scalar L1 Data Cache per SQC */
579 .cache_size = 16,
580 .cache_level = 1,
581 .cache_line_size = 64,
582 .flags = (CRAT_CACHE_FLAGS_ENABLED |
583 CRAT_CACHE_FLAGS_DATA_CACHE |
584 CRAT_CACHE_FLAGS_SIMD_CACHE),
585 .num_cu_shared = 2,
586 },
587 {
588 /* GL1 Data Cache per SA */
589 .cache_size = 128,
590 .cache_level = 1,
591 .cache_line_size = 128,
592 .flags = (CRAT_CACHE_FLAGS_ENABLED |
593 CRAT_CACHE_FLAGS_DATA_CACHE |
594 CRAT_CACHE_FLAGS_SIMD_CACHE),
595 .num_cu_shared = 10,
596 },
597 {
598 /* L2 Data Cache per GPU (Total Tex Cache) */
599 .cache_size = 4096,
600 .cache_level = 2,
601 .cache_line_size = 128,
602 .flags = (CRAT_CACHE_FLAGS_ENABLED |
603 CRAT_CACHE_FLAGS_DATA_CACHE |
604 CRAT_CACHE_FLAGS_SIMD_CACHE),
605 .num_cu_shared = 10,
606 },
607 {
608 /* L3 Data Cache per GPU */
609 .cache_size = 128*1024,
610 .cache_level = 3,
611 .cache_line_size = 64,
612 .flags = (CRAT_CACHE_FLAGS_ENABLED |
613 CRAT_CACHE_FLAGS_DATA_CACHE |
614 CRAT_CACHE_FLAGS_SIMD_CACHE),
615 .num_cu_shared = 10,
616 },
617 };
618
619 static struct kfd_gpu_cache_info navy_flounder_cache_info[] = {
620 {
621 /* TCP L1 Cache per CU */
622 .cache_size = 16,
623 .cache_level = 1,
624 .cache_line_size = 128,
625 .flags = (CRAT_CACHE_FLAGS_ENABLED |
626 CRAT_CACHE_FLAGS_DATA_CACHE |
627 CRAT_CACHE_FLAGS_SIMD_CACHE),
628 .num_cu_shared = 1,
629 },
630 {
631 /* Scalar L1 Instruction Cache per SQC */
632 .cache_size = 32,
633 .cache_level = 1,
634 .cache_line_size = 64,
635 .flags = (CRAT_CACHE_FLAGS_ENABLED |
636 CRAT_CACHE_FLAGS_INST_CACHE |
637 CRAT_CACHE_FLAGS_SIMD_CACHE),
638 .num_cu_shared = 2,
639 },
640 {
641 /* Scalar L1 Data Cache per SQC */
642 .cache_size = 16,
643 .cache_level = 1,
644 .cache_line_size = 64,
645 .flags = (CRAT_CACHE_FLAGS_ENABLED |
646 CRAT_CACHE_FLAGS_DATA_CACHE |
647 CRAT_CACHE_FLAGS_SIMD_CACHE),
648 .num_cu_shared = 2,
649 },
650 {
651 /* GL1 Data Cache per SA */
652 .cache_size = 128,
653 .cache_level = 1,
654 .cache_line_size = 128,
655 .flags = (CRAT_CACHE_FLAGS_ENABLED |
656 CRAT_CACHE_FLAGS_DATA_CACHE |
657 CRAT_CACHE_FLAGS_SIMD_CACHE),
658 .num_cu_shared = 10,
659 },
660 {
661 /* L2 Data Cache per GPU (Total Tex Cache) */
662 .cache_size = 3072,
663 .cache_level = 2,
664 .cache_line_size = 128,
665 .flags = (CRAT_CACHE_FLAGS_ENABLED |
666 CRAT_CACHE_FLAGS_DATA_CACHE |
667 CRAT_CACHE_FLAGS_SIMD_CACHE),
668 .num_cu_shared = 10,
669 },
670 {
671 /* L3 Data Cache per GPU */
672 .cache_size = 96*1024,
673 .cache_level = 3,
674 .cache_line_size = 64,
675 .flags = (CRAT_CACHE_FLAGS_ENABLED |
676 CRAT_CACHE_FLAGS_DATA_CACHE |
677 CRAT_CACHE_FLAGS_SIMD_CACHE),
678 .num_cu_shared = 10,
679 },
680 };
681
682 static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = {
683 {
684 /* TCP L1 Cache per CU */
685 .cache_size = 16,
686 .cache_level = 1,
687 .cache_line_size = 128,
688 .flags = (CRAT_CACHE_FLAGS_ENABLED |
689 CRAT_CACHE_FLAGS_DATA_CACHE |
690 CRAT_CACHE_FLAGS_SIMD_CACHE),
691 .num_cu_shared = 1,
692 },
693 {
694 /* Scalar L1 Instruction Cache per SQC */
695 .cache_size = 32,
696 .cache_level = 1,
697 .cache_line_size = 64,
698 .flags = (CRAT_CACHE_FLAGS_ENABLED |
699 CRAT_CACHE_FLAGS_INST_CACHE |
700 CRAT_CACHE_FLAGS_SIMD_CACHE),
701 .num_cu_shared = 2,
702 },
703 {
704 /* Scalar L1 Data Cache per SQC */
705 .cache_size = 16,
706 .cache_level = 1,
707 .cache_line_size = 64,
708 .flags = (CRAT_CACHE_FLAGS_ENABLED |
709 CRAT_CACHE_FLAGS_DATA_CACHE |
710 CRAT_CACHE_FLAGS_SIMD_CACHE),
711 .num_cu_shared = 2,
712 },
713 {
714 /* GL1 Data Cache per SA */
715 .cache_size = 128,
716 .cache_level = 1,
717 .cache_line_size = 128,
718 .flags = (CRAT_CACHE_FLAGS_ENABLED |
719 CRAT_CACHE_FLAGS_DATA_CACHE |
720 CRAT_CACHE_FLAGS_SIMD_CACHE),
721 .num_cu_shared = 8,
722 },
723 {
724 /* L2 Data Cache per GPU (Total Tex Cache) */
725 .cache_size = 2048,
726 .cache_level = 2,
727 .cache_line_size = 128,
728 .flags = (CRAT_CACHE_FLAGS_ENABLED |
729 CRAT_CACHE_FLAGS_DATA_CACHE |
730 CRAT_CACHE_FLAGS_SIMD_CACHE),
731 .num_cu_shared = 8,
732 },
733 {
734 /* L3 Data Cache per GPU */
735 .cache_size = 32*1024,
736 .cache_level = 3,
737 .cache_line_size = 64,
738 .flags = (CRAT_CACHE_FLAGS_ENABLED |
739 CRAT_CACHE_FLAGS_DATA_CACHE |
740 CRAT_CACHE_FLAGS_SIMD_CACHE),
741 .num_cu_shared = 8,
742 },
743 };
744
745 static struct kfd_gpu_cache_info beige_goby_cache_info[] = {
746 {
747 /* TCP L1 Cache per CU */
748 .cache_size = 16,
749 .cache_level = 1,
750 .cache_line_size = 128,
751 .flags = (CRAT_CACHE_FLAGS_ENABLED |
752 CRAT_CACHE_FLAGS_DATA_CACHE |
753 CRAT_CACHE_FLAGS_SIMD_CACHE),
754 .num_cu_shared = 1,
755 },
756 {
757 /* Scalar L1 Instruction Cache per SQC */
758 .cache_size = 32,
759 .cache_level = 1,
760 .cache_line_size = 64,
761 .flags = (CRAT_CACHE_FLAGS_ENABLED |
762 CRAT_CACHE_FLAGS_INST_CACHE |
763 CRAT_CACHE_FLAGS_SIMD_CACHE),
764 .num_cu_shared = 2,
765 },
766 {
767 /* Scalar L1 Data Cache per SQC */
768 .cache_size = 16,
769 .cache_level = 1,
770 .cache_line_size = 64,
771 .flags = (CRAT_CACHE_FLAGS_ENABLED |
772 CRAT_CACHE_FLAGS_DATA_CACHE |
773 CRAT_CACHE_FLAGS_SIMD_CACHE),
774 .num_cu_shared = 2,
775 },
776 {
777 /* GL1 Data Cache per SA */
778 .cache_size = 128,
779 .cache_level = 1,
780 .cache_line_size = 128,
781 .flags = (CRAT_CACHE_FLAGS_ENABLED |
782 CRAT_CACHE_FLAGS_DATA_CACHE |
783 CRAT_CACHE_FLAGS_SIMD_CACHE),
784 .num_cu_shared = 8,
785 },
786 {
787 /* L2 Data Cache per GPU (Total Tex Cache) */
788 .cache_size = 1024,
789 .cache_level = 2,
790 .cache_line_size = 128,
791 .flags = (CRAT_CACHE_FLAGS_ENABLED |
792 CRAT_CACHE_FLAGS_DATA_CACHE |
793 CRAT_CACHE_FLAGS_SIMD_CACHE),
794 .num_cu_shared = 8,
795 },
796 {
797 /* L3 Data Cache per GPU */
798 .cache_size = 16*1024,
799 .cache_level = 3,
800 .cache_line_size = 64,
801 .flags = (CRAT_CACHE_FLAGS_ENABLED |
802 CRAT_CACHE_FLAGS_DATA_CACHE |
803 CRAT_CACHE_FLAGS_SIMD_CACHE),
804 .num_cu_shared = 8,
805 },
806 };
807
808 static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
809 {
810 /* TCP L1 Cache per CU */
811 .cache_size = 16,
812 .cache_level = 1,
813 .cache_line_size = 128,
814 .flags = (CRAT_CACHE_FLAGS_ENABLED |
815 CRAT_CACHE_FLAGS_DATA_CACHE |
816 CRAT_CACHE_FLAGS_SIMD_CACHE),
817 .num_cu_shared = 1,
818 },
819 {
820 /* Scalar L1 Instruction Cache per SQC */
821 .cache_size = 32,
822 .cache_level = 1,
823 .cache_line_size = 64,
824 .flags = (CRAT_CACHE_FLAGS_ENABLED |
825 CRAT_CACHE_FLAGS_INST_CACHE |
826 CRAT_CACHE_FLAGS_SIMD_CACHE),
827 .num_cu_shared = 2,
828 },
829 {
830 /* Scalar L1 Data Cache per SQC */
831 .cache_size = 16,
832 .cache_level = 1,
833 .cache_line_size = 64,
834 .flags = (CRAT_CACHE_FLAGS_ENABLED |
835 CRAT_CACHE_FLAGS_DATA_CACHE |
836 CRAT_CACHE_FLAGS_SIMD_CACHE),
837 .num_cu_shared = 2,
838 },
839 {
840 /* GL1 Data Cache per SA */
841 .cache_size = 128,
842 .cache_level = 1,
843 .cache_line_size = 128,
844 .flags = (CRAT_CACHE_FLAGS_ENABLED |
845 CRAT_CACHE_FLAGS_DATA_CACHE |
846 CRAT_CACHE_FLAGS_SIMD_CACHE),
847 .num_cu_shared = 6,
848 },
849 {
850 /* L2 Data Cache per GPU (Total Tex Cache) */
851 .cache_size = 2048,
852 .cache_level = 2,
853 .cache_line_size = 128,
854 .flags = (CRAT_CACHE_FLAGS_ENABLED |
855 CRAT_CACHE_FLAGS_DATA_CACHE |
856 CRAT_CACHE_FLAGS_SIMD_CACHE),
857 .num_cu_shared = 6,
858 },
859 };
860
861 static struct kfd_gpu_cache_info gfx1037_cache_info[] = {
862 {
863 /* TCP L1 Cache per CU */
864 .cache_size = 16,
865 .cache_level = 1,
866 .cache_line_size = 128,
867 .flags = (CRAT_CACHE_FLAGS_ENABLED |
868 CRAT_CACHE_FLAGS_DATA_CACHE |
869 CRAT_CACHE_FLAGS_SIMD_CACHE),
870 .num_cu_shared = 1,
871 },
872 {
873 /* Scalar L1 Instruction Cache per SQC */
874 .cache_size = 32,
875 .cache_level = 1,
876 .cache_line_size = 64,
877 .flags = (CRAT_CACHE_FLAGS_ENABLED |
878 CRAT_CACHE_FLAGS_INST_CACHE |
879 CRAT_CACHE_FLAGS_SIMD_CACHE),
880 .num_cu_shared = 2,
881 },
882 {
883 /* Scalar L1 Data Cache per SQC */
884 .cache_size = 16,
885 .cache_level = 1,
886 .cache_line_size = 64,
887 .flags = (CRAT_CACHE_FLAGS_ENABLED |
888 CRAT_CACHE_FLAGS_DATA_CACHE |
889 CRAT_CACHE_FLAGS_SIMD_CACHE),
890 .num_cu_shared = 2,
891 },
892 {
893 /* GL1 Data Cache per SA */
894 .cache_size = 128,
895 .cache_level = 1,
896 .cache_line_size = 128,
897 .flags = (CRAT_CACHE_FLAGS_ENABLED |
898 CRAT_CACHE_FLAGS_DATA_CACHE |
899 CRAT_CACHE_FLAGS_SIMD_CACHE),
900 .num_cu_shared = 2,
901 },
902 {
903 /* L2 Data Cache per GPU (Total Tex Cache) */
904 .cache_size = 256,
905 .cache_level = 2,
906 .cache_line_size = 128,
907 .flags = (CRAT_CACHE_FLAGS_ENABLED |
908 CRAT_CACHE_FLAGS_DATA_CACHE |
909 CRAT_CACHE_FLAGS_SIMD_CACHE),
910 .num_cu_shared = 2,
911 },
912 };
913
914 static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {
915 {
916 /* TCP L1 Cache per CU */
917 .cache_size = 16,
918 .cache_level = 1,
919 .cache_line_size = 128,
920 .flags = (CRAT_CACHE_FLAGS_ENABLED |
921 CRAT_CACHE_FLAGS_DATA_CACHE |
922 CRAT_CACHE_FLAGS_SIMD_CACHE),
923 .num_cu_shared = 1,
924 },
925 {
926 /* Scalar L1 Instruction Cache per SQC */
927 .cache_size = 32,
928 .cache_level = 1,
929 .cache_line_size = 64,
930 .flags = (CRAT_CACHE_FLAGS_ENABLED |
931 CRAT_CACHE_FLAGS_INST_CACHE |
932 CRAT_CACHE_FLAGS_SIMD_CACHE),
933 .num_cu_shared = 2,
934 },
935 {
936 /* Scalar L1 Data Cache per SQC */
937 .cache_size = 16,
938 .cache_level = 1,
939 .cache_line_size = 64,
940 .flags = (CRAT_CACHE_FLAGS_ENABLED |
941 CRAT_CACHE_FLAGS_DATA_CACHE |
942 CRAT_CACHE_FLAGS_SIMD_CACHE),
943 .num_cu_shared = 2,
944 },
945 {
946 /* GL1 Data Cache per SA */
947 .cache_size = 128,
948 .cache_level = 1,
949 .cache_line_size = 128,
950 .flags = (CRAT_CACHE_FLAGS_ENABLED |
951 CRAT_CACHE_FLAGS_DATA_CACHE |
952 CRAT_CACHE_FLAGS_SIMD_CACHE),
953 .num_cu_shared = 2,
954 },
955 {
956 /* L2 Data Cache per GPU (Total Tex Cache) */
957 .cache_size = 256,
958 .cache_level = 2,
959 .cache_line_size = 128,
960 .flags = (CRAT_CACHE_FLAGS_ENABLED |
961 CRAT_CACHE_FLAGS_DATA_CACHE |
962 CRAT_CACHE_FLAGS_SIMD_CACHE),
963 .num_cu_shared = 2,
964 },
965 };
966
967 static struct kfd_gpu_cache_info dummy_cache_info[] = {
968 {
969 /* TCP L1 Cache per CU */
970 .cache_size = 16,
971 .cache_level = 1,
972 .cache_line_size = 64,
973 .flags = (CRAT_CACHE_FLAGS_ENABLED |
974 CRAT_CACHE_FLAGS_DATA_CACHE |
975 CRAT_CACHE_FLAGS_SIMD_CACHE),
976 .num_cu_shared = 1,
977 },
978 {
979 /* Scalar L1 Instruction Cache per SQC */
980 .cache_size = 32,
981 .cache_level = 1,
982 .cache_line_size = 64,
983 .flags = (CRAT_CACHE_FLAGS_ENABLED |
984 CRAT_CACHE_FLAGS_INST_CACHE |
985 CRAT_CACHE_FLAGS_SIMD_CACHE),
986 .num_cu_shared = 2,
987 },
988 {
989 /* Scalar L1 Data Cache per SQC */
990 .cache_size = 16,
991 .cache_level = 1,
992 .cache_line_size = 64,
993 .flags = (CRAT_CACHE_FLAGS_ENABLED |
994 CRAT_CACHE_FLAGS_DATA_CACHE |
995 CRAT_CACHE_FLAGS_SIMD_CACHE),
996 .num_cu_shared = 2,
997 },
998 {
999 /* GL1 Data Cache per SA */
1000 .cache_size = 128,
1001 .cache_level = 1,
1002 .cache_line_size = 64,
1003 .flags = (CRAT_CACHE_FLAGS_ENABLED |
1004 CRAT_CACHE_FLAGS_DATA_CACHE |
1005 CRAT_CACHE_FLAGS_SIMD_CACHE),
1006 .num_cu_shared = 6,
1007 },
1008 {
1009 /* L2 Data Cache per GPU (Total Tex Cache) */
1010 .cache_size = 2048,
1011 .cache_level = 2,
1012 .cache_line_size = 64,
1013 .flags = (CRAT_CACHE_FLAGS_ENABLED |
1014 CRAT_CACHE_FLAGS_DATA_CACHE |
1015 CRAT_CACHE_FLAGS_SIMD_CACHE),
1016 .num_cu_shared = 6,
1017 },
1018 };
1019
kfd_populated_cu_info_cpu(struct kfd_topology_device * dev,struct crat_subtype_computeunit * cu)1020 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
1021 struct crat_subtype_computeunit *cu)
1022 {
1023 dev->node_props.cpu_cores_count = cu->num_cpu_cores;
1024 dev->node_props.cpu_core_id_base = cu->processor_id_low;
1025 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
1026 dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
1027
1028 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
1029 cu->processor_id_low);
1030 }
1031
kfd_populated_cu_info_gpu(struct kfd_topology_device * dev,struct crat_subtype_computeunit * cu)1032 static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
1033 struct crat_subtype_computeunit *cu)
1034 {
1035 dev->node_props.simd_id_base = cu->processor_id_low;
1036 dev->node_props.simd_count = cu->num_simd_cores;
1037 dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
1038 dev->node_props.max_waves_per_simd = cu->max_waves_simd;
1039 dev->node_props.wave_front_size = cu->wave_front_size;
1040 dev->node_props.array_count = cu->array_count;
1041 dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
1042 dev->node_props.simd_per_cu = cu->num_simd_per_cu;
1043 dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
1044 if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
1045 dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
1046 pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
1047 }
1048
1049 /* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
1050 * topology device present in the device_list
1051 */
kfd_parse_subtype_cu(struct crat_subtype_computeunit * cu,struct list_head * device_list)1052 static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
1053 struct list_head *device_list)
1054 {
1055 struct kfd_topology_device *dev;
1056
1057 pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
1058 cu->proximity_domain, cu->hsa_capability);
1059 list_for_each_entry(dev, device_list, list) {
1060 if (cu->proximity_domain == dev->proximity_domain) {
1061 if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
1062 kfd_populated_cu_info_cpu(dev, cu);
1063
1064 if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
1065 kfd_populated_cu_info_gpu(dev, cu);
1066 break;
1067 }
1068 }
1069
1070 return 0;
1071 }
1072
1073 static struct kfd_mem_properties *
find_subtype_mem(uint32_t heap_type,uint32_t flags,uint32_t width,struct kfd_topology_device * dev)1074 find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,
1075 struct kfd_topology_device *dev)
1076 {
1077 struct kfd_mem_properties *props;
1078
1079 list_for_each_entry(props, &dev->mem_props, list) {
1080 if (props->heap_type == heap_type
1081 && props->flags == flags
1082 && props->width == width)
1083 return props;
1084 }
1085
1086 return NULL;
1087 }
1088 /* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
1089 * topology device present in the device_list
1090 */
kfd_parse_subtype_mem(struct crat_subtype_memory * mem,struct list_head * device_list)1091 static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
1092 struct list_head *device_list)
1093 {
1094 struct kfd_mem_properties *props;
1095 struct kfd_topology_device *dev;
1096 uint32_t heap_type;
1097 uint64_t size_in_bytes;
1098 uint32_t flags = 0;
1099 uint32_t width;
1100
1101 pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
1102 mem->proximity_domain);
1103 list_for_each_entry(dev, device_list, list) {
1104 if (mem->proximity_domain == dev->proximity_domain) {
1105 /* We're on GPU node */
1106 if (dev->node_props.cpu_cores_count == 0) {
1107 /* APU */
1108 if (mem->visibility_type == 0)
1109 heap_type =
1110 HSA_MEM_HEAP_TYPE_FB_PRIVATE;
1111 /* dGPU */
1112 else
1113 heap_type = mem->visibility_type;
1114 } else
1115 heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
1116
1117 if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
1118 flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
1119 if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
1120 flags |= HSA_MEM_FLAGS_NON_VOLATILE;
1121
1122 size_in_bytes =
1123 ((uint64_t)mem->length_high << 32) +
1124 mem->length_low;
1125 width = mem->width;
1126
1127 /* Multiple banks of the same type are aggregated into
1128 * one. User mode doesn't care about multiple physical
1129 * memory segments. It's managed as a single virtual
1130 * heap for user mode.
1131 */
1132 props = find_subtype_mem(heap_type, flags, width, dev);
1133 if (props) {
1134 props->size_in_bytes += size_in_bytes;
1135 break;
1136 }
1137
1138 props = kfd_alloc_struct(props);
1139 if (!props)
1140 return -ENOMEM;
1141
1142 props->heap_type = heap_type;
1143 props->flags = flags;
1144 props->size_in_bytes = size_in_bytes;
1145 props->width = width;
1146
1147 dev->node_props.mem_banks_count++;
1148 list_add_tail(&props->list, &dev->mem_props);
1149
1150 break;
1151 }
1152 }
1153
1154 return 0;
1155 }
1156
1157 /* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
1158 * topology device present in the device_list
1159 */
kfd_parse_subtype_cache(struct crat_subtype_cache * cache,struct list_head * device_list)1160 static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
1161 struct list_head *device_list)
1162 {
1163 struct kfd_cache_properties *props;
1164 struct kfd_topology_device *dev;
1165 uint32_t id;
1166 uint32_t total_num_of_cu;
1167
1168 id = cache->processor_id_low;
1169
1170 pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
1171 list_for_each_entry(dev, device_list, list) {
1172 total_num_of_cu = (dev->node_props.array_count *
1173 dev->node_props.cu_per_simd_array);
1174
1175 /* Cache infomration in CRAT doesn't have proximity_domain
1176 * information as it is associated with a CPU core or GPU
1177 * Compute Unit. So map the cache using CPU core Id or SIMD
1178 * (GPU) ID.
1179 * TODO: This works because currently we can safely assume that
1180 * Compute Units are parsed before caches are parsed. In
1181 * future, remove this dependency
1182 */
1183 if ((id >= dev->node_props.cpu_core_id_base &&
1184 id <= dev->node_props.cpu_core_id_base +
1185 dev->node_props.cpu_cores_count) ||
1186 (id >= dev->node_props.simd_id_base &&
1187 id < dev->node_props.simd_id_base +
1188 total_num_of_cu)) {
1189 props = kfd_alloc_struct(props);
1190 if (!props)
1191 return -ENOMEM;
1192
1193 props->processor_id_low = id;
1194 props->cache_level = cache->cache_level;
1195 props->cache_size = cache->cache_size;
1196 props->cacheline_size = cache->cache_line_size;
1197 props->cachelines_per_tag = cache->lines_per_tag;
1198 props->cache_assoc = cache->associativity;
1199 props->cache_latency = cache->cache_latency;
1200
1201 memcpy(props->sibling_map, cache->sibling_map,
1202 CRAT_SIBLINGMAP_SIZE);
1203
1204 /* set the sibling_map_size as 32 for CRAT from ACPI */
1205 props->sibling_map_size = CRAT_SIBLINGMAP_SIZE;
1206
1207 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1208 props->cache_type |= HSA_CACHE_TYPE_DATA;
1209 if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
1210 props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1211 if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1212 props->cache_type |= HSA_CACHE_TYPE_CPU;
1213 if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1214 props->cache_type |= HSA_CACHE_TYPE_HSACU;
1215
1216 dev->node_props.caches_count++;
1217 list_add_tail(&props->list, &dev->cache_props);
1218
1219 break;
1220 }
1221 }
1222
1223 return 0;
1224 }
1225
1226 /* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
1227 * topology device present in the device_list
1228 */
kfd_parse_subtype_iolink(struct crat_subtype_iolink * iolink,struct list_head * device_list)1229 static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
1230 struct list_head *device_list)
1231 {
1232 struct kfd_iolink_properties *props = NULL, *props2;
1233 struct kfd_topology_device *dev, *to_dev;
1234 uint32_t id_from;
1235 uint32_t id_to;
1236
1237 id_from = iolink->proximity_domain_from;
1238 id_to = iolink->proximity_domain_to;
1239
1240 pr_debug("Found IO link entry in CRAT table with id_from=%d, id_to %d\n",
1241 id_from, id_to);
1242 list_for_each_entry(dev, device_list, list) {
1243 if (id_from == dev->proximity_domain) {
1244 props = kfd_alloc_struct(props);
1245 if (!props)
1246 return -ENOMEM;
1247
1248 props->node_from = id_from;
1249 props->node_to = id_to;
1250 props->ver_maj = iolink->version_major;
1251 props->ver_min = iolink->version_minor;
1252 props->iolink_type = iolink->io_interface_type;
1253
1254 if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
1255 props->weight = 20;
1256 else if (props->iolink_type == CRAT_IOLINK_TYPE_XGMI)
1257 props->weight = iolink->weight_xgmi;
1258 else
1259 props->weight = node_distance(id_from, id_to);
1260
1261 props->min_latency = iolink->minimum_latency;
1262 props->max_latency = iolink->maximum_latency;
1263 props->min_bandwidth = iolink->minimum_bandwidth_mbs;
1264 props->max_bandwidth = iolink->maximum_bandwidth_mbs;
1265 props->rec_transfer_size =
1266 iolink->recommended_transfer_size;
1267
1268 dev->node_props.io_links_count++;
1269 list_add_tail(&props->list, &dev->io_link_props);
1270 break;
1271 }
1272 }
1273
1274 /* CPU topology is created before GPUs are detected, so CPU->GPU
1275 * links are not built at that time. If a PCIe type is discovered, it
1276 * means a GPU is detected and we are adding GPU->CPU to the topology.
1277 * At this time, also add the corresponded CPU->GPU link if GPU
1278 * is large bar.
1279 * For xGMI, we only added the link with one direction in the crat
1280 * table, add corresponded reversed direction link now.
1281 */
1282 if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) {
1283 to_dev = kfd_topology_device_by_proximity_domain_no_lock(id_to);
1284 if (!to_dev)
1285 return -ENODEV;
1286 /* same everything but the other direction */
1287 props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
1288 if (!props2)
1289 return -ENOMEM;
1290
1291 props2->node_from = id_to;
1292 props2->node_to = id_from;
1293 props2->kobj = NULL;
1294 to_dev->node_props.io_links_count++;
1295 list_add_tail(&props2->list, &to_dev->io_link_props);
1296 }
1297
1298 return 0;
1299 }
1300
1301 /* kfd_parse_subtype - parse subtypes and attach it to correct topology device
1302 * present in the device_list
1303 * @sub_type_hdr - subtype section of crat_image
1304 * @device_list - list of topology devices present in this crat_image
1305 */
kfd_parse_subtype(struct crat_subtype_generic * sub_type_hdr,struct list_head * device_list)1306 static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
1307 struct list_head *device_list)
1308 {
1309 struct crat_subtype_computeunit *cu;
1310 struct crat_subtype_memory *mem;
1311 struct crat_subtype_cache *cache;
1312 struct crat_subtype_iolink *iolink;
1313 int ret = 0;
1314
1315 switch (sub_type_hdr->type) {
1316 case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
1317 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
1318 ret = kfd_parse_subtype_cu(cu, device_list);
1319 break;
1320 case CRAT_SUBTYPE_MEMORY_AFFINITY:
1321 mem = (struct crat_subtype_memory *)sub_type_hdr;
1322 ret = kfd_parse_subtype_mem(mem, device_list);
1323 break;
1324 case CRAT_SUBTYPE_CACHE_AFFINITY:
1325 cache = (struct crat_subtype_cache *)sub_type_hdr;
1326 ret = kfd_parse_subtype_cache(cache, device_list);
1327 break;
1328 case CRAT_SUBTYPE_TLB_AFFINITY:
1329 /*
1330 * For now, nothing to do here
1331 */
1332 pr_debug("Found TLB entry in CRAT table (not processing)\n");
1333 break;
1334 case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
1335 /*
1336 * For now, nothing to do here
1337 */
1338 pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
1339 break;
1340 case CRAT_SUBTYPE_IOLINK_AFFINITY:
1341 iolink = (struct crat_subtype_iolink *)sub_type_hdr;
1342 ret = kfd_parse_subtype_iolink(iolink, device_list);
1343 break;
1344 default:
1345 pr_warn("Unknown subtype %d in CRAT\n",
1346 sub_type_hdr->type);
1347 }
1348
1349 return ret;
1350 }
1351
1352 /* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
1353 * create a kfd_topology_device and add in to device_list. Also parse
1354 * CRAT subtypes and attach it to appropriate kfd_topology_device
1355 * @crat_image - input image containing CRAT
1356 * @device_list - [OUT] list of kfd_topology_device generated after
1357 * parsing crat_image
1358 * @proximity_domain - Proximity domain of the first device in the table
1359 *
1360 * Return - 0 if successful else -ve value
1361 */
kfd_parse_crat_table(void * crat_image,struct list_head * device_list,uint32_t proximity_domain)1362 int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
1363 uint32_t proximity_domain)
1364 {
1365 struct kfd_topology_device *top_dev = NULL;
1366 struct crat_subtype_generic *sub_type_hdr;
1367 uint16_t node_id;
1368 int ret = 0;
1369 struct crat_header *crat_table = (struct crat_header *)crat_image;
1370 uint16_t num_nodes;
1371 uint32_t image_len;
1372
1373 if (!crat_image)
1374 return -EINVAL;
1375
1376 if (!list_empty(device_list)) {
1377 pr_warn("Error device list should be empty\n");
1378 return -EINVAL;
1379 }
1380
1381 num_nodes = crat_table->num_domains;
1382 image_len = crat_table->length;
1383
1384 pr_debug("Parsing CRAT table with %d nodes\n", num_nodes);
1385
1386 for (node_id = 0; node_id < num_nodes; node_id++) {
1387 top_dev = kfd_create_topology_device(device_list);
1388 if (!top_dev)
1389 break;
1390 top_dev->proximity_domain = proximity_domain++;
1391 }
1392
1393 if (!top_dev) {
1394 ret = -ENOMEM;
1395 goto err;
1396 }
1397
1398 memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
1399 memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
1400 CRAT_OEMTABLEID_LENGTH);
1401 top_dev->oem_revision = crat_table->oem_revision;
1402
1403 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
1404 while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
1405 ((char *)crat_image) + image_len) {
1406 if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
1407 ret = kfd_parse_subtype(sub_type_hdr, device_list);
1408 if (ret)
1409 break;
1410 }
1411
1412 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1413 sub_type_hdr->length);
1414 }
1415
1416 err:
1417 if (ret)
1418 kfd_release_topology_device_list(device_list);
1419
1420 return ret;
1421 }
1422
1423
kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev * kdev,bool cache_line_size_missing,struct kfd_gpu_cache_info * pcache_info)1424 static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
1425 bool cache_line_size_missing,
1426 struct kfd_gpu_cache_info *pcache_info)
1427 {
1428 struct amdgpu_device *adev = kdev->adev;
1429 int i = 0;
1430
1431 /* TCP L1 Cache per CU */
1432 if (adev->gfx.config.gc_tcp_l1_size) {
1433 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size;
1434 pcache_info[i].cache_level = 1;
1435 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1436 CRAT_CACHE_FLAGS_DATA_CACHE |
1437 CRAT_CACHE_FLAGS_SIMD_CACHE);
1438 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
1439 pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;
1440 if (cache_line_size_missing && !pcache_info[i].cache_line_size)
1441 pcache_info[i].cache_line_size = 128;
1442 i++;
1443 }
1444 /* Scalar L1 Instruction Cache per SQC */
1445 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
1446 pcache_info[i].cache_size =
1447 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1448 pcache_info[i].cache_level = 1;
1449 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1450 CRAT_CACHE_FLAGS_INST_CACHE |
1451 CRAT_CACHE_FLAGS_SIMD_CACHE);
1452 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1453 pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;
1454 if (cache_line_size_missing && !pcache_info[i].cache_line_size)
1455 pcache_info[i].cache_line_size = 128;
1456 i++;
1457 }
1458 /* Scalar L1 Data Cache per SQC */
1459 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
1460 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1461 pcache_info[i].cache_level = 1;
1462 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1463 CRAT_CACHE_FLAGS_DATA_CACHE |
1464 CRAT_CACHE_FLAGS_SIMD_CACHE);
1465 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1466 pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;
1467 if (cache_line_size_missing && !pcache_info[i].cache_line_size)
1468 pcache_info[i].cache_line_size = 64;
1469 i++;
1470 }
1471 /* GL1 Data Cache per SA */
1472 if (adev->gfx.config.gc_gl1c_per_sa &&
1473 adev->gfx.config.gc_gl1c_size_per_instance) {
1474 pcache_info[i].cache_size = adev->gfx.config.gc_gl1c_per_sa *
1475 adev->gfx.config.gc_gl1c_size_per_instance;
1476 pcache_info[i].cache_level = 1;
1477 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1478 CRAT_CACHE_FLAGS_DATA_CACHE |
1479 CRAT_CACHE_FLAGS_SIMD_CACHE);
1480 pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1481 if (cache_line_size_missing)
1482 pcache_info[i].cache_line_size = 128;
1483 i++;
1484 }
1485 /* L2 Data Cache per GPU (Total Tex Cache) */
1486 if (adev->gfx.config.gc_gl2c_per_gpu) {
1487 pcache_info[i].cache_size = adev->gfx.config.gc_gl2c_per_gpu;
1488 pcache_info[i].cache_level = 2;
1489 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1490 CRAT_CACHE_FLAGS_DATA_CACHE |
1491 CRAT_CACHE_FLAGS_SIMD_CACHE);
1492 pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1493 pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;
1494 if (cache_line_size_missing && !pcache_info[i].cache_line_size)
1495 pcache_info[i].cache_line_size = 128;
1496 i++;
1497 }
1498 /* L3 Data Cache per GPU */
1499 if (adev->gmc.mall_size) {
1500 pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
1501 pcache_info[i].cache_level = 3;
1502 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1503 CRAT_CACHE_FLAGS_DATA_CACHE |
1504 CRAT_CACHE_FLAGS_SIMD_CACHE);
1505 pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1506 pcache_info[i].cache_line_size = 64;
1507 i++;
1508 }
1509 return i;
1510 }
1511
kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev * kdev,struct kfd_gpu_cache_info * pcache_info)1512 static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
1513 struct kfd_gpu_cache_info *pcache_info)
1514 {
1515 struct amdgpu_device *adev = kdev->adev;
1516 int i = 0;
1517
1518 /* TCP L1 Cache per CU */
1519 if (adev->gfx.config.gc_tcp_size_per_cu) {
1520 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_size_per_cu;
1521 pcache_info[i].cache_level = 1;
1522 /* Cacheline size not available in IP discovery for gc943,gc944 */
1523 pcache_info[i].cache_line_size = 128;
1524 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1525 CRAT_CACHE_FLAGS_DATA_CACHE |
1526 CRAT_CACHE_FLAGS_SIMD_CACHE);
1527 pcache_info[i].num_cu_shared = 1;
1528 i++;
1529 }
1530 /* Scalar L1 Instruction Cache per SQC */
1531 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
1532 pcache_info[i].cache_size =
1533 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1534 pcache_info[i].cache_level = 1;
1535 pcache_info[i].cache_line_size = 64;
1536 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1537 CRAT_CACHE_FLAGS_INST_CACHE |
1538 CRAT_CACHE_FLAGS_SIMD_CACHE);
1539 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
1540 i++;
1541 }
1542 /* Scalar L1 Data Cache per SQC */
1543 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
1544 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1545 pcache_info[i].cache_level = 1;
1546 pcache_info[i].cache_line_size = 64;
1547 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1548 CRAT_CACHE_FLAGS_DATA_CACHE |
1549 CRAT_CACHE_FLAGS_SIMD_CACHE);
1550 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
1551 i++;
1552 }
1553 /* L2 Data Cache per GPU (Total Tex Cache) */
1554 if (adev->gfx.config.gc_tcc_size) {
1555 pcache_info[i].cache_size = adev->gfx.config.gc_tcc_size;
1556 pcache_info[i].cache_level = 2;
1557 pcache_info[i].cache_line_size = 128;
1558 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1559 CRAT_CACHE_FLAGS_DATA_CACHE |
1560 CRAT_CACHE_FLAGS_SIMD_CACHE);
1561 pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1562 i++;
1563 }
1564 /* L3 Data Cache per GPU */
1565 if (adev->gmc.mall_size) {
1566 pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
1567 pcache_info[i].cache_level = 3;
1568 pcache_info[i].cache_line_size = 64;
1569 pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1570 CRAT_CACHE_FLAGS_DATA_CACHE |
1571 CRAT_CACHE_FLAGS_SIMD_CACHE);
1572 pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1573 i++;
1574 }
1575 return i;
1576 }
1577
kfd_get_gpu_cache_info(struct kfd_node * kdev,struct kfd_gpu_cache_info ** pcache_info)1578 int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)
1579 {
1580 int num_of_cache_types = 0;
1581 bool cache_line_size_missing = false;
1582
1583 switch (kdev->adev->asic_type) {
1584 case CHIP_KAVERI:
1585 *pcache_info = kaveri_cache_info;
1586 num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
1587 break;
1588 case CHIP_HAWAII:
1589 *pcache_info = hawaii_cache_info;
1590 num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
1591 break;
1592 case CHIP_CARRIZO:
1593 *pcache_info = carrizo_cache_info;
1594 num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
1595 break;
1596 case CHIP_TONGA:
1597 *pcache_info = tonga_cache_info;
1598 num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
1599 break;
1600 case CHIP_FIJI:
1601 *pcache_info = fiji_cache_info;
1602 num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
1603 break;
1604 case CHIP_POLARIS10:
1605 *pcache_info = polaris10_cache_info;
1606 num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
1607 break;
1608 case CHIP_POLARIS11:
1609 *pcache_info = polaris11_cache_info;
1610 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
1611 break;
1612 case CHIP_POLARIS12:
1613 *pcache_info = polaris12_cache_info;
1614 num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);
1615 break;
1616 case CHIP_VEGAM:
1617 *pcache_info = vegam_cache_info;
1618 num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
1619 break;
1620 default:
1621 switch (KFD_GC_VERSION(kdev)) {
1622 case IP_VERSION(9, 0, 1):
1623 *pcache_info = vega10_cache_info;
1624 num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
1625 break;
1626 case IP_VERSION(9, 2, 1):
1627 *pcache_info = vega12_cache_info;
1628 num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
1629 break;
1630 case IP_VERSION(9, 4, 0):
1631 case IP_VERSION(9, 4, 1):
1632 *pcache_info = vega20_cache_info;
1633 num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
1634 break;
1635 case IP_VERSION(9, 4, 2):
1636 *pcache_info = aldebaran_cache_info;
1637 num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
1638 break;
1639 case IP_VERSION(9, 4, 3):
1640 case IP_VERSION(9, 4, 4):
1641 num_of_cache_types =
1642 kfd_fill_gpu_cache_info_from_gfx_config_v2(kdev->kfd,
1643 *pcache_info);
1644 break;
1645 case IP_VERSION(9, 1, 0):
1646 case IP_VERSION(9, 2, 2):
1647 *pcache_info = raven_cache_info;
1648 num_of_cache_types = ARRAY_SIZE(raven_cache_info);
1649 break;
1650 case IP_VERSION(9, 3, 0):
1651 *pcache_info = renoir_cache_info;
1652 num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
1653 break;
1654 case IP_VERSION(10, 1, 10):
1655 case IP_VERSION(10, 1, 2):
1656 case IP_VERSION(10, 1, 3):
1657 case IP_VERSION(10, 1, 4):
1658 *pcache_info = navi10_cache_info;
1659 num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
1660 break;
1661 case IP_VERSION(10, 1, 1):
1662 *pcache_info = navi14_cache_info;
1663 num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
1664 break;
1665 case IP_VERSION(10, 3, 0):
1666 *pcache_info = sienna_cichlid_cache_info;
1667 num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
1668 break;
1669 case IP_VERSION(10, 3, 2):
1670 *pcache_info = navy_flounder_cache_info;
1671 num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
1672 break;
1673 case IP_VERSION(10, 3, 4):
1674 *pcache_info = dimgrey_cavefish_cache_info;
1675 num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
1676 break;
1677 case IP_VERSION(10, 3, 1):
1678 *pcache_info = vangogh_cache_info;
1679 num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
1680 break;
1681 case IP_VERSION(10, 3, 5):
1682 *pcache_info = beige_goby_cache_info;
1683 num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
1684 break;
1685 case IP_VERSION(10, 3, 3):
1686 *pcache_info = yellow_carp_cache_info;
1687 num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
1688 break;
1689 case IP_VERSION(10, 3, 6):
1690 *pcache_info = gc_10_3_6_cache_info;
1691 num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);
1692 break;
1693 case IP_VERSION(10, 3, 7):
1694 *pcache_info = gfx1037_cache_info;
1695 num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);
1696 break;
1697 case IP_VERSION(11, 0, 0):
1698 case IP_VERSION(11, 0, 1):
1699 case IP_VERSION(11, 0, 2):
1700 case IP_VERSION(11, 0, 3):
1701 case IP_VERSION(11, 0, 4):
1702 case IP_VERSION(11, 5, 0):
1703 case IP_VERSION(11, 5, 1):
1704 case IP_VERSION(11, 5, 2):
1705 /* Cacheline size not available in IP discovery for gc11.
1706 * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
1707 */
1708 cache_line_size_missing = true;
1709 fallthrough;
1710 case IP_VERSION(12, 0, 0):
1711 case IP_VERSION(12, 0, 1):
1712 num_of_cache_types =
1713 kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd,
1714 cache_line_size_missing,
1715 *pcache_info);
1716 break;
1717 default:
1718 *pcache_info = dummy_cache_info;
1719 num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
1720 pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
1721 break;
1722 }
1723 }
1724 return num_of_cache_types;
1725 }
1726
1727 /* Memory required to create Virtual CRAT.
1728 * Since there is no easy way to predict the amount of memory required, the
1729 * following amount is allocated for GPU Virtual CRAT. This is
1730 * expected to cover all known conditions. But to be safe additional check
1731 * is put in the code to ensure we don't overwrite.
1732 */
1733 #define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE)
1734
1735 /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
1736 *
1737 * @numa_node_id: CPU NUMA node id
1738 * @avail_size: Available size in the memory
1739 * @sub_type_hdr: Memory into which compute info will be filled in
1740 *
1741 * Return 0 if successful else return -ve value
1742 */
kfd_fill_cu_for_cpu(int numa_node_id,int * avail_size,int proximity_domain,struct crat_subtype_computeunit * sub_type_hdr)1743 static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
1744 int proximity_domain,
1745 struct crat_subtype_computeunit *sub_type_hdr)
1746 {
1747 const struct cpumask *cpumask;
1748
1749 *avail_size -= sizeof(struct crat_subtype_computeunit);
1750 if (*avail_size < 0)
1751 return -ENOMEM;
1752
1753 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
1754
1755 /* Fill in subtype header data */
1756 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
1757 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
1758 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1759
1760 cpumask = cpumask_of_node(numa_node_id);
1761
1762 /* Fill in CU data */
1763 sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
1764 sub_type_hdr->proximity_domain = proximity_domain;
1765 sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
1766 if (sub_type_hdr->processor_id_low == -1)
1767 return -EINVAL;
1768
1769 sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
1770
1771 return 0;
1772 }
1773
1774 /* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
1775 *
1776 * @numa_node_id: CPU NUMA node id
1777 * @avail_size: Available size in the memory
1778 * @sub_type_hdr: Memory into which compute info will be filled in
1779 *
1780 * Return 0 if successful else return -ve value
1781 */
kfd_fill_mem_info_for_cpu(int numa_node_id,int * avail_size,int proximity_domain,struct crat_subtype_memory * sub_type_hdr)1782 static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
1783 int proximity_domain,
1784 struct crat_subtype_memory *sub_type_hdr)
1785 {
1786 uint64_t mem_in_bytes = 0;
1787 pg_data_t *pgdat;
1788 int zone_type;
1789
1790 *avail_size -= sizeof(struct crat_subtype_memory);
1791 if (*avail_size < 0)
1792 return -ENOMEM;
1793
1794 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1795
1796 /* Fill in subtype header data */
1797 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1798 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1799 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1800
1801 /* Fill in Memory Subunit data */
1802
1803 /* Unlike si_meminfo, si_meminfo_node is not exported. So
1804 * the following lines are duplicated from si_meminfo_node
1805 * function
1806 */
1807 pgdat = NODE_DATA(numa_node_id);
1808 for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
1809 mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]);
1810 mem_in_bytes <<= PAGE_SHIFT;
1811
1812 sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
1813 sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
1814 sub_type_hdr->proximity_domain = proximity_domain;
1815
1816 return 0;
1817 }
1818
1819 #ifdef CONFIG_X86_64
kfd_fill_iolink_info_for_cpu(int numa_node_id,int * avail_size,uint32_t * num_entries,struct crat_subtype_iolink * sub_type_hdr)1820 static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
1821 uint32_t *num_entries,
1822 struct crat_subtype_iolink *sub_type_hdr)
1823 {
1824 int nid;
1825 struct cpuinfo_x86 *c = &cpu_data(0);
1826 uint8_t link_type;
1827
1828 if (c->x86_vendor == X86_VENDOR_AMD)
1829 link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
1830 else
1831 link_type = CRAT_IOLINK_TYPE_QPI_1_1;
1832
1833 *num_entries = 0;
1834
1835 /* Create IO links from this node to other CPU nodes */
1836 for_each_online_node(nid) {
1837 if (nid == numa_node_id) /* node itself */
1838 continue;
1839
1840 *avail_size -= sizeof(struct crat_subtype_iolink);
1841 if (*avail_size < 0)
1842 return -ENOMEM;
1843
1844 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1845
1846 /* Fill in subtype header data */
1847 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1848 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1849 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1850
1851 /* Fill in IO link data */
1852 sub_type_hdr->proximity_domain_from = numa_node_id;
1853 sub_type_hdr->proximity_domain_to = nid;
1854 sub_type_hdr->io_interface_type = link_type;
1855
1856 (*num_entries)++;
1857 sub_type_hdr++;
1858 }
1859
1860 return 0;
1861 }
1862 #endif
1863
1864 /* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
1865 *
1866 * @pcrat_image: Fill in VCRAT for CPU
1867 * @size: [IN] allocated size of crat_image.
1868 * [OUT] actual size of data filled in crat_image
1869 */
kfd_create_vcrat_image_cpu(void * pcrat_image,size_t * size)1870 static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
1871 {
1872 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
1873 struct acpi_table_header *acpi_table;
1874 acpi_status status;
1875 struct crat_subtype_generic *sub_type_hdr;
1876 int avail_size = *size;
1877 int numa_node_id;
1878 #ifdef CONFIG_X86_64
1879 uint32_t entries = 0;
1880 #endif
1881 int ret = 0;
1882
1883 if (!pcrat_image)
1884 return -EINVAL;
1885
1886 /* Fill in CRAT Header.
1887 * Modify length and total_entries as subunits are added.
1888 */
1889 avail_size -= sizeof(struct crat_header);
1890 if (avail_size < 0)
1891 return -ENOMEM;
1892
1893 memset(crat_table, 0, sizeof(struct crat_header));
1894 memcpy(&crat_table->signature, CRAT_SIGNATURE,
1895 sizeof(crat_table->signature));
1896 crat_table->length = sizeof(struct crat_header);
1897
1898 status = acpi_get_table("DSDT", 0, &acpi_table);
1899 if (status != AE_OK)
1900 pr_warn("DSDT table not found for OEM information\n");
1901 else {
1902 crat_table->oem_revision = acpi_table->revision;
1903 memcpy(crat_table->oem_id, acpi_table->oem_id,
1904 CRAT_OEMID_LENGTH);
1905 memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
1906 CRAT_OEMTABLEID_LENGTH);
1907 acpi_put_table(acpi_table);
1908 }
1909 crat_table->total_entries = 0;
1910 crat_table->num_domains = 0;
1911
1912 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
1913
1914 for_each_online_node(numa_node_id) {
1915 if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
1916 continue;
1917
1918 /* Fill in Subtype: Compute Unit */
1919 ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
1920 crat_table->num_domains,
1921 (struct crat_subtype_computeunit *)sub_type_hdr);
1922 if (ret < 0)
1923 return ret;
1924 crat_table->length += sub_type_hdr->length;
1925 crat_table->total_entries++;
1926
1927 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1928 sub_type_hdr->length);
1929
1930 /* Fill in Subtype: Memory */
1931 ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
1932 crat_table->num_domains,
1933 (struct crat_subtype_memory *)sub_type_hdr);
1934 if (ret < 0)
1935 return ret;
1936 crat_table->length += sub_type_hdr->length;
1937 crat_table->total_entries++;
1938
1939 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1940 sub_type_hdr->length);
1941
1942 /* Fill in Subtype: IO Link */
1943 #ifdef CONFIG_X86_64
1944 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
1945 &entries,
1946 (struct crat_subtype_iolink *)sub_type_hdr);
1947 if (ret < 0)
1948 return ret;
1949
1950 if (entries) {
1951 crat_table->length += (sub_type_hdr->length * entries);
1952 crat_table->total_entries += entries;
1953
1954 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1955 sub_type_hdr->length * entries);
1956 }
1957 #else
1958 pr_info("IO link not available for non x86 platforms\n");
1959 #endif
1960
1961 crat_table->num_domains++;
1962 }
1963
1964 /* TODO: Add cache Subtype for CPU.
1965 * Currently, CPU cache information is available in function
1966 * detect_cache_attributes(cpu) defined in the file
1967 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
1968 * exported and to get the same information the code needs to be
1969 * duplicated.
1970 */
1971
1972 *size = crat_table->length;
1973 pr_info("Virtual CRAT table created for CPU\n");
1974
1975 return 0;
1976 }
1977
kfd_fill_gpu_memory_affinity(int * avail_size,struct kfd_node * kdev,uint8_t type,uint64_t size,struct crat_subtype_memory * sub_type_hdr,uint32_t proximity_domain,const struct kfd_local_mem_info * local_mem_info)1978 static int kfd_fill_gpu_memory_affinity(int *avail_size,
1979 struct kfd_node *kdev, uint8_t type, uint64_t size,
1980 struct crat_subtype_memory *sub_type_hdr,
1981 uint32_t proximity_domain,
1982 const struct kfd_local_mem_info *local_mem_info)
1983 {
1984 *avail_size -= sizeof(struct crat_subtype_memory);
1985 if (*avail_size < 0)
1986 return -ENOMEM;
1987
1988 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1989 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1990 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1991 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1992
1993 sub_type_hdr->proximity_domain = proximity_domain;
1994
1995 pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
1996 type, size);
1997
1998 sub_type_hdr->length_low = lower_32_bits(size);
1999 sub_type_hdr->length_high = upper_32_bits(size);
2000
2001 sub_type_hdr->width = local_mem_info->vram_width;
2002 sub_type_hdr->visibility_type = type;
2003
2004 return 0;
2005 }
2006
2007 #ifdef CONFIG_ACPI_NUMA
kfd_find_numa_node_in_srat(struct kfd_node * kdev)2008 static void kfd_find_numa_node_in_srat(struct kfd_node *kdev)
2009 {
2010 struct acpi_table_header *table_header = NULL;
2011 struct acpi_subtable_header *sub_header = NULL;
2012 unsigned long table_end, subtable_len;
2013 u32 pci_id = pci_domain_nr(kdev->adev->pdev->bus) << 16 |
2014 pci_dev_id(kdev->adev->pdev);
2015 u32 bdf;
2016 acpi_status status;
2017 struct acpi_srat_cpu_affinity *cpu;
2018 struct acpi_srat_generic_affinity *gpu;
2019 int pxm = 0, max_pxm = 0;
2020 int numa_node = NUMA_NO_NODE;
2021 bool found = false;
2022
2023 /* Fetch the SRAT table from ACPI */
2024 status = acpi_get_table(ACPI_SIG_SRAT, 0, &table_header);
2025 if (status == AE_NOT_FOUND) {
2026 pr_warn("SRAT table not found\n");
2027 return;
2028 } else if (ACPI_FAILURE(status)) {
2029 const char *err = acpi_format_exception(status);
2030 pr_err("SRAT table error: %s\n", err);
2031 return;
2032 }
2033
2034 table_end = (unsigned long)table_header + table_header->length;
2035
2036 /* Parse all entries looking for a match. */
2037 sub_header = (struct acpi_subtable_header *)
2038 ((unsigned long)table_header +
2039 sizeof(struct acpi_table_srat));
2040 subtable_len = sub_header->length;
2041
2042 while (((unsigned long)sub_header) + subtable_len < table_end) {
2043 /*
2044 * If length is 0, break from this loop to avoid
2045 * infinite loop.
2046 */
2047 if (subtable_len == 0) {
2048 pr_err("SRAT invalid zero length\n");
2049 break;
2050 }
2051
2052 switch (sub_header->type) {
2053 case ACPI_SRAT_TYPE_CPU_AFFINITY:
2054 cpu = (struct acpi_srat_cpu_affinity *)sub_header;
2055 pxm = *((u32 *)cpu->proximity_domain_hi) << 8 |
2056 cpu->proximity_domain_lo;
2057 if (pxm > max_pxm)
2058 max_pxm = pxm;
2059 break;
2060 case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
2061 gpu = (struct acpi_srat_generic_affinity *)sub_header;
2062 bdf = *((u16 *)(&gpu->device_handle[0])) << 16 |
2063 *((u16 *)(&gpu->device_handle[2]));
2064 if (bdf == pci_id) {
2065 found = true;
2066 numa_node = pxm_to_node(gpu->proximity_domain);
2067 }
2068 break;
2069 default:
2070 break;
2071 }
2072
2073 if (found)
2074 break;
2075
2076 sub_header = (struct acpi_subtable_header *)
2077 ((unsigned long)sub_header + subtable_len);
2078 subtable_len = sub_header->length;
2079 }
2080
2081 acpi_put_table(table_header);
2082
2083 /* Workaround bad cpu-gpu binding case */
2084 if (found && (numa_node < 0 ||
2085 numa_node > pxm_to_node(max_pxm)))
2086 numa_node = 0;
2087
2088 if (numa_node != NUMA_NO_NODE)
2089 set_dev_node(&kdev->adev->pdev->dev, numa_node);
2090 }
2091 #endif
2092
2093 #define KFD_CRAT_INTRA_SOCKET_WEIGHT 13
2094 #define KFD_CRAT_XGMI_WEIGHT 15
2095
2096 /* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
2097 * to its NUMA node
2098 * @avail_size: Available size in the memory
2099 * @kdev - [IN] GPU device
2100 * @sub_type_hdr: Memory into which io link info will be filled in
2101 * @proximity_domain - proximity domain of the GPU node
2102 *
2103 * Return 0 if successful else return -ve value
2104 */
kfd_fill_gpu_direct_io_link_to_cpu(int * avail_size,struct kfd_node * kdev,struct crat_subtype_iolink * sub_type_hdr,uint32_t proximity_domain)2105 static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
2106 struct kfd_node *kdev,
2107 struct crat_subtype_iolink *sub_type_hdr,
2108 uint32_t proximity_domain)
2109 {
2110 *avail_size -= sizeof(struct crat_subtype_iolink);
2111 if (*avail_size < 0)
2112 return -ENOMEM;
2113
2114 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
2115
2116 /* Fill in subtype header data */
2117 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
2118 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
2119 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
2120 if (kfd_dev_is_large_bar(kdev))
2121 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2122
2123 /* Fill in IOLINK subtype.
2124 * TODO: Fill-in other fields of iolink subtype
2125 */
2126 if (kdev->adev->gmc.xgmi.connected_to_cpu ||
2127 (KFD_GC_VERSION(kdev) == IP_VERSION(9, 4, 3) &&
2128 kdev->adev->smuio.funcs->get_pkg_type(kdev->adev) ==
2129 AMDGPU_PKG_TYPE_APU)) {
2130 bool ext_cpu = KFD_GC_VERSION(kdev) != IP_VERSION(9, 4, 3);
2131 int mem_bw = 819200, weight = ext_cpu ? KFD_CRAT_XGMI_WEIGHT :
2132 KFD_CRAT_INTRA_SOCKET_WEIGHT;
2133 uint32_t bandwidth = ext_cpu ? amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
2134 kdev->adev, NULL, true) : mem_bw;
2135
2136 /*
2137 * with host gpu xgmi link, host can access gpu memory whether
2138 * or not pcie bar type is large, so always create bidirectional
2139 * io link.
2140 */
2141 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2142 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
2143 sub_type_hdr->weight_xgmi = weight;
2144 sub_type_hdr->minimum_bandwidth_mbs = bandwidth;
2145 sub_type_hdr->maximum_bandwidth_mbs = bandwidth;
2146 } else {
2147 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
2148 sub_type_hdr->minimum_bandwidth_mbs =
2149 amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, true);
2150 sub_type_hdr->maximum_bandwidth_mbs =
2151 amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, false);
2152 }
2153
2154 sub_type_hdr->proximity_domain_from = proximity_domain;
2155
2156 #ifdef CONFIG_ACPI_NUMA
2157 if (kdev->adev->pdev->dev.numa_node == NUMA_NO_NODE &&
2158 num_possible_nodes() > 1)
2159 kfd_find_numa_node_in_srat(kdev);
2160 #endif
2161 #ifdef CONFIG_NUMA
2162 if (kdev->adev->pdev->dev.numa_node == NUMA_NO_NODE)
2163 sub_type_hdr->proximity_domain_to = 0;
2164 else
2165 sub_type_hdr->proximity_domain_to = kdev->adev->pdev->dev.numa_node;
2166 #else
2167 sub_type_hdr->proximity_domain_to = 0;
2168 #endif
2169 return 0;
2170 }
2171
kfd_fill_gpu_xgmi_link_to_gpu(int * avail_size,struct kfd_node * kdev,struct kfd_node * peer_kdev,struct crat_subtype_iolink * sub_type_hdr,uint32_t proximity_domain_from,uint32_t proximity_domain_to)2172 static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,
2173 struct kfd_node *kdev,
2174 struct kfd_node *peer_kdev,
2175 struct crat_subtype_iolink *sub_type_hdr,
2176 uint32_t proximity_domain_from,
2177 uint32_t proximity_domain_to)
2178 {
2179 bool use_ta_info = kdev->kfd->num_nodes == 1;
2180
2181 *avail_size -= sizeof(struct crat_subtype_iolink);
2182 if (*avail_size < 0)
2183 return -ENOMEM;
2184
2185 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
2186
2187 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
2188 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
2189 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED |
2190 CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2191
2192 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
2193 sub_type_hdr->proximity_domain_from = proximity_domain_from;
2194 sub_type_hdr->proximity_domain_to = proximity_domain_to;
2195
2196 if (use_ta_info) {
2197 sub_type_hdr->weight_xgmi = KFD_CRAT_XGMI_WEIGHT *
2198 amdgpu_amdkfd_get_xgmi_hops_count(kdev->adev, peer_kdev->adev);
2199 sub_type_hdr->maximum_bandwidth_mbs =
2200 amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->adev,
2201 peer_kdev->adev, false);
2202 sub_type_hdr->minimum_bandwidth_mbs = sub_type_hdr->maximum_bandwidth_mbs ?
2203 amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->adev, NULL, true) : 0;
2204 } else {
2205 bool is_single_hop = kdev->kfd == peer_kdev->kfd;
2206 int weight = is_single_hop ? KFD_CRAT_INTRA_SOCKET_WEIGHT :
2207 (2 * KFD_CRAT_INTRA_SOCKET_WEIGHT) + KFD_CRAT_XGMI_WEIGHT;
2208 int mem_bw = 819200;
2209
2210 sub_type_hdr->weight_xgmi = weight;
2211 sub_type_hdr->maximum_bandwidth_mbs = is_single_hop ? mem_bw : 0;
2212 sub_type_hdr->minimum_bandwidth_mbs = is_single_hop ? mem_bw : 0;
2213 }
2214
2215 return 0;
2216 }
2217
2218 /* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
2219 *
2220 * @pcrat_image: Fill in VCRAT for GPU
2221 * @size: [IN] allocated size of crat_image.
2222 * [OUT] actual size of data filled in crat_image
2223 */
kfd_create_vcrat_image_gpu(void * pcrat_image,size_t * size,struct kfd_node * kdev,uint32_t proximity_domain)2224 static int kfd_create_vcrat_image_gpu(void *pcrat_image,
2225 size_t *size, struct kfd_node *kdev,
2226 uint32_t proximity_domain)
2227 {
2228 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
2229 struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;
2230 struct amdgpu_cu_info *cu_info = &kdev->adev->gfx.cu_info;
2231 struct crat_subtype_generic *sub_type_hdr;
2232 struct kfd_local_mem_info local_mem_info;
2233 struct kfd_topology_device *peer_dev;
2234 struct crat_subtype_computeunit *cu;
2235 int avail_size = *size;
2236 uint32_t total_num_of_cu;
2237 uint32_t nid = 0;
2238 int ret = 0;
2239
2240 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
2241 return -EINVAL;
2242
2243 /* Fill the CRAT Header.
2244 * Modify length and total_entries as subunits are added.
2245 */
2246 avail_size -= sizeof(struct crat_header);
2247 memset(crat_table, 0, sizeof(struct crat_header));
2248
2249 memcpy(&crat_table->signature, CRAT_SIGNATURE,
2250 sizeof(crat_table->signature));
2251 /* Change length as we add more subtypes*/
2252 crat_table->length = sizeof(struct crat_header);
2253 crat_table->num_domains = 1;
2254 crat_table->total_entries = 0;
2255
2256 /* Fill in Subtype: Compute Unit
2257 * First fill in the sub type header and then sub type data
2258 */
2259 avail_size -= sizeof(struct crat_subtype_computeunit);
2260 sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
2261 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
2262
2263 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
2264 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
2265 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
2266
2267 /* Fill CU subtype data */
2268 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
2269 cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
2270 cu->proximity_domain = proximity_domain;
2271
2272 cu->num_simd_per_cu = cu_info->simd_per_cu;
2273 cu->num_simd_cores = cu_info->simd_per_cu *
2274 (cu_info->number / kdev->kfd->num_nodes);
2275 cu->max_waves_simd = cu_info->max_waves_per_simd;
2276
2277 cu->wave_front_size = cu_info->wave_front_size;
2278 cu->array_count = gfx_info->max_sh_per_se *
2279 gfx_info->max_shader_engines;
2280 total_num_of_cu = (cu->array_count * gfx_info->max_cu_per_sh);
2281 cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
2282 cu->num_cu_per_array = gfx_info->max_cu_per_sh;
2283 cu->max_slots_scatch_cu = cu_info->max_scratch_slots_per_cu;
2284 cu->num_banks = gfx_info->max_shader_engines;
2285 cu->lds_size_in_kb = cu_info->lds_size;
2286
2287 cu->hsa_capability = 0;
2288
2289 crat_table->length += sub_type_hdr->length;
2290 crat_table->total_entries++;
2291
2292 /* Fill in Subtype: Memory. Only on systems with large BAR (no
2293 * private FB), report memory as public. On other systems
2294 * report the total FB size (public+private) as a single
2295 * private heap.
2296 */
2297 local_mem_info = kdev->local_mem_info;
2298 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
2299 sub_type_hdr->length);
2300
2301 if (kdev->adev->debug_largebar)
2302 local_mem_info.local_mem_size_private = 0;
2303
2304 if (local_mem_info.local_mem_size_private == 0)
2305 ret = kfd_fill_gpu_memory_affinity(&avail_size,
2306 kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
2307 local_mem_info.local_mem_size_public,
2308 (struct crat_subtype_memory *)sub_type_hdr,
2309 proximity_domain,
2310 &local_mem_info);
2311 else
2312 ret = kfd_fill_gpu_memory_affinity(&avail_size,
2313 kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
2314 local_mem_info.local_mem_size_public +
2315 local_mem_info.local_mem_size_private,
2316 (struct crat_subtype_memory *)sub_type_hdr,
2317 proximity_domain,
2318 &local_mem_info);
2319 if (ret < 0)
2320 return ret;
2321
2322 crat_table->length += sizeof(struct crat_subtype_memory);
2323 crat_table->total_entries++;
2324
2325 /* Fill in Subtype: IO_LINKS
2326 * Only direct links are added here which is Link from GPU to
2327 * its NUMA node. Indirect links are added by userspace.
2328 */
2329 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
2330 sub_type_hdr->length);
2331 ret = kfd_fill_gpu_direct_io_link_to_cpu(&avail_size, kdev,
2332 (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
2333
2334 if (ret < 0)
2335 return ret;
2336
2337 crat_table->length += sub_type_hdr->length;
2338 crat_table->total_entries++;
2339
2340
2341 /* Fill in Subtype: IO_LINKS
2342 * Direct links from GPU to other GPUs through xGMI.
2343 * We will loop GPUs that already be processed (with lower value
2344 * of proximity_domain), add the link for the GPUs with same
2345 * hive id (from this GPU to other GPU) . The reversed iolink
2346 * (from other GPU to this GPU) will be added
2347 * in kfd_parse_subtype_iolink.
2348 */
2349 if (kdev->kfd->hive_id) {
2350 for (nid = 0; nid < proximity_domain; ++nid) {
2351 peer_dev = kfd_topology_device_by_proximity_domain_no_lock(nid);
2352 if (!peer_dev->gpu)
2353 continue;
2354 if (peer_dev->gpu->kfd->hive_id != kdev->kfd->hive_id)
2355 continue;
2356 sub_type_hdr = (typeof(sub_type_hdr))(
2357 (char *)sub_type_hdr +
2358 sizeof(struct crat_subtype_iolink));
2359 ret = kfd_fill_gpu_xgmi_link_to_gpu(
2360 &avail_size, kdev, peer_dev->gpu,
2361 (struct crat_subtype_iolink *)sub_type_hdr,
2362 proximity_domain, nid);
2363 if (ret < 0)
2364 return ret;
2365 crat_table->length += sub_type_hdr->length;
2366 crat_table->total_entries++;
2367 }
2368 }
2369 *size = crat_table->length;
2370 pr_info("Virtual CRAT table created for GPU\n");
2371
2372 return ret;
2373 }
2374
2375 /* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
2376 * creates a Virtual CRAT (VCRAT) image
2377 *
2378 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
2379 *
2380 * @crat_image: VCRAT image created because ACPI does not have a
2381 * CRAT for this device
2382 * @size: [OUT] size of virtual crat_image
2383 * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device
2384 * COMPUTE_UNIT_GPU - Create VCRAT for GPU
2385 * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
2386 * -- this option is not currently implemented.
2387 * The assumption is that all AMD APUs will have CRAT
2388 * @kdev: Valid kfd_node required if flags contain COMPUTE_UNIT_GPU
2389 *
2390 * Return 0 if successful else return -ve value
2391 */
kfd_create_crat_image_virtual(void ** crat_image,size_t * size,int flags,struct kfd_node * kdev,uint32_t proximity_domain)2392 int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
2393 int flags, struct kfd_node *kdev,
2394 uint32_t proximity_domain)
2395 {
2396 void *pcrat_image = NULL;
2397 int ret = 0, num_nodes;
2398 size_t dyn_size;
2399
2400 if (!crat_image)
2401 return -EINVAL;
2402
2403 *crat_image = NULL;
2404
2405 /* Allocate the CPU Virtual CRAT size based on the number of online
2406 * nodes. Allocate VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image.
2407 * This should cover all the current conditions. A check is put not
2408 * to overwrite beyond allocated size for GPUs
2409 */
2410 switch (flags) {
2411 case COMPUTE_UNIT_CPU:
2412 num_nodes = num_online_nodes();
2413 dyn_size = sizeof(struct crat_header) +
2414 num_nodes * (sizeof(struct crat_subtype_computeunit) +
2415 sizeof(struct crat_subtype_memory) +
2416 (num_nodes - 1) * sizeof(struct crat_subtype_iolink));
2417 pcrat_image = kvmalloc(dyn_size, GFP_KERNEL);
2418 if (!pcrat_image)
2419 return -ENOMEM;
2420 *size = dyn_size;
2421 pr_debug("CRAT size is %ld", dyn_size);
2422 ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
2423 break;
2424 case COMPUTE_UNIT_GPU:
2425 if (!kdev)
2426 return -EINVAL;
2427 pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
2428 if (!pcrat_image)
2429 return -ENOMEM;
2430 *size = VCRAT_SIZE_FOR_GPU;
2431 ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
2432 proximity_domain);
2433 break;
2434 case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
2435 /* TODO: */
2436 ret = -EINVAL;
2437 pr_err("VCRAT not implemented for APU\n");
2438 break;
2439 default:
2440 ret = -EINVAL;
2441 }
2442
2443 if (!ret)
2444 *crat_image = pcrat_image;
2445 else
2446 kvfree(pcrat_image);
2447
2448 return ret;
2449 }
2450
2451
2452 /* kfd_destroy_crat_image
2453 *
2454 * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
2455 *
2456 */
kfd_destroy_crat_image(void * crat_image)2457 void kfd_destroy_crat_image(void *crat_image)
2458 {
2459 kvfree(crat_image);
2460 }
2461