1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38
39 #define MQD_SIZE_ALIGNED 768
40
41 /*
42 * kfd_locked is used to lock the kfd driver during suspend or reset
43 * once locked, kfd driver will stop any further GPU execution.
44 * create process (open) will return -EAGAIN.
45 */
46 static int kfd_locked;
47
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd;
60
61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
62 unsigned int chunk_size);
63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
64
65 static int kfd_resume(struct kfd_node *kfd);
66
kfd_device_info_set_sdma_info(struct kfd_dev * kfd)67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
68 {
69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);
70
71 switch (sdma_version) {
72 case IP_VERSION(4, 0, 0):/* VEGA10 */
73 case IP_VERSION(4, 0, 1):/* VEGA12 */
74 case IP_VERSION(4, 1, 0):/* RAVEN */
75 case IP_VERSION(4, 1, 1):/* RAVEN */
76 case IP_VERSION(4, 1, 2):/* RENOIR */
77 case IP_VERSION(5, 2, 1):/* VANGOGH */
78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
81 kfd->device_info.num_sdma_queues_per_engine = 2;
82 break;
83 case IP_VERSION(4, 2, 0):/* VEGA20 */
84 case IP_VERSION(4, 2, 2):/* ARCTURUS */
85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */
86 case IP_VERSION(4, 4, 2):
87 case IP_VERSION(4, 4, 5):
88 case IP_VERSION(5, 0, 0):/* NAVI10 */
89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
90 case IP_VERSION(5, 0, 2):/* NAVI14 */
91 case IP_VERSION(5, 0, 5):/* NAVI12 */
92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
96 case IP_VERSION(6, 0, 0):
97 case IP_VERSION(6, 0, 1):
98 case IP_VERSION(6, 0, 2):
99 case IP_VERSION(6, 0, 3):
100 case IP_VERSION(6, 1, 0):
101 case IP_VERSION(6, 1, 1):
102 case IP_VERSION(6, 1, 2):
103 case IP_VERSION(7, 0, 0):
104 case IP_VERSION(7, 0, 1):
105 kfd->device_info.num_sdma_queues_per_engine = 8;
106 break;
107 default:
108 dev_warn(kfd_device,
109 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
110 sdma_version);
111 kfd->device_info.num_sdma_queues_per_engine = 8;
112 }
113
114 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
115
116 switch (sdma_version) {
117 case IP_VERSION(6, 0, 0):
118 case IP_VERSION(6, 0, 1):
119 case IP_VERSION(6, 0, 2):
120 case IP_VERSION(6, 0, 3):
121 case IP_VERSION(6, 1, 0):
122 case IP_VERSION(6, 1, 1):
123 case IP_VERSION(6, 1, 2):
124 case IP_VERSION(7, 0, 0):
125 case IP_VERSION(7, 0, 1):
126 /* Reserve 1 for paging and 1 for gfx */
127 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
128 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
129 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
130 kfd->adev->sdma.num_instances *
131 kfd->device_info.num_reserved_sdma_queues_per_engine);
132 break;
133 default:
134 break;
135 }
136 }
137
kfd_device_info_set_event_interrupt_class(struct kfd_dev * kfd)138 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
139 {
140 uint32_t gc_version = KFD_GC_VERSION(kfd);
141
142 switch (gc_version) {
143 case IP_VERSION(9, 0, 1): /* VEGA10 */
144 case IP_VERSION(9, 1, 0): /* RAVEN */
145 case IP_VERSION(9, 2, 1): /* VEGA12 */
146 case IP_VERSION(9, 2, 2): /* RAVEN */
147 case IP_VERSION(9, 3, 0): /* RENOIR */
148 case IP_VERSION(9, 4, 0): /* VEGA20 */
149 case IP_VERSION(9, 4, 1): /* ARCTURUS */
150 case IP_VERSION(9, 4, 2): /* ALDEBARAN */
151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
152 break;
153 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
154 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */
155 kfd->device_info.event_interrupt_class =
156 &event_interrupt_class_v9_4_3;
157 break;
158 case IP_VERSION(10, 3, 1): /* VANGOGH */
159 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
160 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
161 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
162 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
163 case IP_VERSION(10, 1, 4):
164 case IP_VERSION(10, 1, 10): /* NAVI10 */
165 case IP_VERSION(10, 1, 2): /* NAVI12 */
166 case IP_VERSION(10, 1, 1): /* NAVI14 */
167 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
168 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
169 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
170 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
171 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
172 break;
173 case IP_VERSION(11, 0, 0):
174 case IP_VERSION(11, 0, 1):
175 case IP_VERSION(11, 0, 2):
176 case IP_VERSION(11, 0, 3):
177 case IP_VERSION(11, 0, 4):
178 case IP_VERSION(11, 5, 0):
179 case IP_VERSION(11, 5, 1):
180 case IP_VERSION(11, 5, 2):
181 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
182 break;
183 case IP_VERSION(12, 0, 0):
184 case IP_VERSION(12, 0, 1):
185 /* GFX12_TODO: Change to v12 version. */
186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
187 break;
188 default:
189 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
190 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
192 }
193 }
194
kfd_device_info_init(struct kfd_dev * kfd,bool vf,uint32_t gfx_target_version)195 static void kfd_device_info_init(struct kfd_dev *kfd,
196 bool vf, uint32_t gfx_target_version)
197 {
198 uint32_t gc_version = KFD_GC_VERSION(kfd);
199 uint32_t asic_type = kfd->adev->asic_type;
200
201 kfd->device_info.max_pasid_bits = 16;
202 kfd->device_info.max_no_of_hqd = 24;
203 kfd->device_info.num_of_watch_points = 4;
204 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
205 kfd->device_info.gfx_target_version = gfx_target_version;
206
207 if (KFD_IS_SOC15(kfd)) {
208 kfd->device_info.doorbell_size = 8;
209 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
210 kfd->device_info.supports_cwsr = true;
211
212 kfd_device_info_set_sdma_info(kfd);
213
214 kfd_device_info_set_event_interrupt_class(kfd);
215
216 if (gc_version < IP_VERSION(11, 0, 0)) {
217 /* Navi2x+, Navi1x+ */
218 if (gc_version == IP_VERSION(10, 3, 6))
219 kfd->device_info.no_atomic_fw_version = 14;
220 else if (gc_version == IP_VERSION(10, 3, 7))
221 kfd->device_info.no_atomic_fw_version = 3;
222 else if (gc_version >= IP_VERSION(10, 3, 0))
223 kfd->device_info.no_atomic_fw_version = 92;
224 else if (gc_version >= IP_VERSION(10, 1, 1))
225 kfd->device_info.no_atomic_fw_version = 145;
226
227 /* Navi1x+ */
228 if (gc_version >= IP_VERSION(10, 1, 1))
229 kfd->device_info.needs_pci_atomics = true;
230 } else if (gc_version < IP_VERSION(12, 0, 0)) {
231 /*
232 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
233 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
234 * PCIe atomics support.
235 */
236 kfd->device_info.needs_pci_atomics = true;
237 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
238 } else if (gc_version < IP_VERSION(13, 0, 0)) {
239 kfd->device_info.needs_pci_atomics = true;
240 kfd->device_info.no_atomic_fw_version = 2090;
241 } else {
242 kfd->device_info.needs_pci_atomics = true;
243 }
244 } else {
245 kfd->device_info.doorbell_size = 4;
246 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
247 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
248 kfd->device_info.num_sdma_queues_per_engine = 2;
249
250 if (asic_type != CHIP_KAVERI &&
251 asic_type != CHIP_HAWAII &&
252 asic_type != CHIP_TONGA)
253 kfd->device_info.supports_cwsr = true;
254
255 if (asic_type != CHIP_HAWAII && !vf)
256 kfd->device_info.needs_pci_atomics = true;
257 }
258 }
259
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)260 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
261 {
262 struct kfd_dev *kfd = NULL;
263 const struct kfd2kgd_calls *f2g = NULL;
264 uint32_t gfx_target_version = 0;
265
266 switch (adev->asic_type) {
267 #ifdef CONFIG_DRM_AMDGPU_CIK
268 case CHIP_KAVERI:
269 gfx_target_version = 70000;
270 if (!vf)
271 f2g = &gfx_v7_kfd2kgd;
272 break;
273 #endif
274 case CHIP_CARRIZO:
275 gfx_target_version = 80001;
276 if (!vf)
277 f2g = &gfx_v8_kfd2kgd;
278 break;
279 #ifdef CONFIG_DRM_AMDGPU_CIK
280 case CHIP_HAWAII:
281 gfx_target_version = 70001;
282 if (!amdgpu_exp_hw_support)
283 pr_info(
284 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
285 );
286 else if (!vf)
287 f2g = &gfx_v7_kfd2kgd;
288 break;
289 #endif
290 case CHIP_TONGA:
291 gfx_target_version = 80002;
292 if (!vf)
293 f2g = &gfx_v8_kfd2kgd;
294 break;
295 case CHIP_FIJI:
296 case CHIP_POLARIS10:
297 gfx_target_version = 80003;
298 f2g = &gfx_v8_kfd2kgd;
299 break;
300 case CHIP_POLARIS11:
301 case CHIP_POLARIS12:
302 case CHIP_VEGAM:
303 gfx_target_version = 80003;
304 if (!vf)
305 f2g = &gfx_v8_kfd2kgd;
306 break;
307 default:
308 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
309 /* Vega 10 */
310 case IP_VERSION(9, 0, 1):
311 gfx_target_version = 90000;
312 f2g = &gfx_v9_kfd2kgd;
313 break;
314 /* Raven */
315 case IP_VERSION(9, 1, 0):
316 case IP_VERSION(9, 2, 2):
317 gfx_target_version = 90002;
318 if (!vf)
319 f2g = &gfx_v9_kfd2kgd;
320 break;
321 /* Vega12 */
322 case IP_VERSION(9, 2, 1):
323 gfx_target_version = 90004;
324 if (!vf)
325 f2g = &gfx_v9_kfd2kgd;
326 break;
327 /* Renoir */
328 case IP_VERSION(9, 3, 0):
329 gfx_target_version = 90012;
330 if (!vf)
331 f2g = &gfx_v9_kfd2kgd;
332 break;
333 /* Vega20 */
334 case IP_VERSION(9, 4, 0):
335 gfx_target_version = 90006;
336 if (!vf)
337 f2g = &gfx_v9_kfd2kgd;
338 break;
339 /* Arcturus */
340 case IP_VERSION(9, 4, 1):
341 gfx_target_version = 90008;
342 f2g = &arcturus_kfd2kgd;
343 break;
344 /* Aldebaran */
345 case IP_VERSION(9, 4, 2):
346 gfx_target_version = 90010;
347 f2g = &aldebaran_kfd2kgd;
348 break;
349 case IP_VERSION(9, 4, 3):
350 gfx_target_version = adev->rev_id >= 1 ? 90402
351 : adev->flags & AMD_IS_APU ? 90400
352 : 90401;
353 f2g = &gc_9_4_3_kfd2kgd;
354 break;
355 case IP_VERSION(9, 4, 4):
356 gfx_target_version = 90402;
357 f2g = &gc_9_4_3_kfd2kgd;
358 break;
359 /* Navi10 */
360 case IP_VERSION(10, 1, 10):
361 gfx_target_version = 100100;
362 if (!vf)
363 f2g = &gfx_v10_kfd2kgd;
364 break;
365 /* Navi12 */
366 case IP_VERSION(10, 1, 2):
367 gfx_target_version = 100101;
368 f2g = &gfx_v10_kfd2kgd;
369 break;
370 /* Navi14 */
371 case IP_VERSION(10, 1, 1):
372 gfx_target_version = 100102;
373 if (!vf)
374 f2g = &gfx_v10_kfd2kgd;
375 break;
376 /* Cyan Skillfish */
377 case IP_VERSION(10, 1, 3):
378 case IP_VERSION(10, 1, 4):
379 gfx_target_version = 100103;
380 if (!vf)
381 f2g = &gfx_v10_kfd2kgd;
382 break;
383 /* Sienna Cichlid */
384 case IP_VERSION(10, 3, 0):
385 gfx_target_version = 100300;
386 f2g = &gfx_v10_3_kfd2kgd;
387 break;
388 /* Navy Flounder */
389 case IP_VERSION(10, 3, 2):
390 gfx_target_version = 100301;
391 f2g = &gfx_v10_3_kfd2kgd;
392 break;
393 /* Van Gogh */
394 case IP_VERSION(10, 3, 1):
395 gfx_target_version = 100303;
396 if (!vf)
397 f2g = &gfx_v10_3_kfd2kgd;
398 break;
399 /* Dimgrey Cavefish */
400 case IP_VERSION(10, 3, 4):
401 gfx_target_version = 100302;
402 f2g = &gfx_v10_3_kfd2kgd;
403 break;
404 /* Beige Goby */
405 case IP_VERSION(10, 3, 5):
406 gfx_target_version = 100304;
407 f2g = &gfx_v10_3_kfd2kgd;
408 break;
409 /* Yellow Carp */
410 case IP_VERSION(10, 3, 3):
411 gfx_target_version = 100305;
412 if (!vf)
413 f2g = &gfx_v10_3_kfd2kgd;
414 break;
415 case IP_VERSION(10, 3, 6):
416 case IP_VERSION(10, 3, 7):
417 gfx_target_version = 100306;
418 if (!vf)
419 f2g = &gfx_v10_3_kfd2kgd;
420 break;
421 case IP_VERSION(11, 0, 0):
422 gfx_target_version = 110000;
423 f2g = &gfx_v11_kfd2kgd;
424 break;
425 case IP_VERSION(11, 0, 1):
426 case IP_VERSION(11, 0, 4):
427 gfx_target_version = 110003;
428 f2g = &gfx_v11_kfd2kgd;
429 break;
430 case IP_VERSION(11, 0, 2):
431 gfx_target_version = 110002;
432 f2g = &gfx_v11_kfd2kgd;
433 break;
434 case IP_VERSION(11, 0, 3):
435 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
436 gfx_target_version = 110001;
437 f2g = &gfx_v11_kfd2kgd;
438 break;
439 case IP_VERSION(11, 5, 0):
440 gfx_target_version = 110500;
441 f2g = &gfx_v11_kfd2kgd;
442 break;
443 case IP_VERSION(11, 5, 1):
444 gfx_target_version = 110501;
445 f2g = &gfx_v11_kfd2kgd;
446 break;
447 case IP_VERSION(11, 5, 2):
448 gfx_target_version = 110502;
449 f2g = &gfx_v11_kfd2kgd;
450 break;
451 case IP_VERSION(12, 0, 0):
452 gfx_target_version = 120000;
453 f2g = &gfx_v12_kfd2kgd;
454 break;
455 case IP_VERSION(12, 0, 1):
456 gfx_target_version = 120001;
457 f2g = &gfx_v12_kfd2kgd;
458 break;
459 default:
460 break;
461 }
462 break;
463 }
464
465 if (!f2g) {
466 if (amdgpu_ip_version(adev, GC_HWIP, 0))
467 dev_info(kfd_device,
468 "GC IP %06x %s not supported in kfd\n",
469 amdgpu_ip_version(adev, GC_HWIP, 0),
470 vf ? "VF" : "");
471 else
472 dev_info(kfd_device, "%s %s not supported in kfd\n",
473 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
474 return NULL;
475 }
476
477 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
478 if (!kfd)
479 return NULL;
480
481 kfd->adev = adev;
482 kfd_device_info_init(kfd, vf, gfx_target_version);
483 kfd->init_complete = false;
484 kfd->kfd2kgd = f2g;
485 atomic_set(&kfd->compute_profile, 0);
486
487 mutex_init(&kfd->doorbell_mutex);
488
489 ida_init(&kfd->doorbell_ida);
490
491 return kfd;
492 }
493
kfd_cwsr_init(struct kfd_dev * kfd)494 static void kfd_cwsr_init(struct kfd_dev *kfd)
495 {
496 if (cwsr_enable && kfd->device_info.supports_cwsr) {
497 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
498 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex)
499 > KFD_CWSR_TMA_OFFSET);
500 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
501 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
502 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
503 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex)
504 > KFD_CWSR_TMA_OFFSET);
505 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
506 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
507 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
508 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex)
509 > KFD_CWSR_TMA_OFFSET);
510 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
511 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
512 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
513 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) {
514 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex)
515 > KFD_CWSR_TMA_OFFSET);
516 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
517 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
518 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
519 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex)
520 > KFD_CWSR_TMA_OFFSET);
521 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
523 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
524 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex)
525 > KFD_CWSR_TMA_OFFSET);
526 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
527 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
528 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
529 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex)
530 > KFD_CWSR_TMA_OFFSET);
531 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
533 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) {
534 /* The gfx11 cwsr trap handler must fit inside a single
535 page. */
536 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
537 kfd->cwsr_isa = cwsr_trap_gfx11_hex;
538 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
539 } else {
540 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex)
541 > KFD_CWSR_TMA_OFFSET);
542 kfd->cwsr_isa = cwsr_trap_gfx12_hex;
543 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex);
544 }
545
546 kfd->cwsr_enabled = true;
547 }
548 }
549
kfd_gws_init(struct kfd_node * node)550 static int kfd_gws_init(struct kfd_node *node)
551 {
552 int ret = 0;
553 struct kfd_dev *kfd = node->kfd;
554 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
555
556 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
557 return 0;
558
559 if (hws_gws_support || (KFD_IS_SOC15(node) &&
560 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
561 && kfd->mec2_fw_version >= 0x81b3) ||
562 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
563 && kfd->mec2_fw_version >= 0x1b3) ||
564 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
565 && kfd->mec2_fw_version >= 0x30) ||
566 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
567 && kfd->mec2_fw_version >= 0x28) ||
568 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) ||
569 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) ||
570 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
571 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
572 && kfd->mec2_fw_version >= 0x6b) ||
573 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
574 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
575 && mes_rev >= 68))))
576 ret = amdgpu_amdkfd_alloc_gws(node->adev,
577 node->adev->gds.gws_size, &node->gws);
578
579 return ret;
580 }
581
kfd_smi_init(struct kfd_node * dev)582 static void kfd_smi_init(struct kfd_node *dev)
583 {
584 INIT_LIST_HEAD(&dev->smi_clients);
585 spin_lock_init(&dev->smi_lock);
586 }
587
kfd_init_node(struct kfd_node * node)588 static int kfd_init_node(struct kfd_node *node)
589 {
590 int err = -1;
591
592 if (kfd_interrupt_init(node)) {
593 dev_err(kfd_device, "Error initializing interrupts\n");
594 goto kfd_interrupt_error;
595 }
596
597 node->dqm = device_queue_manager_init(node);
598 if (!node->dqm) {
599 dev_err(kfd_device, "Error initializing queue manager\n");
600 goto device_queue_manager_error;
601 }
602
603 if (kfd_gws_init(node)) {
604 dev_err(kfd_device, "Could not allocate %d gws\n",
605 node->adev->gds.gws_size);
606 goto gws_error;
607 }
608
609 if (kfd_resume(node))
610 goto kfd_resume_error;
611
612 if (kfd_topology_add_device(node)) {
613 dev_err(kfd_device, "Error adding device to topology\n");
614 goto kfd_topology_add_device_error;
615 }
616
617 kfd_smi_init(node);
618
619 return 0;
620
621 kfd_topology_add_device_error:
622 kfd_resume_error:
623 gws_error:
624 device_queue_manager_uninit(node->dqm);
625 device_queue_manager_error:
626 kfd_interrupt_exit(node);
627 kfd_interrupt_error:
628 if (node->gws)
629 amdgpu_amdkfd_free_gws(node->adev, node->gws);
630
631 /* Cleanup the node memory here */
632 kfree(node);
633 return err;
634 }
635
kfd_cleanup_nodes(struct kfd_dev * kfd,unsigned int num_nodes)636 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
637 {
638 struct kfd_node *knode;
639 unsigned int i;
640
641 /*
642 * flush_work ensures that there are no outstanding
643 * work-queue items that will access interrupt_ring. New work items
644 * can't be created because we stopped interrupt handling above.
645 */
646 flush_workqueue(kfd->ih_wq);
647 destroy_workqueue(kfd->ih_wq);
648
649 for (i = 0; i < num_nodes; i++) {
650 knode = kfd->nodes[i];
651 device_queue_manager_uninit(knode->dqm);
652 kfd_interrupt_exit(knode);
653 kfd_topology_remove_device(knode);
654 if (knode->gws)
655 amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
656 kfree(knode);
657 kfd->nodes[i] = NULL;
658 }
659 }
660
kfd_setup_interrupt_bitmap(struct kfd_node * node,unsigned int kfd_node_idx)661 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
662 unsigned int kfd_node_idx)
663 {
664 struct amdgpu_device *adev = node->adev;
665 uint32_t xcc_mask = node->xcc_mask;
666 uint32_t xcc, mapped_xcc;
667 /*
668 * Interrupt bitmap is setup for processing interrupts from
669 * different XCDs and AIDs.
670 * Interrupt bitmap is defined as follows:
671 * 1. Bits 0-15 - correspond to the NodeId field.
672 * Each bit corresponds to NodeId number. For example, if
673 * a KFD node has interrupt bitmap set to 0x7, then this
674 * KFD node will process interrupts with NodeId = 0, 1 and 2
675 * in the IH cookie.
676 * 2. Bits 16-31 - unused.
677 *
678 * Please note that the kfd_node_idx argument passed to this
679 * function is not related to NodeId field received in the
680 * IH cookie.
681 *
682 * In CPX mode, a KFD node will process an interrupt if:
683 * - the Node Id matches the corresponding bit set in
684 * Bits 0-15.
685 * - AND VMID reported in the interrupt lies within the
686 * VMID range of the node.
687 */
688 for_each_inst(xcc, xcc_mask) {
689 mapped_xcc = GET_INST(GC, xcc);
690 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
691 }
692 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
693 node->interrupt_bitmap);
694 }
695
kgd2kfd_device_init(struct kfd_dev * kfd,const struct kgd2kfd_shared_resources * gpu_resources)696 bool kgd2kfd_device_init(struct kfd_dev *kfd,
697 const struct kgd2kfd_shared_resources *gpu_resources)
698 {
699 unsigned int size, map_process_packet_size, i;
700 struct kfd_node *node;
701 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
702 unsigned int max_proc_per_quantum;
703 int partition_mode;
704 int xcp_idx;
705
706 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
707 KGD_ENGINE_MEC1);
708 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
709 KGD_ENGINE_MEC2);
710 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
711 KGD_ENGINE_SDMA1);
712 kfd->shared_resources = *gpu_resources;
713
714 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
715
716 if (kfd->num_nodes == 0) {
717 dev_err(kfd_device,
718 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
719 kfd->adev->gfx.num_xcc_per_xcp);
720 goto out;
721 }
722
723 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
724 * 32 and 64-bit requests are possible and must be
725 * supported.
726 */
727 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
728 if (!kfd->pci_atomic_requested &&
729 kfd->device_info.needs_pci_atomics &&
730 (!kfd->device_info.no_atomic_fw_version ||
731 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
732 dev_info(kfd_device,
733 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
734 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
735 kfd->mec_fw_version,
736 kfd->device_info.no_atomic_fw_version);
737 return false;
738 }
739
740 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
741 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
742 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
743
744 /* For GFX9.4.3, we need special handling for VMIDs depending on
745 * partition mode.
746 * In CPX mode, the VMID range needs to be shared between XCDs.
747 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
748 * divide them equally, we change starting VMID to 4 and not use
749 * VMID 3.
750 * If the VMID range changes for GFX9.4.3, then this code MUST be
751 * revisited.
752 */
753 if (kfd->adev->xcp_mgr) {
754 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
755 AMDGPU_XCP_FL_LOCKED);
756 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
757 kfd->num_nodes != 1) {
758 vmid_num_kfd /= 2;
759 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
760 }
761 }
762
763 /* Verify module parameters regarding mapped process number*/
764 if (hws_max_conc_proc >= 0)
765 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
766 else
767 max_proc_per_quantum = vmid_num_kfd;
768
769 /* calculate max size of mqds needed for queues */
770 size = max_num_of_queues_per_device *
771 kfd->device_info.mqd_size_aligned;
772
773 /*
774 * calculate max size of runlist packet.
775 * There can be only 2 packets at once
776 */
777 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
778 sizeof(struct pm4_mes_map_process_aldebaran) :
779 sizeof(struct pm4_mes_map_process);
780 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
781 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
782 + sizeof(struct pm4_mes_runlist)) * 2;
783
784 /* Add size of HIQ & DIQ */
785 size += KFD_KERNEL_QUEUE_SIZE * 2;
786
787 /* add another 512KB for all other allocations on gart (HPD, fences) */
788 size += 512 * 1024;
789
790 if (amdgpu_amdkfd_alloc_gtt_mem(
791 kfd->adev, size, &kfd->gtt_mem,
792 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
793 false)) {
794 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
795 goto alloc_gtt_mem_failure;
796 }
797
798 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
799
800 /* Initialize GTT sa with 512 byte chunk size */
801 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
802 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
803 goto kfd_gtt_sa_init_error;
804 }
805
806 if (kfd_doorbell_init(kfd)) {
807 dev_err(kfd_device,
808 "Error initializing doorbell aperture\n");
809 goto kfd_doorbell_error;
810 }
811
812 if (amdgpu_use_xgmi_p2p)
813 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
814
815 /*
816 * For GFX9.4.3, the KFD abstracts all partitions within a socket as
817 * xGMI connected in the topology so assign a unique hive id per
818 * device based on the pci device location if device is in PCIe mode.
819 */
820 if (!kfd->hive_id &&
821 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
822 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) &&
823 kfd->num_nodes > 1)
824 kfd->hive_id = pci_dev_id(kfd->adev->pdev);
825
826 kfd->noretry = kfd->adev->gmc.noretry;
827
828 kfd_cwsr_init(kfd);
829
830 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
831 kfd->num_nodes);
832
833 /* Allocate the KFD nodes */
834 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
835 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
836 if (!node)
837 goto node_alloc_error;
838
839 node->node_id = i;
840 node->adev = kfd->adev;
841 node->kfd = kfd;
842 node->kfd2kgd = kfd->kfd2kgd;
843 node->vm_info.vmid_num_kfd = vmid_num_kfd;
844 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
845 /* TODO : Check if error handling is needed */
846 if (node->xcp) {
847 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
848 &node->xcc_mask);
849 ++xcp_idx;
850 } else {
851 node->xcc_mask =
852 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
853 }
854
855 if (node->xcp) {
856 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
857 node->node_id, node->xcp->mem_id,
858 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
859 }
860
861 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
862 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) &&
863 partition_mode == AMDGPU_CPX_PARTITION_MODE &&
864 kfd->num_nodes != 1) {
865 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range
866 * 4-9 and second XCD gets VMID range 10-15.
867 */
868
869 node->vm_info.first_vmid_kfd = (i%2 == 0) ?
870 first_vmid_kfd :
871 first_vmid_kfd+vmid_num_kfd;
872 node->vm_info.last_vmid_kfd = (i%2 == 0) ?
873 last_vmid_kfd-vmid_num_kfd :
874 last_vmid_kfd;
875 node->compute_vmid_bitmap =
876 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
877 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
878 } else {
879 node->vm_info.first_vmid_kfd = first_vmid_kfd;
880 node->vm_info.last_vmid_kfd = last_vmid_kfd;
881 node->compute_vmid_bitmap =
882 gpu_resources->compute_vmid_bitmap;
883 }
884 node->max_proc_per_quantum = max_proc_per_quantum;
885 atomic_set(&node->sram_ecc_flag, 0);
886
887 amdgpu_amdkfd_get_local_mem_info(kfd->adev,
888 &node->local_mem_info, node->xcp);
889
890 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
891 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4))
892 kfd_setup_interrupt_bitmap(node, i);
893
894 /* Initialize the KFD node */
895 if (kfd_init_node(node)) {
896 dev_err(kfd_device, "Error initializing KFD node\n");
897 goto node_init_error;
898 }
899
900 spin_lock_init(&node->watch_points_lock);
901
902 kfd->nodes[i] = node;
903 }
904
905 svm_range_set_max_pages(kfd->adev);
906
907 kfd->init_complete = true;
908 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
909 kfd->adev->pdev->device);
910
911 pr_debug("Starting kfd with the following scheduling policy %d\n",
912 node->dqm->sched_policy);
913
914 goto out;
915
916 node_init_error:
917 node_alloc_error:
918 kfd_cleanup_nodes(kfd, i);
919 kfd_doorbell_fini(kfd);
920 kfd_doorbell_error:
921 kfd_gtt_sa_fini(kfd);
922 kfd_gtt_sa_init_error:
923 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
924 alloc_gtt_mem_failure:
925 dev_err(kfd_device,
926 "device %x:%x NOT added due to errors\n",
927 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
928 out:
929 return kfd->init_complete;
930 }
931
kgd2kfd_device_exit(struct kfd_dev * kfd)932 void kgd2kfd_device_exit(struct kfd_dev *kfd)
933 {
934 if (kfd->init_complete) {
935 /* Cleanup KFD nodes */
936 kfd_cleanup_nodes(kfd, kfd->num_nodes);
937 /* Cleanup common/shared resources */
938 kfd_doorbell_fini(kfd);
939 ida_destroy(&kfd->doorbell_ida);
940 kfd_gtt_sa_fini(kfd);
941 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
942 }
943
944 kfree(kfd);
945 }
946
kgd2kfd_pre_reset(struct kfd_dev * kfd,struct amdgpu_reset_context * reset_context)947 int kgd2kfd_pre_reset(struct kfd_dev *kfd,
948 struct amdgpu_reset_context *reset_context)
949 {
950 struct kfd_node *node;
951 int i;
952
953 if (!kfd->init_complete)
954 return 0;
955
956 for (i = 0; i < kfd->num_nodes; i++) {
957 node = kfd->nodes[i];
958 kfd_smi_event_update_gpu_reset(node, false, reset_context);
959 }
960
961 kgd2kfd_suspend(kfd, false);
962
963 for (i = 0; i < kfd->num_nodes; i++)
964 kfd_signal_reset_event(kfd->nodes[i]);
965
966 return 0;
967 }
968
969 /*
970 * Fix me. KFD won't be able to resume existing process for now.
971 * We will keep all existing process in a evicted state and
972 * wait the process to be terminated.
973 */
974
kgd2kfd_post_reset(struct kfd_dev * kfd)975 int kgd2kfd_post_reset(struct kfd_dev *kfd)
976 {
977 int ret;
978 struct kfd_node *node;
979 int i;
980
981 if (!kfd->init_complete)
982 return 0;
983
984 for (i = 0; i < kfd->num_nodes; i++) {
985 ret = kfd_resume(kfd->nodes[i]);
986 if (ret)
987 return ret;
988 }
989
990 mutex_lock(&kfd_processes_mutex);
991 --kfd_locked;
992 mutex_unlock(&kfd_processes_mutex);
993
994 for (i = 0; i < kfd->num_nodes; i++) {
995 node = kfd->nodes[i];
996 atomic_set(&node->sram_ecc_flag, 0);
997 kfd_smi_event_update_gpu_reset(node, true, NULL);
998 }
999
1000 return 0;
1001 }
1002
kfd_is_locked(void)1003 bool kfd_is_locked(void)
1004 {
1005 lockdep_assert_held(&kfd_processes_mutex);
1006 return (kfd_locked > 0);
1007 }
1008
kgd2kfd_suspend(struct kfd_dev * kfd,bool run_pm)1009 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
1010 {
1011 struct kfd_node *node;
1012 int i;
1013
1014 if (!kfd->init_complete)
1015 return;
1016
1017 /* for runtime suspend, skip locking kfd */
1018 if (!run_pm) {
1019 mutex_lock(&kfd_processes_mutex);
1020 /* For first KFD device suspend all the KFD processes */
1021 if (++kfd_locked == 1)
1022 kfd_suspend_all_processes();
1023 mutex_unlock(&kfd_processes_mutex);
1024 }
1025
1026 for (i = 0; i < kfd->num_nodes; i++) {
1027 node = kfd->nodes[i];
1028 node->dqm->ops.stop(node->dqm);
1029 }
1030 }
1031
kgd2kfd_resume(struct kfd_dev * kfd,bool run_pm)1032 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
1033 {
1034 int ret, i;
1035
1036 if (!kfd->init_complete)
1037 return 0;
1038
1039 for (i = 0; i < kfd->num_nodes; i++) {
1040 ret = kfd_resume(kfd->nodes[i]);
1041 if (ret)
1042 return ret;
1043 }
1044
1045 /* for runtime resume, skip unlocking kfd */
1046 if (!run_pm) {
1047 mutex_lock(&kfd_processes_mutex);
1048 if (--kfd_locked == 0)
1049 ret = kfd_resume_all_processes();
1050 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
1051 mutex_unlock(&kfd_processes_mutex);
1052 }
1053
1054 return ret;
1055 }
1056
kfd_resume(struct kfd_node * node)1057 static int kfd_resume(struct kfd_node *node)
1058 {
1059 int err = 0;
1060
1061 err = node->dqm->ops.start(node->dqm);
1062 if (err)
1063 dev_err(kfd_device,
1064 "Error starting queue manager for device %x:%x\n",
1065 node->adev->pdev->vendor, node->adev->pdev->device);
1066
1067 return err;
1068 }
1069
1070 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)1071 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1072 {
1073 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1074 bool is_patched = false;
1075 unsigned long flags;
1076 struct kfd_node *node;
1077
1078 if (!kfd->init_complete)
1079 return;
1080
1081 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1082 dev_err_once(kfd_device, "Ring entry too small\n");
1083 return;
1084 }
1085
1086 for (i = 0; i < kfd->num_nodes; i++) {
1087 node = kfd->nodes[i];
1088 spin_lock_irqsave(&node->interrupt_lock, flags);
1089
1090 if (node->interrupts_active
1091 && interrupt_is_wanted(node, ih_ring_entry,
1092 patched_ihre, &is_patched)
1093 && enqueue_ih_ring_entry(node,
1094 is_patched ? patched_ihre : ih_ring_entry)) {
1095 queue_work(node->kfd->ih_wq, &node->interrupt_work);
1096 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1097 return;
1098 }
1099 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1100 }
1101
1102 }
1103
kgd2kfd_quiesce_mm(struct mm_struct * mm,uint32_t trigger)1104 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1105 {
1106 struct kfd_process *p;
1107 int r;
1108
1109 /* Because we are called from arbitrary context (workqueue) as opposed
1110 * to process context, kfd_process could attempt to exit while we are
1111 * running so the lookup function increments the process ref count.
1112 */
1113 p = kfd_lookup_process_by_mm(mm);
1114 if (!p)
1115 return -ESRCH;
1116
1117 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1118 r = kfd_process_evict_queues(p, trigger);
1119
1120 kfd_unref_process(p);
1121 return r;
1122 }
1123
kgd2kfd_resume_mm(struct mm_struct * mm)1124 int kgd2kfd_resume_mm(struct mm_struct *mm)
1125 {
1126 struct kfd_process *p;
1127 int r;
1128
1129 /* Because we are called from arbitrary context (workqueue) as opposed
1130 * to process context, kfd_process could attempt to exit while we are
1131 * running so the lookup function increments the process ref count.
1132 */
1133 p = kfd_lookup_process_by_mm(mm);
1134 if (!p)
1135 return -ESRCH;
1136
1137 r = kfd_process_restore_queues(p);
1138
1139 kfd_unref_process(p);
1140 return r;
1141 }
1142
1143 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1144 * prepare for safe eviction of KFD BOs that belong to the specified
1145 * process.
1146 *
1147 * @mm: mm_struct that identifies the specified KFD process
1148 * @fence: eviction fence attached to KFD process BOs
1149 *
1150 */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1151 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1152 struct dma_fence *fence)
1153 {
1154 struct kfd_process *p;
1155 unsigned long active_time;
1156 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1157
1158 if (!fence)
1159 return -EINVAL;
1160
1161 if (dma_fence_is_signaled(fence))
1162 return 0;
1163
1164 p = kfd_lookup_process_by_mm(mm);
1165 if (!p)
1166 return -ENODEV;
1167
1168 if (fence->seqno == p->last_eviction_seqno)
1169 goto out;
1170
1171 p->last_eviction_seqno = fence->seqno;
1172
1173 /* Avoid KFD process starvation. Wait for at least
1174 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1175 */
1176 active_time = get_jiffies_64() - p->last_restore_timestamp;
1177 if (delay_jiffies > active_time)
1178 delay_jiffies -= active_time;
1179 else
1180 delay_jiffies = 0;
1181
1182 /* During process initialization eviction_work.dwork is initialized
1183 * to kfd_evict_bo_worker
1184 */
1185 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1186 p->lead_thread->pid, delay_jiffies);
1187 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1188 out:
1189 kfd_unref_process(p);
1190 return 0;
1191 }
1192
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1193 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1194 unsigned int chunk_size)
1195 {
1196 if (WARN_ON(buf_size < chunk_size))
1197 return -EINVAL;
1198 if (WARN_ON(buf_size == 0))
1199 return -EINVAL;
1200 if (WARN_ON(chunk_size == 0))
1201 return -EINVAL;
1202
1203 kfd->gtt_sa_chunk_size = chunk_size;
1204 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1205
1206 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1207 GFP_KERNEL);
1208 if (!kfd->gtt_sa_bitmap)
1209 return -ENOMEM;
1210
1211 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1212 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1213
1214 mutex_init(&kfd->gtt_sa_lock);
1215
1216 return 0;
1217 }
1218
kfd_gtt_sa_fini(struct kfd_dev * kfd)1219 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1220 {
1221 mutex_destroy(&kfd->gtt_sa_lock);
1222 bitmap_free(kfd->gtt_sa_bitmap);
1223 }
1224
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1225 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1226 unsigned int bit_num,
1227 unsigned int chunk_size)
1228 {
1229 return start_addr + bit_num * chunk_size;
1230 }
1231
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1232 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1233 unsigned int bit_num,
1234 unsigned int chunk_size)
1235 {
1236 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1237 }
1238
kfd_gtt_sa_allocate(struct kfd_node * node,unsigned int size,struct kfd_mem_obj ** mem_obj)1239 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1240 struct kfd_mem_obj **mem_obj)
1241 {
1242 unsigned int found, start_search, cur_size;
1243 struct kfd_dev *kfd = node->kfd;
1244
1245 if (size == 0)
1246 return -EINVAL;
1247
1248 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1249 return -ENOMEM;
1250
1251 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1252 if (!(*mem_obj))
1253 return -ENOMEM;
1254
1255 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1256
1257 start_search = 0;
1258
1259 mutex_lock(&kfd->gtt_sa_lock);
1260
1261 kfd_gtt_restart_search:
1262 /* Find the first chunk that is free */
1263 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1264 kfd->gtt_sa_num_of_chunks,
1265 start_search);
1266
1267 pr_debug("Found = %d\n", found);
1268
1269 /* If there wasn't any free chunk, bail out */
1270 if (found == kfd->gtt_sa_num_of_chunks)
1271 goto kfd_gtt_no_free_chunk;
1272
1273 /* Update fields of mem_obj */
1274 (*mem_obj)->range_start = found;
1275 (*mem_obj)->range_end = found;
1276 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1277 kfd->gtt_start_gpu_addr,
1278 found,
1279 kfd->gtt_sa_chunk_size);
1280 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1281 kfd->gtt_start_cpu_ptr,
1282 found,
1283 kfd->gtt_sa_chunk_size);
1284
1285 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1286 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1287
1288 /* If we need only one chunk, mark it as allocated and get out */
1289 if (size <= kfd->gtt_sa_chunk_size) {
1290 pr_debug("Single bit\n");
1291 __set_bit(found, kfd->gtt_sa_bitmap);
1292 goto kfd_gtt_out;
1293 }
1294
1295 /* Otherwise, try to see if we have enough contiguous chunks */
1296 cur_size = size - kfd->gtt_sa_chunk_size;
1297 do {
1298 (*mem_obj)->range_end =
1299 find_next_zero_bit(kfd->gtt_sa_bitmap,
1300 kfd->gtt_sa_num_of_chunks, ++found);
1301 /*
1302 * If next free chunk is not contiguous than we need to
1303 * restart our search from the last free chunk we found (which
1304 * wasn't contiguous to the previous ones
1305 */
1306 if ((*mem_obj)->range_end != found) {
1307 start_search = found;
1308 goto kfd_gtt_restart_search;
1309 }
1310
1311 /*
1312 * If we reached end of buffer, bail out with error
1313 */
1314 if (found == kfd->gtt_sa_num_of_chunks)
1315 goto kfd_gtt_no_free_chunk;
1316
1317 /* Check if we don't need another chunk */
1318 if (cur_size <= kfd->gtt_sa_chunk_size)
1319 cur_size = 0;
1320 else
1321 cur_size -= kfd->gtt_sa_chunk_size;
1322
1323 } while (cur_size > 0);
1324
1325 pr_debug("range_start = %d, range_end = %d\n",
1326 (*mem_obj)->range_start, (*mem_obj)->range_end);
1327
1328 /* Mark the chunks as allocated */
1329 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1330 (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1331
1332 kfd_gtt_out:
1333 mutex_unlock(&kfd->gtt_sa_lock);
1334 return 0;
1335
1336 kfd_gtt_no_free_chunk:
1337 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1338 mutex_unlock(&kfd->gtt_sa_lock);
1339 kfree(*mem_obj);
1340 return -ENOMEM;
1341 }
1342
kfd_gtt_sa_free(struct kfd_node * node,struct kfd_mem_obj * mem_obj)1343 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1344 {
1345 struct kfd_dev *kfd = node->kfd;
1346
1347 /* Act like kfree when trying to free a NULL object */
1348 if (!mem_obj)
1349 return 0;
1350
1351 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1352 mem_obj, mem_obj->range_start, mem_obj->range_end);
1353
1354 mutex_lock(&kfd->gtt_sa_lock);
1355
1356 /* Mark the chunks as free */
1357 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1358 mem_obj->range_end - mem_obj->range_start + 1);
1359
1360 mutex_unlock(&kfd->gtt_sa_lock);
1361
1362 kfree(mem_obj);
1363 return 0;
1364 }
1365
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1366 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1367 {
1368 /*
1369 * TODO: Currently update SRAM ECC flag for first node.
1370 * This needs to be updated later when we can
1371 * identify SRAM ECC error on other nodes also.
1372 */
1373 if (kfd)
1374 atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1375 }
1376
kfd_inc_compute_active(struct kfd_node * node)1377 void kfd_inc_compute_active(struct kfd_node *node)
1378 {
1379 if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1380 amdgpu_amdkfd_set_compute_idle(node->adev, false);
1381 }
1382
kfd_dec_compute_active(struct kfd_node * node)1383 void kfd_dec_compute_active(struct kfd_node *node)
1384 {
1385 int count = atomic_dec_return(&node->kfd->compute_profile);
1386
1387 if (count == 0)
1388 amdgpu_amdkfd_set_compute_idle(node->adev, true);
1389 WARN_ONCE(count < 0, "Compute profile ref. count error");
1390 }
1391
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)1392 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1393 {
1394 /*
1395 * TODO: For now, raise the throttling event only on first node.
1396 * This will need to change after we are able to determine
1397 * which node raised the throttling event.
1398 */
1399 if (kfd && kfd->init_complete)
1400 kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1401 throttle_bitmask);
1402 }
1403
1404 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1405 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1406 * When the device has more than two engines, we reserve two for PCIe to enable
1407 * full-duplex and the rest are used as XGMI.
1408 */
kfd_get_num_sdma_engines(struct kfd_node * node)1409 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1410 {
1411 /* If XGMI is not supported, all SDMA engines are PCIe */
1412 if (!node->adev->gmc.xgmi.supported)
1413 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1414
1415 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1416 }
1417
kfd_get_num_xgmi_sdma_engines(struct kfd_node * node)1418 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1419 {
1420 /* After reserved for PCIe, the rest of engines are XGMI */
1421 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1422 kfd_get_num_sdma_engines(node);
1423 }
1424
kgd2kfd_check_and_lock_kfd(void)1425 int kgd2kfd_check_and_lock_kfd(void)
1426 {
1427 mutex_lock(&kfd_processes_mutex);
1428 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {
1429 mutex_unlock(&kfd_processes_mutex);
1430 return -EBUSY;
1431 }
1432
1433 ++kfd_locked;
1434 mutex_unlock(&kfd_processes_mutex);
1435
1436 return 0;
1437 }
1438
kgd2kfd_unlock_kfd(void)1439 void kgd2kfd_unlock_kfd(void)
1440 {
1441 mutex_lock(&kfd_processes_mutex);
1442 --kfd_locked;
1443 mutex_unlock(&kfd_processes_mutex);
1444 }
1445
kgd2kfd_start_sched(struct kfd_dev * kfd,uint32_t node_id)1446 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)
1447 {
1448 struct kfd_node *node;
1449 int ret;
1450
1451 if (!kfd->init_complete)
1452 return 0;
1453
1454 if (node_id >= kfd->num_nodes) {
1455 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1456 node_id, kfd->num_nodes - 1);
1457 return -EINVAL;
1458 }
1459 node = kfd->nodes[node_id];
1460
1461 ret = node->dqm->ops.unhalt(node->dqm);
1462 if (ret)
1463 dev_err(kfd_device, "Error in starting scheduler\n");
1464
1465 return ret;
1466 }
1467
kgd2kfd_stop_sched(struct kfd_dev * kfd,uint32_t node_id)1468 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)
1469 {
1470 struct kfd_node *node;
1471
1472 if (!kfd->init_complete)
1473 return 0;
1474
1475 if (node_id >= kfd->num_nodes) {
1476 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1477 node_id, kfd->num_nodes - 1);
1478 return -EINVAL;
1479 }
1480
1481 node = kfd->nodes[node_id];
1482 return node->dqm->ops.halt(node->dqm);
1483 }
1484
1485 #if defined(CONFIG_DEBUG_FS)
1486
1487 /* This function will send a package to HIQ to hang the HWS
1488 * which will trigger a GPU reset and bring the HWS back to normal state
1489 */
kfd_debugfs_hang_hws(struct kfd_node * dev)1490 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1491 {
1492 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1493 pr_err("HWS is not enabled");
1494 return -EINVAL;
1495 }
1496
1497 if (dev->kfd->shared_resources.enable_mes) {
1498 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n");
1499 return -EINVAL;
1500 }
1501
1502 return dqm_debugfs_hang_hws(dev->dqm);
1503 }
1504
1505 #endif
1506