1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_blend.h>
29 #include <drm/drm_gem_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_gem_framebuffer_helper.h>
32 #include <drm/drm_fourcc.h>
33
34 #include "amdgpu.h"
35 #include "dal_asic_id.h"
36 #include "amdgpu_display.h"
37 #include "amdgpu_dm_trace.h"
38 #include "amdgpu_dm_plane.h"
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41
42 /*
43 * TODO: these are currently initialized to rgb formats only.
44 * For future use cases we should either initialize them dynamically based on
45 * plane capabilities, or initialize this array to all formats, so internal drm
46 * check will succeed, and let DC implement proper check
47 */
48 static const uint32_t rgb_formats[] = {
49 DRM_FORMAT_XRGB8888,
50 DRM_FORMAT_ARGB8888,
51 DRM_FORMAT_RGBA8888,
52 DRM_FORMAT_XRGB2101010,
53 DRM_FORMAT_XBGR2101010,
54 DRM_FORMAT_ARGB2101010,
55 DRM_FORMAT_ABGR2101010,
56 DRM_FORMAT_XRGB16161616,
57 DRM_FORMAT_XBGR16161616,
58 DRM_FORMAT_ARGB16161616,
59 DRM_FORMAT_ABGR16161616,
60 DRM_FORMAT_XBGR8888,
61 DRM_FORMAT_ABGR8888,
62 DRM_FORMAT_RGB565,
63 };
64
65 static const uint32_t overlay_formats[] = {
66 DRM_FORMAT_XRGB8888,
67 DRM_FORMAT_ARGB8888,
68 DRM_FORMAT_RGBA8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_ABGR8888,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_NV21,
73 DRM_FORMAT_NV12,
74 DRM_FORMAT_P010
75 };
76
77 static const uint32_t video_formats[] = {
78 DRM_FORMAT_NV21,
79 DRM_FORMAT_NV12,
80 DRM_FORMAT_P010
81 };
82
83 static const u32 cursor_formats[] = {
84 DRM_FORMAT_ARGB8888
85 };
86
87 enum dm_micro_swizzle {
88 MICRO_SWIZZLE_Z = 0,
89 MICRO_SWIZZLE_S = 1,
90 MICRO_SWIZZLE_D = 2,
91 MICRO_SWIZZLE_R = 3
92 };
93
amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 * cmd)94 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
95 {
96 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
97 }
98
amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state * plane_state,bool * per_pixel_alpha,bool * pre_multiplied_alpha,bool * global_alpha,int * global_alpha_value)99 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
100 bool *per_pixel_alpha, bool *pre_multiplied_alpha,
101 bool *global_alpha, int *global_alpha_value)
102 {
103 *per_pixel_alpha = false;
104 *pre_multiplied_alpha = true;
105 *global_alpha = false;
106 *global_alpha_value = 0xff;
107
108
109 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||
110 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
111 static const uint32_t alpha_formats[] = {
112 DRM_FORMAT_ARGB8888,
113 DRM_FORMAT_RGBA8888,
114 DRM_FORMAT_ABGR8888,
115 DRM_FORMAT_ARGB2101010,
116 DRM_FORMAT_ABGR2101010,
117 DRM_FORMAT_ARGB16161616,
118 DRM_FORMAT_ABGR16161616,
119 DRM_FORMAT_ARGB16161616F,
120 };
121 uint32_t format = plane_state->fb->format->format;
122 unsigned int i;
123
124 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
125 if (format == alpha_formats[i]) {
126 *per_pixel_alpha = true;
127 break;
128 }
129 }
130
131 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
132 *pre_multiplied_alpha = false;
133 }
134
135 if (plane_state->alpha < 0xffff) {
136 *global_alpha = true;
137 *global_alpha_value = plane_state->alpha >> 8;
138 }
139 }
140
amdgpu_dm_plane_add_modifier(uint64_t ** mods,uint64_t * size,uint64_t * cap,uint64_t mod)141 static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
142 {
143 if (!*mods)
144 return;
145
146 if (*cap - *size < 1) {
147 uint64_t new_cap = *cap * 2;
148 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
149
150 if (!new_mods) {
151 kfree(*mods);
152 *mods = NULL;
153 return;
154 }
155
156 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
157 kfree(*mods);
158 *mods = new_mods;
159 *cap = new_cap;
160 }
161
162 (*mods)[*size] = mod;
163 *size += 1;
164 }
165
amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)166 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
167 {
168 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
169 }
170
amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier)171 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier)
172 {
173 if (modifier == DRM_FORMAT_MOD_LINEAR)
174 return 0;
175
176 return AMD_FMT_MOD_GET(TILE, modifier);
177 }
178
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info * tiling_info,uint64_t tiling_flags)179 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
180 uint64_t tiling_flags)
181 {
182 /* Fill GFX8 params */
183 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
184 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
185
186 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
187 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
188 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
189 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
190 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
191
192 /* XXX fix me for VI */
193 tiling_info->gfx8.num_banks = num_banks;
194 tiling_info->gfx8.array_mode =
195 DC_ARRAY_2D_TILED_THIN1;
196 tiling_info->gfx8.tile_split = tile_split;
197 tiling_info->gfx8.bank_width = bankw;
198 tiling_info->gfx8.bank_height = bankh;
199 tiling_info->gfx8.tile_aspect = mtaspect;
200 tiling_info->gfx8.tile_mode =
201 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
202 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
203 == DC_ARRAY_1D_TILED_THIN1) {
204 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
205 }
206
207 tiling_info->gfx8.pipe_config =
208 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
209 }
210
amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device * adev,union dc_tiling_info * tiling_info)211 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
212 union dc_tiling_info *tiling_info)
213 {
214 /* Fill GFX9 params */
215 tiling_info->gfx9.num_pipes =
216 adev->gfx.config.gb_addr_config_fields.num_pipes;
217 tiling_info->gfx9.num_banks =
218 adev->gfx.config.gb_addr_config_fields.num_banks;
219 tiling_info->gfx9.pipe_interleave =
220 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
221 tiling_info->gfx9.num_shader_engines =
222 adev->gfx.config.gb_addr_config_fields.num_se;
223 tiling_info->gfx9.max_compressed_frags =
224 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
225 tiling_info->gfx9.num_rb_per_se =
226 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
227 tiling_info->gfx9.shaderEnable = 1;
228 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
229 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
230 }
231
amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device * adev,union dc_tiling_info * tiling_info,uint64_t modifier)232 static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
233 union dc_tiling_info *tiling_info,
234 uint64_t modifier)
235 {
236 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
237 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
238 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
239 unsigned int pipes_log2;
240
241 pipes_log2 = min(5u, mod_pipe_xor_bits);
242
243 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
244
245 if (!IS_AMD_FMT_MOD(modifier))
246 return;
247
248 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
249 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
250
251 if (adev->family >= AMDGPU_FAMILY_NV) {
252 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
253 } else {
254 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
255
256 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
257 }
258 }
259
amdgpu_dm_plane_validate_dcc(struct amdgpu_device * adev,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const union dc_tiling_info * tiling_info,const struct dc_plane_dcc_param * dcc,const struct dc_plane_address * address,const struct plane_size * plane_size)260 static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
261 const enum surface_pixel_format format,
262 const enum dc_rotation_angle rotation,
263 const union dc_tiling_info *tiling_info,
264 const struct dc_plane_dcc_param *dcc,
265 const struct dc_plane_address *address,
266 const struct plane_size *plane_size)
267 {
268 struct dc *dc = adev->dm.dc;
269 struct dc_dcc_surface_param input;
270 struct dc_surface_dcc_cap output;
271
272 memset(&input, 0, sizeof(input));
273 memset(&output, 0, sizeof(output));
274
275 if (!dcc->enable)
276 return 0;
277
278 if (adev->family < AMDGPU_FAMILY_GC_12_0_0 &&
279 format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
280 return -EINVAL;
281
282 if (!dc->cap_funcs.get_dcc_compression_cap)
283 return -EINVAL;
284
285 input.format = format;
286 input.surface_size.width = plane_size->surface_size.width;
287 input.surface_size.height = plane_size->surface_size.height;
288 input.swizzle_mode = tiling_info->gfx9.swizzle;
289
290 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
291 input.scan = SCAN_DIRECTION_HORIZONTAL;
292 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
293 input.scan = SCAN_DIRECTION_VERTICAL;
294
295 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
296 return -EINVAL;
297
298 if (!output.capable)
299 return -EINVAL;
300
301 if (dcc->independent_64b_blks == 0 &&
302 output.grph.rgb.independent_64b_blks != 0)
303 return -EINVAL;
304
305 return 0;
306 }
307
amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const struct plane_size * plane_size,union dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)308 static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
309 const struct amdgpu_framebuffer *afb,
310 const enum surface_pixel_format format,
311 const enum dc_rotation_angle rotation,
312 const struct plane_size *plane_size,
313 union dc_tiling_info *tiling_info,
314 struct dc_plane_dcc_param *dcc,
315 struct dc_plane_address *address)
316 {
317 const uint64_t modifier = afb->base.modifier;
318 int ret = 0;
319
320 amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
321 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
322
323 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
324 uint64_t dcc_address = afb->address + afb->base.offsets[1];
325 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
326 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
327
328 dcc->enable = 1;
329 dcc->meta_pitch = afb->base.pitches[1];
330 dcc->independent_64b_blks = independent_64b_blks;
331 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
332 if (independent_64b_blks && independent_128b_blks)
333 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
334 else if (independent_128b_blks)
335 dcc->dcc_ind_blk = hubp_ind_block_128b;
336 else if (independent_64b_blks && !independent_128b_blks)
337 dcc->dcc_ind_blk = hubp_ind_block_64b;
338 else
339 dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
340 } else {
341 if (independent_64b_blks)
342 dcc->dcc_ind_blk = hubp_ind_block_64b;
343 else
344 dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
345 }
346
347 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
348 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
349 }
350
351 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
352 if (ret)
353 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret);
354
355 return ret;
356 }
357
amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const struct plane_size * plane_size,union dc_tiling_info * tiling_info,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address)358 static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev,
359 const struct amdgpu_framebuffer *afb,
360 const enum surface_pixel_format format,
361 const enum dc_rotation_angle rotation,
362 const struct plane_size *plane_size,
363 union dc_tiling_info *tiling_info,
364 struct dc_plane_dcc_param *dcc,
365 struct dc_plane_address *address)
366 {
367 const uint64_t modifier = afb->base.modifier;
368 int ret = 0;
369
370 /* TODO: Most of this function shouldn't be needed on GFX12. */
371 amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
372
373 tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
374
375 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
376 int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
377
378 dcc->enable = 1;
379 dcc->independent_64b_blks = max_compressed_block == 0;
380
381 if (max_compressed_block == 0)
382 dcc->dcc_ind_blk = hubp_ind_block_64b;
383 else if (max_compressed_block == 1)
384 dcc->dcc_ind_blk = hubp_ind_block_128b;
385 else
386 dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
387 }
388
389 /* TODO: This seems wrong because there is no DCC plane on GFX12. */
390 ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
391 if (ret)
392 drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret);
393
394 return ret;
395 }
396
amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device * adev,uint64_t ** mods,uint64_t * size,uint64_t * capacity)397 static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev,
398 uint64_t **mods,
399 uint64_t *size,
400 uint64_t *capacity)
401 {
402 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
403
404 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
405 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
406 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
407 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
408 AMD_FMT_MOD_SET(DCC, 1) |
409 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
410 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
411 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
412
413 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
414 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
415 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
416 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
417 AMD_FMT_MOD_SET(DCC, 1) |
418 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
419 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
420 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
421 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
422
423 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
424 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
425 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
426 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
427
428 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
429 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
430 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
431 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
432
433
434 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */
435 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
436 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
437 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
438
439 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
440 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
441 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
442 }
443
amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device * adev,uint64_t ** mods,uint64_t * size,uint64_t * capacity)444 static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev,
445 uint64_t **mods,
446 uint64_t *size,
447 uint64_t *capacity)
448 {
449 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
450 int pipe_xor_bits = min(8, pipes +
451 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
452 int bank_xor_bits = min(8 - pipe_xor_bits,
453 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
454 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
455 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
456
457
458 if (adev->family == AMDGPU_FAMILY_RV) {
459 /* Raven2 and later */
460 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
461
462 /*
463 * No _D DCC swizzles yet because we only allow 32bpp, which
464 * doesn't support _D on DCN
465 */
466
467 if (has_constant_encode) {
468 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
469 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
470 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
471 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
472 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
473 AMD_FMT_MOD_SET(DCC, 1) |
474 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
475 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
476 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
477 }
478
479 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
480 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
481 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
482 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
483 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
484 AMD_FMT_MOD_SET(DCC, 1) |
485 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
486 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
487 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
488
489 if (has_constant_encode) {
490 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
491 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
492 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
493 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
494 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
495 AMD_FMT_MOD_SET(DCC, 1) |
496 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
497 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
498 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
499 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
500 AMD_FMT_MOD_SET(RB, rb) |
501 AMD_FMT_MOD_SET(PIPE, pipes));
502 }
503
504 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
505 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
506 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
507 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
508 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
509 AMD_FMT_MOD_SET(DCC, 1) |
510 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
511 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
512 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
513 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
514 AMD_FMT_MOD_SET(RB, rb) |
515 AMD_FMT_MOD_SET(PIPE, pipes));
516 }
517
518 /*
519 * Only supported for 64bpp on Raven, will be filtered on format in
520 * amdgpu_dm_plane_format_mod_supported.
521 */
522 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
523 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
524 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
525 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
526 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
527
528 if (adev->family == AMDGPU_FAMILY_RV) {
529 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
530 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
531 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
532 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
533 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
534 }
535
536 /*
537 * Only supported for 64bpp on Raven, will be filtered on format in
538 * amdgpu_dm_plane_format_mod_supported.
539 */
540 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
541 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
542 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
543
544 if (adev->family == AMDGPU_FAMILY_RV) {
545 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
546 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
547 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
548 }
549 }
550
amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device * adev,uint64_t ** mods,uint64_t * size,uint64_t * capacity)551 static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev,
552 uint64_t **mods,
553 uint64_t *size,
554 uint64_t *capacity)
555 {
556 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
557 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
558
559 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
560 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
561 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
562 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
563 AMD_FMT_MOD_SET(PACKERS, pkrs) |
564 AMD_FMT_MOD_SET(DCC, 1) |
565 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
566 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
567 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
568 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
569
570 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
571 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
572 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
573 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
574 AMD_FMT_MOD_SET(PACKERS, pkrs) |
575 AMD_FMT_MOD_SET(DCC, 1) |
576 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
577 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
578 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
579
580 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
581 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
582 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
583 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
584 AMD_FMT_MOD_SET(PACKERS, pkrs) |
585 AMD_FMT_MOD_SET(DCC, 1) |
586 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
587 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
588 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
589 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
590 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
591
592 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
593 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
594 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
595 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
596 AMD_FMT_MOD_SET(PACKERS, pkrs) |
597 AMD_FMT_MOD_SET(DCC, 1) |
598 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
599 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
600 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
601 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
602
603 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
604 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
605 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
606 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
607 AMD_FMT_MOD_SET(PACKERS, pkrs));
608
609 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
610 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
611 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
612 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
613 AMD_FMT_MOD_SET(PACKERS, pkrs));
614
615 /* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */
616 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
617 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
618 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
619
620 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
621 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
622 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
623 }
624
amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device * adev,uint64_t ** mods,uint64_t * size,uint64_t * capacity)625 static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev,
626 uint64_t **mods, uint64_t *size, uint64_t *capacity)
627 {
628 int num_pipes = 0;
629 int pipe_xor_bits = 0;
630 int num_pkrs = 0;
631 int pkrs = 0;
632 u32 gb_addr_config;
633 u8 i = 0;
634 unsigned int swizzle_r_x;
635 uint64_t modifier_r_x;
636 uint64_t modifier_dcc_best;
637 uint64_t modifier_dcc_4k;
638
639 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from
640 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes}
641 */
642 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
643 ASSERT(gb_addr_config != 0);
644
645 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
646 pkrs = ilog2(num_pkrs);
647 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
648 pipe_xor_bits = ilog2(num_pipes);
649
650 for (i = 0; i < 2; i++) {
651 /* Insert the best one first. */
652 /* R_X swizzle modes are the best for rendering and DCC requires them. */
653 if (num_pipes > 16)
654 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X;
655 else
656 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X;
657
658 modifier_r_x = AMD_FMT_MOD |
659 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
660 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
661 AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
662 AMD_FMT_MOD_SET(PACKERS, pkrs);
663
664 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
665 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
666 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
667 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
668 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
669
670 /* DCC settings for 4K and greater resolutions. (required by display hw) */
671 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
672 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
673 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
674 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
675
676 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best);
677 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k);
678
679 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
680 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
681
682 amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x);
683 }
684
685 amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
686 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
687 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
688 }
689
amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device * adev,uint64_t ** mods,uint64_t * size,uint64_t * capacity)690 static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev,
691 uint64_t **mods, uint64_t *size, uint64_t *capacity)
692 {
693 uint64_t ver = AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12);
694 uint64_t mod_256k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256K_2D);
695 uint64_t mod_64k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D);
696 uint64_t mod_4k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D);
697 uint64_t mod_256b = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D);
698 uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1);
699 uint8_t max_comp_block[] = {1, 0};
700 uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0};
701 uint8_t i = 0, j = 0;
702 uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR};
703
704 for (i = 0; i < ARRAY_SIZE(max_comp_block); i++)
705 max_comp_block_mod[i] = AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block[i]);
706
707 /* With DCC: Best choice should be kept first. Hence, add all 256k modifiers of different
708 * max compressed blocks first and then move on to the next smaller sized layouts.
709 * Do not add the linear modifier here, and hence the condition of size-1 for the loop
710 */
711 for (j = 0; j < ARRAY_SIZE(gfx12_modifiers) - 1; j++)
712 for (i = 0; i < ARRAY_SIZE(max_comp_block); i++)
713 amdgpu_dm_plane_add_modifier(mods, size, capacity,
714 ver | dcc | max_comp_block_mod[i] | gfx12_modifiers[j]);
715
716 /* Without DCC. Add all modifiers including linear at the end */
717 for (i = 0; i < ARRAY_SIZE(gfx12_modifiers); i++)
718 amdgpu_dm_plane_add_modifier(mods, size, capacity, gfx12_modifiers[i]);
719
720 }
721
amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device * adev,unsigned int plane_type,uint64_t ** mods)722 static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
723 {
724 uint64_t size = 0, capacity = 128;
725 *mods = NULL;
726
727 /* We have not hooked up any pre-GFX9 modifiers. */
728 if (adev->family < AMDGPU_FAMILY_AI)
729 return 0;
730
731 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
732
733 if (plane_type == DRM_PLANE_TYPE_CURSOR) {
734 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
735 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
736 return *mods ? 0 : -ENOMEM;
737 }
738
739 switch (adev->family) {
740 case AMDGPU_FAMILY_AI:
741 case AMDGPU_FAMILY_RV:
742 amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity);
743 break;
744 case AMDGPU_FAMILY_NV:
745 case AMDGPU_FAMILY_VGH:
746 case AMDGPU_FAMILY_YC:
747 case AMDGPU_FAMILY_GC_10_3_6:
748 case AMDGPU_FAMILY_GC_10_3_7:
749 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
750 amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity);
751 else
752 amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity);
753 break;
754 case AMDGPU_FAMILY_GC_11_0_0:
755 case AMDGPU_FAMILY_GC_11_0_1:
756 case AMDGPU_FAMILY_GC_11_5_0:
757 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity);
758 break;
759 case AMDGPU_FAMILY_GC_12_0_0:
760 amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &size, &capacity);
761 break;
762 }
763
764 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
765
766 /* INVALID marks the end of the list. */
767 amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
768
769 if (!*mods)
770 return -ENOMEM;
771
772 return 0;
773 }
774
amdgpu_dm_plane_get_plane_formats(const struct drm_plane * plane,const struct dc_plane_cap * plane_cap,uint32_t * formats,int max_formats)775 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane,
776 const struct dc_plane_cap *plane_cap,
777 uint32_t *formats, int max_formats)
778 {
779 int i, num_formats = 0;
780
781 /*
782 * TODO: Query support for each group of formats directly from
783 * DC plane caps. This will require adding more formats to the
784 * caps list.
785 */
786
787 if (plane->type == DRM_PLANE_TYPE_PRIMARY ||
788 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) {
789 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
790 if (num_formats >= max_formats)
791 break;
792
793 formats[num_formats++] = rgb_formats[i];
794 }
795
796 if (plane_cap && plane_cap->pixel_format_support.nv12)
797 formats[num_formats++] = DRM_FORMAT_NV12;
798 if (plane_cap && plane_cap->pixel_format_support.p010)
799 formats[num_formats++] = DRM_FORMAT_P010;
800 if (plane_cap && plane_cap->pixel_format_support.fp16) {
801 formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
802 formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
803 formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
804 formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
805 }
806 } else {
807 switch (plane->type) {
808 case DRM_PLANE_TYPE_OVERLAY:
809 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
810 if (num_formats >= max_formats)
811 break;
812
813 formats[num_formats++] = overlay_formats[i];
814 }
815 break;
816
817 case DRM_PLANE_TYPE_CURSOR:
818 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
819 if (num_formats >= max_formats)
820 break;
821
822 formats[num_formats++] = cursor_formats[i];
823 }
824 break;
825
826 default:
827 break;
828 }
829 }
830
831 return num_formats;
832 }
833
amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device * adev,const struct amdgpu_framebuffer * afb,const enum surface_pixel_format format,const enum dc_rotation_angle rotation,const uint64_t tiling_flags,union dc_tiling_info * tiling_info,struct plane_size * plane_size,struct dc_plane_dcc_param * dcc,struct dc_plane_address * address,bool tmz_surface)834 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
835 const struct amdgpu_framebuffer *afb,
836 const enum surface_pixel_format format,
837 const enum dc_rotation_angle rotation,
838 const uint64_t tiling_flags,
839 union dc_tiling_info *tiling_info,
840 struct plane_size *plane_size,
841 struct dc_plane_dcc_param *dcc,
842 struct dc_plane_address *address,
843 bool tmz_surface)
844 {
845 const struct drm_framebuffer *fb = &afb->base;
846 int ret;
847
848 memset(tiling_info, 0, sizeof(*tiling_info));
849 memset(plane_size, 0, sizeof(*plane_size));
850 memset(dcc, 0, sizeof(*dcc));
851 memset(address, 0, sizeof(*address));
852
853 address->tmz_surface = tmz_surface;
854
855 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
856 uint64_t addr = afb->address + fb->offsets[0];
857
858 plane_size->surface_size.x = 0;
859 plane_size->surface_size.y = 0;
860 plane_size->surface_size.width = fb->width;
861 plane_size->surface_size.height = fb->height;
862 plane_size->surface_pitch =
863 fb->pitches[0] / fb->format->cpp[0];
864
865 address->type = PLN_ADDR_TYPE_GRAPHICS;
866 address->grph.addr.low_part = lower_32_bits(addr);
867 address->grph.addr.high_part = upper_32_bits(addr);
868 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
869 uint64_t luma_addr = afb->address + fb->offsets[0];
870 uint64_t chroma_addr = afb->address + fb->offsets[1];
871
872 plane_size->surface_size.x = 0;
873 plane_size->surface_size.y = 0;
874 plane_size->surface_size.width = fb->width;
875 plane_size->surface_size.height = fb->height;
876 plane_size->surface_pitch =
877 fb->pitches[0] / fb->format->cpp[0];
878
879 plane_size->chroma_size.x = 0;
880 plane_size->chroma_size.y = 0;
881 /* TODO: set these based on surface format */
882 plane_size->chroma_size.width = fb->width / 2;
883 plane_size->chroma_size.height = fb->height / 2;
884
885 plane_size->chroma_pitch =
886 fb->pitches[1] / fb->format->cpp[1];
887
888 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
889 address->video_progressive.luma_addr.low_part =
890 lower_32_bits(luma_addr);
891 address->video_progressive.luma_addr.high_part =
892 upper_32_bits(luma_addr);
893 address->video_progressive.chroma_addr.low_part =
894 lower_32_bits(chroma_addr);
895 address->video_progressive.chroma_addr.high_part =
896 upper_32_bits(chroma_addr);
897 }
898
899 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) {
900 ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format,
901 rotation, plane_size,
902 tiling_info, dcc,
903 address);
904 if (ret)
905 return ret;
906 } else if (adev->family >= AMDGPU_FAMILY_AI) {
907 ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
908 rotation, plane_size,
909 tiling_info, dcc,
910 address);
911 if (ret)
912 return ret;
913 } else {
914 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
915 }
916
917 return 0;
918 }
919
amdgpu_dm_plane_helper_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)920 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
921 struct drm_plane_state *new_state)
922 {
923 struct amdgpu_framebuffer *afb;
924 struct drm_gem_object *obj;
925 struct amdgpu_device *adev;
926 struct amdgpu_bo *rbo;
927 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
928 uint32_t domain;
929 int r;
930
931 if (!new_state->fb) {
932 DRM_DEBUG_KMS("No FB bound\n");
933 return 0;
934 }
935
936 afb = to_amdgpu_framebuffer(new_state->fb);
937 obj = drm_gem_fb_get_obj(new_state->fb, 0);
938 if (!obj) {
939 DRM_ERROR("Failed to get obj from framebuffer\n");
940 return -EINVAL;
941 }
942
943 rbo = gem_to_amdgpu_bo(obj);
944 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
945 r = amdgpu_bo_reserve(rbo, true);
946 if (r) {
947 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
948 return r;
949 }
950
951 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
952 if (r) {
953 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r);
954 goto error_unlock;
955 }
956
957 if (plane->type != DRM_PLANE_TYPE_CURSOR)
958 domain = amdgpu_display_supported_domains(adev, rbo->flags);
959 else
960 domain = AMDGPU_GEM_DOMAIN_VRAM;
961
962 rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
963 r = amdgpu_bo_pin(rbo, domain);
964 if (unlikely(r != 0)) {
965 if (r != -ERESTARTSYS)
966 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
967 goto error_unlock;
968 }
969
970 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
971 if (unlikely(r != 0)) {
972 DRM_ERROR("%p bind failed\n", rbo);
973 goto error_unpin;
974 }
975
976 r = drm_gem_plane_helper_prepare_fb(plane, new_state);
977 if (unlikely(r != 0))
978 goto error_unpin;
979
980 amdgpu_bo_unreserve(rbo);
981
982 afb->address = amdgpu_bo_gpu_offset(rbo);
983
984 amdgpu_bo_ref(rbo);
985
986 /**
987 * We don't do surface updates on planes that have been newly created,
988 * but we also don't have the afb->address during atomic check.
989 *
990 * Fill in buffer attributes depending on the address here, but only on
991 * newly created planes since they're not being used by DC yet and this
992 * won't modify global state.
993 */
994 dm_plane_state_old = to_dm_plane_state(plane->state);
995 dm_plane_state_new = to_dm_plane_state(new_state);
996
997 if (dm_plane_state_new->dc_state &&
998 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
999 struct dc_plane_state *plane_state =
1000 dm_plane_state_new->dc_state;
1001
1002 amdgpu_dm_plane_fill_plane_buffer_attributes(
1003 adev, afb, plane_state->format, plane_state->rotation,
1004 afb->tiling_flags,
1005 &plane_state->tiling_info, &plane_state->plane_size,
1006 &plane_state->dcc, &plane_state->address,
1007 afb->tmz_surface);
1008 }
1009
1010 return 0;
1011
1012 error_unpin:
1013 amdgpu_bo_unpin(rbo);
1014
1015 error_unlock:
1016 amdgpu_bo_unreserve(rbo);
1017 return r;
1018 }
1019
amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)1020 static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane,
1021 struct drm_plane_state *old_state)
1022 {
1023 struct amdgpu_bo *rbo;
1024 int r;
1025
1026 if (!old_state->fb)
1027 return;
1028
1029 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
1030 r = amdgpu_bo_reserve(rbo, false);
1031 if (unlikely(r)) {
1032 DRM_ERROR("failed to reserve rbo before unpin\n");
1033 return;
1034 }
1035
1036 amdgpu_bo_unpin(rbo);
1037 amdgpu_bo_unreserve(rbo);
1038 amdgpu_bo_unref(&rbo);
1039 }
1040
amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device * dev,struct drm_framebuffer * fb,int * min_downscale,int * max_upscale)1041 static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev,
1042 struct drm_framebuffer *fb,
1043 int *min_downscale, int *max_upscale)
1044 {
1045 struct amdgpu_device *adev = drm_to_adev(dev);
1046 struct dc *dc = adev->dm.dc;
1047 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
1048 struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
1049
1050 switch (fb->format->format) {
1051 case DRM_FORMAT_P010:
1052 case DRM_FORMAT_NV12:
1053 case DRM_FORMAT_NV21:
1054 *max_upscale = plane_cap->max_upscale_factor.nv12;
1055 *min_downscale = plane_cap->max_downscale_factor.nv12;
1056 break;
1057
1058 case DRM_FORMAT_XRGB16161616F:
1059 case DRM_FORMAT_ARGB16161616F:
1060 case DRM_FORMAT_XBGR16161616F:
1061 case DRM_FORMAT_ABGR16161616F:
1062 *max_upscale = plane_cap->max_upscale_factor.fp16;
1063 *min_downscale = plane_cap->max_downscale_factor.fp16;
1064 break;
1065
1066 default:
1067 *max_upscale = plane_cap->max_upscale_factor.argb8888;
1068 *min_downscale = plane_cap->max_downscale_factor.argb8888;
1069 break;
1070 }
1071
1072 /*
1073 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
1074 * scaling factor of 1.0 == 1000 units.
1075 */
1076 if (*max_upscale == 1)
1077 *max_upscale = 1000;
1078
1079 if (*min_downscale == 1)
1080 *min_downscale = 1000;
1081 }
1082
amdgpu_dm_plane_helper_check_state(struct drm_plane_state * state,struct drm_crtc_state * new_crtc_state)1083 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state,
1084 struct drm_crtc_state *new_crtc_state)
1085 {
1086 struct drm_framebuffer *fb = state->fb;
1087 int min_downscale, max_upscale;
1088 int min_scale = 0;
1089 int max_scale = INT_MAX;
1090
1091 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
1092 if (fb && state->crtc) {
1093 /* Validate viewport to cover the case when only the position changes */
1094 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
1095 int viewport_width = state->crtc_w;
1096 int viewport_height = state->crtc_h;
1097
1098 if (state->crtc_x < 0)
1099 viewport_width += state->crtc_x;
1100 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
1101 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
1102
1103 if (state->crtc_y < 0)
1104 viewport_height += state->crtc_y;
1105 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
1106 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
1107
1108 if (viewport_width < 0 || viewport_height < 0) {
1109 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n");
1110 return -EINVAL;
1111 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */
1112 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2);
1113 return -EINVAL;
1114 } else if (viewport_height < MIN_VIEWPORT_SIZE) {
1115 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE);
1116 return -EINVAL;
1117 }
1118
1119 }
1120
1121 /* Get min/max allowed scaling factors from plane caps. */
1122 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb,
1123 &min_downscale, &max_upscale);
1124 /*
1125 * Convert to drm convention: 16.16 fixed point, instead of dc's
1126 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
1127 * dst/src, so min_scale = 1.0 / max_upscale, etc.
1128 */
1129 min_scale = (1000 << 16) / max_upscale;
1130 max_scale = (1000 << 16) / min_downscale;
1131 }
1132
1133 return drm_atomic_helper_check_plane_state(
1134 state, new_crtc_state, min_scale, max_scale, true, true);
1135 }
1136
amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device * adev,const struct drm_plane_state * state,struct dc_scaling_info * scaling_info)1137 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev,
1138 const struct drm_plane_state *state,
1139 struct dc_scaling_info *scaling_info)
1140 {
1141 int scale_w, scale_h, min_downscale, max_upscale;
1142
1143 memset(scaling_info, 0, sizeof(*scaling_info));
1144
1145 /* Source is fixed 16.16 but we ignore mantissa for now... */
1146 scaling_info->src_rect.x = state->src_x >> 16;
1147 scaling_info->src_rect.y = state->src_y >> 16;
1148
1149 /*
1150 * For reasons we don't (yet) fully understand a non-zero
1151 * src_y coordinate into an NV12 buffer can cause a
1152 * system hang on DCN1x.
1153 * To avoid hangs (and maybe be overly cautious)
1154 * let's reject both non-zero src_x and src_y.
1155 *
1156 * We currently know of only one use-case to reproduce a
1157 * scenario with non-zero src_x and src_y for NV12, which
1158 * is to gesture the YouTube Android app into full screen
1159 * on ChromeOS.
1160 */
1161 if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1162 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) &&
1163 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 &&
1164 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0)))
1165 return -EINVAL;
1166
1167 scaling_info->src_rect.width = state->src_w >> 16;
1168 if (scaling_info->src_rect.width == 0)
1169 return -EINVAL;
1170
1171 scaling_info->src_rect.height = state->src_h >> 16;
1172 if (scaling_info->src_rect.height == 0)
1173 return -EINVAL;
1174
1175 scaling_info->dst_rect.x = state->crtc_x;
1176 scaling_info->dst_rect.y = state->crtc_y;
1177
1178 if (state->crtc_w == 0)
1179 return -EINVAL;
1180
1181 scaling_info->dst_rect.width = state->crtc_w;
1182
1183 if (state->crtc_h == 0)
1184 return -EINVAL;
1185
1186 scaling_info->dst_rect.height = state->crtc_h;
1187
1188 /* DRM doesn't specify clipping on destination output. */
1189 scaling_info->clip_rect = scaling_info->dst_rect;
1190
1191 /* Validate scaling per-format with DC plane caps */
1192 if (state->plane && state->plane->dev && state->fb) {
1193 amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
1194 &min_downscale, &max_upscale);
1195 } else {
1196 min_downscale = 250;
1197 max_upscale = 16000;
1198 }
1199
1200 scale_w = scaling_info->dst_rect.width * 1000 /
1201 scaling_info->src_rect.width;
1202
1203 if (scale_w < min_downscale || scale_w > max_upscale)
1204 return -EINVAL;
1205
1206 scale_h = scaling_info->dst_rect.height * 1000 /
1207 scaling_info->src_rect.height;
1208
1209 if (scale_h < min_downscale || scale_h > max_upscale)
1210 return -EINVAL;
1211
1212 /*
1213 * The "scaling_quality" can be ignored for now, quality = 0 has DC
1214 * assume reasonable defaults based on the format.
1215 */
1216
1217 return 0;
1218 }
1219
amdgpu_dm_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)1220 static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,
1221 struct drm_atomic_state *state)
1222 {
1223 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1224 plane);
1225 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1226 struct dc *dc = adev->dm.dc;
1227 struct dm_plane_state *dm_plane_state;
1228 struct dc_scaling_info scaling_info;
1229 struct drm_crtc_state *new_crtc_state;
1230 int ret;
1231
1232 trace_amdgpu_dm_plane_atomic_check(new_plane_state);
1233
1234 dm_plane_state = to_dm_plane_state(new_plane_state);
1235
1236 if (!dm_plane_state->dc_state)
1237 return 0;
1238
1239 new_crtc_state =
1240 drm_atomic_get_new_crtc_state(state,
1241 new_plane_state->crtc);
1242 if (!new_crtc_state)
1243 return -EINVAL;
1244
1245 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
1246 if (ret)
1247 return ret;
1248
1249 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info);
1250 if (ret)
1251 return ret;
1252
1253 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
1254 return 0;
1255
1256 return -EINVAL;
1257 }
1258
amdgpu_dm_plane_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state)1259 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,
1260 struct drm_atomic_state *state)
1261 {
1262 struct drm_crtc_state *new_crtc_state;
1263 struct drm_plane_state *new_plane_state;
1264 struct dm_crtc_state *dm_new_crtc_state;
1265
1266 /* Only support async updates on cursor planes. */
1267 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1268 return -EINVAL;
1269
1270 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
1271 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
1272 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1273 /* Reject overlay cursors for now*/
1274 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)
1275 return -EINVAL;
1276
1277 return 0;
1278 }
1279
amdgpu_dm_plane_get_cursor_position(struct drm_plane * plane,struct drm_crtc * crtc,struct dc_cursor_position * position)1280 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
1281 struct dc_cursor_position *position)
1282 {
1283 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1284 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1285 int x, y;
1286 int xorigin = 0, yorigin = 0;
1287
1288 if (!crtc || !plane->state->fb)
1289 return 0;
1290
1291 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
1292 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
1293 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
1294 __func__,
1295 plane->state->crtc_w,
1296 plane->state->crtc_h);
1297 return -EINVAL;
1298 }
1299
1300 x = plane->state->crtc_x;
1301 y = plane->state->crtc_y;
1302
1303 if (x <= -amdgpu_crtc->max_cursor_width ||
1304 y <= -amdgpu_crtc->max_cursor_height)
1305 return 0;
1306
1307 if (x < 0) {
1308 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1309 x = 0;
1310 }
1311 if (y < 0) {
1312 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1313 y = 0;
1314 }
1315 position->enable = true;
1316 position->x = x;
1317 position->y = y;
1318 position->x_hotspot = xorigin;
1319 position->y_hotspot = yorigin;
1320
1321 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(4, 0, 1))
1322 position->translate_by_source = true;
1323
1324 return 0;
1325 }
1326
amdgpu_dm_plane_handle_cursor_update(struct drm_plane * plane,struct drm_plane_state * old_plane_state)1327 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
1328 struct drm_plane_state *old_plane_state)
1329 {
1330 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1331 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
1332 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
1333 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
1334 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1335 uint64_t address = afb ? afb->address : 0;
1336 struct dc_cursor_position position = {0};
1337 struct dc_cursor_attributes attributes;
1338 int ret;
1339
1340 if (!plane->state->fb && !old_plane_state->fb)
1341 return;
1342
1343 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n",
1344 amdgpu_crtc->crtc_id, plane->state->crtc_w,
1345 plane->state->crtc_h);
1346
1347 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);
1348 if (ret)
1349 return;
1350
1351 if (!position.enable) {
1352 /* turn off cursor */
1353 if (crtc_state && crtc_state->stream) {
1354 mutex_lock(&adev->dm.dc_lock);
1355 dc_stream_program_cursor_position(crtc_state->stream,
1356 &position);
1357 mutex_unlock(&adev->dm.dc_lock);
1358 }
1359 return;
1360 }
1361
1362 amdgpu_crtc->cursor_width = plane->state->crtc_w;
1363 amdgpu_crtc->cursor_height = plane->state->crtc_h;
1364
1365 memset(&attributes, 0, sizeof(attributes));
1366 attributes.address.high_part = upper_32_bits(address);
1367 attributes.address.low_part = lower_32_bits(address);
1368 attributes.width = plane->state->crtc_w;
1369 attributes.height = plane->state->crtc_h;
1370 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
1371 attributes.rotation_angle = 0;
1372 attributes.attribute_flags.value = 0;
1373
1374 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
1375 * legacy gamma setup.
1376 */
1377 if (crtc_state->cm_is_degamma_srgb &&
1378 adev->dm.dc->caps.color.dpp.gamma_corr)
1379 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
1380
1381 if (afb)
1382 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
1383
1384 if (crtc_state->stream) {
1385 mutex_lock(&adev->dm.dc_lock);
1386 if (!dc_stream_program_cursor_attributes(crtc_state->stream,
1387 &attributes))
1388 DRM_ERROR("DC failed to set cursor attributes\n");
1389
1390 if (!dc_stream_program_cursor_position(crtc_state->stream,
1391 &position))
1392 DRM_ERROR("DC failed to set cursor position\n");
1393 mutex_unlock(&adev->dm.dc_lock);
1394 }
1395 }
1396
amdgpu_dm_plane_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)1397 static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane,
1398 struct drm_atomic_state *state)
1399 {
1400 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1401 plane);
1402 struct drm_plane_state *old_state =
1403 drm_atomic_get_old_plane_state(state, plane);
1404
1405 trace_amdgpu_dm_atomic_update_cursor(new_state);
1406
1407 swap(plane->state->fb, new_state->fb);
1408
1409 plane->state->src_x = new_state->src_x;
1410 plane->state->src_y = new_state->src_y;
1411 plane->state->src_w = new_state->src_w;
1412 plane->state->src_h = new_state->src_h;
1413 plane->state->crtc_x = new_state->crtc_x;
1414 plane->state->crtc_y = new_state->crtc_y;
1415 plane->state->crtc_w = new_state->crtc_w;
1416 plane->state->crtc_h = new_state->crtc_h;
1417
1418 amdgpu_dm_plane_handle_cursor_update(plane, old_state);
1419 }
1420
1421 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1422 .prepare_fb = amdgpu_dm_plane_helper_prepare_fb,
1423 .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb,
1424 .atomic_check = amdgpu_dm_plane_atomic_check,
1425 .atomic_async_check = amdgpu_dm_plane_atomic_async_check,
1426 .atomic_async_update = amdgpu_dm_plane_atomic_async_update
1427 };
1428
amdgpu_dm_plane_drm_plane_reset(struct drm_plane * plane)1429 static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)
1430 {
1431 struct dm_plane_state *amdgpu_state = NULL;
1432
1433 if (plane->state)
1434 plane->funcs->atomic_destroy_state(plane, plane->state);
1435
1436 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1437 WARN_ON(amdgpu_state == NULL);
1438
1439 if (!amdgpu_state)
1440 return;
1441
1442 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
1443 amdgpu_state->degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
1444 amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT;
1445 amdgpu_state->shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
1446 amdgpu_state->blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
1447 }
1448
amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane * plane)1449 static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane)
1450 {
1451 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
1452
1453 old_dm_plane_state = to_dm_plane_state(plane->state);
1454 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
1455 if (!dm_plane_state)
1456 return NULL;
1457
1458 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
1459
1460 if (old_dm_plane_state->dc_state) {
1461 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
1462 dc_plane_state_retain(dm_plane_state->dc_state);
1463 }
1464
1465 if (old_dm_plane_state->degamma_lut)
1466 dm_plane_state->degamma_lut =
1467 drm_property_blob_get(old_dm_plane_state->degamma_lut);
1468 if (old_dm_plane_state->ctm)
1469 dm_plane_state->ctm =
1470 drm_property_blob_get(old_dm_plane_state->ctm);
1471 if (old_dm_plane_state->shaper_lut)
1472 dm_plane_state->shaper_lut =
1473 drm_property_blob_get(old_dm_plane_state->shaper_lut);
1474 if (old_dm_plane_state->lut3d)
1475 dm_plane_state->lut3d =
1476 drm_property_blob_get(old_dm_plane_state->lut3d);
1477 if (old_dm_plane_state->blend_lut)
1478 dm_plane_state->blend_lut =
1479 drm_property_blob_get(old_dm_plane_state->blend_lut);
1480
1481 dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
1482 dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
1483 dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf;
1484 dm_plane_state->blend_tf = old_dm_plane_state->blend_tf;
1485
1486 return &dm_plane_state->base;
1487 }
1488
amdgpu_dm_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)1489 static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,
1490 uint32_t format,
1491 uint64_t modifier)
1492 {
1493 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1494 const struct drm_format_info *info = drm_format_info(format);
1495 int i;
1496
1497 if (!info)
1498 return false;
1499
1500 /*
1501 * We always have to allow these modifiers:
1502 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers.
1503 * 2. Not passing any modifiers is the same as explicitly passing INVALID.
1504 */
1505 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1506 modifier == DRM_FORMAT_MOD_INVALID) {
1507 return true;
1508 }
1509
1510 /* Check that the modifier is on the list of the plane's supported modifiers. */
1511 for (i = 0; i < plane->modifier_count; i++) {
1512 if (modifier == plane->modifiers[i])
1513 break;
1514 }
1515 if (i == plane->modifier_count)
1516 return false;
1517
1518 /* GFX12 doesn't have these limitations. */
1519 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11) {
1520 enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3;
1521
1522 /*
1523 * For D swizzle the canonical modifier depends on the bpp, so check
1524 * it here.
1525 */
1526 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
1527 adev->family >= AMDGPU_FAMILY_NV) {
1528 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
1529 return false;
1530 }
1531
1532 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
1533 info->cpp[0] < 8)
1534 return false;
1535
1536 if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
1537 /* Per radeonsi comments 16/64 bpp are more complicated. */
1538 if (info->cpp[0] != 4)
1539 return false;
1540 /* We support multi-planar formats, but not when combined with
1541 * additional DCC metadata planes.
1542 */
1543 if (info->num_planes > 1)
1544 return false;
1545 }
1546 }
1547
1548 return true;
1549 }
1550
amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)1551 static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
1552 struct drm_plane_state *state)
1553 {
1554 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1555
1556 if (dm_plane_state->degamma_lut)
1557 drm_property_blob_put(dm_plane_state->degamma_lut);
1558 if (dm_plane_state->ctm)
1559 drm_property_blob_put(dm_plane_state->ctm);
1560 if (dm_plane_state->lut3d)
1561 drm_property_blob_put(dm_plane_state->lut3d);
1562 if (dm_plane_state->shaper_lut)
1563 drm_property_blob_put(dm_plane_state->shaper_lut);
1564 if (dm_plane_state->blend_lut)
1565 drm_property_blob_put(dm_plane_state->blend_lut);
1566
1567 if (dm_plane_state->dc_state)
1568 dc_plane_state_release(dm_plane_state->dc_state);
1569
1570 drm_atomic_helper_plane_destroy_state(plane, state);
1571 }
1572
1573 #ifdef AMD_PRIVATE_COLOR
1574 static void
dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager * dm,struct drm_plane * plane)1575 dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
1576 struct drm_plane *plane)
1577 {
1578 struct amdgpu_mode_info mode_info = dm->adev->mode_info;
1579 struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;
1580
1581 /* Check HW color pipeline capabilities on DPP block (pre-blending)
1582 * before exposing related properties.
1583 */
1584 if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) {
1585 drm_object_attach_property(&plane->base,
1586 mode_info.plane_degamma_lut_property,
1587 0);
1588 drm_object_attach_property(&plane->base,
1589 mode_info.plane_degamma_lut_size_property,
1590 MAX_COLOR_LUT_ENTRIES);
1591 drm_object_attach_property(&plane->base,
1592 dm->adev->mode_info.plane_degamma_tf_property,
1593 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
1594 }
1595 /* HDR MULT is always available */
1596 drm_object_attach_property(&plane->base,
1597 dm->adev->mode_info.plane_hdr_mult_property,
1598 AMDGPU_HDR_MULT_DEFAULT);
1599
1600 /* Only enable plane CTM if both DPP and MPC gamut remap is available. */
1601 if (dm->dc->caps.color.mpc.gamut_remap)
1602 drm_object_attach_property(&plane->base,
1603 dm->adev->mode_info.plane_ctm_property, 0);
1604
1605 if (dpp_color_caps.hw_3d_lut) {
1606 drm_object_attach_property(&plane->base,
1607 mode_info.plane_shaper_lut_property, 0);
1608 drm_object_attach_property(&plane->base,
1609 mode_info.plane_shaper_lut_size_property,
1610 MAX_COLOR_LUT_ENTRIES);
1611 drm_object_attach_property(&plane->base,
1612 mode_info.plane_shaper_tf_property,
1613 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
1614 drm_object_attach_property(&plane->base,
1615 mode_info.plane_lut3d_property, 0);
1616 drm_object_attach_property(&plane->base,
1617 mode_info.plane_lut3d_size_property,
1618 MAX_COLOR_3DLUT_SIZE);
1619 }
1620
1621 if (dpp_color_caps.ogam_ram) {
1622 drm_object_attach_property(&plane->base,
1623 mode_info.plane_blend_lut_property, 0);
1624 drm_object_attach_property(&plane->base,
1625 mode_info.plane_blend_lut_size_property,
1626 MAX_COLOR_LUT_ENTRIES);
1627 drm_object_attach_property(&plane->base,
1628 mode_info.plane_blend_tf_property,
1629 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
1630 }
1631 }
1632
1633 static int
dm_atomic_plane_set_property(struct drm_plane * plane,struct drm_plane_state * state,struct drm_property * property,uint64_t val)1634 dm_atomic_plane_set_property(struct drm_plane *plane,
1635 struct drm_plane_state *state,
1636 struct drm_property *property,
1637 uint64_t val)
1638 {
1639 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1640 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1641 bool replaced = false;
1642 int ret;
1643
1644 if (property == adev->mode_info.plane_degamma_lut_property) {
1645 ret = drm_property_replace_blob_from_id(plane->dev,
1646 &dm_plane_state->degamma_lut,
1647 val, -1,
1648 sizeof(struct drm_color_lut),
1649 &replaced);
1650 dm_plane_state->base.color_mgmt_changed |= replaced;
1651 return ret;
1652 } else if (property == adev->mode_info.plane_degamma_tf_property) {
1653 if (dm_plane_state->degamma_tf != val) {
1654 dm_plane_state->degamma_tf = val;
1655 dm_plane_state->base.color_mgmt_changed = 1;
1656 }
1657 } else if (property == adev->mode_info.plane_hdr_mult_property) {
1658 if (dm_plane_state->hdr_mult != val) {
1659 dm_plane_state->hdr_mult = val;
1660 dm_plane_state->base.color_mgmt_changed = 1;
1661 }
1662 } else if (property == adev->mode_info.plane_ctm_property) {
1663 ret = drm_property_replace_blob_from_id(plane->dev,
1664 &dm_plane_state->ctm,
1665 val,
1666 sizeof(struct drm_color_ctm_3x4), -1,
1667 &replaced);
1668 dm_plane_state->base.color_mgmt_changed |= replaced;
1669 return ret;
1670 } else if (property == adev->mode_info.plane_shaper_lut_property) {
1671 ret = drm_property_replace_blob_from_id(plane->dev,
1672 &dm_plane_state->shaper_lut,
1673 val, -1,
1674 sizeof(struct drm_color_lut),
1675 &replaced);
1676 dm_plane_state->base.color_mgmt_changed |= replaced;
1677 return ret;
1678 } else if (property == adev->mode_info.plane_shaper_tf_property) {
1679 if (dm_plane_state->shaper_tf != val) {
1680 dm_plane_state->shaper_tf = val;
1681 dm_plane_state->base.color_mgmt_changed = 1;
1682 }
1683 } else if (property == adev->mode_info.plane_lut3d_property) {
1684 ret = drm_property_replace_blob_from_id(plane->dev,
1685 &dm_plane_state->lut3d,
1686 val, -1,
1687 sizeof(struct drm_color_lut),
1688 &replaced);
1689 dm_plane_state->base.color_mgmt_changed |= replaced;
1690 return ret;
1691 } else if (property == adev->mode_info.plane_blend_lut_property) {
1692 ret = drm_property_replace_blob_from_id(plane->dev,
1693 &dm_plane_state->blend_lut,
1694 val, -1,
1695 sizeof(struct drm_color_lut),
1696 &replaced);
1697 dm_plane_state->base.color_mgmt_changed |= replaced;
1698 return ret;
1699 } else if (property == adev->mode_info.plane_blend_tf_property) {
1700 if (dm_plane_state->blend_tf != val) {
1701 dm_plane_state->blend_tf = val;
1702 dm_plane_state->base.color_mgmt_changed = 1;
1703 }
1704 } else {
1705 drm_dbg_atomic(plane->dev,
1706 "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n",
1707 plane->base.id, plane->name,
1708 property->base.id, property->name);
1709 return -EINVAL;
1710 }
1711
1712 return 0;
1713 }
1714
1715 static int
dm_atomic_plane_get_property(struct drm_plane * plane,const struct drm_plane_state * state,struct drm_property * property,uint64_t * val)1716 dm_atomic_plane_get_property(struct drm_plane *plane,
1717 const struct drm_plane_state *state,
1718 struct drm_property *property,
1719 uint64_t *val)
1720 {
1721 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1722 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1723
1724 if (property == adev->mode_info.plane_degamma_lut_property) {
1725 *val = (dm_plane_state->degamma_lut) ?
1726 dm_plane_state->degamma_lut->base.id : 0;
1727 } else if (property == adev->mode_info.plane_degamma_tf_property) {
1728 *val = dm_plane_state->degamma_tf;
1729 } else if (property == adev->mode_info.plane_hdr_mult_property) {
1730 *val = dm_plane_state->hdr_mult;
1731 } else if (property == adev->mode_info.plane_ctm_property) {
1732 *val = (dm_plane_state->ctm) ?
1733 dm_plane_state->ctm->base.id : 0;
1734 } else if (property == adev->mode_info.plane_shaper_lut_property) {
1735 *val = (dm_plane_state->shaper_lut) ?
1736 dm_plane_state->shaper_lut->base.id : 0;
1737 } else if (property == adev->mode_info.plane_shaper_tf_property) {
1738 *val = dm_plane_state->shaper_tf;
1739 } else if (property == adev->mode_info.plane_lut3d_property) {
1740 *val = (dm_plane_state->lut3d) ?
1741 dm_plane_state->lut3d->base.id : 0;
1742 } else if (property == adev->mode_info.plane_blend_lut_property) {
1743 *val = (dm_plane_state->blend_lut) ?
1744 dm_plane_state->blend_lut->base.id : 0;
1745 } else if (property == adev->mode_info.plane_blend_tf_property) {
1746 *val = dm_plane_state->blend_tf;
1747
1748 } else {
1749 return -EINVAL;
1750 }
1751
1752 return 0;
1753 }
1754 #endif
1755
1756 static const struct drm_plane_funcs dm_plane_funcs = {
1757 .update_plane = drm_atomic_helper_update_plane,
1758 .disable_plane = drm_atomic_helper_disable_plane,
1759 .destroy = drm_plane_helper_destroy,
1760 .reset = amdgpu_dm_plane_drm_plane_reset,
1761 .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,
1762 .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
1763 .format_mod_supported = amdgpu_dm_plane_format_mod_supported,
1764 #ifdef AMD_PRIVATE_COLOR
1765 .atomic_set_property = dm_atomic_plane_set_property,
1766 .atomic_get_property = dm_atomic_plane_get_property,
1767 #endif
1768 };
1769
amdgpu_dm_plane_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,unsigned long possible_crtcs,const struct dc_plane_cap * plane_cap)1770 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1771 struct drm_plane *plane,
1772 unsigned long possible_crtcs,
1773 const struct dc_plane_cap *plane_cap)
1774 {
1775 uint32_t formats[32];
1776 int num_formats;
1777 int res = -EPERM;
1778 unsigned int supported_rotations;
1779 uint64_t *modifiers = NULL;
1780 unsigned int primary_zpos = dm->dc->caps.max_slave_planes;
1781
1782 num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
1783 ARRAY_SIZE(formats));
1784
1785 res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers);
1786 if (res)
1787 return res;
1788
1789 if (modifiers == NULL)
1790 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true;
1791
1792 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
1793 &dm_plane_funcs, formats, num_formats,
1794 modifiers, plane->type, NULL);
1795 kfree(modifiers);
1796 if (res)
1797 return res;
1798
1799 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
1800 plane_cap && plane_cap->per_pixel_alpha) {
1801 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1802 BIT(DRM_MODE_BLEND_PREMULTI) |
1803 BIT(DRM_MODE_BLEND_COVERAGE);
1804
1805 drm_plane_create_alpha_property(plane);
1806 drm_plane_create_blend_mode_property(plane, blend_caps);
1807 }
1808
1809 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
1810 /*
1811 * Allow OVERLAY planes to be used as underlays by assigning an
1812 * immutable zpos = # of OVERLAY planes to the PRIMARY plane.
1813 */
1814 drm_plane_create_zpos_immutable_property(plane, primary_zpos);
1815 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
1816 /*
1817 * OVERLAY planes can be below or above the PRIMARY, but cannot
1818 * be above the CURSOR plane.
1819 */
1820 unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane);
1821
1822 drm_plane_create_zpos_property(plane, zpos, 0, 254);
1823 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
1824 drm_plane_create_zpos_immutable_property(plane, 255);
1825 }
1826
1827 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
1828 plane_cap &&
1829 (plane_cap->pixel_format_support.nv12 ||
1830 plane_cap->pixel_format_support.p010)) {
1831 /* This only affects YUV formats. */
1832 drm_plane_create_color_properties(
1833 plane,
1834 BIT(DRM_COLOR_YCBCR_BT601) |
1835 BIT(DRM_COLOR_YCBCR_BT709) |
1836 BIT(DRM_COLOR_YCBCR_BT2020),
1837 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1838 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1839 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
1840 }
1841
1842 supported_rotations =
1843 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1844 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1845
1846 if (dm->adev->asic_type >= CHIP_BONAIRE &&
1847 plane->type != DRM_PLANE_TYPE_CURSOR)
1848 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1849 supported_rotations);
1850
1851 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) > IP_VERSION(3, 0, 1) &&
1852 plane->type != DRM_PLANE_TYPE_CURSOR)
1853 drm_plane_enable_fb_damage_clips(plane);
1854
1855 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
1856
1857 #ifdef AMD_PRIVATE_COLOR
1858 dm_atomic_plane_attach_color_mgmt_properties(dm, plane);
1859 #endif
1860 /* Create (reset) the plane state */
1861 if (plane->funcs->reset)
1862 plane->funcs->reset(plane);
1863
1864 return 0;
1865 }
1866
amdgpu_dm_plane_is_video_format(uint32_t format)1867 bool amdgpu_dm_plane_is_video_format(uint32_t format)
1868 {
1869 int i;
1870
1871 for (i = 0; i < ARRAY_SIZE(video_formats); i++)
1872 if (format == video_formats[i])
1873 return true;
1874
1875 return false;
1876 }
1877
1878