1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dccg.h"
6 #include "clk_mgr_internal.h"
7 #include "dcn401/dcn401_clk_mgr_smu_msg.h"
8 #include "dcn20/dcn20_clk_mgr.h"
9 #include "dce100/dce_clk_mgr.h"
10 #include "dcn31/dcn31_clk_mgr.h"
11 #include "dcn32/dcn32_clk_mgr.h"
12 #include "dcn401/dcn401_clk_mgr.h"
13 #include "reg_helper.h"
14 #include "core_types.h"
15 #include "dm_helpers.h"
16 #include "link.h"
17 #include "dc_state_priv.h"
18 #include "atomfirmware.h"
19
20 #include "dcn401_smu14_driver_if.h"
21
22 #include "dcn/dcn_4_1_0_offset.h"
23 #include "dcn/dcn_4_1_0_sh_mask.h"
24
25 #include "dml/dcn401/dcn401_fpu.h"
26
27 #define DCN_BASE__INST0_SEG1 0x000000C0
28
29 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
30 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E69
31 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E6C
32 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6F
33 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E72
34 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E75
35 #define mmCLK20_CLK2_CLK2_DFS_CNTL 0x1B051
36
37 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
38 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
39 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
40 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
41 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
42 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
43
44 #undef FN
45 #define FN(reg_name, field_name) \
46 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47
48 #define REG(reg) \
49 (clk_mgr->regs->reg)
50
51 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
52
53 #define BASE(seg) BASE_INNER(seg)
54
55 #define SR(reg_name)\
56 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
57 reg ## reg_name
58
59 #define CLK_SR_DCN401(reg_name, block, inst)\
60 .reg_name = mm ## block ## _ ## reg_name
61
62 static const struct clk_mgr_registers clk_mgr_regs_dcn401 = {
63 CLK_REG_LIST_DCN401()
64 };
65
66 static const struct clk_mgr_shift clk_mgr_shift_dcn401 = {
67 CLK_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
68 };
69
70 static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {
71 CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)
72 };
73
74 #define TO_DCN401_CLK_MGR(clk_mgr)\
75 container_of(clk_mgr, struct dcn401_clk_mgr, base)
76
dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)77 static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
78 {
79 bool ppclk_dpm_enabled = false;
80
81 switch (clk) {
82 case PPCLK_SOCCLK:
83 ppclk_dpm_enabled =
84 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1;
85 break;
86 case PPCLK_UCLK:
87 ppclk_dpm_enabled =
88 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1;
89 break;
90 case PPCLK_FCLK:
91 ppclk_dpm_enabled =
92 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1;
93 break;
94 case PPCLK_DISPCLK:
95 ppclk_dpm_enabled =
96 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1;
97 break;
98 case PPCLK_DPPCLK:
99 ppclk_dpm_enabled =
100 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1;
101 break;
102 case PPCLK_DPREFCLK:
103 ppclk_dpm_enabled = false;
104 break;
105 case PPCLK_DCFCLK:
106 ppclk_dpm_enabled =
107 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1;
108 break;
109 case PPCLK_DTBCLK:
110 ppclk_dpm_enabled =
111 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1;
112 break;
113 default:
114 ppclk_dpm_enabled = false;
115 }
116
117 ppclk_dpm_enabled &= clk_mgr->smu_present;
118
119 return ppclk_dpm_enabled;
120 }
121
dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)122 static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
123 {
124 bool ppclk_idle_dpm_enabled = false;
125
126 switch (clk) {
127 case PPCLK_UCLK:
128 case PPCLK_FCLK:
129 if (ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
130 clk_mgr->smu_ver >= 0x681800) {
131 ppclk_idle_dpm_enabled = true;
132 } else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
133 clk_mgr->smu_ver >= 0x661300) {
134 ppclk_idle_dpm_enabled = true;
135 }
136 break;
137 default:
138 ppclk_idle_dpm_enabled = false;
139 }
140
141 ppclk_idle_dpm_enabled &= clk_mgr->smu_present;
142
143 return ppclk_idle_dpm_enabled;
144 }
145
146 /* Query SMU for all clock states for a particular clock */
dcn401_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)147 static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
148 unsigned int *num_levels)
149 {
150 unsigned int i;
151 char *entry_i = (char *)entry_0;
152
153 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
154
155 if (ret & (1 << 31))
156 /* fine-grained, only min and max */
157 *num_levels = 2;
158 else
159 /* discrete, a number of fixed states */
160 /* will set num_levels to 0 on failure */
161 *num_levels = ret & 0xFF;
162
163 /* if the initial message failed, num_levels will be 0 */
164 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
165 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
166 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
167 }
168 }
169
dcn401_build_wm_range_table(struct clk_mgr * clk_mgr)170 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
171 {
172 /* legacy */
173 DC_FP_START();
174 dcn401_build_wm_range_table_fpu(clk_mgr);
175 DC_FP_END();
176
177 if (clk_mgr->ctx->dc->debug.using_dml21) {
178 /* For min clocks use as reported by PM FW and report those as min */
179 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
180 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
181
182 /* Set A - Normal - default values */
183 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
184 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
185 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
186 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
187 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
188 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
189
190 /* Set B - Unused on dcn4 */
191 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
192
193 /* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
194 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
195 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
196 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
197 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
198 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
199 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
200 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
201 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
202 } else {
203 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
204 }
205
206 /* Set 1B - Unused on dcn4 */
207 clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
208 }
209 }
210
dcn401_init_clocks(struct clk_mgr * clk_mgr_base)211 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
212 {
213 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
214 struct clk_limit_num_entries *num_entries_per_clk;
215 unsigned int i;
216
217 if (!clk_mgr_base->bw_params)
218 return;
219
220 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
221
222 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
223 clk_mgr_base->clks.p_state_change_support = true;
224 clk_mgr_base->clks.prev_p_state_change_support = true;
225 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
226 clk_mgr->smu_present = false;
227 clk_mgr->dpm_present = false;
228
229 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
230 clk_mgr->smu_present = true;
231
232 if (!clk_mgr->smu_present)
233 return;
234
235 dcn30_smu_check_driver_if_version(clk_mgr);
236 dcn30_smu_check_msg_header_version(clk_mgr);
237
238 /* DCFCLK */
239 dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
240 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
241 &num_entries_per_clk->num_dcfclk_levels);
242 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
243 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
244 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz)
245 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
246
247 /* SOCCLK */
248 dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
249 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
250 &num_entries_per_clk->num_socclk_levels);
251 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
252 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
253 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz)
254 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
255
256 /* DTBCLK */
257 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
258 dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
259 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
260 &num_entries_per_clk->num_dtbclk_levels);
261 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
262 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
263 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz)
264 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
265 }
266
267 /* DISPCLK */
268 dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
269 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
270 &num_entries_per_clk->num_dispclk_levels);
271 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
272 if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
273 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz)
274 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
275
276 /* DPPCLK */
277 dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,
278 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
279 &num_entries_per_clk->num_dppclk_levels);
280
281 if (num_entries_per_clk->num_dcfclk_levels &&
282 num_entries_per_clk->num_dtbclk_levels &&
283 num_entries_per_clk->num_dispclk_levels)
284 clk_mgr->dpm_present = true;
285
286 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
287 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++)
288 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
289 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
290 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
291 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
292 }
293
294 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
295 for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++)
296 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
297 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
298 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
299 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
300 }
301
302 /* Get UCLK, update bounding box */
303 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
304
305 /* WM range table */
306 dcn401_build_wm_range_table(clk_mgr_base);
307 }
308
dcn401_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)309 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
310 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
311 {
312 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
313 uint32_t dprefclk_did = 0;
314 uint32_t dcfclk_did = 0;
315 uint32_t dtbclk_did = 0;
316 uint32_t dispclk_did = 0;
317 uint32_t dppclk_did = 0;
318 uint32_t fclk_did = 0;
319 uint32_t target_div = 0;
320
321 /* DFS Slice 0 is used for DISPCLK */
322 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
323 /* DFS Slice 1 is used for DPPCLK */
324 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
325 /* DFS Slice 2 is used for DPREFCLK */
326 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
327 /* DFS Slice 3 is used for DCFCLK */
328 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
329 /* DFS Slice 4 is used for DTBCLK */
330 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
331 /* DFS Slice _ is used for FCLK */
332 fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);
333
334 /* Convert DISPCLK DFS Slice DID to divider*/
335 target_div = dentist_get_divider_from_did(dispclk_did);
336 //Get dispclk in khz
337 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
338 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
339
340 /* Convert DISPCLK DFS Slice DID to divider*/
341 target_div = dentist_get_divider_from_did(dppclk_did);
342 //Get dppclk in khz
343 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
344 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
345
346 /* Convert DPREFCLK DFS Slice DID to divider*/
347 target_div = dentist_get_divider_from_did(dprefclk_did);
348 //Get dprefclk in khz
349 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
350 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
351
352 /* Convert DCFCLK DFS Slice DID to divider*/
353 target_div = dentist_get_divider_from_did(dcfclk_did);
354 //Get dcfclk in khz
355 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
356 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
357
358 /* Convert DTBCLK DFS Slice DID to divider*/
359 target_div = dentist_get_divider_from_did(dtbclk_did);
360 //Get dtbclk in khz
361 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
362 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
363
364 /* Convert DTBCLK DFS Slice DID to divider*/
365 target_div = dentist_get_divider_from_did(fclk_did);
366 //Get fclk in khz
367 regs_and_bypass->fclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
368 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
369 }
370
dcn401_check_native_scaling(struct pipe_ctx * pipe)371 static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)
372 {
373 bool is_native_scaling = false;
374 int width = pipe->plane_state->src_rect.width;
375 int height = pipe->plane_state->src_rect.height;
376
377 if (pipe->stream->timing.h_addressable == width &&
378 pipe->stream->timing.v_addressable == height &&
379 pipe->plane_state->dst_rect.width == width &&
380 pipe->plane_state->dst_rect.height == height)
381 is_native_scaling = true;
382
383 return is_native_scaling;
384 }
385
dcn401_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)386 static void dcn401_auto_dpm_test_log(
387 struct dc_clocks *new_clocks,
388 struct clk_mgr_internal *clk_mgr,
389 struct dc_state *context)
390 {
391 unsigned int mall_ss_size_bytes;
392 int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
393
394 struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
395 int active_pipe_count = 0;
396
397 for (int i = 0; i < MAX_PIPES; i++) {
398 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
399
400 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
401 pipe_ctx_list[active_pipe_count] = pipe_ctx;
402 active_pipe_count++;
403 }
404 }
405
406 msleep(5);
407
408 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
409
410 struct clk_log_info log_info = {0};
411 struct clk_state_registers_and_bypass clk_register_dump;
412
413 dcn401_dump_clk_registers(&clk_register_dump, &clk_mgr->base, &log_info);
414
415 // Overrides for these clocks in case there is no p_state change support
416 dramclk_khz_override = new_clocks->dramclk_khz;
417 fclk_khz_override = new_clocks->fclk_khz;
418
419 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
420
421 if (!new_clocks->p_state_change_support)
422 dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
423
424 if (!new_clocks->fclk_p_state_change_support)
425 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
426
427
428 ////////////////////////////////////////////////////////////////////////////
429 // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
430 // anywhere other than at the very end of the string.
431 //
432 // Formatting example (make sure to have " - " between each entry):
433 //
434 // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
435 ////////////////////////////////////////////////////////////////////////////
436 if (active_pipe_count > 0 &&
437 new_clocks->dramclk_khz > 0 &&
438 new_clocks->fclk_khz > 0 &&
439 new_clocks->dcfclk_khz > 0 &&
440 new_clocks->dppclk_khz > 0) {
441
442 uint32_t pix_clk_list[MAX_PIPES] = {0};
443 int p_state_list[MAX_PIPES] = {0};
444 int disp_src_width_list[MAX_PIPES] = {0};
445 int disp_src_height_list[MAX_PIPES] = {0};
446 uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
447 bool is_scaled_list[MAX_PIPES] = {0};
448
449 for (int i = 0; i < active_pipe_count; i++) {
450 struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
451 uint64_t refresh_rate;
452
453 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
454 p_state_list[i] = curr_pipe_ctx->p_state_type;
455
456 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
457 curr_pipe_ctx->stream->timing.v_total
458 * (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
459 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
460 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
461 disp_src_refresh_list[i] = refresh_rate;
462
463 if (curr_pipe_ctx->plane_state) {
464 is_scaled_list[i] = !(dcn401_check_native_scaling(curr_pipe_ctx));
465 disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
466 disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
467 }
468 }
469
470 DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
471 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
472 "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
473 "dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
474 "pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
475 "p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
476 "pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
477 "pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
478 "pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
479 "pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
480 dramclk_khz_override,
481 fclk_khz_override,
482 new_clocks->dcfclk_khz,
483 new_clocks->dppclk_khz,
484 clk_register_dump.dispclk,
485 clk_register_dump.dppclk,
486 clk_register_dump.dprefclk,
487 clk_register_dump.dcfclk,
488 clk_register_dump.dtbclk,
489 clk_register_dump.fclk,
490 pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
491 mall_ss_size_bytes,
492 p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
493 disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
494 disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
495 disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
496 disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
497 }
498 }
499
dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)500 static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
501 struct dc_state *context,
502 int ref_dtbclk_khz)
503 {
504 int i;
505 struct dccg *dccg = clk_mgr->dccg;
506 struct pipe_ctx *otg_master;
507 bool use_hpo_encoder;
508
509
510 for (i = 0; i < context->stream_count; i++) {
511 otg_master = resource_get_otg_master_for_stream(
512 &context->res_ctx, context->streams[i]);
513 ASSERT(otg_master);
514 ASSERT(otg_master->clock_source);
515 ASSERT(otg_master->clock_source->funcs->program_pix_clk);
516 ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
517
518 use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
519 if (!use_hpo_encoder)
520 continue;
521
522 if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
523 otg_master->clock_source->funcs->program_pix_clk(
524 otg_master->clock_source,
525 &otg_master->stream_res.pix_clk_params,
526 dccg->ctx->dc->link_srv->dp_get_encoding_format(
527 &otg_master->link_config.dp_link_settings),
528 &otg_master->pll_settings);
529 }
530 }
531
dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower,int ref_dppclk_khz)532 static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
533 struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
534 {
535 int i;
536
537 clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
538 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
539 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
540
541 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
542
543 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
544 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
545 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
546 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
547 * In this case just continue in loop
548 */
549 continue;
550 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
551 /* The software state is not valid if dpp resource is NULL and
552 * dppclk_khz > 0.
553 */
554 ASSERT(false);
555 continue;
556 }
557
558 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
559
560 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
561 clk_mgr->dccg->funcs->update_dpp_dto(
562 clk_mgr->dccg, dpp_inst, dppclk_khz);
563 }
564 }
565
dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,int requested_clk_khz)566 static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
567 {
568 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
569 return 0;
570
571 /*
572 * SMU set hard min interface takes requested clock in mhz and return
573 * actual clock configured in khz. If we floor requested clk to mhz,
574 * there is a chance that the actual clock configured in khz is less
575 * than requested. If we ceil it to mhz, there is a chance that it
576 * unnecessarily dumps up to a higher dpm level, which burns more power.
577 * The solution is to set by flooring it to mhz first. If the actual
578 * clock returned is less than requested, then we will ceil the
579 * requested value to mhz and call it again.
580 */
581 int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
582
583 if (actual_clk_khz < requested_clk_khz)
584 actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
585
586 return actual_clk_khz;
587 }
588
dcn401_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)589 static void dcn401_update_clocks_update_dentist(
590 struct clk_mgr_internal *clk_mgr,
591 struct dc_state *context)
592 {
593 uint32_t new_disp_divider = 0;
594 uint32_t new_dispclk_wdivider = 0;
595 uint32_t dentist_dispclk_wdivider_readback = 0;
596 struct dc *dc = clk_mgr->base.ctx->dc;
597
598 if (clk_mgr->base.clks.dispclk_khz == 0)
599 return;
600
601 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
602 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
603
604 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
605
606 if (dc->debug.override_dispclk_programming) {
607 REG_GET(DENTIST_DISPCLK_CNTL,
608 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
609
610 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
611 REG_UPDATE(DENTIST_DISPCLK_CNTL,
612 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
613 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
614 }
615 }
616
617 }
618
dcn401_update_clocks_legacy(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)619 static void dcn401_update_clocks_legacy(struct clk_mgr *clk_mgr_base,
620 struct dc_state *context,
621 bool safe_to_lower)
622 {
623 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
624 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
625 struct dc *dc = clk_mgr_base->ctx->dc;
626 int display_count;
627 bool update_dppclk = false;
628 bool update_dispclk = false;
629 bool enter_display_off = false;
630 bool dpp_clock_lowered = false;
631 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
632 bool force_reset = false;
633 bool update_uclk = false, update_fclk = false;
634 bool p_state_change_support;
635 bool fclk_p_state_change_support;
636 int total_plane_count;
637
638 if (dc->work_arounds.skip_clock_update)
639 return;
640
641 if (clk_mgr_base->clks.dispclk_khz == 0 ||
642 (dc->debug.force_clock_mode & 0x1)) {
643 /* This is from resume or boot up, if forced_clock cfg option used,
644 * we bypass program dispclk and DPPCLK, but need set them for S3.
645 */
646 force_reset = true;
647
648 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
649
650 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
651 * as long as it is in Passive level.
652 */
653 }
654 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
655
656 if (display_count == 0)
657 enter_display_off = true;
658
659 if (clk_mgr->smu_present) {
660 if (enter_display_off == safe_to_lower)
661 dcn401_smu_set_num_of_displays(clk_mgr, display_count);
662
663 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
664
665 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
666 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
667
668 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
669 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
670
671 /* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
672 if (clk_mgr_base->clks.fclk_p_state_change_support) {
673 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
674 dcn401_smu_send_fclk_pstate_message(clk_mgr, true);
675 }
676 }
677
678 if (dc->debug.force_min_dcfclk_mhz > 0)
679 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
680 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
681
682 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
683 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
684 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
685 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
686 }
687
688 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
689 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
690 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
691 dcn401_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
692 }
693
694 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
695 /* We don't actually care about socclk, don't notify SMU of hard min */
696 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
697
698 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
699 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
700
701 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
702 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
703 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
704 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
705 dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
706 }
707
708
709 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
710 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
711 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
712 clk_mgr_base->clks.fw_based_mclk_switching = p_state_change_support && new_clocks->fw_based_mclk_switching;
713
714 /* to disable P-State switching, set UCLK min = max */
715 if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
716 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
717 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
718 }
719
720 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
721 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
722 update_fclk = true;
723 }
724
725 if (!clk_mgr_base->clks.fclk_p_state_change_support &&
726 update_fclk &&
727 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_FCLK)) {
728 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
729 dcn401_smu_send_fclk_pstate_message(clk_mgr, false);
730 }
731
732 /* Always update saved value, even if new value not set due to P-State switching unsupported */
733 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
734 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
735 update_uclk = true;
736 }
737
738 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
739 if (clk_mgr_base->clks.p_state_change_support &&
740 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
741 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
742 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
743
744 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
745 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
746 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
747 if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
748 dcn401_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
749 }
750 }
751
752 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
753 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
754 dpp_clock_lowered = true;
755
756 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
757 clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
758
759 if (clk_mgr->smu_present && !dpp_clock_lowered && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK))
760 clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK, clk_mgr_base->clks.dppclk_khz);
761 update_dppclk = true;
762 }
763
764 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
765 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
766
767 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK))
768 clk_mgr_base->clks.actual_dispclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz);
769
770 update_dispclk = true;
771 }
772
773 if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
774 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
775 }
776
777 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
778 if (!dc->debug.disable_dtb_ref_clk_switch &&
779 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) &&
780 dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
781 /* DCCG requires KHz precision for DTBCLK */
782 clk_mgr_base->clks.ref_dtbclk_khz =
783 dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
784
785 dcn401_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
786 }
787
788 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
789 if (dpp_clock_lowered) {
790 /* if clock is being lowered, increase DTO before lowering refclk */
791 dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
792 safe_to_lower, clk_mgr_base->clks.dppclk_khz);
793 dcn401_update_clocks_update_dentist(clk_mgr, context);
794 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK)) {
795 clk_mgr_base->clks.actual_dppclk_khz = dcn401_set_hard_min_by_freq_optimized(clk_mgr, PPCLK_DPPCLK,
796 clk_mgr_base->clks.dppclk_khz);
797 dcn401_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower,
798 clk_mgr_base->clks.actual_dppclk_khz);
799 }
800
801 } else {
802 /* if clock is being raised, increase refclk before lowering DTO */
803 if (update_dppclk || update_dispclk)
804 dcn401_update_clocks_update_dentist(clk_mgr, context);
805 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
806 * that we do not lower dto when it is not safe to lower. We do not need to
807 * compare the current and new dppclk before calling this function.
808 */
809 dcn401_update_clocks_update_dpp_dto(clk_mgr, context,
810 safe_to_lower, clk_mgr_base->clks.actual_dppclk_khz);
811 }
812 }
813
814 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
815 /*update dmcu for wait_loop count*/
816 dmcu->funcs->set_psr_wait_loop(dmcu,
817 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
818 }
819
dcn401_execute_block_sequence(struct clk_mgr * clk_mgr_base,unsigned int num_steps)820 static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
821 {
822 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
823 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
824
825 unsigned int i;
826 union dcn401_clk_mgr_block_sequence_params *params;
827
828 /* execute sequence */
829 for (i = 0; i < num_steps; i++) {
830 params = &clk_mgr401->block_sequence[i].params;
831
832 switch (clk_mgr401->block_sequence[i].func) {
833 case CLK_MGR401_READ_CLOCKS_FROM_DENTIST:
834 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
835 break;
836 case CLK_MGR401_UPDATE_NUM_DISPLAYS:
837 dcn401_smu_set_num_of_displays(clk_mgr_internal,
838 params->update_num_displays_params.num_displays);
839 break;
840 case CLK_MGR401_UPDATE_HARDMIN_PPCLK:
841 if (params->update_hardmin_params.response)
842 *params->update_hardmin_params.response = dcn401_smu_set_hard_min_by_freq(
843 clk_mgr_internal,
844 params->update_hardmin_params.ppclk,
845 params->update_hardmin_params.freq_mhz);
846 else
847 dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,
848 params->update_hardmin_params.ppclk,
849 params->update_hardmin_params.freq_mhz);
850 break;
851 case CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED:
852 if (params->update_hardmin_optimized_params.response)
853 *params->update_hardmin_optimized_params.response = dcn401_set_hard_min_by_freq_optimized(
854 clk_mgr_internal,
855 params->update_hardmin_optimized_params.ppclk,
856 params->update_hardmin_optimized_params.freq_khz);
857 else
858 dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,
859 params->update_hardmin_optimized_params.ppclk,
860 params->update_hardmin_optimized_params.freq_khz);
861 break;
862 case CLK_MGR401_UPDATE_ACTIVE_HARDMINS:
863 dcn401_smu_set_active_uclk_fclk_hardmin(
864 clk_mgr_internal,
865 params->update_idle_hardmin_params.uclk_mhz,
866 params->update_idle_hardmin_params.fclk_mhz);
867 break;
868 case CLK_MGR401_UPDATE_IDLE_HARDMINS:
869 dcn401_smu_set_idle_uclk_fclk_hardmin(
870 clk_mgr_internal,
871 params->update_idle_hardmin_params.uclk_mhz,
872 params->update_idle_hardmin_params.fclk_mhz);
873 break;
874 case CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK:
875 dcn401_smu_set_min_deep_sleep_dcef_clk(
876 clk_mgr_internal,
877 params->update_deep_sleep_dcfclk_params.freq_mhz);
878 break;
879 case CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT:
880 dcn401_smu_send_fclk_pstate_message(
881 clk_mgr_internal,
882 params->update_pstate_support_params.support);
883 break;
884 case CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT:
885 dcn401_smu_send_uclk_pstate_message(
886 clk_mgr_internal,
887 params->update_pstate_support_params.support);
888 break;
889 case CLK_MGR401_UPDATE_CAB_FOR_UCLK:
890 dcn401_smu_send_cab_for_uclk_message(
891 clk_mgr_internal,
892 params->update_cab_for_uclk_params.num_ways);
893 break;
894 case CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK:
895 dcn401_smu_wait_for_dmub_ack_mclk(
896 clk_mgr_internal,
897 params->update_wait_for_dmub_ack_params.enable);
898 break;
899 case CLK_MGR401_INDICATE_DRR_STATUS:
900 dcn401_smu_indicate_drr_status(
901 clk_mgr_internal,
902 params->indicate_drr_status_params.mod_drr_for_pstate);
903 break;
904 case CLK_MGR401_UPDATE_DPPCLK_DTO:
905 dcn401_update_clocks_update_dpp_dto(
906 clk_mgr_internal,
907 params->update_dppclk_dto_params.context,
908 params->update_dppclk_dto_params.safe_to_lower,
909 *params->update_dppclk_dto_params.ref_dppclk_khz);
910 break;
911 case CLK_MGR401_UPDATE_DTBCLK_DTO:
912 dcn401_update_clocks_update_dtb_dto(
913 clk_mgr_internal,
914 params->update_dtbclk_dto_params.context,
915 *params->update_dtbclk_dto_params.ref_dtbclk_khz);
916 break;
917 case CLK_MGR401_UPDATE_DENTIST:
918 dcn401_update_clocks_update_dentist(
919 clk_mgr_internal,
920 params->update_dentist_params.context);
921 break;
922 case CLK_MGR401_UPDATE_PSR_WAIT_LOOP:
923 params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(
924 params->update_psr_wait_loop_params.dmcu,
925 params->update_psr_wait_loop_params.wait);
926 break;
927 default:
928 /* this should never happen */
929 BREAK_TO_DEBUGGER();
930 break;
931 }
932 }
933 }
934
dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)935 static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
936 struct clk_mgr *clk_mgr_base,
937 struct dc_state *context,
938 struct dc_clocks *new_clocks,
939 bool safe_to_lower)
940 {
941 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
942 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
943 struct dc *dc = clk_mgr_base->ctx->dc;
944 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
945 bool enter_display_off = false;
946 bool update_active_fclk = false;
947 bool update_active_uclk = false;
948 bool update_idle_fclk = false;
949 bool update_idle_uclk = false;
950 bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
951 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&
952 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
953 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);
954 int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
955 int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
956 int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
957 int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
958 int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
959
960 unsigned int num_steps = 0;
961
962 int display_count;
963 bool fclk_p_state_change_support, uclk_p_state_change_support;
964
965 /* CLK_MGR401_UPDATE_NUM_DISPLAYS */
966 if (clk_mgr_internal->smu_present) {
967 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
968
969 if (display_count == 0)
970 enter_display_off = true;
971
972 if (enter_display_off == safe_to_lower) {
973 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;
974 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;
975 num_steps++;
976 }
977 }
978
979 /* CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT */
980 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
981 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
982 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
983 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
984 update_active_fclk = true;
985 update_idle_fclk = true;
986
987 /* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW */
988 if (clk_mgr_base->clks.fclk_p_state_change_support) {
989 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
990 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
991 block_sequence[num_steps].params.update_pstate_support_params.support = true;
992 block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
993 num_steps++;
994 }
995 }
996 }
997
998 if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
999 /* when P-State switching disabled, set UCLK min = max */
1000 idle_fclk_mhz =
1001 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
1002 active_fclk_mhz = idle_fclk_mhz;
1003 }
1004
1005 /* UPDATE DCFCLK */
1006 if (dc->debug.force_min_dcfclk_mhz > 0)
1007 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
1008 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
1009
1010 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
1011 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1012 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
1013 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
1014 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
1015 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1016 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1017 num_steps++;
1018 }
1019 }
1020
1021 /* CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK */
1022 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
1023 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1024 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
1025 block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
1026 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
1027 num_steps++;
1028 }
1029 }
1030
1031 /* SOCCLK */
1032 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
1033 /* We don't actually care about socclk, don't notify SMU of hard min */
1034 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
1035
1036 /* UCLK */
1037 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1038 new_clocks->fw_based_mclk_switching) {
1039 /* enable FAMS features */
1040 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1041
1042 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1043 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1044 num_steps++;
1045
1046 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1047 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1048 num_steps++;
1049 }
1050
1051 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1052 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
1053 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1054 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
1055 /* increase num ways for subvp */
1056 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1057 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1058 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1059 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1060 num_steps++;
1061 }
1062 }
1063
1064 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
1065 uclk_p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
1066 if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
1067 clk_mgr_base->clks.p_state_change_support = uclk_p_state_change_support;
1068 update_active_uclk = true;
1069 update_idle_uclk = true;
1070
1071 if (clk_mgr_base->clks.p_state_change_support) {
1072 /* enable UCLK switching */
1073 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1074 block_sequence[num_steps].params.update_pstate_support_params.support = true;
1075 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1076 num_steps++;
1077 }
1078 }
1079 }
1080
1081 if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1082 /* when P-State switching disabled, set UCLK min = max */
1083 if (dc->clk_mgr->dc_mode_softmax_enabled) {
1084 /* will never have the functional UCLK min above the softmax
1085 * since we calculate mode support based on softmax being the max UCLK
1086 * frequency.
1087 */
1088 active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
1089 } else {
1090 active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
1091 }
1092 idle_uclk_mhz = active_uclk_mhz;
1093 }
1094
1095 /* Always update saved value, even if new value not set due to P-State switching unsupported */
1096 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
1097 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
1098
1099 if (clk_mgr_base->clks.p_state_change_support) {
1100 update_active_uclk = true;
1101 active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
1102 }
1103 }
1104
1105 if (should_set_clock(safe_to_lower, new_clocks->idle_dramclk_khz, clk_mgr_base->clks.idle_dramclk_khz)) {
1106 clk_mgr_base->clks.idle_dramclk_khz = new_clocks->idle_dramclk_khz;
1107
1108 if (clk_mgr_base->clks.p_state_change_support) {
1109 update_idle_uclk = true;
1110 idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
1111 }
1112 }
1113
1114 /* FCLK */
1115 /* Always update saved value, even if new value not set due to P-State switching unsupported */
1116 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
1117 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
1118
1119 if (clk_mgr_base->clks.fclk_p_state_change_support) {
1120 update_active_fclk = true;
1121 active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
1122 }
1123 }
1124
1125 if (should_set_clock(safe_to_lower, new_clocks->idle_fclk_khz, clk_mgr_base->clks.idle_fclk_khz)) {
1126 clk_mgr_base->clks.idle_fclk_khz = new_clocks->idle_fclk_khz;
1127
1128 if (clk_mgr_base->clks.fclk_p_state_change_support) {
1129 update_idle_fclk = true;
1130 idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
1131 }
1132 }
1133
1134 /* When idle DPM is enabled, need to send active and idle hardmins separately */
1135 /* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
1136 if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
1137 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
1138 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
1139 block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
1140 num_steps++;
1141 }
1142
1143 /* CLK_MGR401_UPDATE_IDLE_HARDMINS */
1144 if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
1145 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
1146 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
1147 block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
1148 num_steps++;
1149 }
1150
1151 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1152 if (update_active_uclk || update_idle_uclk) {
1153 if (!is_idle_dpm_enabled) {
1154 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
1155 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
1156 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1157 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1158 num_steps++;
1159 }
1160
1161 /* disable UCLK P-State support if needed */
1162 if (!uclk_p_state_change_support &&
1163 should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support) &&
1164 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1165 block_sequence[num_steps].params.update_pstate_support_params.support = false;
1166 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1167 num_steps++;
1168 }
1169 }
1170
1171 /* set FCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1172 if (update_active_fclk || update_idle_fclk) {
1173 /* No need to send active FCLK hardmin, automatically set based on DCFCLK */
1174 // if (!is_idle_dpm_enabled) {
1175 // block_sequence[*num_steps].update_hardmin_params.clk_mgr = clk_mgr;
1176 // block_sequence[*num_steps].update_hardmin_params.ppclk = PPCLK_FCLK;
1177 // block_sequence[*num_steps].update_hardmin_params.freq_mhz = active_fclk_mhz;
1178 // block_sequence[*num_steps].update_hardmin_params.response = NULL;
1179 // block_sequence[*num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1180 // (*num_steps)++;
1181 // }
1182
1183 /* disable FCLK P-State support if needed */
1184 if (!fclk_p_state_change_support &&
1185 should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
1186 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
1187 block_sequence[num_steps].params.update_pstate_support_params.support = false;
1188 block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
1189 num_steps++;
1190 }
1191 }
1192
1193 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1194 safe_to_lower && !new_clocks->fw_based_mclk_switching) {
1195 /* disable FAMS features */
1196 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1197
1198 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1199 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1200 num_steps++;
1201
1202 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1203 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1204 num_steps++;
1205 }
1206
1207 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1208 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1209 safe_to_lower && clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
1210 /* decrease num ways for subvp */
1211 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1212 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1213 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1214 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1215 num_steps++;
1216 }
1217 }
1218
1219 return num_steps;
1220 }
1221
dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)1222 static unsigned int dcn401_build_update_display_clocks_sequence(
1223 struct clk_mgr *clk_mgr_base,
1224 struct dc_state *context,
1225 struct dc_clocks *new_clocks,
1226 bool safe_to_lower)
1227 {
1228 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1229 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
1230 struct dc *dc = clk_mgr_base->ctx->dc;
1231 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
1232 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
1233 bool force_reset = false;
1234 bool update_dispclk = false;
1235 bool update_dppclk = false;
1236 bool dppclk_lowered = false;
1237
1238 unsigned int num_steps = 0;
1239
1240 /* CLK_MGR401_READ_CLOCKS_FROM_DENTIST */
1241 if (clk_mgr_base->clks.dispclk_khz == 0 ||
1242 (dc->debug.force_clock_mode & 0x1)) {
1243 /* This is from resume or boot up, if forced_clock cfg option used,
1244 * we bypass program dispclk and DPPCLK, but need set them for S3.
1245 * Force_clock_mode 0x1: force reset the clock even it is the same clock
1246 * as long as it is in Passive level.
1247 */
1248 force_reset = true;
1249
1250 clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk;
1251 clk_mgr_base->clks.actual_dispclk_khz = clk_mgr_base->clks.dispclk_khz;
1252
1253 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk;
1254 clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.dppclk_khz;
1255 }
1256
1257 /* DTBCLK */
1258 if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1259 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
1260 }
1261
1262 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
1263 if (!dc->debug.disable_dtb_ref_clk_switch &&
1264 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) && //TODO these should be ceiled
1265 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1266 /* DCCG requires KHz precision for DTBCLK */
1267 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
1268 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
1269 block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
1270 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1271 num_steps++;
1272
1273 /* Update DTO in DCCG */
1274 block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
1275 block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
1276 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
1277 num_steps++;
1278 }
1279
1280 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
1281 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
1282 dppclk_lowered = true;
1283
1284 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
1285 clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
1286
1287 update_dppclk = true;
1288 }
1289
1290 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
1291 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
1292
1293 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
1294 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;
1295 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;
1296 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1297 num_steps++;
1298
1299 update_dispclk = true;
1300 }
1301
1302 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
1303 if (dppclk_lowered) {
1304 /* if clock is being lowered, increase DTO before lowering refclk */
1305 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1306 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
1307 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1308 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1309 num_steps++;
1310
1311 block_sequence[num_steps].params.update_dentist_params.context = context;
1312 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1313 num_steps++;
1314
1315 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1316 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1317 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1318 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1319 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1320 num_steps++;
1321
1322 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1323 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1324 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1325 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1326 num_steps++;
1327 }
1328 } else {
1329 /* if clock is being raised, increase refclk before lowering DTO */
1330 if (update_dppclk && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1331 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1332 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1333 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1334 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1335 num_steps++;
1336 }
1337
1338 if (update_dppclk || update_dispclk) {
1339 block_sequence[num_steps].params.update_dentist_params.context = context;
1340 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1341 num_steps++;
1342 }
1343
1344 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1345 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1346 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1347 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1348 num_steps++;
1349 }
1350 }
1351
1352 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
1353 /*update dmcu for wait_loop count*/
1354 block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;
1355 block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;
1356 block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;
1357 num_steps++;
1358 }
1359
1360 return num_steps;
1361 }
1362
dcn401_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)1363 static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
1364 struct dc_state *context,
1365 bool safe_to_lower)
1366 {
1367 struct dc *dc = clk_mgr_base->ctx->dc;
1368
1369 unsigned int num_steps = 0;
1370
1371 if (dc->debug.enable_legacy_clock_update) {
1372 dcn401_update_clocks_legacy(clk_mgr_base, context, safe_to_lower);
1373 return;
1374 }
1375
1376 /* build bandwidth related clocks update sequence */
1377 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1378 context,
1379 &context->bw_ctx.bw.dcn.clk,
1380 safe_to_lower);
1381
1382 /* execute sequence */
1383 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1384
1385 /* build display related clocks update sequence */
1386 num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,
1387 context,
1388 &context->bw_ctx.bw.dcn.clk,
1389 safe_to_lower);
1390
1391 /* execute sequence */
1392 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1393
1394 if (dc->config.enable_auto_dpm_test_logs)
1395 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);
1396
1397 }
1398
1399
dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)1400 static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
1401 {
1402 struct fixed31_32 pll_req;
1403 uint32_t pll_req_reg = 0;
1404
1405 /* get FbMult value */
1406 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
1407
1408 /* set up a fixed-point number
1409 * this works because the int part is on the right edge of the register
1410 * and the frac part is on the left edge
1411 */
1412 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
1413 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
1414
1415 /* multiply by REFCLK period */
1416 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
1417
1418 return dc_fixpt_floor(pll_req);
1419 }
1420
dcn401_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)1421 static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
1422 {
1423 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
1424 int ss_info_num = bp->funcs->get_ss_entry_number(
1425 bp, AS_SIGNAL_TYPE_GPU_PLL);
1426
1427 if (ss_info_num) {
1428 struct spread_spectrum_info info = { { 0 } };
1429 enum bp_result result = bp->funcs->get_spread_spectrum_info(
1430 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
1431
1432 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
1433 * that SS is enabled
1434 */
1435 if (result == BP_RESULT_OK &&
1436 info.spread_spectrum_percentage != 0) {
1437 clk_mgr->ss_on_dprefclk = true;
1438 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
1439
1440 if (info.type.CENTER_MODE == 0) {
1441 /* Currently for DP Reference clock we
1442 * need only SS percentage for
1443 * downspread
1444 */
1445 clk_mgr->dprefclk_ss_percentage =
1446 info.spread_spectrum_percentage;
1447 }
1448 }
1449 }
1450 }
dcn401_notify_wm_ranges(struct clk_mgr * clk_mgr_base)1451 static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
1452 {
1453 unsigned int i;
1454 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1455 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
1456
1457 if (!clk_mgr->smu_present)
1458 return;
1459
1460 if (!table)
1461 return;
1462
1463 memset(table, 0, sizeof(*table));
1464
1465 /* collect valid ranges, place in pmfw table */
1466 for (i = 0; i < WM_SET_COUNT; i++)
1467 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
1468 table->Watermarks.WatermarkRow[i].WmSetting = i;
1469 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
1470 }
1471 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1472 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
1473 dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
1474 }
1475
1476 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn401_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)1477 static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
1478 {
1479 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1480 const struct dc *dc = clk_mgr->base.ctx->dc;
1481 struct dc_state *context = dc->current_state;
1482 struct dc_clocks new_clocks;
1483 int num_steps;
1484
1485 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
1486 return;
1487
1488 /* build clock update */
1489 memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
1490
1491 if (current_mode) {
1492 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;
1493 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;
1494 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1495 } else {
1496 new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000;
1497 new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;
1498 new_clocks.p_state_change_support = true;
1499 }
1500
1501 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1502 context,
1503 &new_clocks,
1504 true);
1505
1506 /* execute sequence */
1507 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1508 }
1509
1510 /* Get current memclk states, update bounding box */
dcn401_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)1511 static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
1512 {
1513 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1514 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1515 unsigned int num_levels;
1516
1517 if (!clk_mgr->smu_present)
1518 return;
1519
1520 /* Refresh memclk and fclk states */
1521 dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,
1522 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1523 &num_entries_per_clk->num_memclk_levels);
1524 if (num_entries_per_clk->num_memclk_levels) {
1525 clk_mgr_base->bw_params->max_memclk_mhz =
1526 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1527 }
1528
1529 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1530 if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
1531 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz)
1532 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
1533 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1534
1535 dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
1536 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1537 &num_entries_per_clk->num_fclk_levels);
1538 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1539 if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
1540 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz)
1541 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;
1542
1543 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
1544 num_levels = num_entries_per_clk->num_memclk_levels;
1545 } else {
1546 num_levels = num_entries_per_clk->num_fclk_levels;
1547 }
1548
1549 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1550
1551 if (clk_mgr->dpm_present && !num_levels)
1552 clk_mgr->dpm_present = false;
1553
1554 /* Refresh bounding box */
1555 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1556 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1557 }
1558
dcn401_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1559 static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
1560 struct dc_clocks *b)
1561 {
1562 if (a->dispclk_khz != b->dispclk_khz)
1563 return false;
1564 else if (a->dppclk_khz != b->dppclk_khz)
1565 return false;
1566 else if (a->dcfclk_khz != b->dcfclk_khz)
1567 return false;
1568 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1569 return false;
1570 else if (a->dramclk_khz != b->dramclk_khz)
1571 return false;
1572 else if (a->p_state_change_support != b->p_state_change_support)
1573 return false;
1574 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1575 return false;
1576
1577 return true;
1578 }
1579
dcn401_enable_pme_wa(struct clk_mgr * clk_mgr_base)1580 static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1581 {
1582 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1583
1584 if (!clk_mgr->smu_present)
1585 return;
1586
1587 dcn401_smu_set_pme_workaround(clk_mgr);
1588 }
1589
dcn401_is_smu_present(struct clk_mgr * clk_mgr_base)1590 static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
1591 {
1592 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1593 return clk_mgr->smu_present;
1594 }
1595
1596
dcn401_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)1597 static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
1598 {
1599 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1600
1601 int dtb_ref_clk_khz = 0;
1602
1603 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
1604 /* DPM enabled, use currently set value */
1605 dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz;
1606 } else {
1607 /* DPM disabled, so use boot snapshot */
1608 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk;
1609 }
1610
1611 return dtb_ref_clk_khz;
1612 }
1613
dcn401_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)1614 static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
1615 {
1616 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1617 uint32_t dispclk_wdivider;
1618 int disp_divider;
1619
1620 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
1621 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
1622
1623 /* Return DISPCLK freq in Khz */
1624 if (disp_divider)
1625 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
1626
1627 return 0;
1628 }
1629
1630 static struct clk_mgr_funcs dcn401_funcs = {
1631 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1632 .get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
1633 .update_clocks = dcn401_update_clocks,
1634 .dump_clk_registers = dcn401_dump_clk_registers,
1635 .init_clocks = dcn401_init_clocks,
1636 .notify_wm_ranges = dcn401_notify_wm_ranges,
1637 .set_hard_min_memclk = dcn401_set_hard_min_memclk,
1638 .get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,
1639 .are_clock_states_equal = dcn401_are_clock_states_equal,
1640 .enable_pme_wa = dcn401_enable_pme_wa,
1641 .is_smu_present = dcn401_is_smu_present,
1642 .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
1643 };
1644
dcn401_clk_mgr_construct(struct dc_context * ctx,struct dccg * dccg)1645 struct clk_mgr_internal *dcn401_clk_mgr_construct(
1646 struct dc_context *ctx,
1647 struct dccg *dccg)
1648 {
1649 struct clk_log_info log_info = {0};
1650 struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);
1651 struct clk_mgr_internal *clk_mgr;
1652
1653 if (!clk_mgr401)
1654 return NULL;
1655
1656 clk_mgr = &clk_mgr401->base;
1657 clk_mgr->base.ctx = ctx;
1658 clk_mgr->base.funcs = &dcn401_funcs;
1659 clk_mgr->regs = &clk_mgr_regs_dcn401;
1660 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn401;
1661 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;
1662
1663 clk_mgr->dccg = dccg;
1664 clk_mgr->dfs_bypass_disp_clk = 0;
1665
1666 clk_mgr->dprefclk_ss_percentage = 0;
1667 clk_mgr->dprefclk_ss_divider = 1000;
1668 clk_mgr->ss_on_dprefclk = false;
1669 clk_mgr->dfs_ref_freq_khz = 100000;
1670
1671 /* Changed from DCN3.2_clock_frequency doc to match
1672 * dcn401_dump_clk_registers from 4 * dentist_vco_freq_khz /
1673 * dprefclk DID divider
1674 */
1675 clk_mgr->base.dprefclk_khz = 720000; //TODO update from VBIOS
1676
1677 /* integer part is now VCO frequency in kHz */
1678 clk_mgr->base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);
1679
1680 /* in case we don't get a value from the register, use default */
1681 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1682 clk_mgr->base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS
1683
1684 dcn401_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1685
1686 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1687 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1688 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1689 }
1690
1691 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1692 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1693 }
1694 dcn401_clock_read_ss_info(clk_mgr);
1695
1696 clk_mgr->dfs_bypass_enabled = false;
1697
1698 clk_mgr->smu_present = false;
1699
1700 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1701 if (!clk_mgr->base.bw_params) {
1702 BREAK_TO_DEBUGGER();
1703 kfree(clk_mgr401);
1704 return NULL;
1705 }
1706
1707 /* need physical address of table to give to PMFW */
1708 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1709 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1710 &clk_mgr->wm_range_table_addr);
1711 if (!clk_mgr->wm_range_table) {
1712 BREAK_TO_DEBUGGER();
1713 kfree(clk_mgr->base.bw_params);
1714 kfree(clk_mgr401);
1715 return NULL;
1716 }
1717
1718 return &clk_mgr401->base;
1719 }
1720
dcn401_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1721 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1722 {
1723 kfree(clk_mgr->base.bw_params);
1724
1725 if (clk_mgr->wm_range_table)
1726 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1727 clk_mgr->wm_range_table);
1728 }
1729
1730