1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "dc_bios_types.h"
29 #include "core_types.h"
30 #include "core_status.h"
31 #include "resource.h"
32 #include "dm_helpers.h"
33 #include "dce110_hwseq.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "dce/dce_hwseq.h"
36 #include "gpio_service_interface.h"
37
38 #include "dce110/dce110_compressor.h"
39
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
43 #include "opp.h"
44 #include "ipp.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "link_enc_cfg.h"
49 #include "link_hwss.h"
50 #include "link.h"
51 #include "dccg.h"
52 #include "clock_source.h"
53 #include "clk_mgr.h"
54 #include "abm.h"
55 #include "audio.h"
56 #include "reg_helper.h"
57 #include "panel_cntl.h"
58 #include "dc_state_priv.h"
59 #include "dpcd_defs.h"
60 #include "dsc.h"
61 /* include DCE11 register header files */
62 #include "dce/dce_11_0_d.h"
63 #include "dce/dce_11_0_sh_mask.h"
64 #include "custom_float.h"
65
66 #include "atomfirmware.h"
67
68 #include "dcn10/dcn10_hwseq.h"
69
70 #define GAMMA_HW_POINTS_NUM 256
71
72 /*
73 * All values are in milliseconds;
74 * For eDP, after power-up/power/down,
75 * 300/500 msec max. delay from LCDVCC to black video generation
76 */
77 #define PANEL_POWER_UP_TIMEOUT 300
78 #define PANEL_POWER_DOWN_TIMEOUT 500
79 #define HPD_CHECK_INTERVAL 10
80 #define OLED_POST_T7_DELAY 100
81 #define OLED_PRE_T11_DELAY 150
82
83 #define CTX \
84 hws->ctx
85
86 #define DC_LOGGER \
87 ctx->logger
88 #define DC_LOGGER_INIT() \
89 struct dc_context *ctx = dc->ctx
90
91 #define REG(reg)\
92 hws->regs->reg
93
94 #undef FN
95 #define FN(reg_name, field_name) \
96 hws->shifts->field_name, hws->masks->field_name
97
98 struct dce110_hw_seq_reg_offsets {
99 uint32_t crtc;
100 };
101
102 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
103 {
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 },
106 {
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
108 },
109 {
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
111 },
112 {
113 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
114 }
115 };
116
117 #define HW_REG_BLND(reg, id)\
118 (reg + reg_offsets[id].blnd)
119
120 #define HW_REG_CRTC(reg, id)\
121 (reg + reg_offsets[id].crtc)
122
123 #define MAX_WATERMARK 0xFFFF
124 #define SAFE_NBP_MARK 0x7FFF
125
126 /*******************************************************************************
127 * Private definitions
128 ******************************************************************************/
129 /***************************PIPE_CONTROL***********************************/
dce110_init_pte(struct dc_context * ctx)130 static void dce110_init_pte(struct dc_context *ctx)
131 {
132 uint32_t addr;
133 uint32_t value = 0;
134 uint32_t chunk_int = 0;
135 uint32_t chunk_mul = 0;
136
137 addr = mmUNP_DVMM_PTE_CONTROL;
138 value = dm_read_reg(ctx, addr);
139
140 set_reg_field_value(
141 value,
142 0,
143 DVMM_PTE_CONTROL,
144 DVMM_USE_SINGLE_PTE);
145
146 set_reg_field_value(
147 value,
148 1,
149 DVMM_PTE_CONTROL,
150 DVMM_PTE_BUFFER_MODE0);
151
152 set_reg_field_value(
153 value,
154 1,
155 DVMM_PTE_CONTROL,
156 DVMM_PTE_BUFFER_MODE1);
157
158 dm_write_reg(ctx, addr, value);
159
160 addr = mmDVMM_PTE_REQ;
161 value = dm_read_reg(ctx, addr);
162
163 chunk_int = get_reg_field_value(
164 value,
165 DVMM_PTE_REQ,
166 HFLIP_PTEREQ_PER_CHUNK_INT);
167
168 chunk_mul = get_reg_field_value(
169 value,
170 DVMM_PTE_REQ,
171 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
172
173 if (chunk_int != 0x4 || chunk_mul != 0x4) {
174
175 set_reg_field_value(
176 value,
177 255,
178 DVMM_PTE_REQ,
179 MAX_PTEREQ_TO_ISSUE);
180
181 set_reg_field_value(
182 value,
183 4,
184 DVMM_PTE_REQ,
185 HFLIP_PTEREQ_PER_CHUNK_INT);
186
187 set_reg_field_value(
188 value,
189 4,
190 DVMM_PTE_REQ,
191 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
192
193 dm_write_reg(ctx, addr, value);
194 }
195 }
196 /**************************************************************************/
197
enable_display_pipe_clock_gating(struct dc_context * ctx,bool clock_gating)198 static void enable_display_pipe_clock_gating(
199 struct dc_context *ctx,
200 bool clock_gating)
201 {
202 /*TODO*/
203 }
204
dce110_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)205 static bool dce110_enable_display_power_gating(
206 struct dc *dc,
207 uint8_t controller_id,
208 struct dc_bios *dcb,
209 enum pipe_gating_control power_gating)
210 {
211 enum bp_result bp_result = BP_RESULT_OK;
212 enum bp_pipe_control_action cntl;
213 struct dc_context *ctx = dc->ctx;
214 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
215
216 if (power_gating == PIPE_GATING_CONTROL_INIT)
217 cntl = ASIC_PIPE_INIT;
218 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
219 cntl = ASIC_PIPE_ENABLE;
220 else
221 cntl = ASIC_PIPE_DISABLE;
222
223 if (controller_id == underlay_idx)
224 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
225
226 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
227
228 bp_result = dcb->funcs->enable_disp_power_gating(
229 dcb, controller_id + 1, cntl);
230
231 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
232 * by default when command table is called
233 *
234 * Bios parser accepts controller_id = 6 as indicative of
235 * underlay pipe in dce110. But we do not support more
236 * than 3.
237 */
238 if (controller_id < CONTROLLER_ID_MAX - 1)
239 dm_write_reg(ctx,
240 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
241 0);
242 }
243
244 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
245 dce110_init_pte(ctx);
246
247 if (bp_result == BP_RESULT_OK)
248 return true;
249 else
250 return false;
251 }
252
dce110_prescale_params(struct ipp_prescale_params * prescale_params,const struct dc_plane_state * plane_state)253 static void dce110_prescale_params(struct ipp_prescale_params *prescale_params,
254 const struct dc_plane_state *plane_state)
255 {
256 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
257
258 switch (plane_state->format) {
259 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
260 prescale_params->scale = 0x2082;
261 break;
262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
263 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
264 prescale_params->scale = 0x2020;
265 break;
266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
268 prescale_params->scale = 0x2008;
269 break;
270 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
272 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
273 prescale_params->scale = 0x2000;
274 break;
275 default:
276 ASSERT(false);
277 break;
278 }
279 }
280
281 static bool
dce110_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)282 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
283 const struct dc_plane_state *plane_state)
284 {
285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
286 const struct dc_transfer_func *tf = NULL;
287 struct ipp_prescale_params prescale_params = { 0 };
288 bool result = true;
289
290 if (ipp == NULL)
291 return false;
292
293 tf = &plane_state->in_transfer_func;
294
295 dce110_prescale_params(&prescale_params, plane_state);
296 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
297
298 if (!plane_state->gamma_correction.is_identity &&
299 dce_use_lut(plane_state->format))
300 ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);
301
302 if (tf->type == TF_TYPE_PREDEFINED) {
303 switch (tf->tf) {
304 case TRANSFER_FUNCTION_SRGB:
305 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
306 break;
307 case TRANSFER_FUNCTION_BT709:
308 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
309 break;
310 case TRANSFER_FUNCTION_LINEAR:
311 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
312 break;
313 case TRANSFER_FUNCTION_PQ:
314 default:
315 result = false;
316 break;
317 }
318 } else if (tf->type == TF_TYPE_BYPASS) {
319 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
320 } else {
321 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
322 result = false;
323 }
324
325 return result;
326 }
327
convert_to_custom_float(struct pwl_result_data * rgb_resulted,struct curve_points * arr_points,uint32_t hw_points_num)328 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
329 struct curve_points *arr_points,
330 uint32_t hw_points_num)
331 {
332 struct custom_float_format fmt;
333
334 struct pwl_result_data *rgb = rgb_resulted;
335
336 uint32_t i = 0;
337
338 fmt.exponenta_bits = 6;
339 fmt.mantissa_bits = 12;
340 fmt.sign = true;
341
342 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
343 &arr_points[0].custom_float_x)) {
344 BREAK_TO_DEBUGGER();
345 return false;
346 }
347
348 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
349 &arr_points[0].custom_float_offset)) {
350 BREAK_TO_DEBUGGER();
351 return false;
352 }
353
354 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
355 &arr_points[0].custom_float_slope)) {
356 BREAK_TO_DEBUGGER();
357 return false;
358 }
359
360 fmt.mantissa_bits = 10;
361 fmt.sign = false;
362
363 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
364 &arr_points[1].custom_float_x)) {
365 BREAK_TO_DEBUGGER();
366 return false;
367 }
368
369 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
370 &arr_points[1].custom_float_y)) {
371 BREAK_TO_DEBUGGER();
372 return false;
373 }
374
375 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
376 &arr_points[1].custom_float_slope)) {
377 BREAK_TO_DEBUGGER();
378 return false;
379 }
380
381 fmt.mantissa_bits = 12;
382 fmt.sign = true;
383
384 while (i != hw_points_num) {
385 if (!convert_to_custom_float_format(rgb->red, &fmt,
386 &rgb->red_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(rgb->green, &fmt,
392 &rgb->green_reg)) {
393 BREAK_TO_DEBUGGER();
394 return false;
395 }
396
397 if (!convert_to_custom_float_format(rgb->blue, &fmt,
398 &rgb->blue_reg)) {
399 BREAK_TO_DEBUGGER();
400 return false;
401 }
402
403 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
404 &rgb->delta_red_reg)) {
405 BREAK_TO_DEBUGGER();
406 return false;
407 }
408
409 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
410 &rgb->delta_green_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
416 &rgb->delta_blue_reg)) {
417 BREAK_TO_DEBUGGER();
418 return false;
419 }
420
421 ++rgb;
422 ++i;
423 }
424
425 return true;
426 }
427
428 #define MAX_LOW_POINT 25
429 #define NUMBER_REGIONS 16
430 #define NUMBER_SW_SEGMENTS 16
431
432 static bool
dce110_translate_regamma_to_hw_format(const struct dc_transfer_func * output_tf,struct pwl_params * regamma_params)433 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
434 struct pwl_params *regamma_params)
435 {
436 struct curve_points *arr_points;
437 struct pwl_result_data *rgb_resulted;
438 struct pwl_result_data *rgb;
439 struct pwl_result_data *rgb_plus_1;
440 struct fixed31_32 y_r;
441 struct fixed31_32 y_g;
442 struct fixed31_32 y_b;
443 struct fixed31_32 y1_min;
444 struct fixed31_32 y3_max;
445
446 int32_t region_start, region_end;
447 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
448
449 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
450 return false;
451
452 arr_points = regamma_params->arr_points;
453 rgb_resulted = regamma_params->rgb_resulted;
454 hw_points = 0;
455
456 memset(regamma_params, 0, sizeof(struct pwl_params));
457
458 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
459 /* 16 segments
460 * segments are from 2^-11 to 2^5
461 */
462 region_start = -11;
463 region_end = region_start + NUMBER_REGIONS;
464
465 for (i = 0; i < NUMBER_REGIONS; i++)
466 seg_distr[i] = 4;
467
468 } else {
469 /* 10 segments
470 * segment is from 2^-10 to 2^1
471 * We include an extra segment for range [2^0, 2^1). This is to
472 * ensure that colors with normalized values of 1 don't miss the
473 * LUT.
474 */
475 region_start = -10;
476 region_end = 1;
477
478 seg_distr[0] = 4;
479 seg_distr[1] = 4;
480 seg_distr[2] = 4;
481 seg_distr[3] = 4;
482 seg_distr[4] = 4;
483 seg_distr[5] = 4;
484 seg_distr[6] = 4;
485 seg_distr[7] = 4;
486 seg_distr[8] = 4;
487 seg_distr[9] = 4;
488 seg_distr[10] = 0;
489 seg_distr[11] = -1;
490 seg_distr[12] = -1;
491 seg_distr[13] = -1;
492 seg_distr[14] = -1;
493 seg_distr[15] = -1;
494 }
495
496 for (k = 0; k < 16; k++) {
497 if (seg_distr[k] != -1)
498 hw_points += (1 << seg_distr[k]);
499 }
500
501 j = 0;
502 for (k = 0; k < (region_end - region_start); k++) {
503 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
504 start_index = (region_start + k + MAX_LOW_POINT) *
505 NUMBER_SW_SEGMENTS;
506 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
507 i += increment) {
508 if (j == hw_points - 1)
509 break;
510 rgb_resulted[j].red = output_tf->tf_pts.red[i];
511 rgb_resulted[j].green = output_tf->tf_pts.green[i];
512 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
513 j++;
514 }
515 }
516
517 /* last point */
518 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
519 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
520 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
521 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
522
523 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
524 dc_fixpt_from_int(region_start));
525 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
526 dc_fixpt_from_int(region_end));
527
528 y_r = rgb_resulted[0].red;
529 y_g = rgb_resulted[0].green;
530 y_b = rgb_resulted[0].blue;
531
532 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
533
534 arr_points[0].y = y1_min;
535 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
536 arr_points[0].x);
537
538 y_r = rgb_resulted[hw_points - 1].red;
539 y_g = rgb_resulted[hw_points - 1].green;
540 y_b = rgb_resulted[hw_points - 1].blue;
541
542 /* see comment above, m_arrPoints[1].y should be the Y value for the
543 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
544 */
545 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
546
547 arr_points[1].y = y3_max;
548
549 arr_points[1].slope = dc_fixpt_zero;
550
551 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
552 /* for PQ, we want to have a straight line from last HW X point,
553 * and the slope to be such that we hit 1.0 at 10000 nits.
554 */
555 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
556
557 arr_points[1].slope = dc_fixpt_div(
558 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
559 dc_fixpt_sub(end_value, arr_points[1].x));
560 }
561
562 regamma_params->hw_points_num = hw_points;
563
564 k = 0;
565 for (i = 1; i < 16; i++) {
566 if (seg_distr[k] != -1) {
567 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
568 regamma_params->arr_curve_points[i].offset =
569 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
570 }
571 k++;
572 }
573
574 if (seg_distr[k] != -1)
575 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
576
577 rgb = rgb_resulted;
578 rgb_plus_1 = rgb_resulted + 1;
579
580 i = 1;
581
582 while (i != hw_points + 1) {
583 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
584 rgb_plus_1->red = rgb->red;
585 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
586 rgb_plus_1->green = rgb->green;
587 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
588 rgb_plus_1->blue = rgb->blue;
589
590 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
591 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
592 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
593
594 ++rgb_plus_1;
595 ++rgb;
596 ++i;
597 }
598
599 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
600
601 return true;
602 }
603
604 static bool
dce110_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)605 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
606 const struct dc_stream_state *stream)
607 {
608 struct transform *xfm = pipe_ctx->plane_res.xfm;
609
610 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
611 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
612
613 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED &&
614 stream->out_transfer_func.tf == TRANSFER_FUNCTION_SRGB) {
615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
616 } else if (dce110_translate_regamma_to_hw_format(&stream->out_transfer_func,
617 &xfm->regamma_params)) {
618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
620 } else {
621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
622 }
623
624 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
625
626 return true;
627 }
628
dce110_update_info_frame(struct pipe_ctx * pipe_ctx)629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
630 {
631 bool is_hdmi_tmds;
632 bool is_dp;
633
634 ASSERT(pipe_ctx->stream);
635
636 if (pipe_ctx->stream_res.stream_enc == NULL)
637 return; /* this is not root pipe */
638
639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
641
642 if (!is_hdmi_tmds && !is_dp)
643 return;
644
645 if (is_hdmi_tmds)
646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
647 pipe_ctx->stream_res.stream_enc,
648 &pipe_ctx->stream_res.encoder_info_frame);
649 else {
650 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
651 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
652 pipe_ctx->stream_res.stream_enc,
653 &pipe_ctx->stream_res.encoder_info_frame);
654
655 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
656 pipe_ctx->stream_res.stream_enc,
657 &pipe_ctx->stream_res.encoder_info_frame);
658 }
659 }
660
dce110_enable_stream(struct pipe_ctx * pipe_ctx)661 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
662 {
663 enum dc_lane_count lane_count =
664 pipe_ctx->stream->link->cur_link_settings.lane_count;
665 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
666 struct dc_link *link = pipe_ctx->stream->link;
667 const struct dc *dc = link->dc;
668 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
669 uint32_t active_total_with_borders;
670 uint32_t early_control = 0;
671 struct timing_generator *tg = pipe_ctx->stream_res.tg;
672
673 link_hwss->setup_stream_encoder(pipe_ctx);
674
675 dc->hwss.update_info_frame(pipe_ctx);
676
677 /* enable early control to avoid corruption on DP monitor*/
678 active_total_with_borders =
679 timing->h_addressable
680 + timing->h_border_left
681 + timing->h_border_right;
682
683 if (lane_count != 0)
684 early_control = active_total_with_borders % lane_count;
685
686 if (early_control == 0)
687 early_control = lane_count;
688
689 tg->funcs->set_early_control(tg, early_control);
690 }
691
link_transmitter_control(struct dc_bios * bios,struct bp_transmitter_control * cntl)692 static enum bp_result link_transmitter_control(
693 struct dc_bios *bios,
694 struct bp_transmitter_control *cntl)
695 {
696 enum bp_result result;
697
698 result = bios->funcs->transmitter_control(bios, cntl);
699
700 return result;
701 }
702
703 /*
704 * @brief
705 * eDP only.
706 */
dce110_edp_wait_for_hpd_ready(struct dc_link * link,bool power_up)707 void dce110_edp_wait_for_hpd_ready(
708 struct dc_link *link,
709 bool power_up)
710 {
711 struct dc_context *ctx = link->ctx;
712 struct graphics_object_id connector = link->link_enc->connector;
713 struct gpio *hpd;
714 bool edp_hpd_high = false;
715 uint32_t time_elapsed = 0;
716 uint32_t timeout = power_up ?
717 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
718
719 if (dal_graphics_object_id_get_connector_id(connector)
720 != CONNECTOR_ID_EDP) {
721 BREAK_TO_DEBUGGER();
722 return;
723 }
724
725 if (!power_up)
726 /*
727 * From KV, we will not HPD low after turning off VCC -
728 * instead, we will check the SW timer in power_up().
729 */
730 return;
731
732 /*
733 * When we power on/off the eDP panel,
734 * we need to wait until SENSE bit is high/low.
735 */
736
737 /* obtain HPD */
738 /* TODO what to do with this? */
739 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
740
741 if (!hpd) {
742 BREAK_TO_DEBUGGER();
743 return;
744 }
745
746 if (link->panel_config.pps.extra_t3_ms > 0) {
747 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
748
749 msleep(extra_t3_in_ms);
750 }
751
752 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
753
754 /* wait until timeout or panel detected */
755
756 do {
757 uint32_t detected = 0;
758
759 dal_gpio_get_value(hpd, &detected);
760
761 if (!(detected ^ power_up)) {
762 edp_hpd_high = true;
763 break;
764 }
765
766 msleep(HPD_CHECK_INTERVAL);
767
768 time_elapsed += HPD_CHECK_INTERVAL;
769 } while (time_elapsed < timeout);
770
771 dal_gpio_close(hpd);
772
773 dal_gpio_destroy_irq(&hpd);
774
775 /* ensure that the panel is detected */
776 if (!edp_hpd_high)
777 DC_LOG_DC("%s: wait timed out!\n", __func__);
778 }
779
dce110_edp_power_control(struct dc_link * link,bool power_up)780 void dce110_edp_power_control(
781 struct dc_link *link,
782 bool power_up)
783 {
784 struct dc_context *ctx = link->ctx;
785 struct bp_transmitter_control cntl = { 0 };
786 enum bp_result bp_result;
787 uint8_t pwrseq_instance;
788
789
790 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
791 != CONNECTOR_ID_EDP) {
792 BREAK_TO_DEBUGGER();
793 return;
794 }
795
796 if (!link->panel_cntl)
797 return;
798 if (power_up !=
799 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
800
801 unsigned long long current_ts = dm_get_timestamp(ctx);
802 unsigned long long time_since_edp_poweroff_ms =
803 div64_u64(dm_get_elapse_time_in_ns(
804 ctx,
805 current_ts,
806 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
807 unsigned long long time_since_edp_poweron_ms =
808 div64_u64(dm_get_elapse_time_in_ns(
809 ctx,
810 current_ts,
811 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
812 DC_LOG_HW_RESUME_S3(
813 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
814 __func__,
815 power_up,
816 current_ts,
817 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
818 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
819 time_since_edp_poweroff_ms,
820 time_since_edp_poweron_ms);
821
822 /* Send VBIOS command to prompt eDP panel power */
823 if (power_up) {
824 /* edp requires a min of 500ms from LCDVDD off to on */
825 unsigned long long remaining_min_edp_poweroff_time_ms = 500;
826
827 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
828 if (link->local_sink != NULL)
829 remaining_min_edp_poweroff_time_ms +=
830 link->panel_config.pps.extra_t12_ms;
831
832 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
833 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
834 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
835 remaining_min_edp_poweroff_time_ms =
836 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
837 else
838 remaining_min_edp_poweroff_time_ms = 0;
839 }
840
841 if (remaining_min_edp_poweroff_time_ms) {
842 DC_LOG_HW_RESUME_S3(
843 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
844 __func__, remaining_min_edp_poweroff_time_ms);
845 msleep(remaining_min_edp_poweroff_time_ms);
846 DC_LOG_HW_RESUME_S3(
847 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
848 __func__, remaining_min_edp_poweroff_time_ms);
849 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
850 __func__, remaining_min_edp_poweroff_time_ms);
851 } else {
852 DC_LOG_HW_RESUME_S3(
853 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
854 __func__, remaining_min_edp_poweroff_time_ms);
855 }
856 }
857
858 DC_LOG_HW_RESUME_S3(
859 "%s: BEGIN: Panel Power action: %s\n",
860 __func__, (power_up ? "On":"Off"));
861
862 cntl.action = power_up ?
863 TRANSMITTER_CONTROL_POWER_ON :
864 TRANSMITTER_CONTROL_POWER_OFF;
865 cntl.transmitter = link->link_enc->transmitter;
866 cntl.connector_obj_id = link->link_enc->connector;
867 cntl.coherent = false;
868 cntl.lanes_number = LANE_COUNT_FOUR;
869 cntl.hpd_sel = link->link_enc->hpd_source;
870 pwrseq_instance = link->panel_cntl->pwrseq_inst;
871
872 if (ctx->dc->ctx->dmub_srv &&
873 ctx->dc->debug.dmub_command_table) {
874
875 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
876 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
877 LVTMA_CONTROL_POWER_ON,
878 pwrseq_instance, link->link_powered_externally);
879 } else {
880 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
881 LVTMA_CONTROL_POWER_OFF,
882 pwrseq_instance, link->link_powered_externally);
883 }
884 }
885
886 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
887
888 DC_LOG_HW_RESUME_S3(
889 "%s: END: Panel Power action: %s bp_result=%u\n",
890 __func__, (power_up ? "On":"Off"),
891 bp_result);
892
893 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
894
895 DC_LOG_HW_RESUME_S3(
896 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
897 __func__,
898 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
899 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
900
901 if (bp_result != BP_RESULT_OK)
902 DC_LOG_ERROR(
903 "%s: Panel Power bp_result: %d\n",
904 __func__, bp_result);
905 } else {
906 DC_LOG_HW_RESUME_S3(
907 "%s: Skipping Panel Power action: %s\n",
908 __func__, (power_up ? "On":"Off"));
909 }
910 }
911
dce110_edp_wait_for_T12(struct dc_link * link)912 void dce110_edp_wait_for_T12(
913 struct dc_link *link)
914 {
915 struct dc_context *ctx = link->ctx;
916
917 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
918 != CONNECTOR_ID_EDP) {
919 BREAK_TO_DEBUGGER();
920 return;
921 }
922
923 if (!link->panel_cntl)
924 return;
925
926 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
927 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
928 unsigned int t12_duration = 500; // Default T12 as per spec
929 unsigned long long current_ts = dm_get_timestamp(ctx);
930 unsigned long long time_since_edp_poweroff_ms =
931 div64_u64(dm_get_elapse_time_in_ns(
932 ctx,
933 current_ts,
934 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
935
936 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
937
938 if (time_since_edp_poweroff_ms < t12_duration)
939 msleep(t12_duration - time_since_edp_poweroff_ms);
940 }
941 }
942 /*todo: cloned in stream enc, fix*/
943 /*
944 * @brief
945 * eDP only. Control the backlight of the eDP panel
946 */
dce110_edp_backlight_control(struct dc_link * link,bool enable)947 void dce110_edp_backlight_control(
948 struct dc_link *link,
949 bool enable)
950 {
951 struct dc_context *ctx = link->ctx;
952 struct bp_transmitter_control cntl = { 0 };
953 uint8_t pwrseq_instance = 0;
954 unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0);
955 unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0);
956
957 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
958 != CONNECTOR_ID_EDP) {
959 BREAK_TO_DEBUGGER();
960 return;
961 }
962
963 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
964 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
965 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
966 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
967
968 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
969 DC_LOG_HW_RESUME_S3(
970 "%s: panel already powered up/off. Do nothing.\n",
971 __func__);
972 return;
973 }
974 }
975
976 /* Send VBIOS command to control eDP panel backlight */
977
978 DC_LOG_HW_RESUME_S3(
979 "%s: backlight action: %s\n",
980 __func__, (enable ? "On":"Off"));
981
982 cntl.action = enable ?
983 TRANSMITTER_CONTROL_BACKLIGHT_ON :
984 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
985
986 /*cntl.engine_id = ctx->engine;*/
987 cntl.transmitter = link->link_enc->transmitter;
988 cntl.connector_obj_id = link->link_enc->connector;
989 /*todo: unhardcode*/
990 cntl.lanes_number = LANE_COUNT_FOUR;
991 cntl.hpd_sel = link->link_enc->hpd_source;
992 cntl.signal = SIGNAL_TYPE_EDP;
993
994 /* For eDP, the following delays might need to be considered
995 * after link training completed:
996 * idle period - min. accounts for required BS-Idle pattern,
997 * max. allows for source frame synchronization);
998 * 50 msec max. delay from valid video data from source
999 * to video on dislpay or backlight enable.
1000 *
1001 * Disable the delay for now.
1002 * Enable it in the future if necessary.
1003 */
1004 /* dc_service_sleep_in_milliseconds(50); */
1005 /*edp 1.2*/
1006 if (link->panel_cntl)
1007 pwrseq_instance = link->panel_cntl->pwrseq_inst;
1008
1009 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1010 if (!link->dc->config.edp_no_power_sequencing)
1011 /*
1012 * Sometimes, DP receiver chip power-controlled externally by an
1013 * Embedded Controller could be treated and used as eDP,
1014 * if it drives mobile display. In this case,
1015 * we shouldn't be doing power-sequencing, hence we can skip
1016 * waiting for T7-ready.
1017 */
1018 ctx->dc->link_srv->edp_receiver_ready_T7(link);
1019 else
1020 DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1021 }
1022
1023 /* Setting link_powered_externally will bypass delays in the backlight
1024 * as they are not required if the link is being powered by a different
1025 * source.
1026 */
1027 if (ctx->dc->ctx->dmub_srv &&
1028 ctx->dc->debug.dmub_command_table) {
1029 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1030 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1031 LVTMA_CONTROL_LCD_BLON,
1032 pwrseq_instance, link->link_powered_externally);
1033 else
1034 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1035 LVTMA_CONTROL_LCD_BLOFF,
1036 pwrseq_instance, link->link_powered_externally);
1037 }
1038
1039 link_transmitter_control(ctx->dc_bios, &cntl);
1040
1041 if (enable && link->dpcd_sink_ext_caps.bits.oled &&
1042 !link->dc->config.edp_no_power_sequencing) {
1043 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1044 msleep(post_T7_delay);
1045 }
1046
1047 if (link->dpcd_sink_ext_caps.bits.oled ||
1048 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1049 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1050 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1051
1052 /*edp 1.2*/
1053 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1054 if (!link->dc->config.edp_no_power_sequencing)
1055 /*
1056 * Sometimes, DP receiver chip power-controlled externally by an
1057 * Embedded Controller could be treated and used as eDP,
1058 * if it drives mobile display. In this case,
1059 * we shouldn't be doing power-sequencing, hence we can skip
1060 * waiting for T9-ready.
1061 */
1062 ctx->dc->link_srv->edp_add_delay_for_T9(link);
1063 else
1064 DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1065 }
1066
1067 if (!enable) {
1068 /*follow oem panel config's requirement*/
1069 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1070 if (pre_T11_delay)
1071 msleep(pre_T11_delay);
1072 }
1073 }
1074
dce110_enable_audio_stream(struct pipe_ctx * pipe_ctx)1075 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1076 {
1077 /* notify audio driver for audio modes of monitor */
1078 struct dc *dc;
1079 struct clk_mgr *clk_mgr;
1080 unsigned int i, num_audio = 1;
1081 const struct link_hwss *link_hwss;
1082
1083 if (!pipe_ctx->stream)
1084 return;
1085
1086 dc = pipe_ctx->stream->ctx->dc;
1087 clk_mgr = dc->clk_mgr;
1088 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1089
1090 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1091 return;
1092
1093 if (pipe_ctx->stream_res.audio) {
1094 for (i = 0; i < MAX_PIPES; i++) {
1095 /*current_state not updated yet*/
1096 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1097 num_audio++;
1098 }
1099
1100 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1101
1102 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1103 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1104 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1105
1106 link_hwss->enable_audio_packet(pipe_ctx);
1107
1108 if (pipe_ctx->stream_res.audio)
1109 pipe_ctx->stream_res.audio->enabled = true;
1110 }
1111 }
1112
dce110_disable_audio_stream(struct pipe_ctx * pipe_ctx)1113 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1114 {
1115 struct dc *dc;
1116 struct clk_mgr *clk_mgr;
1117 const struct link_hwss *link_hwss;
1118
1119 if (!pipe_ctx || !pipe_ctx->stream)
1120 return;
1121
1122 dc = pipe_ctx->stream->ctx->dc;
1123 clk_mgr = dc->clk_mgr;
1124 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1125
1126 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1127 return;
1128
1129 link_hwss->disable_audio_packet(pipe_ctx);
1130
1131 if (pipe_ctx->stream_res.audio) {
1132 pipe_ctx->stream_res.audio->enabled = false;
1133
1134 if (clk_mgr->funcs->enable_pme_wa)
1135 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1136 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1137
1138 /* TODO: notify audio driver for if audio modes list changed
1139 * add audio mode list change flag */
1140 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1141 * stream->stream_engine_id);
1142 */
1143 }
1144 }
1145
dce110_disable_stream(struct pipe_ctx * pipe_ctx)1146 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1147 {
1148 struct dc_stream_state *stream = pipe_ctx->stream;
1149 struct dc_link *link = stream->link;
1150 struct dc *dc = pipe_ctx->stream->ctx->dc;
1151 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1152 struct dccg *dccg = dc->res_pool->dccg;
1153 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1154 struct dtbclk_dto_params dto_params = {0};
1155 int dp_hpo_inst;
1156 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1157 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1158
1159 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1160 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1161 pipe_ctx->stream_res.stream_enc);
1162 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1163 pipe_ctx->stream_res.stream_enc);
1164 }
1165
1166 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1167 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1168 pipe_ctx->stream_res.hpo_dp_stream_enc);
1169 } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1170 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1171 pipe_ctx->stream_res.stream_enc);
1172
1173 dc->hwss.disable_audio_stream(pipe_ctx);
1174
1175 link_hwss->reset_stream_encoder(pipe_ctx);
1176
1177 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {
1178 dto_params.otg_inst = tg->inst;
1179 dto_params.timing = &pipe_ctx->stream->timing;
1180 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1181 if (dccg) {
1182 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1183 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1184 if (dccg && dccg->funcs->set_dtbclk_dto)
1185 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1186 }
1187 } else if (dccg && dccg->funcs->disable_symclk_se) {
1188 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1189 link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1190 }
1191 }
1192
dce110_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1193 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1194 struct dc_link_settings *link_settings)
1195 {
1196 struct encoder_unblank_param params = { { 0 } };
1197 struct dc_stream_state *stream = pipe_ctx->stream;
1198 struct dc_link *link = stream->link;
1199 struct dce_hwseq *hws = link->dc->hwseq;
1200
1201 /* only 3 items below are used by unblank */
1202 params.timing = pipe_ctx->stream->timing;
1203 params.link_settings.link_rate = link_settings->link_rate;
1204
1205 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1206 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1207
1208 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1209 hws->funcs.edp_backlight_control(link, true);
1210 }
1211 }
1212
dce110_blank_stream(struct pipe_ctx * pipe_ctx)1213 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1214 {
1215 struct dc_stream_state *stream = pipe_ctx->stream;
1216 struct dc_link *link = stream->link;
1217 struct dce_hwseq *hws = link->dc->hwseq;
1218
1219 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1220 if (!link->skip_implict_edp_power_control && hws)
1221 hws->funcs.edp_backlight_control(link, false);
1222 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1223 }
1224
1225 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1226 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1227 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1228 pipe_ctx->stream_res.hpo_dp_stream_enc);
1229 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1230 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1231
1232 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1233 /*
1234 * After output is idle pattern some sinks need time to recognize the stream
1235 * has changed or they enter protection state and hang.
1236 */
1237 msleep(60);
1238 }
1239 }
1240
1241 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
1242 !link->dc->config.edp_no_power_sequencing) {
1243 /*
1244 * Sometimes, DP receiver chip power-controlled externally by an
1245 * Embedded Controller could be treated and used as eDP,
1246 * if it drives mobile display. In this case,
1247 * we shouldn't be doing power-sequencing, hence we can skip
1248 * waiting for T9-ready.
1249 */
1250 link->dc->link_srv->edp_receiver_ready_T9(link);
1251 }
1252
1253 }
1254
1255
dce110_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)1256 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1257 {
1258 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1259 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1260 }
1261
translate_to_dto_source(enum controller_id crtc_id)1262 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1263 {
1264 switch (crtc_id) {
1265 case CONTROLLER_ID_D0:
1266 return DTO_SOURCE_ID0;
1267 case CONTROLLER_ID_D1:
1268 return DTO_SOURCE_ID1;
1269 case CONTROLLER_ID_D2:
1270 return DTO_SOURCE_ID2;
1271 case CONTROLLER_ID_D3:
1272 return DTO_SOURCE_ID3;
1273 case CONTROLLER_ID_D4:
1274 return DTO_SOURCE_ID4;
1275 case CONTROLLER_ID_D5:
1276 return DTO_SOURCE_ID5;
1277 default:
1278 return DTO_SOURCE_UNKNOWN;
1279 }
1280 }
1281
populate_audio_dp_link_info(const struct pipe_ctx * pipe_ctx,struct audio_dp_link_info * dp_link_info)1282 static void populate_audio_dp_link_info(
1283 const struct pipe_ctx *pipe_ctx,
1284 struct audio_dp_link_info *dp_link_info)
1285 {
1286 const struct dc_stream_state *stream = pipe_ctx->stream;
1287 const struct dc_link *link = stream->link;
1288 struct fixed31_32 link_bw_kbps;
1289
1290 dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format(
1291 &pipe_ctx->link_config.dp_link_settings);
1292 dp_link_info->is_mst = (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
1293 dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;
1294 dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;
1295
1296 link_bw_kbps = dc_fixpt_from_int(dc_link_bandwidth_kbps(link,
1297 &pipe_ctx->link_config.dp_link_settings));
1298
1299 /* For audio stream calculations, the video stream should not include FEC or SSC
1300 * in order to get the most pessimistic values.
1301 */
1302 if (dp_link_info->encoding == DP_8b_10b_ENCODING &&
1303 link->dc->link_srv->dp_is_fec_supported(link)) {
1304 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,
1305 dc_fixpt_from_fraction(100, DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100));
1306 } else if (dp_link_info->encoding == DP_128b_132b_ENCODING) {
1307 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,
1308 dc_fixpt_from_fraction(10000, 9975)); /* 99.75% SSC overhead*/
1309 }
1310
1311 dp_link_info->link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps);
1312
1313 /* Calculates hblank_min_symbol_width for 128b/132b
1314 * Corresponding HBLANK_MIN_SYMBOL_WIDTH register is calculated as:
1315 * floor(h_blank * bits_per_pixel / 128)
1316 */
1317 if (dp_link_info->encoding == DP_128b_132b_ENCODING) {
1318 struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;
1319
1320 uint32_t h_active = crtc_timing->h_addressable + crtc_timing->h_border_left
1321 + crtc_timing->h_border_right;
1322 uint32_t h_blank = crtc_timing->h_total - h_active;
1323
1324 uint32_t bpp;
1325
1326 if (crtc_timing->flags.DSC) {
1327 bpp = crtc_timing->dsc_cfg.bits_per_pixel;
1328 } else {
1329 /* When the timing is using DSC, dsc_cfg.bits_per_pixel is in 16th bits.
1330 * The bpp in this path is scaled to 16th bits so the final calculation
1331 * is correct for both cases.
1332 */
1333 bpp = 16;
1334 switch (crtc_timing->display_color_depth) {
1335 case COLOR_DEPTH_666:
1336 bpp *= 18;
1337 break;
1338 case COLOR_DEPTH_888:
1339 bpp *= 24;
1340 break;
1341 case COLOR_DEPTH_101010:
1342 bpp *= 30;
1343 break;
1344 case COLOR_DEPTH_121212:
1345 bpp *= 36;
1346 break;
1347 default:
1348 bpp = 0;
1349 break;
1350 }
1351
1352 switch (crtc_timing->pixel_encoding) {
1353 case PIXEL_ENCODING_YCBCR422:
1354 bpp = bpp * 2 / 3;
1355 break;
1356 case PIXEL_ENCODING_YCBCR420:
1357 bpp /= 2;
1358 break;
1359 default:
1360 break;
1361 }
1362 }
1363
1364 /* Min symbol width = floor(h_blank * (bpp/16) / 128) */
1365 dp_link_info->hblank_min_symbol_width = dc_fixpt_floor(
1366 dc_fixpt_div(dc_fixpt_from_int(h_blank * bpp),
1367 dc_fixpt_from_int(128 / 16)));
1368
1369 } else {
1370 dp_link_info->hblank_min_symbol_width = 0;
1371 }
1372 }
1373
build_audio_output(struct dc_state * state,const struct pipe_ctx * pipe_ctx,struct audio_output * audio_output)1374 static void build_audio_output(
1375 struct dc_state *state,
1376 const struct pipe_ctx *pipe_ctx,
1377 struct audio_output *audio_output)
1378 {
1379 const struct dc_stream_state *stream = pipe_ctx->stream;
1380 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1381
1382 audio_output->signal = pipe_ctx->stream->signal;
1383
1384 /* audio_crtc_info */
1385
1386 audio_output->crtc_info.h_total =
1387 stream->timing.h_total;
1388
1389 /*
1390 * Audio packets are sent during actual CRTC blank physical signal, we
1391 * need to specify actual active signal portion
1392 */
1393 audio_output->crtc_info.h_active =
1394 stream->timing.h_addressable
1395 + stream->timing.h_border_left
1396 + stream->timing.h_border_right;
1397
1398 audio_output->crtc_info.v_active =
1399 stream->timing.v_addressable
1400 + stream->timing.v_border_top
1401 + stream->timing.v_border_bottom;
1402
1403 audio_output->crtc_info.pixel_repetition = 1;
1404
1405 audio_output->crtc_info.interlaced =
1406 stream->timing.flags.INTERLACE;
1407
1408 audio_output->crtc_info.refresh_rate =
1409 (stream->timing.pix_clk_100hz*100)/
1410 (stream->timing.h_total*stream->timing.v_total);
1411
1412 audio_output->crtc_info.color_depth =
1413 stream->timing.display_color_depth;
1414
1415 audio_output->crtc_info.requested_pixel_clock_100Hz =
1416 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1417
1418 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1419 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1420
1421 audio_output->crtc_info.pixel_encoding =
1422 stream->timing.pixel_encoding;
1423
1424 audio_output->crtc_info.dsc_bits_per_pixel =
1425 stream->timing.dsc_cfg.bits_per_pixel;
1426
1427 audio_output->crtc_info.dsc_num_slices =
1428 stream->timing.dsc_cfg.num_slices_h;
1429
1430 /*for HDMI, audio ACR is with deep color ratio factor*/
1431 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1432 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1433 (stream->timing.pix_clk_100hz)) {
1434 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1435 audio_output->crtc_info.requested_pixel_clock_100Hz =
1436 audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1437 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1438 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1439
1440 }
1441 }
1442
1443 if (state->clk_mgr &&
1444 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1445 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1446 audio_output->pll_info.audio_dto_source_clock_in_khz =
1447 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1448 state->clk_mgr);
1449 }
1450
1451 audio_output->pll_info.feed_back_divider =
1452 pipe_ctx->pll_settings.feedback_divider;
1453
1454 audio_output->pll_info.dto_source =
1455 translate_to_dto_source(
1456 pipe_ctx->stream_res.tg->inst + 1);
1457
1458 /* TODO hard code to enable for now. Need get from stream */
1459 audio_output->pll_info.ss_enabled = true;
1460
1461 audio_output->pll_info.ss_percentage =
1462 pipe_ctx->pll_settings.ss_percentage;
1463
1464 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1465 populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);
1466 }
1467 }
1468
program_scaler(const struct dc * dc,const struct pipe_ctx * pipe_ctx)1469 static void program_scaler(const struct dc *dc,
1470 const struct pipe_ctx *pipe_ctx)
1471 {
1472 struct tg_color color = {0};
1473
1474 /* TOFPGA */
1475 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1476 return;
1477
1478 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1479 get_surface_visual_confirm_color(pipe_ctx, &color);
1480 else
1481 color_space_to_black_color(dc,
1482 pipe_ctx->stream->output_color_space,
1483 &color);
1484
1485 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1486 pipe_ctx->plane_res.xfm,
1487 pipe_ctx->plane_res.scl_data.lb_params.depth,
1488 &pipe_ctx->stream->bit_depth_params);
1489
1490 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1491 /*
1492 * The way 420 is packed, 2 channels carry Y component, 1 channel
1493 * alternate between Cb and Cr, so both channels need the pixel
1494 * value for Y
1495 */
1496 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1497 color.color_r_cr = color.color_g_y;
1498
1499 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1500 pipe_ctx->stream_res.tg,
1501 &color);
1502 }
1503
1504 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1505 &pipe_ctx->plane_res.scl_data);
1506 }
1507
dce110_enable_stream_timing(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1508 static enum dc_status dce110_enable_stream_timing(
1509 struct pipe_ctx *pipe_ctx,
1510 struct dc_state *context,
1511 struct dc *dc)
1512 {
1513 struct dc_stream_state *stream = pipe_ctx->stream;
1514 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1515 pipe_ctx[pipe_ctx->pipe_idx];
1516 struct tg_color black_color = {0};
1517
1518 if (!pipe_ctx_old->stream) {
1519
1520 /* program blank color */
1521 color_space_to_black_color(dc,
1522 stream->output_color_space, &black_color);
1523 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1524 pipe_ctx->stream_res.tg,
1525 &black_color);
1526
1527 /*
1528 * Must blank CRTC after disabling power gating and before any
1529 * programming, otherwise CRTC will be hung in bad state
1530 */
1531 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1532
1533 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1534 pipe_ctx->clock_source,
1535 &pipe_ctx->stream_res.pix_clk_params,
1536 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1537 &pipe_ctx->pll_settings)) {
1538 BREAK_TO_DEBUGGER();
1539 return DC_ERROR_UNEXPECTED;
1540 }
1541
1542 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1543 stream->link->phy_state.symclk_ref_cnts.otg = 1;
1544 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1545 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1546 else
1547 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1548 }
1549
1550 pipe_ctx->stream_res.tg->funcs->program_timing(
1551 pipe_ctx->stream_res.tg,
1552 &stream->timing,
1553 0,
1554 0,
1555 0,
1556 0,
1557 0,
1558 pipe_ctx->stream->signal,
1559 true);
1560 }
1561
1562 if (!pipe_ctx_old->stream) {
1563 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1564 pipe_ctx->stream_res.tg)) {
1565 BREAK_TO_DEBUGGER();
1566 return DC_ERROR_UNEXPECTED;
1567 }
1568 }
1569
1570 return DC_OK;
1571 }
1572
dce110_apply_single_controller_ctx_to_hw(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1573 enum dc_status dce110_apply_single_controller_ctx_to_hw(
1574 struct pipe_ctx *pipe_ctx,
1575 struct dc_state *context,
1576 struct dc *dc)
1577 {
1578 struct dc_stream_state *stream = pipe_ctx->stream;
1579 struct dc_link *link = stream->link;
1580 struct drr_params params = {0};
1581 unsigned int event_triggers = 0;
1582 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1583 struct dce_hwseq *hws = dc->hwseq;
1584 const struct link_hwss *link_hwss = get_link_hwss(
1585 link, &pipe_ctx->link_res);
1586
1587
1588 if (hws->funcs.disable_stream_gating) {
1589 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1590 }
1591
1592 if (pipe_ctx->stream_res.audio != NULL) {
1593 struct audio_output audio_output = {0};
1594
1595 build_audio_output(context, pipe_ctx, &audio_output);
1596
1597 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1598 pipe_ctx->stream_res.audio->inst);
1599
1600 pipe_ctx->stream_res.audio->funcs->az_configure(
1601 pipe_ctx->stream_res.audio,
1602 pipe_ctx->stream->signal,
1603 &audio_output.crtc_info,
1604 &pipe_ctx->stream->audio_info,
1605 &audio_output.dp_link_info);
1606
1607 if (dc->config.disable_hbr_audio_dp2)
1608 if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&
1609 dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))
1610 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);
1611 }
1612
1613 /* make sure no pipes syncd to the pipe being enabled */
1614 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1615 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1616
1617 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1618 pipe_ctx->stream_res.opp,
1619 &stream->bit_depth_params,
1620 &stream->clamping);
1621
1622 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1623 pipe_ctx->stream_res.opp,
1624 COLOR_SPACE_YCBCR601,
1625 stream->timing.display_color_depth,
1626 stream->signal);
1627
1628 while (odm_pipe) {
1629 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1630 odm_pipe->stream_res.opp,
1631 COLOR_SPACE_YCBCR601,
1632 stream->timing.display_color_depth,
1633 stream->signal);
1634
1635 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1636 odm_pipe->stream_res.opp,
1637 &stream->bit_depth_params,
1638 &stream->clamping);
1639 odm_pipe = odm_pipe->next_odm_pipe;
1640 }
1641
1642 /* DCN3.1 FPGA Workaround
1643 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1644 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1645 * function core_link_enable_stream
1646 */
1647 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1648 /* */
1649 /* Do not touch stream timing on seamless boot optimization. */
1650 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1651 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1652
1653 if (hws->funcs.setup_vupdate_interrupt)
1654 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1655
1656 params.vertical_total_min = stream->adjust.v_total_min;
1657 params.vertical_total_max = stream->adjust.v_total_max;
1658 set_drr_and_clear_adjust_pending(pipe_ctx, stream, ¶ms);
1659
1660 // DRR should set trigger event to monitor surface update event
1661 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1662 event_triggers = 0x80;
1663 /* Event triggers and num frames initialized for DRR, but can be
1664 * later updated for PSR use. Note DRR trigger events are generated
1665 * regardless of whether num frames met.
1666 */
1667 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1668 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1669 pipe_ctx->stream_res.tg, event_triggers, 2);
1670
1671 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1672 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1673 pipe_ctx->stream_res.stream_enc,
1674 pipe_ctx->stream_res.tg->inst);
1675
1676 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1677 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1678
1679 if (!stream->dpms_off)
1680 dc->link_srv->set_dpms_on(context, pipe_ctx);
1681
1682 /* DCN3.1 FPGA Workaround
1683 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1684 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1685 * function core_link_enable_stream
1686 */
1687 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1688 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1689 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1690 }
1691
1692 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1693
1694 /* Phantom and main stream share the same link (because the stream
1695 * is constructed with the same sink). Make sure not to override
1696 * and link programming on the main.
1697 */
1698 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
1699 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1700 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1701 }
1702 return DC_OK;
1703 }
1704
1705 /******************************************************************************/
1706
power_down_encoders(struct dc * dc)1707 static void power_down_encoders(struct dc *dc)
1708 {
1709 int i;
1710
1711 for (i = 0; i < dc->link_count; i++) {
1712 enum signal_type signal = dc->links[i]->connector_signal;
1713
1714 dc->link_srv->blank_dp_stream(dc->links[i], false);
1715
1716 if (signal != SIGNAL_TYPE_EDP)
1717 signal = SIGNAL_TYPE_NONE;
1718
1719 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1720 dc->links[i]->link_enc->funcs->disable_output(
1721 dc->links[i]->link_enc, signal);
1722
1723 dc->links[i]->link_status.link_active = false;
1724 memset(&dc->links[i]->cur_link_settings, 0,
1725 sizeof(dc->links[i]->cur_link_settings));
1726 }
1727 }
1728
power_down_controllers(struct dc * dc)1729 static void power_down_controllers(struct dc *dc)
1730 {
1731 int i;
1732
1733 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1734 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1735 dc->res_pool->timing_generators[i]);
1736 }
1737 }
1738
power_down_clock_sources(struct dc * dc)1739 static void power_down_clock_sources(struct dc *dc)
1740 {
1741 int i;
1742
1743 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1744 dc->res_pool->dp_clock_source) == false)
1745 dm_error("Failed to power down pll! (dp clk src)\n");
1746
1747 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1748 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1749 dc->res_pool->clock_sources[i]) == false)
1750 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1751 }
1752 }
1753
power_down_all_hw_blocks(struct dc * dc)1754 static void power_down_all_hw_blocks(struct dc *dc)
1755 {
1756 power_down_encoders(dc);
1757
1758 power_down_controllers(dc);
1759
1760 power_down_clock_sources(dc);
1761
1762 if (dc->fbc_compressor)
1763 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1764 }
1765
disable_vga_and_power_gate_all_controllers(struct dc * dc)1766 static void disable_vga_and_power_gate_all_controllers(
1767 struct dc *dc)
1768 {
1769 int i;
1770 struct timing_generator *tg;
1771 struct dc_context *ctx = dc->ctx;
1772
1773 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1774 tg = dc->res_pool->timing_generators[i];
1775
1776 if (tg->funcs->disable_vga)
1777 tg->funcs->disable_vga(tg);
1778 }
1779 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1780 /* Enable CLOCK gating for each pipe BEFORE controller
1781 * powergating. */
1782 enable_display_pipe_clock_gating(ctx,
1783 true);
1784
1785 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1786 dc->hwss.disable_plane(dc, dc->current_state,
1787 &dc->current_state->res_ctx.pipe_ctx[i]);
1788 }
1789 }
1790
1791
get_edp_streams(struct dc_state * context,struct dc_stream_state ** edp_streams,int * edp_stream_num)1792 static void get_edp_streams(struct dc_state *context,
1793 struct dc_stream_state **edp_streams,
1794 int *edp_stream_num)
1795 {
1796 int i;
1797
1798 *edp_stream_num = 0;
1799 for (i = 0; i < context->stream_count; i++) {
1800 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1801 edp_streams[*edp_stream_num] = context->streams[i];
1802 if (++(*edp_stream_num) == MAX_NUM_EDP)
1803 return;
1804 }
1805 }
1806 }
1807
get_edp_links_with_sink(struct dc * dc,struct dc_link ** edp_links_with_sink,int * edp_with_sink_num)1808 static void get_edp_links_with_sink(
1809 struct dc *dc,
1810 struct dc_link **edp_links_with_sink,
1811 int *edp_with_sink_num)
1812 {
1813 int i;
1814
1815 /* check if there is an eDP panel not in use */
1816 *edp_with_sink_num = 0;
1817 for (i = 0; i < dc->link_count; i++) {
1818 if (dc->links[i]->local_sink &&
1819 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1820 edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1821 if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1822 return;
1823 }
1824 }
1825 }
1826
clean_up_dsc_blocks(struct dc * dc)1827 static void clean_up_dsc_blocks(struct dc *dc)
1828 {
1829 struct display_stream_compressor *dsc = NULL;
1830 struct timing_generator *tg = NULL;
1831 struct stream_encoder *se = NULL;
1832 struct dccg *dccg = dc->res_pool->dccg;
1833 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
1834 int i;
1835
1836 if (dc->ctx->dce_version != DCN_VERSION_3_5 &&
1837 dc->ctx->dce_version != DCN_VERSION_3_51)
1838 return;
1839
1840 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1841 struct dcn_dsc_state s = {0};
1842
1843 dsc = dc->res_pool->dscs[i];
1844 dsc->funcs->dsc_read_state(dsc, &s);
1845 if (s.dsc_fw_en) {
1846 /* disable DSC in OPTC */
1847 if (i < dc->res_pool->timing_generator_count) {
1848 tg = dc->res_pool->timing_generators[i];
1849 tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);
1850 }
1851 /* disable DSC in stream encoder */
1852 if (i < dc->res_pool->stream_enc_count) {
1853 se = dc->res_pool->stream_enc[i];
1854 se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);
1855 se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);
1856 }
1857 /* disable DSC block */
1858 if (dccg->funcs->set_ref_dscclk)
1859 dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
1860 dsc->funcs->dsc_disable(dsc);
1861
1862 /* power down DSC */
1863 if (pg_cntl != NULL)
1864 pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
1865 }
1866 }
1867 }
1868
1869 /*
1870 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1871 * 1. Power down all DC HW blocks
1872 * 2. Disable VGA engine on all controllers
1873 * 3. Enable power gating for controller
1874 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1875 */
dce110_enable_accelerated_mode(struct dc * dc,struct dc_state * context)1876 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1877 {
1878 struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1879 struct dc_link *edp_links[MAX_NUM_EDP];
1880 struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1881 struct dc_link *edp_link_with_sink = NULL;
1882 struct dc_link *edp_link = NULL;
1883 struct pipe_ctx *pipe_ctx = NULL;
1884 struct dce_hwseq *hws = dc->hwseq;
1885 int edp_with_sink_num;
1886 int edp_num;
1887 int edp_stream_num;
1888 int i;
1889 bool can_apply_edp_fast_boot = false;
1890 bool can_apply_seamless_boot = false;
1891 bool keep_edp_vdd_on = false;
1892 struct dc_bios *dcb = dc->ctx->dc_bios;
1893 DC_LOGGER_INIT();
1894
1895
1896 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1897 dc_get_edp_links(dc, edp_links, &edp_num);
1898
1899 if (hws->funcs.init_pipes)
1900 hws->funcs.init_pipes(dc, context);
1901
1902 get_edp_streams(context, edp_streams, &edp_stream_num);
1903
1904 // Check fastboot support, disable on DCE8 because of blank screens
1905 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1906 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1907 dc->ctx->dce_version != DCE_VERSION_8_3) {
1908 for (i = 0; i < edp_num; i++) {
1909 edp_link = edp_links[i];
1910 if (edp_link != edp_streams[0]->link)
1911 continue;
1912 // enable fastboot if backend is enabled on eDP
1913 if (edp_link->link_enc->funcs->is_dig_enabled &&
1914 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1915 edp_link->link_status.link_active) {
1916 struct dc_stream_state *edp_stream = edp_streams[0];
1917
1918 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1919 edp_stream->sink, &edp_stream->timing);
1920 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1921 if (can_apply_edp_fast_boot) {
1922 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot Enable\n");
1923
1924 // Vbios & Driver support different pixel rate div policy.
1925 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);
1926 if (pipe_ctx &&
1927 hws->funcs.is_dp_dig_pixel_rate_div_policy &&
1928 hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1929 // Get Vbios div factor from register
1930 dc->res_pool->dccg->funcs->get_pixel_rate_div(
1931 dc->res_pool->dccg,
1932 pipe_ctx->stream_res.tg->inst,
1933 &pipe_ctx->pixel_rate_divider.div_factor1,
1934 &pipe_ctx->pixel_rate_divider.div_factor2);
1935
1936 // VBios doesn't support pixel rate div, so force it.
1937 // If VBios supports it, we check it from reigster or other flags.
1938 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;
1939 }
1940 }
1941 break;
1942 }
1943 }
1944 // We are trying to enable eDP, don't power down VDD
1945 if (can_apply_edp_fast_boot)
1946 keep_edp_vdd_on = true;
1947 }
1948
1949 // Check seamless boot support
1950 for (i = 0; i < context->stream_count; i++) {
1951 if (context->streams[i]->apply_seamless_boot_optimization) {
1952 can_apply_seamless_boot = true;
1953 break;
1954 }
1955 }
1956
1957 /* eDP should not have stream in resume from S4 and so even with VBios post
1958 * it should get turned off
1959 */
1960 if (edp_with_sink_num)
1961 edp_link_with_sink = edp_links_with_sink[0];
1962
1963 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1964 if (edp_link_with_sink && !keep_edp_vdd_on) {
1965 /*turn off backlight before DP_blank and encoder powered down*/
1966 hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1967 }
1968 /*resume from S3, no vbios posting, no need to power down again*/
1969 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))
1970 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1971
1972 power_down_all_hw_blocks(dc);
1973
1974 /* DSC could be enabled on eDP during VBIOS post.
1975 * To clean up dsc blocks if eDP is in link but not active.
1976 */
1977 if (edp_link_with_sink && (edp_stream_num == 0))
1978 clean_up_dsc_blocks(dc);
1979
1980 disable_vga_and_power_gate_all_controllers(dc);
1981 if (edp_link_with_sink && !keep_edp_vdd_on)
1982 dc->hwss.edp_power_control(edp_link_with_sink, false);
1983 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))
1984 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1985 }
1986 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1987 }
1988
compute_pstate_blackout_duration(struct bw_fixed blackout_duration,const struct dc_stream_state * stream)1989 static uint32_t compute_pstate_blackout_duration(
1990 struct bw_fixed blackout_duration,
1991 const struct dc_stream_state *stream)
1992 {
1993 uint32_t total_dest_line_time_ns;
1994 uint32_t pstate_blackout_duration_ns;
1995
1996 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1997
1998 total_dest_line_time_ns = 1000000UL *
1999 (stream->timing.h_total * 10) /
2000 stream->timing.pix_clk_100hz +
2001 pstate_blackout_duration_ns;
2002
2003 return total_dest_line_time_ns;
2004 }
2005
dce110_set_displaymarks(const struct dc * dc,struct dc_state * context)2006 static void dce110_set_displaymarks(
2007 const struct dc *dc,
2008 struct dc_state *context)
2009 {
2010 uint8_t i, num_pipes;
2011 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2012
2013 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
2014 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2015 uint32_t total_dest_line_time_ns;
2016
2017 if (pipe_ctx->stream == NULL)
2018 continue;
2019
2020 total_dest_line_time_ns = compute_pstate_blackout_duration(
2021 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
2022 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
2023 pipe_ctx->plane_res.mi,
2024 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
2025 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
2026 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
2027 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
2028 total_dest_line_time_ns);
2029 if (i == underlay_idx) {
2030 num_pipes++;
2031 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
2032 pipe_ctx->plane_res.mi,
2033 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
2034 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
2035 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
2036 total_dest_line_time_ns);
2037 }
2038 num_pipes++;
2039 }
2040 }
2041
dce110_set_safe_displaymarks(struct resource_context * res_ctx,const struct resource_pool * pool)2042 void dce110_set_safe_displaymarks(
2043 struct resource_context *res_ctx,
2044 const struct resource_pool *pool)
2045 {
2046 int i;
2047 int underlay_idx = pool->underlay_pipe_index;
2048 struct dce_watermarks max_marks = {
2049 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
2050 struct dce_watermarks nbp_marks = {
2051 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
2052 struct dce_watermarks min_marks = { 0, 0, 0, 0};
2053
2054 for (i = 0; i < MAX_PIPES; i++) {
2055 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
2056 continue;
2057
2058 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
2059 res_ctx->pipe_ctx[i].plane_res.mi,
2060 nbp_marks,
2061 max_marks,
2062 min_marks,
2063 max_marks,
2064 MAX_WATERMARK);
2065
2066 if (i == underlay_idx)
2067 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
2068 res_ctx->pipe_ctx[i].plane_res.mi,
2069 nbp_marks,
2070 max_marks,
2071 max_marks,
2072 MAX_WATERMARK);
2073
2074 }
2075 }
2076
2077 /*******************************************************************************
2078 * Public functions
2079 ******************************************************************************/
2080
set_drr(struct pipe_ctx ** pipe_ctx,int num_pipes,struct dc_crtc_timing_adjust adjust)2081 static void set_drr(struct pipe_ctx **pipe_ctx,
2082 int num_pipes, struct dc_crtc_timing_adjust adjust)
2083 {
2084 int i = 0;
2085 struct drr_params params = {0};
2086 // DRR should set trigger event to monitor surface update event
2087 unsigned int event_triggers = 0x80;
2088 // Note DRR trigger events are generated regardless of whether num frames met.
2089 unsigned int num_frames = 2;
2090
2091 params.vertical_total_max = adjust.v_total_max;
2092 params.vertical_total_min = adjust.v_total_min;
2093
2094 /* TODO: If multiple pipes are to be supported, you need
2095 * some GSL stuff. Static screen triggers may be programmed differently
2096 * as well.
2097 */
2098 for (i = 0; i < num_pipes; i++) {
2099 /* dc_state_destruct() might null the stream resources, so fetch tg
2100 * here first to avoid a race condition. The lifetime of the pointee
2101 * itself (the timing_generator object) is not a problem here.
2102 */
2103 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
2104
2105 if ((tg != NULL) && tg->funcs) {
2106 set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, ¶ms);
2107 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
2108 if (tg->funcs->set_static_screen_control)
2109 tg->funcs->set_static_screen_control(
2110 tg, event_triggers, num_frames);
2111 }
2112 }
2113 }
2114
get_position(struct pipe_ctx ** pipe_ctx,int num_pipes,struct crtc_position * position)2115 static void get_position(struct pipe_ctx **pipe_ctx,
2116 int num_pipes,
2117 struct crtc_position *position)
2118 {
2119 int i = 0;
2120
2121 /* TODO: handle pipes > 1
2122 */
2123 for (i = 0; i < num_pipes; i++)
2124 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2125 }
2126
set_static_screen_control(struct pipe_ctx ** pipe_ctx,int num_pipes,const struct dc_static_screen_params * params)2127 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2128 int num_pipes, const struct dc_static_screen_params *params)
2129 {
2130 unsigned int i;
2131 unsigned int triggers = 0;
2132
2133 if (params->triggers.overlay_update)
2134 triggers |= 0x100;
2135 if (params->triggers.surface_update)
2136 triggers |= 0x80;
2137 if (params->triggers.cursor_update)
2138 triggers |= 0x2;
2139 if (params->triggers.force_trigger)
2140 triggers |= 0x1;
2141
2142 if (num_pipes) {
2143 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
2144
2145 if (dc->fbc_compressor)
2146 triggers |= 0x84;
2147 }
2148
2149 for (i = 0; i < num_pipes; i++)
2150 pipe_ctx[i]->stream_res.tg->funcs->
2151 set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2152 triggers, params->num_frames);
2153 }
2154
2155 /*
2156 * Check if FBC can be enabled
2157 */
should_enable_fbc(struct dc * dc,struct dc_state * context,uint32_t * pipe_idx)2158 static bool should_enable_fbc(struct dc *dc,
2159 struct dc_state *context,
2160 uint32_t *pipe_idx)
2161 {
2162 uint32_t i;
2163 struct pipe_ctx *pipe_ctx = NULL;
2164 struct resource_context *res_ctx = &context->res_ctx;
2165 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2166
2167
2168 ASSERT(dc->fbc_compressor);
2169
2170 /* FBC memory should be allocated */
2171 if (!dc->ctx->fbc_gpu_addr)
2172 return false;
2173
2174 /* Only supports single display */
2175 if (context->stream_count != 1)
2176 return false;
2177
2178 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2179 if (res_ctx->pipe_ctx[i].stream) {
2180
2181 pipe_ctx = &res_ctx->pipe_ctx[i];
2182
2183 /* fbc not applicable on underlay pipe */
2184 if (pipe_ctx->pipe_idx != underlay_idx) {
2185 *pipe_idx = i;
2186 break;
2187 }
2188 }
2189 }
2190
2191 if (i == dc->res_pool->pipe_count)
2192 return false;
2193
2194 if (!pipe_ctx->stream->link)
2195 return false;
2196
2197 /* Only supports eDP */
2198 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2199 return false;
2200
2201 /* PSR should not be enabled */
2202 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2203 return false;
2204
2205 /* Replay should not be enabled */
2206 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2207 return false;
2208
2209 /* Nothing to compress */
2210 if (!pipe_ctx->plane_state)
2211 return false;
2212
2213 /* Only for non-linear tiling */
2214 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2215 return false;
2216
2217 return true;
2218 }
2219
2220 /*
2221 * Enable FBC
2222 */
enable_fbc(struct dc * dc,struct dc_state * context)2223 static void enable_fbc(
2224 struct dc *dc,
2225 struct dc_state *context)
2226 {
2227 uint32_t pipe_idx = 0;
2228
2229 if (should_enable_fbc(dc, context, &pipe_idx)) {
2230 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2231 struct compr_addr_and_pitch_params params = {0, 0, 0};
2232 struct compressor *compr = dc->fbc_compressor;
2233 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2234
2235 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2236 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2237 params.inst = pipe_ctx->stream_res.tg->inst;
2238 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2239
2240 compr->funcs->surface_address_and_pitch(compr, ¶ms);
2241 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2242
2243 compr->funcs->enable_fbc(compr, ¶ms);
2244 }
2245 }
2246
dce110_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)2247 static void dce110_reset_hw_ctx_wrap(
2248 struct dc *dc,
2249 struct dc_state *context)
2250 {
2251 int i;
2252
2253 /* Reset old context */
2254 /* look up the targets that have been removed since last commit */
2255 for (i = 0; i < MAX_PIPES; i++) {
2256 struct pipe_ctx *pipe_ctx_old =
2257 &dc->current_state->res_ctx.pipe_ctx[i];
2258 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2259
2260 /* Note: We need to disable output if clock sources change,
2261 * since bios does optimization and doesn't apply if changing
2262 * PHY when not already disabled.
2263 */
2264
2265 /* Skip underlay pipe since it will be handled in commit surface*/
2266 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2267 continue;
2268
2269 if (!pipe_ctx->stream ||
2270 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2271 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2272
2273 /* Disable if new stream is null. O/w, if stream is
2274 * disabled already, no need to disable again.
2275 */
2276 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2277 dc->link_srv->set_dpms_off(pipe_ctx_old);
2278
2279 /* free acquired resources*/
2280 if (pipe_ctx_old->stream_res.audio) {
2281 /*disable az_endpoint*/
2282 pipe_ctx_old->stream_res.audio->funcs->
2283 az_disable(pipe_ctx_old->stream_res.audio);
2284
2285 /*free audio*/
2286 if (dc->caps.dynamic_audio == true) {
2287 /*we have to dynamic arbitrate the audio endpoints*/
2288 /*we free the resource, need reset is_audio_acquired*/
2289 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2290 pipe_ctx_old->stream_res.audio, false);
2291 pipe_ctx_old->stream_res.audio = NULL;
2292 }
2293 }
2294 }
2295
2296 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2297 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2298 dm_error("DC: failed to blank crtc!\n");
2299 BREAK_TO_DEBUGGER();
2300 }
2301 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2302 if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
2303 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2304 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2305 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2306
2307 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2308 dc->res_pool,
2309 old_clk))
2310 old_clk->funcs->cs_power_down(old_clk);
2311
2312 dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old);
2313
2314 pipe_ctx_old->stream = NULL;
2315 }
2316 }
2317 }
2318
dce110_setup_audio_dto(struct dc * dc,struct dc_state * context)2319 static void dce110_setup_audio_dto(
2320 struct dc *dc,
2321 struct dc_state *context)
2322 {
2323 unsigned int i;
2324
2325 /* program audio wall clock. use HDMI as clock source if HDMI
2326 * audio active. Otherwise, use DP as clock source
2327 * first, loop to find any HDMI audio, if not, loop find DP audio
2328 */
2329 /* Setup audio rate clock source */
2330 /* Issue:
2331 * Audio lag happened on DP monitor when unplug a HDMI monitor
2332 *
2333 * Cause:
2334 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2335 * is set to either dto0 or dto1, audio should work fine.
2336 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2337 * set to dto0 will cause audio lag.
2338 *
2339 * Solution:
2340 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2341 * find first available pipe with audio, setup audio wall DTO per topology
2342 * instead of per pipe.
2343 */
2344 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2345 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2346
2347 if (pipe_ctx->stream == NULL)
2348 continue;
2349
2350 if (pipe_ctx->top_pipe)
2351 continue;
2352 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2353 continue;
2354 if (pipe_ctx->stream_res.audio != NULL) {
2355 struct audio_output audio_output;
2356
2357 build_audio_output(context, pipe_ctx, &audio_output);
2358
2359 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2360 struct dtbclk_dto_params dto_params = {0};
2361
2362 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2363 dc->res_pool->dccg, &dto_params);
2364
2365 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2366 pipe_ctx->stream_res.audio,
2367 pipe_ctx->stream->signal,
2368 &audio_output.crtc_info,
2369 &audio_output.pll_info);
2370 } else
2371 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2372 pipe_ctx->stream_res.audio,
2373 pipe_ctx->stream->signal,
2374 &audio_output.crtc_info,
2375 &audio_output.pll_info);
2376 break;
2377 }
2378 }
2379
2380 /* no HDMI audio is found, try DP audio */
2381 if (i == dc->res_pool->pipe_count) {
2382 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2383 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2384
2385 if (pipe_ctx->stream == NULL)
2386 continue;
2387
2388 if (pipe_ctx->top_pipe)
2389 continue;
2390
2391 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2392 continue;
2393
2394 if (pipe_ctx->stream_res.audio != NULL) {
2395 struct audio_output audio_output = {0};
2396
2397 build_audio_output(context, pipe_ctx, &audio_output);
2398
2399 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2400 pipe_ctx->stream_res.audio,
2401 pipe_ctx->stream->signal,
2402 &audio_output.crtc_info,
2403 &audio_output.pll_info);
2404 break;
2405 }
2406 }
2407 }
2408 }
2409
dce110_apply_ctx_to_hw(struct dc * dc,struct dc_state * context)2410 enum dc_status dce110_apply_ctx_to_hw(
2411 struct dc *dc,
2412 struct dc_state *context)
2413 {
2414 struct dce_hwseq *hws = dc->hwseq;
2415 struct dc_bios *dcb = dc->ctx->dc_bios;
2416 enum dc_status status;
2417 int i;
2418 bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);
2419 bool is_hpo_acquired = resource_is_hpo_acquired(context);
2420
2421 /* reset syncd pipes from disabled pipes */
2422 if (dc->config.use_pipe_ctx_sync_logic)
2423 reset_syncd_pipes_from_disabled_pipes(dc, context);
2424
2425 /* Reset old context */
2426 /* look up the targets that have been removed since last commit */
2427 hws->funcs.reset_hw_ctx_wrap(dc, context);
2428
2429 /* Skip applying if no targets */
2430 if (context->stream_count <= 0)
2431 return DC_OK;
2432
2433 /* Apply new context */
2434 dcb->funcs->set_scratch_critical_state(dcb, true);
2435
2436 /* below is for real asic only */
2437 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2438 struct pipe_ctx *pipe_ctx_old =
2439 &dc->current_state->res_ctx.pipe_ctx[i];
2440 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2441
2442 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2443 continue;
2444
2445 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2446 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2447 dce_crtc_switch_to_clk_src(dc->hwseq,
2448 pipe_ctx->clock_source, i);
2449 continue;
2450 }
2451
2452 hws->funcs.enable_display_power_gating(
2453 dc, i, dc->ctx->dc_bios,
2454 PIPE_GATING_CONTROL_DISABLE);
2455 }
2456
2457 if (dc->fbc_compressor)
2458 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2459
2460 dce110_setup_audio_dto(dc, context);
2461
2462 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {
2463 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);
2464 }
2465
2466 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2467 struct pipe_ctx *pipe_ctx_old =
2468 &dc->current_state->res_ctx.pipe_ctx[i];
2469 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2470
2471 if (pipe_ctx->stream == NULL)
2472 continue;
2473
2474 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2475 pipe_ctx->stream->link->link_state_valid) {
2476 continue;
2477 }
2478
2479 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2480 continue;
2481
2482 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2483 continue;
2484
2485 status = dce110_apply_single_controller_ctx_to_hw(
2486 pipe_ctx,
2487 context,
2488 dc);
2489
2490 if (DC_OK != status)
2491 return status;
2492
2493 #ifdef CONFIG_DRM_AMD_DC_FP
2494 if (hws->funcs.resync_fifo_dccg_dio)
2495 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
2496 #endif
2497 }
2498
2499 if (dc->fbc_compressor)
2500 enable_fbc(dc, dc->current_state);
2501
2502 dcb->funcs->set_scratch_critical_state(dcb, false);
2503
2504 return DC_OK;
2505 }
2506
2507 /*******************************************************************************
2508 * Front End programming
2509 ******************************************************************************/
set_default_colors(struct pipe_ctx * pipe_ctx)2510 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2511 {
2512 struct default_adjustment default_adjust = { 0 };
2513
2514 default_adjust.force_hw_default = false;
2515 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2516 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2517 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2518 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2519
2520 /* display color depth */
2521 default_adjust.color_depth =
2522 pipe_ctx->stream->timing.display_color_depth;
2523
2524 /* Lb color depth */
2525 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2526
2527 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2528 pipe_ctx->plane_res.xfm, &default_adjust);
2529 }
2530
2531
2532 /*******************************************************************************
2533 * In order to turn on/off specific surface we will program
2534 * Blender + CRTC
2535 *
2536 * In case that we have two surfaces and they have a different visibility
2537 * we can't turn off the CRTC since it will turn off the entire display
2538 *
2539 * |----------------------------------------------- |
2540 * |bottom pipe|curr pipe | | |
2541 * |Surface |Surface | Blender | CRCT |
2542 * |visibility |visibility | Configuration| |
2543 * |------------------------------------------------|
2544 * | off | off | CURRENT_PIPE | blank |
2545 * | off | on | CURRENT_PIPE | unblank |
2546 * | on | off | OTHER_PIPE | unblank |
2547 * | on | on | BLENDING | unblank |
2548 * -------------------------------------------------|
2549 *
2550 ******************************************************************************/
program_surface_visibility(const struct dc * dc,struct pipe_ctx * pipe_ctx)2551 static void program_surface_visibility(const struct dc *dc,
2552 struct pipe_ctx *pipe_ctx)
2553 {
2554 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2555 bool blank_target = false;
2556
2557 if (pipe_ctx->bottom_pipe) {
2558
2559 /* For now we are supporting only two pipes */
2560 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2561
2562 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2563 if (pipe_ctx->plane_state->visible)
2564 blender_mode = BLND_MODE_BLENDING;
2565 else
2566 blender_mode = BLND_MODE_OTHER_PIPE;
2567
2568 } else if (!pipe_ctx->plane_state->visible)
2569 blank_target = true;
2570
2571 } else if (!pipe_ctx->plane_state->visible)
2572 blank_target = true;
2573
2574 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2575 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2576
2577 }
2578
program_gamut_remap(struct pipe_ctx * pipe_ctx)2579 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2580 {
2581 int i = 0;
2582 struct xfm_grph_csc_adjustment adjust;
2583 memset(&adjust, 0, sizeof(adjust));
2584 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2585
2586
2587 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2588 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2589
2590 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2591 adjust.temperature_matrix[i] =
2592 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2593 }
2594
2595 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2596 }
update_plane_addr(const struct dc * dc,struct pipe_ctx * pipe_ctx)2597 static void update_plane_addr(const struct dc *dc,
2598 struct pipe_ctx *pipe_ctx)
2599 {
2600 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2601
2602 if (plane_state == NULL)
2603 return;
2604
2605 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2606 pipe_ctx->plane_res.mi,
2607 &plane_state->address,
2608 plane_state->flip_immediate);
2609
2610 plane_state->status.requested_address = plane_state->address;
2611 }
2612
dce110_update_pending_status(struct pipe_ctx * pipe_ctx)2613 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2614 {
2615 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2616
2617 if (plane_state == NULL)
2618 return;
2619
2620 plane_state->status.is_flip_pending =
2621 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2622 pipe_ctx->plane_res.mi);
2623
2624 if (plane_state->status.is_flip_pending && !plane_state->visible)
2625 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2626
2627 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2628 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2629 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2630 plane_state->status.is_right_eye =\
2631 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2632 }
2633 }
2634
dce110_power_down(struct dc * dc)2635 void dce110_power_down(struct dc *dc)
2636 {
2637 power_down_all_hw_blocks(dc);
2638 disable_vga_and_power_gate_all_controllers(dc);
2639 }
2640
wait_for_reset_trigger_to_occur(struct dc_context * dc_ctx,struct timing_generator * tg)2641 static bool wait_for_reset_trigger_to_occur(
2642 struct dc_context *dc_ctx,
2643 struct timing_generator *tg)
2644 {
2645 struct dc_context *ctx = dc_ctx;
2646 bool rc = false;
2647
2648 /* To avoid endless loop we wait at most
2649 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2650 const uint32_t frames_to_wait_on_triggered_reset = 10;
2651 uint32_t i;
2652
2653 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2654
2655 if (!tg->funcs->is_counter_moving(tg)) {
2656 DC_ERROR("TG counter is not moving!\n");
2657 break;
2658 }
2659
2660 if (tg->funcs->did_triggered_reset_occur(tg)) {
2661 rc = true;
2662 /* usually occurs at i=1 */
2663 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2664 i);
2665 break;
2666 }
2667
2668 /* Wait for one frame. */
2669 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2670 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2671 }
2672
2673 if (false == rc)
2674 DC_ERROR("GSL: Timeout on reset trigger!\n");
2675
2676 return rc;
2677 }
2678
2679 /* Enable timing synchronization for a group of Timing Generators. */
dce110_enable_timing_synchronization(struct dc * dc,struct dc_state * state,int group_index,int group_size,struct pipe_ctx * grouped_pipes[])2680 static void dce110_enable_timing_synchronization(
2681 struct dc *dc,
2682 struct dc_state *state,
2683 int group_index,
2684 int group_size,
2685 struct pipe_ctx *grouped_pipes[])
2686 {
2687 struct dc_context *dc_ctx = dc->ctx;
2688 struct dcp_gsl_params gsl_params = { 0 };
2689 int i;
2690 DC_LOGGER_INIT();
2691
2692 DC_SYNC_INFO("GSL: Setting-up...\n");
2693
2694 /* Designate a single TG in the group as a master.
2695 * Since HW doesn't care which one, we always assign
2696 * the 1st one in the group. */
2697 gsl_params.gsl_group = 0;
2698 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2699
2700 for (i = 0; i < group_size; i++)
2701 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2702 grouped_pipes[i]->stream_res.tg, &gsl_params);
2703
2704 /* Reset slave controllers on master VSync */
2705 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2706
2707 for (i = 1 /* skip the master */; i < group_size; i++)
2708 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2709 grouped_pipes[i]->stream_res.tg,
2710 gsl_params.gsl_group);
2711
2712 for (i = 1 /* skip the master */; i < group_size; i++) {
2713 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2714 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2715 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2716 grouped_pipes[i]->stream_res.tg);
2717 }
2718
2719 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2720 * is that the sync'ed displays will not drift out of sync over time*/
2721 DC_SYNC_INFO("GSL: Restoring register states.\n");
2722 for (i = 0; i < group_size; i++)
2723 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2724
2725 DC_SYNC_INFO("GSL: Set-up complete.\n");
2726 }
2727
dce110_enable_per_frame_crtc_position_reset(struct dc * dc,int group_size,struct pipe_ctx * grouped_pipes[])2728 static void dce110_enable_per_frame_crtc_position_reset(
2729 struct dc *dc,
2730 int group_size,
2731 struct pipe_ctx *grouped_pipes[])
2732 {
2733 struct dc_context *dc_ctx = dc->ctx;
2734 struct dcp_gsl_params gsl_params = { 0 };
2735 int i;
2736 DC_LOGGER_INIT();
2737
2738 gsl_params.gsl_group = 0;
2739 gsl_params.gsl_master = 0;
2740
2741 for (i = 0; i < group_size; i++)
2742 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2743 grouped_pipes[i]->stream_res.tg, &gsl_params);
2744
2745 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2746
2747 for (i = 1; i < group_size; i++)
2748 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2749 grouped_pipes[i]->stream_res.tg,
2750 gsl_params.gsl_master,
2751 &grouped_pipes[i]->stream->triggered_crtc_reset);
2752
2753 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2754 for (i = 1; i < group_size; i++)
2755 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2756
2757 for (i = 0; i < group_size; i++)
2758 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2759
2760 }
2761
init_pipes(struct dc * dc,struct dc_state * context)2762 static void init_pipes(struct dc *dc, struct dc_state *context)
2763 {
2764 // Do nothing
2765 }
2766
init_hw(struct dc * dc)2767 static void init_hw(struct dc *dc)
2768 {
2769 int i;
2770 struct dc_bios *bp;
2771 struct transform *xfm;
2772 struct abm *abm;
2773 struct dmcu *dmcu;
2774 struct dce_hwseq *hws = dc->hwseq;
2775 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2776 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
2777
2778 bp = dc->ctx->dc_bios;
2779 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2780 xfm = dc->res_pool->transforms[i];
2781 xfm->funcs->transform_reset(xfm);
2782
2783 hws->funcs.enable_display_power_gating(
2784 dc, i, bp,
2785 PIPE_GATING_CONTROL_INIT);
2786 hws->funcs.enable_display_power_gating(
2787 dc, i, bp,
2788 PIPE_GATING_CONTROL_DISABLE);
2789 hws->funcs.enable_display_pipe_clock_gating(
2790 dc->ctx,
2791 true);
2792 }
2793
2794 dce_clock_gating_power_up(dc->hwseq, false);
2795 /***************************************/
2796
2797 for (i = 0; i < dc->link_count; i++) {
2798 /****************************************/
2799 /* Power up AND update implementation according to the
2800 * required signal (which may be different from the
2801 * default signal on connector). */
2802 struct dc_link *link = dc->links[i];
2803
2804 link->link_enc->funcs->hw_init(link->link_enc);
2805 }
2806
2807 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2808 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2809
2810 tg->funcs->disable_vga(tg);
2811
2812 /* Blank controller using driver code instead of
2813 * command table. */
2814 tg->funcs->set_blank(tg, true);
2815 hwss_wait_for_blank_complete(tg);
2816 }
2817
2818 for (i = 0; i < dc->res_pool->audio_count; i++) {
2819 struct audio *audio = dc->res_pool->audios[i];
2820 audio->funcs->hw_init(audio);
2821 }
2822
2823 for (i = 0; i < dc->link_count; i++) {
2824 struct dc_link *link = dc->links[i];
2825
2826 if (link->panel_cntl) {
2827 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2828 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
2829 }
2830 }
2831
2832 abm = dc->res_pool->abm;
2833 if (abm != NULL)
2834 abm->funcs->abm_init(abm, backlight, user_level);
2835
2836 dmcu = dc->res_pool->dmcu;
2837 if (dmcu != NULL && abm != NULL)
2838 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2839
2840 if (dc->fbc_compressor)
2841 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2842
2843 }
2844
2845
dce110_prepare_bandwidth(struct dc * dc,struct dc_state * context)2846 void dce110_prepare_bandwidth(
2847 struct dc *dc,
2848 struct dc_state *context)
2849 {
2850 struct clk_mgr *dccg = dc->clk_mgr;
2851
2852 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2853 if (dccg)
2854 dccg->funcs->update_clocks(
2855 dccg,
2856 context,
2857 false);
2858 }
2859
dce110_optimize_bandwidth(struct dc * dc,struct dc_state * context)2860 void dce110_optimize_bandwidth(
2861 struct dc *dc,
2862 struct dc_state *context)
2863 {
2864 struct clk_mgr *dccg = dc->clk_mgr;
2865
2866 dce110_set_displaymarks(dc, context);
2867
2868 if (dccg)
2869 dccg->funcs->update_clocks(
2870 dccg,
2871 context,
2872 true);
2873 }
2874
dce110_program_front_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx)2875 static void dce110_program_front_end_for_pipe(
2876 struct dc *dc, struct pipe_ctx *pipe_ctx)
2877 {
2878 struct mem_input *mi = pipe_ctx->plane_res.mi;
2879 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2880 struct xfm_grph_csc_adjustment adjust;
2881 struct out_csc_color_matrix tbl_entry;
2882 unsigned int i;
2883 struct dce_hwseq *hws = dc->hwseq;
2884
2885 memset(&tbl_entry, 0, sizeof(tbl_entry));
2886
2887 memset(&adjust, 0, sizeof(adjust));
2888 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2889
2890 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2891
2892 set_default_colors(pipe_ctx);
2893 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2894 == true) {
2895 tbl_entry.color_space =
2896 pipe_ctx->stream->output_color_space;
2897
2898 for (i = 0; i < 12; i++)
2899 tbl_entry.regval[i] =
2900 pipe_ctx->stream->csc_color_matrix.matrix[i];
2901
2902 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2903 (pipe_ctx->plane_res.xfm, &tbl_entry);
2904 }
2905
2906 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2907 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2908
2909 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2910 adjust.temperature_matrix[i] =
2911 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2912 }
2913
2914 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2915
2916 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2917
2918 program_scaler(dc, pipe_ctx);
2919
2920 mi->funcs->mem_input_program_surface_config(
2921 mi,
2922 plane_state->format,
2923 &plane_state->tiling_info,
2924 &plane_state->plane_size,
2925 plane_state->rotation,
2926 NULL,
2927 false);
2928 if (mi->funcs->set_blank)
2929 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2930
2931 if (dc->config.gpu_vm_support)
2932 mi->funcs->mem_input_program_pte_vm(
2933 pipe_ctx->plane_res.mi,
2934 plane_state->format,
2935 &plane_state->tiling_info,
2936 plane_state->rotation);
2937
2938 /* Moved programming gamma from dc to hwss */
2939 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2940 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2941 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2942 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2943
2944 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2945 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2946
2947 DC_LOG_SURFACE(
2948 "Pipe:%d %p: addr hi:0x%x, "
2949 "addr low:0x%x, "
2950 "src: %d, %d, %d,"
2951 " %d; dst: %d, %d, %d, %d;"
2952 "clip: %d, %d, %d, %d\n",
2953 pipe_ctx->pipe_idx,
2954 (void *) pipe_ctx->plane_state,
2955 pipe_ctx->plane_state->address.grph.addr.high_part,
2956 pipe_ctx->plane_state->address.grph.addr.low_part,
2957 pipe_ctx->plane_state->src_rect.x,
2958 pipe_ctx->plane_state->src_rect.y,
2959 pipe_ctx->plane_state->src_rect.width,
2960 pipe_ctx->plane_state->src_rect.height,
2961 pipe_ctx->plane_state->dst_rect.x,
2962 pipe_ctx->plane_state->dst_rect.y,
2963 pipe_ctx->plane_state->dst_rect.width,
2964 pipe_ctx->plane_state->dst_rect.height,
2965 pipe_ctx->plane_state->clip_rect.x,
2966 pipe_ctx->plane_state->clip_rect.y,
2967 pipe_ctx->plane_state->clip_rect.width,
2968 pipe_ctx->plane_state->clip_rect.height);
2969
2970 DC_LOG_SURFACE(
2971 "Pipe %d: width, height, x, y\n"
2972 "viewport:%d, %d, %d, %d\n"
2973 "recout: %d, %d, %d, %d\n",
2974 pipe_ctx->pipe_idx,
2975 pipe_ctx->plane_res.scl_data.viewport.width,
2976 pipe_ctx->plane_res.scl_data.viewport.height,
2977 pipe_ctx->plane_res.scl_data.viewport.x,
2978 pipe_ctx->plane_res.scl_data.viewport.y,
2979 pipe_ctx->plane_res.scl_data.recout.width,
2980 pipe_ctx->plane_res.scl_data.recout.height,
2981 pipe_ctx->plane_res.scl_data.recout.x,
2982 pipe_ctx->plane_res.scl_data.recout.y);
2983 }
2984
dce110_apply_ctx_for_surface(struct dc * dc,const struct dc_stream_state * stream,int num_planes,struct dc_state * context)2985 static void dce110_apply_ctx_for_surface(
2986 struct dc *dc,
2987 const struct dc_stream_state *stream,
2988 int num_planes,
2989 struct dc_state *context)
2990 {
2991 int i;
2992
2993 if (num_planes == 0)
2994 return;
2995
2996 if (dc->fbc_compressor)
2997 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2998
2999 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3000 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3001
3002 if (pipe_ctx->stream != stream)
3003 continue;
3004
3005 /* Need to allocate mem before program front end for Fiji */
3006 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
3007 pipe_ctx->plane_res.mi,
3008 pipe_ctx->stream->timing.h_total,
3009 pipe_ctx->stream->timing.v_total,
3010 pipe_ctx->stream->timing.pix_clk_100hz / 10,
3011 context->stream_count);
3012
3013 dce110_program_front_end_for_pipe(dc, pipe_ctx);
3014
3015 dc->hwss.update_plane_addr(dc, pipe_ctx);
3016
3017 program_surface_visibility(dc, pipe_ctx);
3018
3019 }
3020
3021 if (dc->fbc_compressor)
3022 enable_fbc(dc, context);
3023 }
3024
dce110_post_unlock_program_front_end(struct dc * dc,struct dc_state * context)3025 static void dce110_post_unlock_program_front_end(
3026 struct dc *dc,
3027 struct dc_state *context)
3028 {
3029 }
3030
dce110_power_down_fe(struct dc * dc,struct dc_state * state,struct pipe_ctx * pipe_ctx)3031 static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
3032 {
3033 struct dce_hwseq *hws = dc->hwseq;
3034 int fe_idx = pipe_ctx->plane_res.mi ?
3035 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
3036
3037 /* Do not power down fe when stream is active on dce*/
3038 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
3039 return;
3040
3041 hws->funcs.enable_display_power_gating(
3042 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
3043
3044 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
3045 dc->res_pool->transforms[fe_idx]);
3046 }
3047
dce110_wait_for_mpcc_disconnect(struct dc * dc,struct resource_pool * res_pool,struct pipe_ctx * pipe_ctx)3048 static void dce110_wait_for_mpcc_disconnect(
3049 struct dc *dc,
3050 struct resource_pool *res_pool,
3051 struct pipe_ctx *pipe_ctx)
3052 {
3053 /* do nothing*/
3054 }
3055
program_output_csc(struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)3056 static void program_output_csc(struct dc *dc,
3057 struct pipe_ctx *pipe_ctx,
3058 enum dc_color_space colorspace,
3059 uint16_t *matrix,
3060 int opp_id)
3061 {
3062 int i;
3063 struct out_csc_color_matrix tbl_entry;
3064
3065 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
3066 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
3067
3068 for (i = 0; i < 12; i++)
3069 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
3070
3071 tbl_entry.color_space = color_space;
3072
3073 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
3074 pipe_ctx->plane_res.xfm, &tbl_entry);
3075 }
3076 }
3077
dce110_set_cursor_position(struct pipe_ctx * pipe_ctx)3078 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
3079 {
3080 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
3081 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
3082 struct mem_input *mi = pipe_ctx->plane_res.mi;
3083 struct dc_cursor_mi_param param = {
3084 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
3085 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
3086 .viewport = pipe_ctx->plane_res.scl_data.viewport,
3087 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
3088 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
3089 .rotation = pipe_ctx->plane_state->rotation,
3090 .mirror = pipe_ctx->plane_state->horizontal_mirror
3091 };
3092
3093 /**
3094 * If the cursor's source viewport is clipped then we need to
3095 * translate the cursor to appear in the correct position on
3096 * the screen.
3097 *
3098 * This translation isn't affected by scaling so it needs to be
3099 * done *after* we adjust the position for the scale factor.
3100 *
3101 * This is only done by opt-in for now since there are still
3102 * some usecases like tiled display that might enable the
3103 * cursor on both streams while expecting dc to clip it.
3104 */
3105 if (pos_cpy.translate_by_source) {
3106 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
3107 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
3108 }
3109
3110 if (pipe_ctx->plane_state->address.type
3111 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
3112 pos_cpy.enable = false;
3113
3114 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
3115 pos_cpy.enable = false;
3116
3117 if (ipp->funcs->ipp_cursor_set_position)
3118 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
3119 if (mi->funcs->set_cursor_position)
3120 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
3121 }
3122
dce110_set_cursor_attribute(struct pipe_ctx * pipe_ctx)3123 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
3124 {
3125 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
3126
3127 if (pipe_ctx->plane_res.ipp &&
3128 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
3129 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
3130 pipe_ctx->plane_res.ipp, attributes);
3131
3132 if (pipe_ctx->plane_res.mi &&
3133 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
3134 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
3135 pipe_ctx->plane_res.mi, attributes);
3136
3137 if (pipe_ctx->plane_res.xfm &&
3138 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
3139 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
3140 pipe_ctx->plane_res.xfm, attributes);
3141 }
3142
dce110_set_backlight_level(struct pipe_ctx * pipe_ctx,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp)3143 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
3144 uint32_t backlight_pwm_u16_16,
3145 uint32_t frame_ramp)
3146 {
3147 struct dc_link *link = pipe_ctx->stream->link;
3148 struct dc *dc = link->ctx->dc;
3149 struct abm *abm = pipe_ctx->stream_res.abm;
3150 struct panel_cntl *panel_cntl = link->panel_cntl;
3151 struct dmcu *dmcu = dc->res_pool->dmcu;
3152 bool fw_set_brightness = true;
3153 /* DMCU -1 for all controller id values,
3154 * therefore +1 here
3155 */
3156 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
3157
3158 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
3159 return false;
3160
3161 if (dmcu)
3162 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3163
3164 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
3165 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
3166 else
3167 abm->funcs->set_backlight_level_pwm(
3168 abm,
3169 backlight_pwm_u16_16,
3170 frame_ramp,
3171 controller_id,
3172 link->panel_cntl->inst);
3173
3174 return true;
3175 }
3176
dce110_set_abm_immediate_disable(struct pipe_ctx * pipe_ctx)3177 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
3178 {
3179 struct abm *abm = pipe_ctx->stream_res.abm;
3180 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3181
3182 if (abm)
3183 abm->funcs->set_abm_immediate_disable(abm,
3184 pipe_ctx->stream->link->panel_cntl->inst);
3185
3186 if (panel_cntl)
3187 panel_cntl->funcs->store_backlight_level(panel_cntl);
3188 }
3189
dce110_set_pipe(struct pipe_ctx * pipe_ctx)3190 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3191 {
3192 struct abm *abm = pipe_ctx->stream_res.abm;
3193 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3194 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3195
3196 if (abm && panel_cntl)
3197 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3198 }
3199
dce110_enable_lvds_link_output(struct dc_link * link,const struct link_resource * link_res,enum clock_source_id clock_source,uint32_t pixel_clock)3200 void dce110_enable_lvds_link_output(struct dc_link *link,
3201 const struct link_resource *link_res,
3202 enum clock_source_id clock_source,
3203 uint32_t pixel_clock)
3204 {
3205 link->link_enc->funcs->enable_lvds_output(
3206 link->link_enc,
3207 clock_source,
3208 pixel_clock);
3209 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3210 }
3211
dce110_enable_tmds_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,enum dc_color_depth color_depth,uint32_t pixel_clock)3212 void dce110_enable_tmds_link_output(struct dc_link *link,
3213 const struct link_resource *link_res,
3214 enum signal_type signal,
3215 enum clock_source_id clock_source,
3216 enum dc_color_depth color_depth,
3217 uint32_t pixel_clock)
3218 {
3219 link->link_enc->funcs->enable_tmds_output(
3220 link->link_enc,
3221 clock_source,
3222 color_depth,
3223 signal,
3224 pixel_clock);
3225 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3226 }
3227
dce110_enable_dp_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,const struct dc_link_settings * link_settings)3228 void dce110_enable_dp_link_output(
3229 struct dc_link *link,
3230 const struct link_resource *link_res,
3231 enum signal_type signal,
3232 enum clock_source_id clock_source,
3233 const struct dc_link_settings *link_settings)
3234 {
3235 struct dc *dc = link->ctx->dc;
3236 struct dmcu *dmcu = dc->res_pool->dmcu;
3237 struct pipe_ctx *pipes =
3238 link->dc->current_state->res_ctx.pipe_ctx;
3239 struct clock_source *dp_cs =
3240 link->dc->res_pool->dp_clock_source;
3241 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3242 unsigned int i;
3243
3244 /*
3245 * Add the logic to extract BOTH power up and power down sequences
3246 * from enable/disable link output and only call edp panel control
3247 * in enable_link_dp and disable_link_dp once.
3248 */
3249 if (link->connector_signal == SIGNAL_TYPE_EDP) {
3250 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3251 }
3252
3253 /* If the current pixel clock source is not DTO(happens after
3254 * switching from HDMI passive dongle to DP on the same connector),
3255 * switch the pixel clock source to DTO.
3256 */
3257
3258 for (i = 0; i < MAX_PIPES; i++) {
3259 if (pipes[i].stream != NULL &&
3260 pipes[i].stream->link == link) {
3261 if (pipes[i].clock_source != NULL &&
3262 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3263 pipes[i].clock_source = dp_cs;
3264 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3265 pipes[i].stream->timing.pix_clk_100hz;
3266 pipes[i].clock_source->funcs->program_pix_clk(
3267 pipes[i].clock_source,
3268 &pipes[i].stream_res.pix_clk_params,
3269 dc->link_srv->dp_get_encoding_format(link_settings),
3270 &pipes[i].pll_settings);
3271 }
3272 }
3273 }
3274
3275 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3276 if (dc->clk_mgr->funcs->notify_link_rate_change)
3277 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3278 }
3279
3280 if (dmcu != NULL && dmcu->funcs->lock_phy)
3281 dmcu->funcs->lock_phy(dmcu);
3282
3283 if (link_hwss->ext.enable_dp_link_output)
3284 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3285 clock_source, link_settings);
3286
3287 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3288
3289 if (dmcu != NULL && dmcu->funcs->unlock_phy)
3290 dmcu->funcs->unlock_phy(dmcu);
3291
3292 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3293 }
3294
dce110_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)3295 void dce110_disable_link_output(struct dc_link *link,
3296 const struct link_resource *link_res,
3297 enum signal_type signal)
3298 {
3299 struct dc *dc = link->ctx->dc;
3300 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3301 struct dmcu *dmcu = dc->res_pool->dmcu;
3302
3303 if (signal == SIGNAL_TYPE_EDP &&
3304 link->dc->hwss.edp_backlight_control &&
3305 !link->skip_implict_edp_power_control)
3306 link->dc->hwss.edp_backlight_control(link, false);
3307 else if (dmcu != NULL && dmcu->funcs->lock_phy)
3308 dmcu->funcs->lock_phy(dmcu);
3309
3310 link_hwss->disable_link_output(link, link_res, signal);
3311 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3312 /*
3313 * Add the logic to extract BOTH power up and power down sequences
3314 * from enable/disable link output and only call edp panel control
3315 * in enable_link_dp and disable_link_dp once.
3316 */
3317 if (dmcu != NULL && dmcu->funcs->lock_phy)
3318 dmcu->funcs->unlock_phy(dmcu);
3319 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3320 }
3321
3322 static const struct hw_sequencer_funcs dce110_funcs = {
3323 .program_gamut_remap = program_gamut_remap,
3324 .program_output_csc = program_output_csc,
3325 .init_hw = init_hw,
3326 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3327 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3328 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3329 .update_plane_addr = update_plane_addr,
3330 .update_pending_status = dce110_update_pending_status,
3331 .enable_accelerated_mode = dce110_enable_accelerated_mode,
3332 .enable_timing_synchronization = dce110_enable_timing_synchronization,
3333 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3334 .update_info_frame = dce110_update_info_frame,
3335 .enable_stream = dce110_enable_stream,
3336 .disable_stream = dce110_disable_stream,
3337 .unblank_stream = dce110_unblank_stream,
3338 .blank_stream = dce110_blank_stream,
3339 .enable_audio_stream = dce110_enable_audio_stream,
3340 .disable_audio_stream = dce110_disable_audio_stream,
3341 .disable_plane = dce110_power_down_fe,
3342 .pipe_control_lock = dce_pipe_control_lock,
3343 .interdependent_update_lock = NULL,
3344 .cursor_lock = dce_pipe_control_lock,
3345 .prepare_bandwidth = dce110_prepare_bandwidth,
3346 .optimize_bandwidth = dce110_optimize_bandwidth,
3347 .set_drr = set_drr,
3348 .get_position = get_position,
3349 .set_static_screen_control = set_static_screen_control,
3350 .setup_stereo = NULL,
3351 .set_avmute = dce110_set_avmute,
3352 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3353 .edp_backlight_control = dce110_edp_backlight_control,
3354 .edp_power_control = dce110_edp_power_control,
3355 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3356 .set_cursor_position = dce110_set_cursor_position,
3357 .set_cursor_attribute = dce110_set_cursor_attribute,
3358 .set_backlight_level = dce110_set_backlight_level,
3359 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3360 .set_pipe = dce110_set_pipe,
3361 .enable_lvds_link_output = dce110_enable_lvds_link_output,
3362 .enable_tmds_link_output = dce110_enable_tmds_link_output,
3363 .enable_dp_link_output = dce110_enable_dp_link_output,
3364 .disable_link_output = dce110_disable_link_output,
3365 };
3366
3367 static const struct hwseq_private_funcs dce110_private_funcs = {
3368 .init_pipes = init_pipes,
3369 .set_input_transfer_func = dce110_set_input_transfer_func,
3370 .set_output_transfer_func = dce110_set_output_transfer_func,
3371 .power_down = dce110_power_down,
3372 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3373 .enable_display_power_gating = dce110_enable_display_power_gating,
3374 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3375 .enable_stream_timing = dce110_enable_stream_timing,
3376 .disable_stream_gating = NULL,
3377 .enable_stream_gating = NULL,
3378 .edp_backlight_control = dce110_edp_backlight_control,
3379 };
3380
dce110_hw_sequencer_construct(struct dc * dc)3381 void dce110_hw_sequencer_construct(struct dc *dc)
3382 {
3383 dc->hwss = dce110_funcs;
3384 dc->hwseq->funcs = dce110_private_funcs;
3385 }
3386
3387